Semiconductor package

Abstract

A semiconductor package includes: a coreless circuit substrate including an insulating member having a plurality of insulating layers and a plurality of cavities, and a plurality of wiring layers disposed on the plurality of insulating layers, respectively; a semiconductor chip disposed on an upper surface of the coreless circuit substrate and electrically connected to an uppermost wiring layer among the plurality of wiring layers; and a plurality of semiconductor-based chip capacitors respectively disposed in the plurality of cavities, and each of the semiconductor-based chip capacitors has an upper surface on which the first pad is disposed and a lower surface on which the second pad is disposed. The first pad is connected to a first wiring layer of the plurality of wiring layers adjacent to the first pad through the conductive bump, and the second pad is connected to an interconnect punch-through of a second wiring layer of the plurality of wiring layers adjacent to the second pad.

Description

Cross-references to related applications

[0001] This application claims the benefit of Korean Patent Application No. 10-2024-0159921, filed with the Korean Intellectual Property Office on November 12, 2024, the entire disclosure of which is incorporated herein by reference for all purposes. Technical Field

[0002] The present invention relates to semiconductor packaging. Background Technology

[0003] As electronic devices become lighter and more powerful, the semiconductor packaging field also needs to develop miniaturized and high-performance semiconductor packages. To achieve miniaturization and high performance of semiconductor packages, packaging technologies that embed passive components in circuit boards are being continuously developed. Summary of the Invention

[0004] An example embodiment provides a semiconductor package having a circuit board in which passive components are embedded.

[0005] According to an example embodiment, a semiconductor package includes: a coreless circuit board including an insulating member and a plurality of wiring layers, the insulating member having a plurality of insulating layers and a plurality of cavities, the plurality of wiring layers being disposed on the plurality of insulating layers and having interconnecting through-holes connecting to adjacent wiring layers; at least one semiconductor chip disposed on the upper surface of the coreless circuit board and electrically connected to the uppermost wiring layer of the plurality of wiring layers; and a plurality of semiconductor-based chip capacitors, the plurality of semiconductor-based chip capacitors being disposed in the plurality of cavities, and each semiconductor-based chip capacitor having an upper surface on which a first pad is disposed and a lower surface on which a second pad is disposed. The first pad is connected to a first wiring layer adjacent to the first pad of the plurality of wiring layers via conductive bumps, and the second pad is connected to an interconnecting through-hole of a second wiring layer adjacent to the second pad of the plurality of wiring layers.

[0006] According to an example embodiment, a semiconductor package includes: a coreless circuit board including an insulating member having multiple insulating layers and multiple wiring layers respectively disposed on the multiple insulating layers, the uppermost wiring layer of the multiple wiring layers including a planar pattern for pads, and each of the multiple wiring layers except the uppermost wiring layer having an interconnecting through-hole connected to another adjacent wiring layer; a semiconductor chip disposed on the upper surface of the coreless circuit board and electrically connected to the planar pattern for pads of the uppermost wiring layer; and multiple semiconductor-based chip capacitors embedded in the coreless circuit board, each having an upper surface on which a first pad is disposed and a lower surface on which a second pad is disposed. The first pad is connected to the lower surface of the planar pattern for pads of the uppermost wiring layer, and the second pad is connected to an interconnecting through-hole of the wiring layer adjacent to the second pad.

[0007] According to an example embodiment, a semiconductor package includes: a coreless circuit board including an insulating member having multiple insulating layers and multiple wiring layers respectively disposed on the multiple insulating layers, the uppermost wiring layer of the multiple wiring layers including a planar pattern for pads, and each of the multiple wiring layers except the uppermost wiring layer having an interconnecting through-hole connecting to another adjacent wiring layer; multiple semiconductor chips disposed on an upper surface of the coreless circuit board and electrically connected to the planar pattern for pads of the uppermost wiring layer; a semiconductor bridge embedded in the coreless circuit board and having interconnecting wiring layers electrically connecting the multiple semiconductor chips; and multiple semiconductor-based chip capacitors embedded in the coreless circuit board and having an upper surface on which a first pad is disposed and a lower surface on which a second pad is disposed. The first pad is connected to a first wiring layer adjacent to the first pad of the multiple wiring layers via a first conductive bump, and the second pad is connected to an interconnecting through-hole of a second wiring layer adjacent to the second pad of the multiple wiring layers.

[0008] According to an example embodiment, a semiconductor-based chip capacitor includes: a semiconductor body having a first surface and a second surface positioned opposite to each other; a capacitor structure disposed on the first surface of the semiconductor body and having a first electrode, a second electrode, and a dielectric layer between the first electrode and the second electrode; a redistribution structure disposed on the capacitor structure and having a redistribution layer connected to the first electrode and the second electrode; a through electrode penetrating the semiconductor body and connected to the second electrode; a first pad disposed on the redistribution structure and connected to the first electrode via the redistribution layer; and a second pad disposed on the second surface of the semiconductor body and connected to the second electrode via the through electrode. Attached Figure Description

[0009] The above and other aspects, features, and advantages of the present invention will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a schematic side cross-sectional view of a semiconductor package according to an example embodiment; Figure 2 It is shown schematically. Figure 1 A plan view of a semiconductor package; Figure 3 It is shown schematically. Figure 1 A cross-sectional view of region "A" of the semiconductor package; Figure 4A It is a schematic illustration of embedding in Figure 1 A side cross-sectional view of an example of a semiconductor-based chip capacitor in a coreless circuit board, and Figure 4B It is shown schematically. Figure 4A A magnified view of region "B" of a semiconductor-based chip capacitor; Figure 5 This is a schematic side cross-sectional view of a semiconductor package according to an example embodiment; Figure 6 It is shown schematically. Figure 5 A plan view of a semiconductor package; Figure 7 This is a schematic side cross-sectional view of a semiconductor package according to an example embodiment; Figure 8 It is shown schematically. Figure 7 A plan view of a semiconductor package; Figure 9 It is a schematic illustration of embedding in Figure 7 A side cross-sectional view of a semiconductor bridge in a coreless circuit board; Figure 10 This is a cross-sectional view illustrating an example of a semiconductor bridge that can be used in a semiconductor package according to an exemplary embodiment; Figures 11A to 11H This is a cross-sectional view illustrating the main processes in a method of manufacturing a semiconductor package according to an example embodiment; and Figures 12A to 12C This is a cross-sectional view illustrating the main process of a method for manufacturing a semiconductor package according to an example embodiment. Detailed Implementation

[0010] In the following description, exemplary embodiments will be referenced in the accompanying drawings. The same reference numerals always denote the same elements.

[0011] It will be understood that when an element is referred to as being “connected” or “coupled” to another element or “on” another element, it may be directly connected or coupled to that other element or directly on that other element, or there may be intermediate elements. Conversely, when an element is referred to as being “directly connected” or “directly coupled” to another element, or referred to as being “in contact” with another element or “in contact with” another element (or any form of using the word “in contact”), there are no intermediate elements at the point of contact.

[0012] When referring to orientation, layout, location, shape, size, quantity, or other measure, terms such as “same,” “equal,” “planar,” or “coplanar” as used herein do not necessarily mean exactly the same orientation, layout, location, shape, size, quantity, or other measure, but are intended to cover substantially the same orientation, layout, location, shape, size, quantity, or other measure within acceptable variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to emphasize this meaning unless the context or other statement indicates otherwise.

[0013] Figure 1 This schematically illustrates a cross-sectional side view of a semiconductor package according to an example embodiment, and Figure 2 It is shown Figure 1 A plan view of a semiconductor package. In this case... Figure 1 It can be understood as along Figure 2 A cross-sectional side view of a semiconductor package taken along line I1-I1'.

[0014] Reference Figure 1 and Figure 2 The semiconductor package 500 according to the example embodiment may include a coreless circuit board 100 and a semiconductor chip 300 mounted on the coreless circuit board 100. The coreless circuit board 100 has a plurality of semiconductor-based chip capacitors 200A, 200B, 200C and 200D embedded therein.

[0015] In this embodiment, the coreless circuit board 100 may include an insulating member 110 having multiple insulating layers 110a to 110j, and multiple wiring layers 150 respectively disposed on the multiple insulating layers 110a to 110j. The multiple wiring layers 150 may include interconnecting through-holes 150V connected to adjacent wiring layers 150.

[0016] The coreless circuit board 100 can be an embedded trace substrate (ETS) formed by a build-up process. Interconnect passes 150V of the plurality of wiring layers 150 can have a width that narrows towards the upper surface of the coreless circuit board 100 along a single build-up direction. For example, the interconnect passes 150V can gradually narrow in the direction towards the upper surface of the coreless circuit board 100. Furthermore, the coreless circuit board 100 does not include a core layer containing reinforcing material (such as nonwoven glass fiber cloth or aramid fiber) to reduce the overall thickness of the semiconductor package 500.

[0017] Each of the plurality of insulating layers 110a to 110j may be formed of or comprise an insulating resin. The insulating resin may include a thermosetting resin such as epoxy resin or a thermoplastic resin such as polyimide. For example, each of the plurality of insulating layers 110a to 110j may include a photosensitive resin, such as prepreg, ABF, flame retardant 4 (FR-4), bismaleimide triazine (BT), or photoimageable dielectric (PID).

[0018] Multiple wiring layers 150 may be formed of or comprise a metallic material including, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Interconnect pass-throughs 150V may similarly comprise metallic materials comprising copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Interconnect pass-throughs 150V are shown as filled pass-throughs, wherein metallic material is filled within the vias of each insulating layer; however, in some embodiments, interconnect pass-throughs 150V may have a conformal pass-through shape, wherein metallic material is formed along the inner wall of the via. In some embodiments, interconnect pass-throughs 150V may have an integral structure formed by a plating process together with the wiring layers 150.

[0019] The coreless circuit board 100 may include a plurality of cavities C1, C2, C3, and C4 formed in an insulating member 110. In this embodiment, four cavities C1, C2, C3, and C4 may be disposed at the same level along horizontal directions D1 and D2 of the coreless circuit board 100. The four cavities C1, C2, C3, and C4 may be provided with depths corresponding to a portion of the uppermost insulating layer 110a and the two next-highest insulating layers 110b and 110C. The inventive concept is not limited thereto; depending on the dimensions of the chip capacitors 200A, 200B, 200C, and 200D, cavities C1, C2, C3, and C4 may have depths corresponding to one to four insulating layers. Furthermore, although the four cavities C1, C2, C3, and C4 are exemplified as having the same depth at the same level, in some embodiments, some cavities may have different depths or be located at different levels (see Figure 5 and Figure 7 ).

[0020] In this embodiment, each of the plurality of cavities C1, C2, C3, and C4 may have an opening facing the lower surface of the coreless circuit board 100. A plurality of semiconductor-based chip capacitors 200A, 200B, 200C, and 200D may be disposed in the plurality of cavities C1, C2, C3, and C4, respectively.

[0021] Figure 3 It is shown Figure 1 An enlarged cross-sectional view of region "A" of the semiconductor package.

[0022] Combination Figure 1 and Figure 2 Reference Figure 3 The space surrounding the surface-mount capacitors 200A, 200B, 200C, and 200D in cavities C1, C2, C3, and C4 may include a filler material. After the surface-mount capacitors 200A, 200B, 200C, and 200D are installed, the filler material may be applied to the remaining space in cavities C1, C2, C3, and C4. For example, the filler material may include Ajinomoto laminated film (ABF).

[0023] In this embodiment, insulating layer 110d, which covers cavities C1, C2, C3, and C4 among the plurality of insulating layers 110a to 110j, can fill a portion of the remaining space in cavities C1, C2, C3, and C4 through which the chip capacitors 200A, 200B, 200C, and 200D are disposed, is located. For example, insulating layer 110d may have a portion (110d_E) that fills a portion of the space along the side of the chip capacitor 200A. Each of cavities C2 to C4 may also have a portion 110d_E that fills a portion of the space along the side of the respective chip capacitors 200B to 200D. Furthermore, the remaining portion of each of cavities C1, C2, C3, and C4 may be filled with filler material 120. Filler material 120 may include ABF material.

[0024] In this embodiment, four cavities C1, C2, C3, and C4 can be disposed in the upper region of the coreless circuit board 100. Chip capacitors 200A, 200B, 200C, and 200D can be mounted in the four cavities C1, C2, C3, and C4, respectively, and disposed adjacent to the semiconductor chip 300. This arrangement can improve power integrity characteristics.

[0025] In this embodiment, the surface-mount capacitors 200A, 200B, 200C, and 200D can have a double-sided pad structure. For example, the first pad 270 and the second pad 280 can be respectively disposed on the upper and lower surfaces of the surface-mount capacitors 200A, 200B, 200C, and 200D. The first pad 270 can be connected to the uppermost wiring layer 150 within the insulating layer 110a that provides the lower surfaces of cavities C1, C2, C3, and C4, and the second pad 280 can be connected to the wiring layer 150 on the insulating layer 110d that covers cavities C1, C2, C3, and C4.

[0026] like Figure 1 and Figure 3As shown, the uppermost wiring layer 150 within the insulating layer 110a can be disposed between the semiconductor-based chip capacitor 200A and the semiconductor chip 300. The uppermost wiring layer 150 may include a planar pattern 150P for pads. The planar pattern 150P for pads can be arranged to correspond to the chip pads 350 of the semiconductor chip 300, respectively. The chip pads 350 of the semiconductor chip 300 can be connected to the upper surface of the planar pattern 150P for pads via a second conductive bump 390. The first pads 270 of the chip capacitors 200A, 200B, 200C, and 200D can be connected to the lower surface of the planar pattern 150P for pads located in cavities C1, C2, C3, and C4 within the planar pattern 150P for pads via the first conductive bump 290. For example, the first conductive bump 290 can contact the upper surface of the first pad 270 and the lower surface of the planar pattern 150P for pads. In this way, since the electrical path between the semiconductor-based chip capacitors 200A, 200B, 200C and 200D and the semiconductor chip 300 is greatly shortened, excellent power integrity (PI) characteristics can be ensured.

[0027] Furthermore, unlike the connection method of the first pad 270, the second pad 280 can be directly connected to the wiring layer 150 on the insulating layer 110d of the covering cavities C1, C2, C3, and C4, as well as the interconnecting through-holes 150V that penetrate the insulating layer 110d. For example, the second pad 280 can contact the interconnecting through-holes 150V that penetrate the insulating layer 110d. In this way, the semiconductor-based chip capacitors 200A, 200B, 200C, and 200D can have increased freedom in connecting to the wiring layer 150 of the coreless circuit board 100.

[0028] In the following text, reference will be made to Figure 4A and Figure 4B This section describes an example of a detailed configuration of the semiconductor-based chip capacitor used in this embodiment.

[0029] Figure 4A Is shown embedded in Figure 1 A cross-sectional view of an example of a semiconductor-based chip capacitor in a coreless circuit board. Figure 4B It is shown Figure 4A An enlarged view of part "B" of a semiconductor-based chip capacitor.

[0030] Reference Figure 4A and Figure 4B as well as Figure 3In this embodiment, each of the semiconductor-based chip capacitors 200A, 200B, 200C, and 200D may include: a semiconductor body 210 having a first surface 210A and a second surface 210B positioned opposite each other; a capacitor structure 230 on the first surface 210A of the semiconductor body 210; and a redistribution structure 240 on the capacitor structure 230. In the semiconductor package 500, the chip capacitors 200A, 200B, 200C, and 200D may be configured such that the first surface 210A of the semiconductor body 210 faces the upper surface of the coreless circuit substrate 100 (or the semiconductor chip 300). For example, the semiconductor body 210 may be a silicon substrate.

[0031] In this embodiment, the rigidity of the coreless circuit board 100 can be enhanced by embedding semiconductor-based chip capacitors 200A, 200B, 200C, and 200D with relatively high rigidity instead of a core layer. As described above, the semiconductor-based chip capacitors 200A, 200B, 200C, and 200D can be arranged non-overlapping and widely distributed in the horizontal directions D1 and D2 at the same level on the coreless circuit board 100, thereby more effectively enhancing the rigidity of the coreless circuit board 100.

[0032] Furthermore, the capacitor structure 230 may include a first electrode 232 and a second electrode 236, as well as a dielectric layer 235 between the first electrode 232 and the second electrode 236. In this embodiment, the capacitor structure 230 may include a capacitor CAP with a trench structure disposed within an interlayer insulating layer 239. The interlayer insulating layer 239 may completely surround the trench structure capacitor CAP. Thus, unlike conventional ceramic multilayer capacitors, the chip capacitors 200A, 200B, 200C, and 200D used in this embodiment have relatively small thicknesses, allowing for enhanced rigidity without significantly increasing the thickness of the coreless circuit board 100. For example, the thickness T of the semiconductor-based chip capacitors 200A, 200B, 200C, and 200D may be in the range of 20 μm to 70 μm. The thickness T of the semiconductor-based chip capacitors 200A, 200B, 200C, and 200D may be the thickness measured from the bottom surface of the second pad 280 to the top surface of the first pad 270.

[0033] Reference Figure 4A and Figure 4BA trench-structured capacitor CAP is disposed on a first surface 210A of a semiconductor body 210 and may include a substrate insulating layer 234 having a plurality of trenches TR. A first electrode 232 and a second electrode 236 respectively include a first internal electrode 232E and a second internal electrode 236E, which are conformally formed along the surfaces within the trenches TR of the substrate insulating layer 234, and a dielectric layer 235 may be disposed between the first internal electrode 232E and the second internal electrode 236E. The first electrode 232 includes a first pad electrode 232P disposed on the lower surface of the substrate insulating layer 234, and the first pad electrode 232P can be connected to the first internal electrode 232E through the bottom of the trenches TR. The second electrode 236 includes a second pad electrode 236P connected to the second internal electrode 236E on the substrate insulating layer 234, and the second pad electrode 236P may be configured to fill the interior of the trenches TR. An insulating layer 239 may surround the capacitor CAP. In an example embodiment, the insulating layer 239 may contact the capacitor CAP.

[0034] The redistribution structure 240 may include a redistribution insulating layer 241 and a redistribution layer 245 within the redistribution insulating layer 241. The redistribution layer 245 includes a redistribution pattern 242 and a redistribution through-hole 243, and may be configured to provide a first path to a first pad 270 and a second path to a second pad 280. In this embodiment, the second path of the redistribution layer 245 may be connected to the first pad electrode 232P via the redistribution pattern 242A through the first through-hole V1, and the first path of the redistribution layer 245 may be connected to the second pad electrode 236P via the redistribution pattern 242B through the second through-hole V2.

[0035] A first passivation film 261 with an open redistribution pattern contact area is formed on the redistribution structure 240. A first pad 270 is formed on the first passivation film 261 and can be connected to a first path of the redistribution layer 245 through the contact area of ​​the redistribution pattern. Simultaneously, the semiconductor-based chip capacitor 200A includes a through electrode 215 penetrating the semiconductor body 210, and the through electrode 215 can be connected to a second path of the redistribution layer 245. On the second surface of the semiconductor body 210, a second passivation film 262 is formed as part of the open through electrode 215, and a second pad 280 is formed on the second passivation film 262 and can be connected to a second path of the redistribution layer 245 through the through electrode 215.

[0036] Thus, the semiconductor-based chip capacitor 200A used in this embodiment can have a dual-sided pad structure, which has a first pad 270 and a second pad 280.

[0037] In this embodiment, the first pad 270 is connected to the second electrode 236 of the capacitor CAP through the first path of the redistribution layer 245, and the second pad 280 is connected to the first electrode 232 of the capacitor CAP through the second path of the through electrode 215 and the redistribution layer 245. However, this is not the only embodiment. In some embodiments, the path of the redistribution layer 245 may be reconfigured such that at least some of the first pads 270 disposed on the upper surface are connected to the first electrode 232 of the capacitor CAP, and at least some of the second pads 280 disposed on the lower surface may be connected to the second electrode 236 of the capacitor CAP.

[0038] A first passivation layer 160 is disposed on the upper surface of the coreless circuit substrate 100, and the first passivation layer 160 may be formed as an area for open mounting of the semiconductor chip 300. An underfill resin 320 may be disposed in the space between the coreless circuit substrate 100 and the semiconductor chip 300. For example, the underfill resin 320 may be formed around a second conductive bump 390 surrounding a connecting chip pad 350 and a planar pattern 150P for the pad. The underfill resin 320 may comprise a polymer material such as epoxy resin.

[0039] A second passivation layer 170 is disposed on the lower surface of the coreless circuit board 100, and the second passivation layer 170 may have multiple openings that open the contact area of ​​the lowermost redistribution layer 150L. A bump under metal (UBM) layer 180 connected to the contact area can be formed through the multiple openings. External connection conductors 190 may be formed on the UBM layer 180.

[0040] Figure 5 This schematically illustrates a side cross-sectional view of a semiconductor package according to an example embodiment, and Figure 6 It is shown Figure 5 A plan view of a semiconductor package. In this case... Figure 5 This can be understood as cutting along line I2-I2'. Figure 6 A side cross-sectional view taken from a semiconductor package.

[0041] Reference Figure 5 and Figure 6 In addition to multiple semiconductor-based chip capacitors 200A1, 200B1, 200C1, 200D1, 200A2, 200B2, 200C2, and 200D2 being disposed at different levels on the coreless circuit board 100, the semiconductor package 500A according to this embodiment can be understood to have the same characteristics as... Figures 1 to 3 The semiconductor package 500 shown has a similar structure. Furthermore, unless otherwise described, it can be understood by referring to... Figures 1 to 3The components of this embodiment are understood by describing the same or similar components as those in the semiconductor package 500 shown.

[0042] In this embodiment, the multiple cavities can be divided into a first group of cavities C1a, C2a, C3a and C4a located at a first level of the coreless circuit substrate 100, and a second group of cavities C1b, C2b, C3b and C4b located at a second level of the coreless circuit substrate 100 that is lower than the first level. Similar to the previous embodiments, the first level can be located in the upper region adjacent to the semiconductor chip 300.

[0043] The first group of surface-mount capacitors 200A1, 200B1, 200C1, and 200D1 can be installed in cavities C1a, C2a, C3a, and C4a of the first group, respectively, and the second group of surface-mount capacitors 200A2, 200B2, 200C2, and 200D2 can be installed in cavities C1b, C2b, C3b, and C4b of the second group, respectively. Each of the first group of surface-mount capacitors 200A1, 200B1, 200C1, and 200D1, and the second group of surface-mount capacitors 200A2, 200B2, 200C2, and 200D2, can be substantially the same as the surface-mount capacitors 200A, 200B, 200C, and 200D.

[0044] First, the first group of chip capacitors 200A1, 200B1, 200C1, and 200D1 can be connected to the lower surface of the planar pattern 150P for pads via a first conductive bump 290. The planar pattern 150P for pads is the uppermost wiring layer exposed through the cavity. The chip pads 350 of the semiconductor chip 300 can be connected to the upper surface of the planar pattern 150P for pads via a second conductive bump 390.

[0045] In this way, the electrical path between the first group of chip capacitors 200A1, 200B1, 200C1 and 200D1 and the semiconductor chip 300 is greatly shortened, which ensures excellent power integrity (PI) characteristics.

[0046] The second pad 280 can be directly connected to the interconnect 150V that penetrates the insulating layer 110d, which covers cavities C1a, C2a, C3a, and C4a on the wiring layer 150. In this way, the first group of chip capacitors 200A1, 200B1, 200C1, and 200D1 can have increased flexibility in connecting to the wiring layer 150 of the coreless circuit board 100.

[0047] In this embodiment, the second group of surface-mount capacitors 200A2, 200B2, 200C2, and 200D2 can be mounted at a second level, which is lower than the first level of the first group of surface-mount capacitors 200A1, 200B1, 200C1, and 200D1. The second group of surface-mount capacitors 200A2, 200B2, 200C2, and 200D2 can be connected to the wiring layer 150 in a similar manner to the first group of surface-mount capacitors 200A1, 200B1, 200C1, and 200D1. The first pads 270 of the second group of chip capacitors 200A2, 200B2, 200C2, and 200D2 are connected to the exposed wiring layer 150 on the bottom of the cavities C1b, C2b, C3b, and C4b of the second group via first conductive bumps 290. The second pads 280 of the second group of chip capacitors 200A2, 200B2, 200C2, and 200D2 are partially covered by the insulating layer 100h covering the cavities C1b, C2b, C3b, and C4b of the second group. The wiring layer on the insulating layer 100h can be connected to the second pads 280 of the second group of chip capacitors 200A2, 200B2, 200C2, and 200D2 via interconnecting through-holes 150V penetrating the insulating layer 100h.

[0048] In this embodiment, the rigidity of the coreless circuit board 100 can be enhanced by embedding the first group of chip capacitors 200A1, 200B1, 200C1, and 200D1 and the second group of chip capacitors 200A2, 200B2, 200C2, and 200D2 at different levels within the coreless circuit board 100. The first group of chip capacitors 200A1, 200B1, 200C1, and 200D1 and the second group of chip capacitors 200A2, 200B2, 200C2, and 200D2 can be arranged so that they do not overlap in the horizontal directions D1 and D2 at the corresponding levels, and can be arranged so that they do not completely overlap with each other in the thickness direction D3 of the coreless circuit board 100 to enhance the rigidity enhancement effect.

[0049] Figure 7 This schematically illustrates a side cross-sectional view of a semiconductor package according to an example embodiment, and Figure 8 It is shown Figure 7 A plan view of a semiconductor package. In this case... Figure 7 It can be understood as along Figure 8 A side cross-sectional view of the semiconductor package taken from line I3-I3'.

[0050] Reference Figure 7 and Figure 8Except that the semiconductor bridge 400 is disposed at a higher level on the coreless circuit board 100, and the plurality of semiconductor-based chip capacitors 200A', 200B', 200C' and 200D' are disposed at a lower level, the semiconductor package 500B according to this embodiment can be understood to have the same characteristics as... Figures 1 to 3 The semiconductor package 500 shown has a similar structure. Furthermore, unless otherwise specifically described, it can be understood by referring to... Figures 1 to 3 The components of this embodiment are understood by describing the same or similar components as those in the semiconductor package 500 shown.

[0051] The semiconductor package 500B according to this embodiment may include a first semiconductor chip 300A and a second semiconductor chip 300B. The first semiconductor chip 300A and the second semiconductor chip 300B may be interconnected via a semiconductor bridge 400 embedded adjacent to the upper surface of the coreless circuit board 100. The semiconductor bridge 400 may be disposed in a cavity C adjacent to the upper surface of the coreless circuit board 100. The first pad 470 of the semiconductor bridge 400 may be connected to the lower surface of a planar pattern 150P for the pad via a first conductive bump 490, the planar pattern 150P for the pad being the uppermost wiring layer open by the cavity C. The chip pads 350 of the first semiconductor chip 300A and the second semiconductor chip 300B may be connected to the upper surface of the planar pattern 150P for the pad via a second conductive bump 390.

[0052] Figure 9 Is shown embedded in Figure 7 A cross-sectional side view of a semiconductor bridge in a circuit board.

[0053] Reference Figure 9 The semiconductor bridge 400 may include a semiconductor body 410 and an interconnect structure 440 disposed on the upper surface of the semiconductor body 410. The interconnect structure 440 may include an insulating layer 441 and a redistribution layer 445 within the insulating layer 441. The redistribution layer 445 includes a redistribution pattern 442 and redistribution through-holes 443 connecting the redistribution pattern, and may be configured to interconnect a first semiconductor chip 300A and a second semiconductor chip 300B. Therefore, the interconnect structure 440 may be provided as a signal path for the interconnection of the first semiconductor chip 300A and the second semiconductor chip 300B.

[0054] The semiconductor bridge 400 used in this embodiment may include first pads 470 aligned only on a cross-section (e.g., the upper surface). The first pads 470 may be disposed on a passivation film 461 and may be connected to contact areas of the redistribution layer 445. Similar to semiconductor-based chip capacitors 200A', 200B', 200C', and 200D', the semiconductor bridge 400 may include a semiconductor body 410 with relatively high rigidity, such as silicon, and thus may help enhance the rigidity of the coreless circuit board 100 used in this embodiment.

[0055] In this embodiment, the coreless circuit board 100 may include multiple (e.g., four) cavities C1', C2', C3', and C4' located at a level lower than cavity C. Semiconductor-based chip capacitors 200A', 200B', 200C', and 200D' may be mounted at a level lower than semiconductor bridge 400. Semiconductor-based chip capacitors 200A', 200B', 200C', and 200D' may be connected to wiring layer 150 in a manner similar to that in previous embodiments. The first pads 270 of the semiconductor-based chip capacitors 200A', 200B', 200C', and 200D' are connected via first conductive bumps 290 to wiring layers 150 exposed on the bottom of cavities C1', C2', C3', and C4'. The second pads 280 of the semiconductor-based chip capacitors 200A', 200B', 200C', and 200D' are partially covered by insulating layers 100h covering cavities C1', C2', C3', and C4'. The wiring layers on the insulating layers 100h can be connected to the second pads 280 of the semiconductor-based chip capacitors 200A', 200B', 200C', and 200D' via interconnecting through-holes 150V penetrating the insulating layers 100h. In this embodiment, at least some of the semiconductor-based chip capacitors 200A', 200B', 200C' and 200D' can be arranged so as not to overlap with the semiconductor bridge 400 in the thickness direction D3 of the coreless circuit substrate 100, in order to extend the area for enhanced stiffness.

[0056] The semiconductor bridge 400 described in the previous embodiments is exemplified as a single-sided pad structure, but it can be implemented as a double-sided pad structure, similar to a semiconductor-based chip capacitor. Figure 10 This is a cross-sectional side view showing an example of a semiconductor bridge with a double-sided pad structure.

[0057] Reference Figure 10Similar to previous embodiments, the semiconductor bridge 400A according to this embodiment may include a semiconductor body 410 and an interconnect structure 440 disposed on the upper surface of the semiconductor body 410. The interconnect structure 440 may include an insulating layer 441 and a redistribution layer 445 that interconnects the first semiconductor chip 300A and the second semiconductor chip 300B.

[0058] The first passivation film 461 and the second passivation film 462 are respectively disposed on the upper surface of the interconnect structure 440 and the lower surface of the semiconductor body 410. In this embodiment, the semiconductor bridge 400A may include a first pad 470 on the first passivation film 461 and a second pad 480 on the second passivation film 462. Furthermore, the semiconductor bridge 400A may include a through electrode 415 connected to the redistribution layer 445 and penetrating the semiconductor body 410. The first pad 470 can be connected to the redistribution pattern 442 of the interconnect structure 440 via the first passivation film 461, and the second pad 480 can be connected to the through electrode 415 via the second passivation film 462.

[0059] Thus, the semiconductor bridge 400A used in this embodiment has a double-sided pad structure with a first pad 470 and a second pad 480, and can be connected to the wiring layer 150 with a high degree of design freedom by utilizing a double-sided pad structure similar to that of a semiconductor-based chip capacitor.

[0060] Figures 11A to 11G This is a cross-sectional view illustrating the main process of a method for manufacturing a semiconductor package according to an example embodiment. Figures 11A to 11G The cross section corresponds to Figure 1 The following description will focus on the construction shown in each section, which is an example embodiment of the cross-section.

[0061] Reference Figure 11A The planar pattern 150P for the pads can be formed as wiring layers on both sides of the separation carrier film 600.

[0062] The separation carrier film 600 may include a carrier core 610 and copper layers 620 respectively disposed on both sides of the carrier core 610. The copper layers may be used to form a planar pattern 150P for pads using a plating process. The planar pattern 150P for pads may be provided as the uppermost wiring layer of a circuit board and may be pads on which semiconductor chips are mounted. The planar pattern 150P for pads may have an arrangement corresponding to the arrangement of chip pads 350 of the semiconductor chip 300. In some embodiments, the arrangement of the planar pattern 150P for pads may correspond to the arrangement of the first pads 270 of the semiconductor-based chip capacitors 200A to 200D.

[0063] In this embodiment, a process for simultaneously building up a multilayer circuit board from both sides of the separation carrier film 600 is described, but it is not limited thereto, and in some embodiments, a process for building up a multilayer circuit board from only one side of the separation carrier film can be performed.

[0064] Next, refer to Figure 11B After forming an insulating layer 110a covering a planar pattern 150P for pads, some wiring layers 150 and some insulating layers 110b and 110c can be formed.

[0065] After forming insulating layer 110a to cover the planar pattern 150P for pads, layers of a specific thickness can be built into the area where cavities are to be formed. Wiring layers 150 formed on insulating layers 110b and 110c can be designed not to be located in the area where cavities are to be formed. Wiring layers 150 may include interconnecting through-holes 150V connected to another adjacent wiring layer 150. In this stacking process, after forming insulating layers 110a, 110b, and 110c respectively, vias can be formed by using mechanical drilling, laser drilling using a CO2 laser or a YAG laser, or by using a blasting process. Conductive material can then be applied to their interiors by plating or paste printing processes.

[0066] Next, refer to Figure 11C Multiple cavities C1 and C2 can be formed in the insulating layers 110a, 110b and 100c.

[0067] Multiple cavities C1 and C2 may be formed having a depth d that is removed to a portion of the uppermost insulating layer 110a. In an example embodiment, the depth d may correspond to the thickness of one to four insulating layers of the multiple insulating layers 110. The planar pattern 150P for the pads may be exposed through the multiple cavities C1 and C2. For example, cavities C1 and C2 may be formed using mechanical drilling or bombardment processes, but are not limited thereto.

[0068] Next, refer to Figure 11D Semiconductor-based chip capacitors 200A and 200B can be installed in cavities C1 and C2, respectively.

[0069] The first pads 270 of the semiconductor-based chip capacitors 200A and 200B can be connected to the lower surface of the planar pattern 150P for the pads via first conductive bumps 290. In subsequent processes, the semiconductor chip (e.g., Figure 1 The semiconductor chip 300 is connected to the upper surface of the planar pattern 150P for pads, such that the semiconductor-based chip capacitors 200A and 200B are connected to the semiconductor chip (e.g., Figure 1The electrical path between semiconductor chips (300) can be significantly shortened.

[0070] Next, refer to Figure 11E This can form an insulating layer 110d covering the semiconductor-based chip capacitors 200A and 200B within cavities C1 and C2.

[0071] In this process, before forming the insulating layer 110d, a filler material 120 can be applied to the remaining space of cavities C1 and C2. For example, the filler material 120 may include ABF material. The insulating layer 110d can then be formed to cover the semiconductor-based chip capacitors 200A and 200B within cavities C1 and C2. In this process, a portion of the remaining space in cavities C1 and C2, where the chip capacitors 200A and 200B are disposed, can be filled through openings in cavities C1 and C2.

[0072] Next, refer to Figure 11F The coreless circuit board 100 can be manufactured by forming other wiring layers 150 and other insulating layers 110e, 110f, 110g, 110h, 110i and 110j.

[0073] First, the wiring layer 150 on the insulating layer 110d can be formed as an interconnect pass-through having a second pad 280 connected to semiconductor-based chip capacitors 200A and 200B.

[0074] Next, the remaining wiring layers 150 and the other insulating layers 110e, 110f, 110g, 110h, 110i, and 110j can be subsequently constructed on insulating layer 110d. Figure 11B The process is similar, and this stacking process can be performed by forming various insulating layers 110e, 110f, 110g, 110h, 110i and 110j, forming vias by using mechanical drilling or laser drilling using a CO2 laser or YAG laser or by using a bombardment process, and then applying conductive material to the interior by a plating process or a paste printing process.

[0075] Next, the coreless circuit board 100 can be separated from the separation carrier film 600. (Refer to...) Figure 11G The image shows a separate coreless circuit board 100.

[0076] A copper layer 620 may be retained on the upper surface of the separate coreless circuit board 100. This copper layer 620 can be removed by an additional etching process, and the desired planar pattern 150P for pads can be opened as the uppermost wiring layer of the coreless circuit board 100. In some embodiments, a surface treatment layer for high-quality bonding may be formed on the planar pattern 150P for pads. The surface treatment layer can be provided by additional plating of a layer such as Au.

[0077] Next, refer to Figure 11H The first passivation layer 160 and the second passivation layer 170 can be formed on the upper and lower surfaces of the coreless circuit substrate 100, respectively. In the first passivation layer 160, openings are formed to open a planar pattern 150P for mounting semiconductor chips on pads. In the second passivation layer 170, multiple openings are formed to open the contact area of ​​the lowermost redistribution layer 150L, ​​and UBM layers 180 and external connection conductors 190 connected to the contact area can be formed through these multiple openings. Finally, as... Figure 1 As shown, the semiconductor package 500 according to this embodiment can be manufactured by mounting a semiconductor chip.

[0078] Figures 12A to 12C This is a cross-sectional view illustrating the main process of a method for manufacturing a semiconductor package according to an example embodiment. Figures 12A to 12C It can be understood as manufacturing Figure 7 This is part of the process of the method for the semiconductor package 500B shown.

[0079] Reference Figure 12A Cavity C can be formed to have a depth d to which a portion of the uppermost insulating layer 110a is removed. This process can be understood as performing the previous embodiment. Figure 11A and Figure 11B The cavity C is a process performed after the process described above. The cavity C can be formed to have an area corresponding to the size of the semiconductor bridge to be mounted in subsequent processes. A planar pattern 150P for pads can be exposed through the cavity C. For example, mechanical drilling or bombardment processes can be used to form the cavity C, but it is not limited to these methods.

[0080] Next, refer to Figure 12B A semiconductor bridge 400 can be installed in cavity C. The semiconductor bridge 400 can be configured adjacent to the upper surface of the coreless circuit board 100. The first pad 470 of the semiconductor bridge 400 can be connected to the lower surface of the planar pattern 150P for the pad via a first conductive bump 490. The planar pattern 150P for the pad is the uppermost wiring layer open through cavity C.

[0081] Reference Figure 12C After performing additional layering processes, multiple additional cavities C1' and C2' can be formed, and semiconductor-based chip capacitors 200A' and 200B' can be mounted in the corresponding cavities C1' and C2' (see [link to documentation]). Figure 11D Then, an insulating layer 110h can be formed covering the semiconductor-based chip capacitors 200A' and 200B'.

[0082] Additionally, the wiring layer 150 on the insulating layer 110h can be formed as having interconnect through-holes connected to second pads 280 of the semiconductor-based chip capacitors 200A' and 200B'. The remaining wiring layer 150, as well as the insulating layers 110i and 110j, can be additionally constructed on the insulating layer 110h (see [link to documentation]). Figure 11F Next, after separation from the separation carrier membrane 600, the copper layer 620 is removed, forming a first passivation layer 160 and a second passivation layer 170, and a UBM layer 180 / external connection conductor 190 is formed, thereby manufacturing... Figure 7 The semiconductor package shown is 500B.

[0083] As described above, according to the example embodiments described, multiple semiconductor-based chip capacitors can be incorporated into a relatively thin coreless circuit board, thereby reducing the size of the package and increasing its rigidity. In the example embodiments, the semiconductor-based chip capacitors can be embedded at a higher level, thereby shortening the path between the capacitor and the semiconductor chip and thus ensuring power integrity characteristics.

[0084] Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor package, comprising: A coreless circuit board includes an insulating member and multiple wiring layers. The insulating member has multiple insulating layers and multiple cavities. The multiple wiring layers are respectively disposed on the multiple insulating layers and have interconnecting through-holes connected to adjacent wiring layers. At least one semiconductor chip is disposed on the upper surface of the coreless circuit substrate and is electrically connected to the uppermost wiring layer of the plurality of wiring layers. as well as A plurality of semiconductor-based chip capacitors are respectively disposed in the plurality of cavities, and each of the plurality of semiconductor-based chip capacitors has an upper surface on which a first pad is disposed and a lower surface on which a second pad is disposed. The first pad is connected to a first wiring layer adjacent to the first pad in the plurality of wiring layers via a conductive bump, and the second pad is connected to an interconnect pass-through in a second wiring layer adjacent to the second pad in the plurality of wiring layers.

2. The semiconductor package according to claim 1, wherein, The uppermost wiring layer includes a planar pattern for the pads corresponding to the chip pads of the at least one semiconductor chip.

3. The semiconductor package according to claim 2, in, The first wiring layer is provided as the uppermost wiring layer, and The first pads of the plurality of semiconductor-based chip capacitors are respectively connected to the lower surface of the planar pattern for the pads.

4. The semiconductor package according to claim 1, wherein, Each of the plurality of semiconductor-based chip capacitors includes: A semiconductor body having a first surface facing the upper surface of the coreless circuit substrate and a second surface positioned opposite the first surface. A capacitor structure having a first electrode and a second electrode on the first surface of the semiconductor body, and a dielectric layer between the first electrode and the second electrode. A redistribution structure having a redistribution layer connected to the first electrode and the second electrode on the capacitor structure, and A through electrode that penetrates the semiconductor body and connects to the second electrode.

5. The semiconductor package according to claim 4, in, The capacitor structure includes a substrate insulating layer disposed on the first surface of the semiconductor body and having a plurality of trenches. The first electrode, the second electrode, and the dielectric layer are disposed along the surface of the plurality of trenches.

6. The semiconductor package according to claim 4, in, The first pad is electrically connected to the first electrode on the redistribution structure via the redistribution layer, and The second pad is electrically connected to the second electrode on the second surface of the semiconductor body via the through electrode.

7. The semiconductor package according to claim 1, wherein, The interconnecting through-holes of the multiple wiring layers have a width that narrows toward the upper surface of the coreless circuit board.

8. The semiconductor package according to claim 1, wherein, Each of the plurality of cavities has a depth corresponding to the thickness of one to four of the plurality of insulating layers.

9. The semiconductor package according to claim 1, in, Each of the plurality of cavities has an opening facing the lower surface of the coreless circuit board, and In this plurality of insulating layers, the insulating layer having the second wiring layer fills at least a portion of the plurality of cavities.

10. The semiconductor package according to claim 1, wherein, The plurality of semiconductor-based chip capacitors include a first chip capacitor located at a first level of the coreless circuit board and a second chip capacitor located at a second level of the coreless circuit board that is lower than the first level.

11. The semiconductor package of claim 10, wherein, At least some of the first chip capacitors are arranged so that they do not overlap with the second chip capacitor in the thickness direction of the coreless circuit board.

12. The semiconductor package according to claim 1, in, The at least one semiconductor chip includes a first semiconductor chip and a second semiconductor chip. The semiconductor package further includes a semiconductor bridge embedded in the coreless circuit substrate and has an interconnect wiring layer that electrically connects the first semiconductor chip and the second semiconductor chip.

13. The semiconductor package according to claim 12, wherein, At least a portion of each of the plurality of semiconductor-based chip capacitors is configured not to overlap with the semiconductor bridge in the thickness direction of the coreless circuit substrate.

14. A semiconductor package, comprising: A coreless circuit board includes an insulating member having multiple insulating layers and multiple wiring layers respectively disposed on the multiple insulating layers, wherein the uppermost wiring layer of the multiple wiring layers includes a planar pattern for pads, and each of the multiple wiring layers except the uppermost wiring layer has an interconnecting through-hole connected to another adjacent wiring layer. A semiconductor chip disposed on the upper surface of the coreless circuit substrate and electrically connected to the planar pattern for pads of the uppermost wiring layer; as well as A plurality of semiconductor-based chip capacitors are embedded in the coreless circuit board, and each of the plurality of semiconductor-based chip capacitors has an upper surface on which a first pad is disposed and a lower surface on which a second pad is disposed. The first pad is connected to the lower surface of the planar pattern for the pad in the uppermost wiring layer, and the second pad is connected to the interconnection pass-through of the wiring layer adjacent to the second pad in the plurality of wiring layers.

15. The semiconductor package of claim 14, wherein, The interconnecting through-holes of the multiple wiring layers have a width that narrows toward the upper surface of the coreless circuit board.

16. The semiconductor package of claim 14, wherein, The multiple insulating layers comprise the same insulating material.

17. The semiconductor package of claim 14, wherein, Each of the plurality of semiconductor-based chip capacitors has a thickness in the range of 20 μm to 70 μm.

18. A semiconductor package, comprising: A coreless circuit board includes an insulating member having multiple insulating layers and multiple wiring layers respectively disposed on the multiple insulating layers, wherein the uppermost wiring layer of the multiple wiring layers includes a planar pattern for pads, and each of the multiple wiring layers except the uppermost wiring layer has an interconnecting through-hole connected to another adjacent wiring layer. Multiple semiconductor chips are disposed on the upper surface of the coreless circuit substrate and electrically connected to the planar pattern for pads of the uppermost wiring layer; A semiconductor bridge is embedded in the coreless circuit substrate and has an interconnect wiring layer that electrically connects the plurality of semiconductor chips. as well as Multiple semiconductor-based chip capacitors are embedded in the coreless circuit board and have an upper surface on which a first pad is disposed and a lower surface on which a second pad is disposed. The first pad is connected to a first wiring layer adjacent to the first pad in the plurality of wiring layers via a first conductive bump, and the second pad is connected to an interconnect pass-through of a second wiring layer adjacent to the second pad in the plurality of wiring layers.

19. The semiconductor package according to claim 18, in, The semiconductor bridge includes connection pads on the interconnect wiring layer, and The connecting pads are connected to the lower surface of the planar pattern for the pads via second conductive bumps.

20. The semiconductor package of claim 18, wherein, At least some of the plurality of semiconductor-based chip capacitors are arranged so as not to overlap with the semiconductor bridge in the thickness direction of the coreless circuit substrate.

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