Light emitting diode and manufacturing method thereof
By covering the sidewalls of the epitaxial layer of a Micro LED with a highly aluminum-doped P-type semiconductor layer to form an energy wall, the non-radiative recombination problem caused by damage to the sidewalls of the step in the micro LED is solved, improving the internal quantum efficiency and luminous efficiency, and enhancing the crystal quality and overall performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HC SEMITEK (SUZHOU) CO LTD
- Filing Date
- 2026-02-12
- Publication Date
- 2026-05-12
AI Technical Summary
In micro LEDs, the ratio of the area to volume of the stepped sidewalls in the epitaxial layer increases dramatically, causing sidewall damage defects caused by mesa etching to become the main centers for nonradiative recombination of charge carriers, resulting in a sharp decrease in internal quantum efficiency and a reduction in luminous efficiency.
A highly aluminum-doped P-type semiconductor layer is covered on the stepped sidewall of the epitaxial layer as a sidewall barrier layer. A wide-bandgap semiconductor is formed by epitaxial growth technology to form an energy wall, which restricts the movement of charge carriers and promotes their recombination in the active region.
It effectively reduces nonradiative recombination, improves internal quantum efficiency and luminous efficiency, enhances crystal quality, and improves the overall performance of light-emitting diodes through band confinement and electrical blocking effects.
Smart Images
Figure CN122028562A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of light-emitting devices, and in particular to a light-emitting diode and a method for manufacturing the same. Background Technology
[0002] A light-emitting diode (LED) chip is a semiconductor electronic component that emits light. As a highly efficient, environmentally friendly, and green new type of solid-state lighting source, it is being rapidly and widely used in applications such as traffic lights, automotive interior and exterior lights, urban landscape lighting, and mobile phone backlights.
[0003] The main structure of a light-emitting diode is an epitaxial layer, which includes stacked N-type semiconductor layers, multiple quantum well layers, and P-type semiconductor layers. The epitaxial layer has steps extending from the P-type semiconductor layer to the N-type semiconductor layer.
[0004] For micro light-emitting diodes, due to the miniaturization design, the ratio of the sidewall area of the steps in the epitaxial layer to the volume of the entire epitaxial layer increases dramatically. The sidewall damage defects caused by mesa etching become the main centers for nonradiative recombination of charge carriers, resulting in a sharp decrease in internal quantum efficiency, which in turn reduces luminous efficiency. Summary of the Invention
[0005] This disclosure provides a light-emitting diode and a method for manufacturing the same, which can reduce non-radiative recombination and improve luminous efficiency. The technical solution is as follows: On one hand, a light-emitting diode is provided, the light-emitting diode comprising: an epitaxial layer and a sidewall barrier layer; The epitaxial layer includes an N-type semiconductor layer, a multiple quantum well layer, and a P-type semiconductor layer. The multiple quantum well layer is located between the N-type semiconductor layer and the P-type semiconductor layer. The epitaxial layer includes a step, the top surface of which is located on the P-type semiconductor layer, the bottom surface of which is located on the N-type semiconductor layer, and the sidewall of which extends from the P-type semiconductor layer to the N-type semiconductor layer. The sidewall barrier layer covers the sidewall of the step, and the sidewall barrier layer is a highly aluminum-doped P-type semiconductor layer.
[0006] Optionally, the sidewall barrier layer is an Al-doped P-type GaN layer, wherein the Al content is 0.35~0.45.
[0007] Optionally, the thickness of the sidewall barrier layer is 30~70nm.
[0008] Optionally, the p-type dopant in the sidewall barrier layer is Mg, and the Mg doping concentration is 4E19~8E19 cm⁻¹. -3 .
[0009] Optionally, the sidewall barrier layer is grown using an epitaxial growth method, wherein the V / III ratio is greater than 4000 and the growth rate is 0.2~0.4 μm / h.
[0010] On the other hand, a method for manufacturing a light-emitting diode is provided, the method comprising: An epitaxial layer is grown, the epitaxial layer comprising an N-type semiconductor layer, a multiple quantum well layer and a P-type semiconductor layer, wherein the multiple quantum well layer is located between the N-type semiconductor layer and the P-type semiconductor layer; The epitaxial layer is patterned to form a step, the top surface of the step is located on the P-type semiconductor layer, the bottom surface of the step is located on the N-type semiconductor layer, and the sidewall of the step extends from the P-type semiconductor layer to the N-type semiconductor layer. A sidewall barrier layer is fabricated to cover the step, wherein the sidewall barrier layer is a highly aluminum-doped P-type semiconductor layer; The sidewall blocking layer is graphically processed to remove the sidewall blocking layer from the top and bottom surfaces of the step, so that the sidewall blocking layer covers the sidewall of the step.
[0011] Optionally, the sidewall barrier layer is an Al-doped P-type GaN layer, wherein the Al content is 0.35~0.45.
[0012] Optionally, a sidewall barrier layer covering the step is fabricated, comprising: Al-doped P-type GaN layers were grown in an MOCVD chamber at a temperature of 930~980℃, with a V / III ratio greater than 4000 and a growth rate of 0.2~0.4 μm / h.
[0013] Optionally, before fabricating the sidewall barrier layer, the method further includes: The steps are pretreated with a TMAH solution, wherein the concentration of the TMAH solution is 2-3 wt%, the solution temperature is 80-90℃, and the treatment time is 10-15 minutes.
[0014] Optionally, before fabricating the sidewall barrier layer, the method further includes: The epitaxial layer is subjected to high-temperature annealing in an MOCVD chamber at a temperature of 930~980℃, with an atmosphere of NH3 and N2 mixture, for a annealing time of 4~8 minutes.
[0015] The beneficial effects of the technical solutions provided in this disclosure are: In this embodiment, by covering the sidewall barrier layer of the epitaxial layer step sidewall, nonradiative recombination centers on the step sidewall are eliminated, thereby reducing nonradiative recombination, improving internal quantum efficiency, and increasing luminescence efficiency. The sidewall barrier layer is an Al-doped P-type GaN layer. The high Al content results in a wide bandgap semiconductor, with a higher conduction band bottom and a lower valence band top compared to a multi-quantum-well layer. This is equivalent to building a high energy wall around the edge of the active region of the multi-quantum-well layer. Thus, electrons moving from the active region to the edge sidewall need to climb a high slope (potential barrier), and holes moving from the active region to the edge sidewall need to jump down a deep pit (also a potential barrier). This energy shield, naturally formed by the energy difference, actively and powerfully pushes electrons and holes back to the center of the active region, forcing them to recombine and emit light in the multi-quantum-well layer. Furthermore, using an Al-doped P-type GaN layer as a defect blocking layer, compared to using materials such as silicon dioxide, not only provides band confinement and electrical blocking but also crystal repair, thus improving the quality of the epitaxial crystal. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 This is a schematic diagram of the structure of a light-emitting diode provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of another light-emitting diode structure provided in an embodiment of this disclosure; Figure 3 This is a flowchart illustrating a method for manufacturing a light-emitting diode according to an embodiment of the present disclosure; Figure 4 This is a flowchart of another method for manufacturing a light-emitting diode provided in this embodiment.
[0018] The attached figures are labeled as follows: 10: Epitaxial layer; 101: N-type semiconductor layer; 102: Multiple quantum wells; 103: P-type semiconductor layer; 110: Step; 120: Isolation trench; 20: Sidewall barrier layer; 30: Current barrier layer; 40: Transparent conductive layer; 50: First electrode; 60: Second electrode; 70: Insulating reflective layer; 701: Through-hole; 80: First pad; 90: Second pad; 100: Substrate. Detailed Implementation
[0019] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.
[0020] Figure 1 This is a schematic diagram of the structure of a light-emitting diode provided in an embodiment of this disclosure. See also... Figure 1 The light-emitting diode includes an epitaxial layer 10 and a sidewall barrier layer 20.
[0021] The epitaxial layer 10 includes an N-type semiconductor layer 101, a multiple quantum well layer 102, and a P-type semiconductor layer 103. The multiple quantum well layer 102 is located between the N-type semiconductor layer 101 and the P-type semiconductor layer 103. The epitaxial layer 10 includes a step 110. The top surface of the step 110 is located on the P-type semiconductor layer 103, the bottom surface of the step 110 is located on the N-type semiconductor layer 101, and the sidewall of the step 110 extends from the P-type semiconductor layer 103 to the N-type semiconductor layer 101.
[0022] The sidewall barrier layer 20 covers the sidewall of the step 110, and the sidewall barrier layer 20 is a highly aluminum-doped P-type semiconductor layer 103.
[0023] In this embodiment, by covering the sidewall barrier layer of the epitaxial layer step sidewall, nonradiative recombination centers on the step sidewall are eliminated, thereby reducing nonradiative recombination, improving internal quantum efficiency, and increasing luminescence efficiency. The sidewall barrier layer is an Al-doped P-type GaN layer. The high Al content results in a wide bandgap semiconductor, with a higher conduction band bottom and a lower valence band top compared to a multi-quantum-well layer. This is equivalent to building a high energy wall around the edge of the active region of the multi-quantum-well layer. Thus, electrons moving from the active region to the edge sidewall need to climb a high slope (potential barrier), and holes moving from the active region to the edge sidewall need to jump down a deep pit (also a potential barrier). This energy shield, naturally formed by the energy difference, actively and powerfully pushes electrons and holes back to the center of the active region, forcing them to recombine and emit light in the multi-quantum-well layer. Furthermore, using an Al-doped P-type GaN layer as a defect blocking layer, compared to using materials such as silicon dioxide, not only provides band confinement and electrical blocking but also crystal repair, thus improving the quality of the epitaxial crystal.
[0024] In this embodiment of the disclosure, the sidewall barrier layer 20 is an Al-doped P-type GaN layer, wherein the Al composition is 0.35~0.45.
[0025] In this implementation, the Al content is at least 0.35, which ensures a high band density in the sidewall barrier layer, thereby limiting the movement of electrons and holes; the Al content is at most 0.45, thus avoiding crystal quality problems caused by excessive Al content.
[0026] For example, the composition of Al is 0.36, 0.40, or 0.42, etc.
[0027] In other embodiments, the Al component can be even higher, and there is no limitation thereto.
[0028] In this embodiment of the disclosure, the N-type semiconductor layer 101 is an N-type GaN layer, the multiple quantum well layer 102 can be an InGaN / GaN superlattice structure, and the P-type semiconductor layer 103 is a P-type GaN layer.
[0029] The N-type GaN layer is a Si-doped GaN layer with a Si doping concentration of 1E19~3E19 cm⁻¹. -3 The thickness of the N-type GaN layer is 1~2μm.
[0030] The multi-quantum well layer 102 comprises an InGaN / GaN superlattice structure with 8 to 15 cycles, wherein the thickness of a single well layer (InGaN) is 20 to 30 angstroms, the thickness of a single barrier layer (GaN) is 90 to 130 angstroms, and the In composition of InGaN is 0.2 to 0.3.
[0031] The p-type GaN layer is a Mg-doped GaN layer with a Mg doping concentration of 5E19~10E19 cm⁻¹. -3 The thickness of the P-type GaN layer is 100~200nm.
[0032] like Figure 1 As shown, the sidewall barrier layer 20 covers the sidewall of the step 110, that is, it covers the N-type semiconductor layer 101, the multiple quantum well layer 102 and the P-type semiconductor layer 103 at the sidewall.
[0033] In this embodiment of the disclosure, the thickness of the sidewall barrier layer 20 is 30~70nm.
[0034] The thickness of the sidewall barrier layer 20 refers to the thickness perpendicular to the sidewall direction.
[0035] In this implementation, for Micro LEDs, the overall volume of the epitaxial layer is relatively small. On this basis, a sidewall barrier layer with a thickness of 30~70nm is set. On the one hand, it can ensure its barrier function, and on the other hand, it will not affect the overall volume of the epitaxial layer due to excessive thickness.
[0036] like Figure 1 As shown, the thickness of the sidewall barrier layer 20 remains uniform.
[0037] For example, the thickness of the sidewall barrier layer 20 is 40, 50 or 60 nm.
[0038] In other embodiments, the thickness of the sidewall barrier layer 20 may also vary, for example, gradually decreasing in thickness from the N-type semiconductor layer 101 to the P-type semiconductor layer 103.
[0039] In one example, step 110 is a ring of steps along the edge of the extension layer 10, and the sidewall barrier layer 20 is also a ring structure covering the outer wall of step 110.
[0040] In another example, step 110 is a groove opened on the epitaxial layer 10, and the sidewall barrier layer 20 is also an annular structure covering the inner sidewall of step 110.
[0041] In another example, step 110 is a notch on one side of the extension layer 10, and the sidewall barrier layer 20 is also an open structure covering the inner sidewall of step 110.
[0042] In this embodiment, the p-type dopant in the sidewall barrier layer 20 is Mg, and the Mg doping concentration is 4E19~8E19 cm⁻¹. -3 .
[0043] For example, the Mg doping concentration in the sidewall barrier layer 20 is 5E19cm⁻¹. -3 .
[0044] In this embodiment of the present disclosure, the sidewall barrier layer 20 is grown by epitaxial growth, and the V / III ratio of the sidewall barrier layer 20 is greater than 4000 during growth, and the growth rate is 0.2~0.4μm / h.
[0045] For example, the V / III ratio of the sidewall barrier layer 20 is 5000 and the growth rate is 0.3 μm / h.
[0046] In this implementation, the above-mentioned doping concentration, V / III ratio and growth rate are used in order to improve the growth quality and ensure that the energy band of the sidewall barrier layer is high.
[0047] In this embodiment, the sidewall barrier layer 20 is epitaxially grown, that is, a film grown using a metal-organic chemical vapor deposition (MOCVD) device. Epitaxial growth can repair crystal defects in the steps.
[0048] In this embodiment, after etching, the step 110 of the epitaxial layer 10 undergoes surface pretreatment to repair defects and provide a suitable surface for the sidewall barrier layer. A suitable surface can refer to a surface with atomic-level cleanliness and appropriate stoichiometry.
[0049] In this embodiment of the disclosure, the step 110 of the epitaxial layer 10 undergoes high-temperature annealing after pretreatment. High-temperature annealing repairs surface lattice defects and reduces nitrogen vacancies, thereby improving the environment for the subsequent growth of a high-quality sidewall barrier layer.
[0050] Figure 2 This is a schematic diagram of another light-emitting diode provided in an embodiment of this disclosure. See also... Figure 2 The light-emitting diode may also include a current blocking layer 30 and a transparent conductive layer 40.
[0051] The current blocking layer 30 is located on the surface of the epitaxial layer 10, and the transparent conductive layer 40 is located on the surface of the epitaxial layer 10 and covers the current blocking layer 30.
[0052] Optionally, the light-emitting diode further includes a first electrode 50 and a second electrode 60, the first electrode 50 being located on the current blocking layer 30 and the second electrode 60 being located within the step 110 of the epitaxial layer 10.
[0053] In this embodiment of the disclosure, the light-emitting diode further includes: an insulating reflective layer 70, a first pad 80, a second pad 90, and a substrate 100.
[0054] The epitaxial layer 10 is located on the substrate 100. The insulating reflective layer 70 covers the epitaxial layer 10, the sidewall barrier layer 30, the transparent conductive layer 40, the first electrode 50, and the second electrode 60. The first pad 80 and the second pad 90 are located on opposite sides of the insulating reflective layer 70. The first pad 80 passes through the insulating reflective layer 70 and is electrically connected to the first electrode 50, and the second pad 90 passes through the insulating reflective layer 70 and is electrically connected to the second electrode 60.
[0055] like Figure 2 As shown, an isolation trench 120 is also formed on the substrate 100 surrounding the epitaxial layer 10.
[0056] In the embodiments disclosed herein, the substrate 100 may be any of the following: sapphire substrate, silicon substrate, etc. The material of the substrate is not limited in this disclosure.
[0057] For example, substrate 100 is a sapphire substrate.
[0058] In this embodiment of the disclosure, the current blocking layer 30 can be a silicon compound layer, such as a SiO2 layer.
[0059] In this embodiment of the disclosure, the transparent conductive layer 40 may be an indium tin oxide (ITO) layer.
[0060] In this embodiment of the disclosure, the first electrode 50 and the second electrode 60 can be multilayer electrodes formed from Cr, Al, Ti, Ni, Pt and Au.
[0061] In this embodiment of the disclosure, the insulating reflective layer 70 may be a distributed Bragg reflector (DBR) layer, which may be a stack of at least one periodic silicon oxide layer (e.g., SiO2) and titanium oxide layer (e.g., TiO2).
[0062] In this embodiment, the insulating reflective layer 70 has through holes 701 corresponding to the first electrode 50 and the second electrode 60, respectively, and the electrodes and pads are electrically connected through the through holes 701.
[0063] In this embodiment of the disclosure, the first pad 80 and the second pad 90 can be multilayer pads formed from various materials such as Ti, Al, Ni and Au.
[0064] In the embodiments disclosed herein, the epitaxial layer may include other film layers, such as buffer layers, in addition to N-type semiconductor layers, multiple quantum wells, and P-type semiconductor layers.
[0065] Figure 3 This is a flowchart illustrating a method for manufacturing a light-emitting diode (LED) according to an embodiment of this disclosure. See also... Figure 3 The method includes the following steps: S11, growth epitaxial layer.
[0066] The epitaxial layer includes an N-type semiconductor layer, a multi-quantum well layer, and a P-type semiconductor layer, with the multi-quantum well layer located between the N-type semiconductor layer and the P-type semiconductor layer.
[0067] S12. The epitaxial layer is patterned to form steps.
[0068] The top surface of the step is located in the P-type semiconductor layer, the bottom surface of the step is located in the N-type semiconductor layer, and the sidewall of the step extends from the P-type semiconductor layer to the N-type semiconductor layer.
[0069] S13. Create a sidewall barrier layer covering the steps.
[0070] The sidewall barrier layer is a highly aluminum-doped P-type semiconductor layer.
[0071] S14. The sidewall blocking layer is graphically processed to remove the sidewall blocking layer from the top and bottom surfaces of the step, so that the sidewall blocking layer covers the sidewall of the step.
[0072] In this embodiment, by covering the sidewall barrier layer of the epitaxial layer step sidewall, nonradiative recombination centers on the step sidewall are eliminated, thereby reducing nonradiative recombination, improving internal quantum efficiency, and increasing luminescence efficiency. The sidewall barrier layer is an Al-doped P-type GaN layer. The high Al content results in a wide bandgap semiconductor, with a higher conduction band bottom and a lower valence band top compared to a multi-quantum-well layer. This is equivalent to building a high energy wall around the edge of the active region of the multi-quantum-well layer. Thus, electrons moving from the active region to the edge sidewall need to climb a high slope (potential barrier), and holes moving from the active region to the edge sidewall need to jump down a deep pit (also a potential barrier). This energy shield, naturally formed by the energy difference, actively and powerfully pushes electrons and holes back to the center of the active region, forcing them to recombine and emit light in the multi-quantum-well layer. Furthermore, using an Al-doped P-type GaN layer as a defect blocking layer, compared to using materials such as silicon dioxide, not only provides band confinement and electrical blocking but also crystal repair, thus improving the quality of the epitaxial crystal.
[0073] Figure 4 This is a flowchart illustrating another method for fabricating a light-emitting diode (LED) as disclosed in this publication. See also... Figure 4 The method includes the following steps: S21. An epitaxial layer is fabricated on the substrate surface.
[0074] In the embodiments of this disclosure, the substrate can be any of the following: sapphire substrate, silicon substrate, etc. This disclosure does not limit the material of the substrate.
[0075] For example, the substrate is a sapphire substrate.
[0076] In one example, step S21 includes: The first step is to grow an N-type GaN layer (N-type semiconductor layer) on the substrate surface.
[0077] For example, an N-type GaN layer can be grown on the substrate surface using an MOCVD device.
[0078] The N-type GaN layer is a Si-doped GaN layer with a Si doping concentration of 1E19~3E19 cm⁻¹. -3 The thickness of the N-type GaN layer is 1~2 μm. The growth rate is 3~8 μm / h, the growth atmosphere is a mixture of N2, H2 and NH3, and the temperature is 1080~1120℃.
[0079] In the embodiments disclosed herein, semiconductor layer growth can be achieved using Veeco K465i, C4, or RB MOCVD equipment or AIXTRON metal-organic chemical vapor deposition equipment. High-purity H2 (hydrogen), high-purity N2 (nitrogen), or a mixture of high-purity H2 and high-purity N2 is used as the carrier gas; high-purity NH3 is used as the N source; trimethylgallium (TMGa) and triethylgallium (TEGa) are used as gallium sources; trimethylindium (TMIn) is used as the indium source; silane (SiH4) is used as the N-type dopant; trimethylaluminum (TMAl) is used as the aluminum source; and magnesium pyrocene (CP2Mg) is used as the P-type dopant.
[0080] The second step is to grow a multiple quantum well (MQW) layer on the surface of the N-type GaN layer.
[0081] Among them, the multiple quantum well layer is an InGaN / GaN superlattice structure.
[0082] For example, an InGaN / GaN layer is grown on the surface of an N-type GaN layer using an MOCVD device.
[0083] The multi-quantum well layer comprises an 8-15 period InGaN / GaN superlattice structure, with a single well layer (InGaN) thickness of 20-30 Å and a single barrier layer (GaN) thickness of 90-130 Å. The In content of the InGaN is 0.2-0.3%. The growth atmosphere is a mixture of N2 and NH3, with the well layer growth temperature at 750-820℃ and the barrier layer growth temperature at 800-880℃.
[0084] The third step is to grow a P-type GaN layer (P-type semiconductor layer) on the surface of the multi-quantum well layer.
[0085] For example, a P-type GaN layer is grown on the surface of an InGaN / GaN layer using an MOCVD device.
[0086] Among them, the p-type GaN layer is a Mg-doped GaN layer with a Mg doping concentration of 5E19~10E19 cm⁻¹. -3 The thickness of the p-type GaN layer is 100~200 nm. The growth atmosphere is a mixture of N2, H2, and NH3, and the temperature is 900~980℃.
[0087] The structure of the epitaxial layer described above is only one example. In other examples, the epitaxial layer may include more film layers, such as buffer layers.
[0088] S22. The epitaxial layer is patterned to form steps.
[0089] The top surface of the step is located on the P-type semiconductor layer, the bottom surface of the step is located on the N-type semiconductor layer, and the sidewalls of the step extend from the P-type semiconductor layer to the N-type semiconductor layer. For example, step S22 includes etching the epitaxial layer using an inductively coupled plasma (ICP) process.
[0090] S23. Perform surface pretreatment on the steps.
[0091] For example, step S23 includes: pretreating the step surface with a TMAH solution, wherein the concentration of the TMAH solution is 2-3 wt%, the solution temperature is 80-90°C, and the treatment time is 10-15 minutes.
[0092] For example, the concentration of the TMAH solution is 2.5 wt%, the solution temperature is 85°C, and the treatment time is 12 minutes.
[0093] In this implementation, after etching, surface pretreatment is performed to repair defects and provide a suitable surface for the sidewall barrier layer. A suitable surface can refer to a surface that is atomically clean and has an appropriate stoichiometric ratio.
[0094] S24. Perform high-temperature annealing on the epitaxial layer.
[0095] For example, step S24 includes: performing high-temperature annealing on the epitaxial layer in an MOCVD chamber at a temperature of 930~980°C, with an atmosphere of NH3 and N2 mixture, for a annealing time of 4~8 minutes.
[0096] For example, the temperature is 950℃ and the annealing time is 6 minutes.
[0097] In this implementation, after pretreatment, the surface lattice defects are repaired by high-temperature annealing, which reduces nitrogen vacancies and improves the environment for the subsequent growth of a high-quality sidewall barrier layer.
[0098] S25. Create a sidewall barrier layer covering the steps.
[0099] The sidewall barrier layer is a highly aluminum-doped P-type semiconductor layer.
[0100] In this embodiment, the sidewall barrier layer is epitaxially grown, that is, a film layer grown using an MOCVD device. Epitaxial growth can repair crystal defects in the steps.
[0101] For example, step S25 includes: growing an Al-doped P-type GaN layer in an MOCVD cavity at a temperature of 930~980℃, with a V / III ratio greater than 4000 and a growth rate of 0.2~0.4μm / h.
[0102] For example, at a temperature of 950°C, the V / III ratio is 5000 and the growth rate is 0.3 μm / h during the growth of the sidewall barrier layer.
[0103] In this embodiment, the P-type dopant in the sidewall barrier layer is Mg, and the Mg doping concentration is 4E19~8E19 cm⁻¹. -3 .
[0104] For example, the Mg doping concentration in the sidewall barrier layer is 5E19cm⁻¹. -3 .
[0105] In this implementation, the above-mentioned doping concentration, V / III ratio and growth rate are used in order to improve the growth quality and ensure that the energy band of the sidewall barrier layer is high.
[0106] In this embodiment of the disclosure, the Al composition in the sidewall barrier layer is 0.35~0.45.
[0107] In this implementation, the Al content is at least 0.35, which ensures a high band density in the sidewall barrier layer, thereby limiting the movement of electrons and holes; the Al content is at most 0.45, thus avoiding crystal quality problems caused by excessive Al content.
[0108] For example, the composition of Al is 0.36, 0.40, or 0.42, etc.
[0109] In other embodiments, the Al component can be even higher, and there is no limitation thereto.
[0110] S26. The sidewall blocking layer is graphically processed to remove the sidewall blocking layer from the top and bottom surfaces of the step, so that the sidewall blocking layer covers the sidewall of the step.
[0111] For example, step S26 includes: etching the sidewall barrier layer using an ICP process.
[0112] In this embodiment of the disclosure, the thickness of the sidewall barrier layer is 30~70nm.
[0113] The thickness of the sidewall barrier layer refers to the thickness perpendicular to the sidewall direction.
[0114] In this implementation, for Micro LEDs, the overall volume of the epitaxial layer is relatively small. On this basis, a sidewall barrier layer with a thickness of 30~70nm is set. On the one hand, it can ensure its barrier function, and on the other hand, it will not affect the overall volume of the epitaxial layer due to excessive thickness.
[0115] like Figure 1 As shown, the thickness of the sidewall barrier layer remains uniform.
[0116] For example, the thickness of the sidewall barrier layer is 40, 50, or 60 nm.
[0117] In other embodiments, the thickness of the sidewall barrier layer may also vary, for example, gradually decreasing in thickness from the N-type semiconductor layer to the P-type semiconductor layer.
[0118] In one example, the step is a ring of steps along the edge of the epitaxial layer, and the sidewall barrier layer is also a ring structure covering the outer wall of the step.
[0119] In another example, the step is a groove opened on the epitaxial layer, and the sidewall barrier layer is also a ring structure covering the inner sidewall of the step.
[0120] In another example, the step is a notch on one side of the epitaxial layer, and the sidewall barrier layer is also an open structure covering the inner sidewall of the step.
[0121] S27. Create a current blocking layer.
[0122] The current blocking layer is located on the surface of the epitaxial layer.
[0123] In this embodiment of the disclosure, the current blocking layer can be a silicon compound layer, such as a SiO2 layer.
[0124] S28. Fabricate a transparent conductive layer.
[0125] The transparent conductive layer is located on the surface of the epitaxial layer and covers the current blocking layer.
[0126] In this embodiment of the disclosure, the transparent conductive layer may be an ITO layer.
[0127] S29. Fabricate a first electrode and a second electrode, wherein the first electrode is located on the transparent conductive layer and the second electrode is located on the step.
[0128] For example, the first electrode and the second electrode are formed by a stack of multiple materials selected from Cr, Al, Ti, Ni, Pt and Au.
[0129] S30. Fabricate an insulating reflective layer covering the epitaxial layer, the sidewall barrier layer, the transparent conductive layer, the first electrode, and the second electrode.
[0130] For example, the insulating reflective layer is a DBR layer, which may be a stack formed by at least one period of silicon oxide layer (e.g., SiO2) and titanium oxide layer (e.g., TiO2).
[0131] S31. A first pad and a second pad are formed on the insulating reflective layer.
[0132] The first pad passes through the insulating reflective layer and is electrically connected to the first electrode, and the second pad passes through the insulating reflective layer and is electrically connected to the second electrode.
[0133] For example, the first pad and the second pad are formed using a stack of Ti, Al, Ni and Au.
[0134] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.
Claims
1. A light-emitting diode, characterized in that, The light-emitting diode includes: an epitaxial layer (10) and a sidewall barrier layer (20); The epitaxial layer (10) includes an N-type semiconductor layer (101), a multi-quantum well layer (102), and a P-type semiconductor layer (103). The multi-quantum well layer (102) is located between the N-type semiconductor layer (101) and the P-type semiconductor layer (103). The epitaxial layer (10) includes a step (110). The top surface of the step (110) is located on the P-type semiconductor layer (103), and the bottom surface of the step (110) is located on the N-type semiconductor layer (101). The sidewall of the step (110) extends from the P-type semiconductor layer (103) to the N-type semiconductor layer (101). The sidewall barrier layer (20) covers the sidewall of the step (110), and the sidewall barrier layer (20) is a highly aluminum-doped P-type semiconductor layer (103).
2. The light-emitting diode according to claim 1, characterized in that, The sidewall barrier layer (20) is an Al-doped P-type GaN layer, wherein the Al content is 0.35~0.
45.
3. The light-emitting diode according to claim 2, characterized in that, The thickness of the sidewall barrier layer (20) is 30~70nm.
4. The light-emitting diode according to claim 2, characterized in that, The p-type dopant in the sidewall barrier layer (20) is Mg, and the doping concentration of Mg is 4E19~8E19 cm⁻¹. -3 .
5. The light-emitting diode according to any one of claims 1 to 4, characterized in that, The sidewall barrier layer (20) is grown by epitaxial growth. The V / III ratio of the sidewall barrier layer (20) is greater than 4000 and the growth rate is 0.2~0.4μm / h.
6. A method for manufacturing a light-emitting diode, characterized in that, The method includes: An epitaxial layer is grown, the epitaxial layer comprising an N-type semiconductor layer, a multiple quantum well layer and a P-type semiconductor layer, wherein the multiple quantum well layer is located between the N-type semiconductor layer and the P-type semiconductor layer; The epitaxial layer is patterned to form a step, the top surface of the step is located on the P-type semiconductor layer, the bottom surface of the step is located on the N-type semiconductor layer, and the sidewall of the step extends from the P-type semiconductor layer to the N-type semiconductor layer. A sidewall barrier layer is fabricated to cover the step, wherein the sidewall barrier layer is a highly aluminum-doped P-type semiconductor layer; The sidewall blocking layer is graphically processed to remove the sidewall blocking layer from the top and bottom surfaces of the step, so that the sidewall blocking layer covers the sidewall of the step.
7. The method according to claim 6, characterized in that, The sidewall barrier layer is an Al-doped P-type GaN layer, wherein the Al content is 0.35~0.
45.
8. The method according to claim 7, characterized in that, Fabricating a sidewall barrier layer covering the steps includes: Al-doped P-type GaN layers were grown in an MOCVD chamber at a temperature of 930~980℃, with a V / III ratio greater than 4000 and a growth rate of 0.2~0.4 μm / h.
9. The method according to claim 8, characterized in that, Before fabricating the sidewall barrier layer, the method further includes: The steps are pretreated with a TMAH solution, wherein the concentration of the TMAH solution is 2-3 wt%, the solution temperature is 80-90℃, and the treatment time is 10-15 minutes.
10. The method according to claim 8, characterized in that, Before fabricating the sidewall barrier layer, the method further includes: The epitaxial layer is subjected to high-temperature annealing in an MOCVD chamber at a temperature of 930~980℃, with an atmosphere of NH3 and N2 mixture, for a annealing time of 4~8 minutes.