Electronic device electrode and preparation method and application thereof

Abstract

The invention discloses an electronic device electrode and a preparation method and application thereof. The assembling method of the electronic device electrode comprises the following steps: 1) preparing an anti-stretching adhesion layer on a substrate, carrying out quenching treatment, preparing an electrode layer on the anti-stretching adhesion layer, carrying out oxygen plasma treatment, and then stripping and fixing on an attaching clamp to obtain an upper layer structure; 2) carrying out electron beam evaporation on another substrate to obtain an electrode layer, spin-coating an interface layer on the electrode layer, carrying out oxygen plasma treatment, spin-coating a semiconductor layer on the interface layer, and fixing the substrate surface on another fitting clamp to obtain a lower layer structure; and 3) aligning and fixing one end of the electrode layer in the upper-layer structure and one end of the semiconductor layer in the lower-layer structure together, extending towards the other end to exhaust air, and cutting off the redundant part of the fitting clamp along the substrate in the lower-layer structure, thereby completing the assembly of the electronic device electrode. According to the invention, the lossless bonding of the electrode and the semiconductor interface under the room temperature condition is realized.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor devices and spintronics technology, and relates to an electronic device electrode, its preparation method and application. Background Technology

[0002] Organic spin valve (OSV) devices are fundamental components in organic spintronics research, showing broad application prospects in fields such as magnetic field sensors, novel memories, electronic switches, and spin logic gates. An OSV device consists of two ferromagnetic (FM) electrodes with different coercivities on either side and an organic semiconductor film in the middle. To achieve effective spin transport in the organic semiconductor layer, the interface between the electrodes and the organic semiconductor must be kept relatively flat. However, during the fabrication of the top electrode using the traditional electron beam evaporation method, metal inevitably penetrates into the semiconductor film and transfers heat to the low thermal conductivity organic film, causing softening and damage to the organic semiconductor film, thus affecting device performance.

[0003] Currently reported polymer-assisted strain-confined transfer techniques have effectively solved the problem of metal cluster infiltration, constructing a uniform and non-destructive interface between ferromagnetic (FM) electrodes and non-magnetic materials (NMMs) in spintronic devices. However, this technique requires an assembly temperature of 400K, which can cause some thermal damage to the semiconductor film, and it requires the use of octadecylsilane (OTS) to modify the surface of the silicon wafer or glass plate. This chemical is highly irritating and corrosive. Therefore, a more efficient, simple, and safe method is needed to achieve non-destructive transfer of ferromagnetic electrodes at room temperature, in order to improve the stability and reliability necessary for organic spin valve devices in the construction of all-spin logic gates and other fields. Summary of the Invention

[0004] The purpose of this invention is to provide an electronic device electrode, its preparation method, and its application.

[0005] This invention eliminates the problem of top electrode penetration into the organic semiconductor film during device manufacturing, achieving a clean, smooth spatial interface for effective spin filtration. It lowers the assembly temperature to room temperature, preventing thermal damage to the organic semiconductor film and thus improving the performance and reliability required for device application. Furthermore, this invention simplifies the electrode stripping process by replacing the previous OTS sacrificial layer stripping technique with a quenching stripping technique. This ensures that the electrode is not stretched during stripping, thereby maintaining the size and regularity of the magnetic domains and guaranteeing the non-destructive transfer of ferromagnetic electrodes.

[0006] The present invention provides an electronic device electrode, which includes an upper structure and a lower structure. The upper structure includes, from top to bottom, a bonding fixture, a tensile adhesive layer, and an electrode layer. The lower structure includes, from top to bottom, a semiconductor layer, an interface layer, an electrode layer, a substrate, and a bonding fixture.

[0007] In the electrodes of the aforementioned electronic devices, the material used to prepare the tensile adhesion layer is selected from at least one of polyvinyl alcohol, polystyrene, and polydimethylsiloxane;

[0008] The thickness of the tensile-resistant adhesive layer can be 1 nm to 100 μm;

[0009] The electrode materials in both the upper and lower electrode layers are selected from at least one of iron, cobalt, and nickel, or alloys of at least two of them.

[0010] The thickness of the electrode layer can be 1 to 100 nm.

[0011] In the electrodes of the aforementioned electronic devices, the material used to prepare the semiconductor layer is selected from at least one of poly(2,5-bis(2-octyldodecyl)-3,6-di(thiophen-2-yl)dionepyrrole[3,4-c]pyrrole-1,4-dione-alt-thiophene[3,2-b]thiophene) (abbreviated as DPPT-TT), poly(2,5-bis(3-alkylthiophene-2-yl)thiophene[3,2-b]thiophene) (abbreviated as PBTTT), poly(tetrathiopheneacetic acid dionepyrrole) (abbreviated as PTDPPTFT4), polyisoindigodithiophene (abbreviated as PII2T), poly(3-hexylthiophene) (abbreviated as P3HT), poly{2,5-bis(2-octyl)-3,6-dithiopyridylthiophene} (abbreviated as N2200) and methyl [6,6]-phenyl-C61-butyrate (abbreviated as PCBM);

[0012] The thickness of the semiconductor layer can be 1 nm to 1 mm.

[0013] In the electrodes of the aforementioned electronic devices, the material used to prepare the interface layer is selected from any one of magnesium oxide, aluminum oxide, gallium nitride, graphene, and barium titanate;

[0014] The thickness of the interface layer can be 0.1 nm to 1 μm.

[0015] In the electrodes of the aforementioned electronic devices, the substrate material is selected from at least one of silicon wafers, glass, ceramics, and quartz;

[0016] The material used to make the bonding clamp is selected from at least one of polyethylene, polypropylene, polyvinyl chloride, polystyrene, polyethylene terephthalate, polycarbonate, and nylon film;

[0017] The thickness of the bonding fixture can be 100 nm to 1 cm.

[0018] The present invention also provides a method for assembling the electrodes of the above-mentioned electronic devices, comprising the following steps: 1) preparing the tensile adhesive layer on the substrate and performing quenching treatment, preparing the electrode layer of the upper structure on the tensile adhesive layer, performing oxygen plasma treatment, then peeling and fixing it on the bonding fixture, and performing vacuum sealing to obtain the upper structure;

[0019] 2) On another substrate, an electrode layer in the lower structure with a different coercivity than the upper electrode layer in the upper structure is obtained by electron beam evaporation. Then, the interface layer is spin-coated on the electrode layer, followed by oxygen plasma treatment. The semiconductor layer is then spin-coated on the interface layer. Finally, the substrate surface after the above treatment is fixed on another bonding fixture and vacuum sealed to obtain the lower structure.

[0020] 3) At room temperature, align and fix one end of the electrode layer in the upper structure with one end of the semiconductor layer in the lower structure, extend to the other end to expel air, and cut off the excess part of the bonding fixture along the substrate in the lower structure to complete the assembly of the electronic device electrode.

[0021] In this invention, the substrate is cleaned before use by ultrasonic cleaning with acetone and isopropanol in sequence, and then dried with a nitrogen gun to obtain a clean substrate.

[0022] The conditions for ultrasonic cleaning are as follows: ultrasonic power of 10 to 100 watts, ultrasonic time of 1 to 30 minutes, and ultrasonic frequency of 10 to 100 kilohertz.

[0023] In the above method, in step 1), the peeling is achieved by a quenching method;

[0024] The tensile adhesive layer is prepared by any one of the following methods: drop coating, spin coating, blade coating, roller coating, brush coating, and stretch coating.

[0025] The solvent for preparing the tensile adhesive layer is selected from at least one of water, ethanol, isopropanol, chloroform, acetone, cyclohexane, n-hexane, isohexane, and toluene;

[0026] The electrode layer in the upper structure is prepared by any one of molecular beam epitaxy, magnetron sputtering, pulsed laser deposition, atomic layer deposition, chemical vapor deposition, thermal evaporation, electron beam evaporation, or stripping.

[0027] In the above method, in step 1), the pre-quenching heating temperature can be 50 to 200°C, the pre-quenching heating time can be 1 min to 48 h, the quenching temperature can be -100 to 100°C, and the quenching time can be 1 min to 48 h.

[0028] In steps 1) and 2), the fastening method used is any one of glue, double-sided tape, tape, clips or rope binding.

[0029] In the above methods, the interface layer is prepared by any one of molecular beam epitaxy, magnetron sputtering, pulsed laser deposition, atomic layer deposition, chemical vapor deposition, thermal evaporation, electron beam evaporation, and lift-off.

[0030] The semiconductor layer is prepared by any one of the following methods: vapor deposition, drop coating, spin coating, blade coating, roller coating, brush coating, and film stretching.

[0031] The solvent used to prepare the semiconductor layer raw material is any one of water, ethanol, isopropanol, chloroform, acetone, cyclohexane, n-hexane, isohexane, and toluene; the concentration of the solvent is 0.1 g / L to 100 g / L.

[0032] The annealing temperature of the semiconductor layer can be from 20°C to 200°C.

[0033] In this invention, the room temperature is common knowledge in the field and is generally 10 to 30°C.

[0034] The electronic device electrode described in this invention is used in the fabrication of organic spin valve devices.

[0035] The present invention has the following beneficial effects:

[0036] This invention achieves non-destructive bonding of the electrode and semiconductor interface at room temperature by separating the top electrode from the semiconductor layer, quenching and peeling the top electrode layer from the polymer adhesive layer, and assembling the device using a flexible substrate. This maintains an atomically flat interface and eliminates the penetration and damage of metal into the semiconductor layer during traditional electron beam evaporation. This lays the foundation for expanding the application of spintronic devices in fields such as spin logic gate circuits. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of the upper and lower structures of the spin valve device assembled in Embodiment 1 of the present invention, as well as the process of attaching and assembling the spin valve device.

[0038] Figure 2 This is a comparison diagram of the magnetoresistance changes of the spin valve devices prepared in Example 1 and Comparative Example 3 of the present invention during the magnetic scanning process.

[0039] Figure 3 This is a high-resolution transmission electron microscope image (scale bar: 100 nm) of the device prepared in Example 1 of the present invention.

[0040] Figure 4This is a comparison chart of the magnitudes of the 90° peel force and 180° shear force in Embodiment 1 of the present invention, compared with Comparative Examples 1 and 2.

[0041] Figure 5 The positive MR curve of the positive organic spin valve device (PSV) prepared from organic semiconductor material N2200 according to Example 1 of the present invention.

[0042] Figure 6 The structure of the organic semiconductor material poly(2,7-bis(2-octyldodecyl)benzo[LMN][3,8]o-diazaphenanthroline-1,3,6,8(2H,7H)-tetraone-4,9-diyl)([2,2']dithienyl-5,5'-diyl)(N2200) is given. Detailed Implementation

[0043] Unless otherwise specified, the experimental methods used in the following examples are conventional methods.

[0044] Unless otherwise specified, all materials and reagents used in the following examples are commercially available.

[0045] The present invention will now be described in further detail with reference to specific embodiments. The given embodiments are merely illustrative of the invention and not intended to limit its scope. The embodiments provided below can serve as a guide for further improvements by those skilled in the art and do not constitute a limitation on the invention in any way.

[0046] Example 1

[0047] In this embodiment, the upper and lower layer structures are prepared separately in the following manner, and the spin interface is non-destructively bonded at room temperature, and then assembled into a spin valve device:

[0048] 1) Place 2×2cm 2 The silicon substrate (with a 300nm SiO2 layer on the surface) was ultrasonicated with acetone and isopropanol at a power of 40W and a frequency of 30kHz for 20 minutes, and then dried with a nitrogen gun.

[0049] 2) Prepare an 80 mg / ml PVA aqueous solution, place the solution on a hot plate, heat and stir at 90°C for 12 hours, and then cool to room temperature.

[0050] 3) Place the cleaned silicon wafer from step 1) on a spin coater, set the spin speed to 2000 rpm and the time to 40 s. Take 0.2 ml of the PVA aqueous solution prepared in step 2) and drop it onto the silicon wafer. Spin coat the PVA solution evenly onto the surface of the silicon wafer. Then, place the silicon wafer on a hot plate and anneal it at 120°C for 20 minutes. After that, transfer it to a 0°C copper plate for rapid quenching for 1 minute.

[0051] 4) In a nitrogen-purified glove box, through 2×10 -5 Pa and Electron beam evaporation deposition of 12nm Ni 80 Fe 20 layer.

[0052] 5) The sample was treated with oxygen plasma at 5% power, circulated three times in a pure oxygen environment at 0.1 mPa for 10 seconds each time, to perform NOSV modification (referred to as negative organic spin valve modification). The resulting metal oxide interface layer NiFeO x The thickness was 1.8 nm. The sample was then vacuum-sealed in preparation for subsequent processing.

[0053] 6) Place 1×1cm 2 A silicon substrate (with a 300nm SiO2 layer on its surface) was sequentially sonicated with acetone and isopropanol at a power of 40W and a frequency of 30kHz for 20 minutes, and then dried with a nitrogen gun. Using the cleaned silicon wafer as a substrate, in a nitrogen-filled glove box, it was subjected to a 2×10⁻⁶ process. -5 Pa and Electron beam evaporation deposition of 20 nm Co and 1.3 nm Al.

[0054] 7) Treat the sample with oxygen plasma at 5% power, using pure oxygen for three atmospheric cycles, and oxidize for 10 seconds.

[0055] 8) Prepare a 12 mg / ml organic semiconductor solution N2200 with chloroform as the solvent. Place the sample on a hot plate and stir at 50°C for 12 hours, then cool to room temperature.

[0056] 9) Place the sample prepared in step 7) on a spin coater, set the speed to 3000 rpm and the time to 40 s, drop the organic semiconductor solution from step 8) onto the sample surface, and spin coat the organic semiconductor solution to make it evenly coated on the sample surface. Seal the sample in a vacuum container for analysis.

[0057] 10) such as Figure 1 As shown, a 0.5 mm thick, 15 cm long, and 10 cm wide PET flexible film was used as the substrate for the bonding jig of the upper sample obtained in step 5) and the bonding jig of the lower sample obtained in step 9), respectively. The upper bonding jig has an 18 mm square cutout in the center and a 1 mm wide polyimide double-sided adhesive strip at the edge for peeling Ni-coated substrates from its SiO2 / Si substrate. 80 Fe 20 (O xThe PVA film of the electrodes. The electrodes face the PET front and include the device electrodes (indicated by the red dashed lines in the cross-sectional view) and assembly alignment marks (black right-angled marks around the electrodes). A lower bonding jig securely holds the lower part of the spin valve device at its center using polyimide double-sided adhesive. During assembly, one end of each half is held together, and the upper half is gradually lowered to align using the alignment marks, starting from the left and extending outwards to expel air. After alignment, a surgical blade cuts along the silicon substrate to complete room-temperature assembly, yielding the final device.

[0058] Comparative Example 1

[0059] Following the same preparation method as in Example 1, the silicon wafer in step 1) was subjected to OTS treatment, that is, the cleaned silicon wafer was immersed in a hexane solution of octadecyltrichlorosilane for 12 hours, then dried with a nitrogen gun, and the quenching step in step 3) was cancelled, allowing the sample to gradually cool to room temperature.

[0060] Comparative Example 2

[0061] Following the exact same preparation method as in Example 1, except that the quenching step in step 3) was omitted, the sample was gradually cooled to room temperature.

[0062] Comparative Example 3

[0063] Complete the construction of the lower structure according to steps 6)-9) in Example 1, and then attach the top electrode Ni. 20 Fe 80 (O x The spin valve device is constructed by directly depositing electron beam evaporation onto a semiconductor film using the traditional evaporation method.

[0064] Depend on Figure 1 As can be seen from the construction of the upper and lower layer structures and the device assembly process in Example 1, a 1.8 nm thick Ni 80 Fe 20 O x The electrode layer is seamlessly assembled into the spin valve device. Utilizing the strong adhesion between the hydroxyl groups in PVA and the organic semiconductor, the top electrode can be tightly bonded to the semiconductor at room temperature, achieving a perfectly intact spin valve device.

[0065] Magnetoresistive measurements were performed using a CRX-EM-HF cryogenic closed-loop cryogenic probe station (Lake Shore Cryotronics Co., Ltd.) in conjunction with a Keithley 4200A-SCS parameter analyzer (Tektronix Inc.). This setup ensures precise control and monitoring of electrical performance under varying magnetic fields, contributing to accurate evaluation of spin valve performance. Results are as follows: Figure 2 As shown, through Figure 2A comparison of the spin valve device constructed in Example 1 with the device in Comparative Example 3 and the magnetoresistance changes of the metal wire shows that the device constructed using this invention exhibits a sharp and stable resistance change, which is superior to the traditional evaporation method in Comparative Example 3. In the high-resistance state (top of the curve), there is a clear difference between Example 1 and the traditional evaporation method in Comparative Example 3: the former maintains a nearly flat profile (red line with circular markings), while the latter shows a significant difference (black line with square markings). The slope of the curve in Comparative Example 3 originates from Ni. 80 Fe 20 During evaporation, the electrode penetrates into the organic semiconductor layer, resulting in a chaotic distribution of domain sizes. Consequently, as the magnetic field changes, domains of different sizes switch sequentially, causing the magnetoresistance change curve to be sloping. Furthermore, the disordered domains and dispersed size distribution reduce the spin polarization effect at the interface; therefore, the magnetoresistance change rate of the spin valve prepared in Comparative Example 3 is only half that of the spin valve prepared in Example 1. Further enhancement by the top electrode penetrating the semiconductor layer may lead to the formation of metal filaments within the semiconductor, potentially causing short circuits in the device. This results in a lack of clear and rapid resistance switching, instead producing a "flat slope," essentially reflecting the minute change in the resistance of the ferromagnetic electrode itself with the magnetic field (unmarked on the bottom black line). The significant differences in magnetoresistance switching speed and stability among the three spin valves highlight the crucial influence of spatial interface quality on device performance, demonstrating that the technology of this invention effectively improves spatial interface quality, thereby achieving rapid and stable magnetoresistance switching of the spin valve at room temperature, providing a necessary component for constructing all-spin valve logic gates.

[0066] In Example 1, the device was tested using the following method, and high-resolution transmission electron microscopy images of the device were obtained. The results are as follows: Figure 3 As shown:

[0067] Sections with a thickness less than 100 nm were prepared using a ThermoFisher Scientific Helios Nanolab G3 CX focused ion beam microscope. Observation and analysis were performed using a spherical aberration-corrected transmission electron microscope (Cs-corrected TEM), specifically a ThermoFisher Scientific Spectra 300 equipped with an electron energy loss spectroscopy (EELS) module and an energy-dispersive spectroscopy (EDS) instrument. Figure 3 As can be seen from the image, the device has a smooth and clear interface.

[0068] Peel force was measured using an F105 series force gauge equipped with a Mark-10 FS05-05 sensor, with a range of 2.5 N and an accuracy of 0.005 N. The load was applied to the substrate at a 90-degree angle. Shear force was measured using an F105 series force gauge paired with an FS05-2 sensor, with a capacity of 10 N and an accuracy of 0.02 N. The load was applied parallel to the substrate surface. The results are as follows: Figure 4 As shown, by Figure 4 A comparison of the adhesion peeling force and shear force between Embodiment 1 of the present invention and Comparative Examples 1 and 3 shows that the quenching process in the present invention improves the adhesion of Ni. 80 Fe 20 O x Thin film peeling efficiency. Compared to traditional direct peeling methods, the quenching method significantly reduces the peeling force by 99.8% (from 1.021 N to 0.002 N) and the shear force by 80.00% (from 15.158 N to 3.031 N). This significant reduction ensures the structural integrity of the electrodes and the preservation of magnetic domains, which is crucial for seamless device integration. Quenching not only minimizes the required force but also improves the quality and reliability of the resulting electronic components.

[0069] Magnetoresistive measurements were performed using a CRX-EM-HF cryogenic closed-loop cryogenic probe station (Lake Shore Cryotronics Co., Ltd.) in conjunction with a Keithley 4200A-SCS parameter analyzer (Tektronix Inc.). This setup ensures precise control and monitoring of electrical performance under varying magnetic fields, contributing to accurate evaluation of spin valve performance. Results are as follows: Figure 5 As shown, by Figure 5 The results show that the PSV exhibits sharp rectangular transitions at room temperature, with an MR of +10%. The excellent performance of the PSV prepared using N2200 semiconductor thin films at room temperature highlights the advantages of this invention for Ni... 80 Fe 20 The effectiveness of spatial interface modification at the device level lays the foundation for constructing spin valve logic circuits.

[0070] The present invention has been described in detail above. Those skilled in the art will recognize that the invention can be practiced in a wide range of ways with equivalent parameters, concentrations, and conditions without departing from its spirit and scope, and without requiring unnecessary experiments. While specific embodiments have been provided, it should be understood that further modifications can be made to the invention. In summary, according to the principles of the invention, this application is intended to include any changes, uses, or improvements to the invention, including changes made using conventional techniques known in the art that depart from the scope disclosed herein.

Claims

1. An electrode for an electronic device, characterized in that, The electrode of the electronic device includes an upper structure and a lower structure. The upper structure, from top to bottom, includes a bonding fixture, a tensile adhesive layer, and an electrode layer. The lower structure, from top to bottom, includes a semiconductor layer, an interface layer, an electrode layer, a substrate, and a bonding fixture.

2. The electronic device electrode according to claim 1, characterized in that, The material used to prepare the tensile adhesive layer is selected from at least one of polyvinyl alcohol, polystyrene, and polydimethylsiloxane; The thickness of the tensile-resistant adhesive layer is 1 nm to 100 μm; The electrode materials in both the upper and lower electrode layers are selected from at least one of iron, cobalt, and nickel, or alloys of at least two of them. The thickness of each electrode layer is 1–100 nm.

3. The electronic device electrode according to claim 1 or 2, characterized in that, The material used to prepare the semiconductor layer is selected from at least one of poly(2,5-bis(2-octyldodecyl)-3,6-di(thiophen-2-yl)dionepyrrole[3,4-c]pyrrole-1,4-dione-alt-thiophene[3,2-b]thiophene), poly(2,5-bis(3-alkylthiophen-2-yl)thiophene[3,2-b]thiophene, poly(tetrathiophene acetate dionepyrrole), polyisoindigo dithiophene, poly(3-hexylthiophene), poly{2,5-bis(2-octyl)-3,6-dithiopyridylthiophene} and methyl [6,6]-phenyl-C61-butyrate; The thickness of the semiconductor layer is 1 nm to 1 mm.

4. The electronic device electrode according to any one of claims 1-3, characterized in that, The material used to prepare the interface layer is selected from any one of magnesium oxide, aluminum oxide, gallium nitride, graphene, and barium titanate; The thickness of the interface layer is 0.1 nm to 1 μm.

5. The electronic device electrode according to any one of claims 1-4, characterized in that, The substrate material is selected from at least one of silicon wafers, glass, ceramics, and quartz; The material used to make the bonding clamp is selected from at least one of polyethylene, polypropylene, polyvinyl chloride, polystyrene, polyethylene terephthalate, polycarbonate, and nylon film; The thickness of the bonding fixture is 100 nm to 1 cm.

6. A method for assembling electrodes for an electronic device according to any one of claims 1-5, characterized in that, The process includes the following steps: 1) On the substrate, the tensile adhesive layer is prepared and quenched. On the tensile adhesive layer, the electrode layer in the upper structure is prepared and oxygen plasma treatment is performed. Then, the electrode layer is peeled off and fixed on the bonding fixture and vacuum sealed to obtain the upper structure. 2) On another substrate, an electrode layer in the lower structure with a different coercivity than the upper electrode layer in the upper structure is obtained by electron beam evaporation. Then, the interface layer is spin-coated on the electrode layer, followed by oxygen plasma treatment. The semiconductor layer is then spin-coated on the interface layer. Finally, the substrate surface after the above treatment is fixed on another bonding fixture and vacuum sealed to obtain the lower structure. 3) At room temperature, align and fix one end of the electrode layer in the upper structure with one end of the semiconductor layer in the lower structure, extend to the other end to expel air, and cut off the excess part of the bonding fixture along the substrate in the lower structure to complete the assembly of the electronic device electrode.

7. The method according to claim 6, characterized in that, In step 1), the peeling is achieved by a quenching method; The tensile adhesive layer is prepared by any one of the following methods: drop coating, spin coating, blade coating, roller coating, brush coating, and stretch coating. The solvent for preparing the tensile adhesive layer is selected from at least one of water, ethanol, isopropanol, chloroform, acetone, cyclohexane, n-hexane, isohexane, and toluene; The electrode layer in the upper structure is prepared by any one of molecular beam epitaxy, magnetron sputtering, pulsed laser deposition, atomic layer deposition, chemical vapor deposition, thermal evaporation, electron beam evaporation, or stripping.

8. The method according to claim 7, characterized in that, In step 1), the pre-quenching heating temperature of the quenching method is 50-200℃, the pre-quenching heating time is 1min-48h, the quenching temperature is -100-100℃, and the quenching time is 1min-48h. In steps 1) and 2), the fastening method used is any one of glue, double-sided tape, tape, clips or rope binding.

9. The method according to any one of claims 6-8, characterized in that, The interface layer is prepared by any one of the following methods: molecular beam epitaxy, magnetron sputtering, pulsed laser deposition, atomic layer deposition, chemical vapor deposition, thermal evaporation, electron beam evaporation, and lift-off. The semiconductor layer is prepared by any one of the following methods: vapor deposition, drop coating, spin coating, blade coating, roller coating, brush coating, and film stretching. The solvent used to prepare the semiconductor layer raw material is any one of water, ethanol, isopropanol, chloroform, acetone, cyclohexane, n-hexane, isohexane, and toluene; the concentration of the solvent is 0.1 g / L to 100 g / L. The annealing temperature of the semiconductor layer is 20 degrees Celsius to 200 degrees Celsius.

10. The use of the electronic device electrode according to any one of claims 1-5 in the fabrication of an organic spin valve device.

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