Method for manufacturing semiconductor device and semiconductor device

Abstract

The invention provides a method for manufacturing a semiconductor device and a semiconductor device, which can be more appropriately singulated. A method of manufacturing a semiconductor device according to an embodiment includes forming a first groove and a second groove in a first surface of a semiconductor wafer, the first groove and the second groove extending along a dicing region of the semiconductor wafer having the first surface and a second surface on an opposite side of the first surface and being arranged side by side. Furthermore, this manufacturing method is provided with a step for forming a modified portion in the semiconductor wafer along the dicing region by irradiating a first laser beam from the second surface side of the semiconductor wafer toward the space between the first groove and the second groove when viewed from above. In addition, this manufacturing method is provided with a step for dividing the semiconductor wafer into a plurality of semiconductor chips by cleaving the semiconductor wafer.

Description

Technical Field

[0001] This embodiment relates to a method for manufacturing a semiconductor device and a semiconductor device. Background Technology

[0002] When using lasers for cutting, in order to properly monolithize the wafer into multiple chips, it is desirable for cracks to progress appropriately from the modified section (modified layer). Summary of the Invention

[0003] The present invention provides a method for manufacturing a semiconductor device and a semiconductor device that can be more appropriately monolithically assembled.

[0004] The semiconductor device manufacturing method of this embodiment includes the following steps: forming a first trench and a second trench on a first surface of a semiconductor wafer, wherein the first trench and the second trench extend side-by-side along a dicing region of the semiconductor wafer having a first surface and a second surface located opposite to the first surface. Furthermore, this manufacturing method includes the step of irradiating a first laser from the second surface side of the semiconductor wafer between the first trench and the second trench when viewed from above, thereby forming a modified portion within the semiconductor wafer along the dicing region. Additionally, this manufacturing method includes the step of monolithically dividing the semiconductor wafer into multiple semiconductor chips by cleaving. Attached Figure Description

[0005] Figure 1 This is a top view showing an example of the partial configuration of the semiconductor wafer in the first embodiment.

[0006] Figure 2 This is a perspective view illustrating the semiconductor device of the first embodiment.

[0007] Figure 3 This is a top view representing a stacked volume.

[0008] Figure 4 This is a cross-sectional view representing an example of a three-dimensional storage unit.

[0009] Figure 5 This is a cross-sectional view representing an example of a three-dimensional storage unit.

[0010] Figure 6 This is a top view showing an example of the semiconductor device according to the first embodiment.

[0011] Figure 7 This is a cross-sectional view showing an example of the structure of the chip area and the cut area.

[0012] Figure 8A This is a perspective view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0013] Figure 8B Is following Figure 8A The following is a perspective view illustrating an example of a method for manufacturing a semiconductor device.

[0014] Figure 8C Is following Figure 8B The following is a perspective view illustrating an example of a method for manufacturing a semiconductor device.

[0015] Figure 8D Is following Figure 8C The following is a perspective view illustrating an example of a method for manufacturing a semiconductor device.

[0016] Figure 8E Is following Figure 8D The following is a perspective view illustrating an example of a method for manufacturing a semiconductor device.

[0017] Figure 8F Is following Figure 8E The following is a perspective view illustrating an example of a method for manufacturing a semiconductor device.

[0018] Figure 8G Is following Figure 8F The following is a perspective view illustrating an example of a method for manufacturing a semiconductor device.

[0019] Figure 8H Is following Figure 8G The following is a perspective view illustrating an example of a method for manufacturing a semiconductor device.

[0020] Figure 9A This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0021] Figure 9B Is following Figure 9A The following is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0022] Figure 9C Is following Figure 9B The following is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0023] Figure 10A This is a cross-sectional view showing an example of the configuration of the semiconductor device according to the first embodiment.

[0024] Figure 10B This is a cross-sectional view showing an example of the configuration of the semiconductor device according to the first embodiment.

[0025] Figure 11A This is a cross-sectional view illustrating an example of a manufacturing method for a comparative semiconductor device.

[0026] Figure 11B Is following Figure 11AThe following is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0027] Figure 12A This is a perspective view illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment.

[0028] Figure 12B Is following Figure 12A The following is a perspective view illustrating an example of a method for manufacturing a semiconductor device.

[0029] Figure 13 This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the third embodiment.

[0030] Figure 14 This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the fourth embodiment.

[0031] Figure 15 This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the fifth embodiment.

[0032] Figure 16A This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the sixth embodiment.

[0033] Figure 16B Is following Figure 16A The following is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0034] Figure 17A This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the seventh embodiment.

[0035] Figure 17B Is following Figure 17A The following is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0036] Figure 18A This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the eighth embodiment.

[0037] Figure 18B Is following Figure 17A The following is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0038] Figure 19A This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the ninth embodiment.

[0039] Figure 19B Is following Figure 19A The following is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0040] Figure 20AThis is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the tenth embodiment.

[0041] Figure 20B Is following Figure 20A The following is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0042] Figure 21A This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the 11th embodiment.

[0043] Figure 21B Is following Figure 21A The following is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0044] Figure 22A This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the 12th embodiment.

[0045] Figure 22B Is following Figure 22A The following is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0046] Figure 23A This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the 13th embodiment.

[0047] Figure 23B Is following Figure 23A The following is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0048] Figure 24A This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the 14th embodiment.

[0049] Figure 24B Is following Figure 24A The following is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0050] Figure 25A This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the 15th embodiment.

[0051] Figure 25B Is following Figure 25A The following is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0052] Figure 26A This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the 15th embodiment.

[0053] Figure 26B Is following Figure 26A The following is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0054] Figure 27A This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the 17th embodiment.

[0055] Figure 27B Is following Figure 27A The following is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Detailed Implementation

[0056] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. These embodiments do not limit the present invention. The drawings are schematic diagrams or conceptual diagrams, and the proportions of the parts may not be the same as those of the actual object. In the specification and drawings, elements that are the same as those described with respect to the drawings are labeled with the same symbols, and detailed descriptions are omitted where appropriate.

[0057] In the following embodiments, a semiconductor device, for example, a semiconductor memory device having a three-dimensional memory cell array, will be described. However, the semiconductor device described in the embodiments is not limited to this.

[0058] (First Embodiment)

[0059] Figure 1 This is a top view showing an example of the partial configuration of the semiconductor wafer W according to the first embodiment. The semiconductor wafer W has a front side on which semiconductor elements are formed and a back side opposite to the front side. Figure 1 A top view of the front of the semiconductor wafer W is shown.

[0060] The front side of the semiconductor wafer W has multiple chip regions Rc and multiple dicing regions Rd. The chip regions Rc are areas where semiconductor chips are monolithically formed into semiconductor chips in subsequent dicing processes. Chip patterns are formed in the chip regions Rc. In this embodiment, the chip pattern may include, for example, a memory cell array MCA. Control circuitry for controlling the memory cell array MCA is disposed below the memory cell array MCA. Figure 1 Not shown in the image.

[0061] The dicing region Rd is positioned between multiple adjacent chip regions Rc, and is cut off (removed) in a subsequent dicing process to monolithize the chip regions Rc. The test pattern TEG is set within the dicing region Rd.

[0062] Figure 2 This is a perspective view illustrating the semiconductor device 100 of the first embodiment. Figure 3 This is a top view showing laminate 2. In this specification, the lamination direction of laminate 2 is defined as the Z-axis direction. One direction orthogonal to the Z-axis direction is defined as the Y-axis direction. The direction orthogonal to both the Z and Y axes is defined as the X-axis direction. Figure 4 and Figure 5These are cross-sectional views representing an example of a three-dimensional storage unit. Figure 6 This is a top view showing an example of the semiconductor device 100 according to the first embodiment. For example... Figures 2-6 As shown, the semiconductor device 100 of the first embodiment is a non-volatile memory with a three-dimensional memory cell array. The semiconductor device 100 is a structure disposed in the chip region Rc, but it can also be disposed in the test pattern TEG and interpreted as a test structure.

[0063] The semiconductor device 100 includes a substrate 1, a laminate 2, a plate-shaped portion 3, a plurality of columnar portions CL, and a plurality of columnar portions CLHR.

[0064] The substrate 1 includes a semiconductor substrate 10, an insulating film 11, a conductive film 12, and a semiconductor portion 13. The insulating film 11 is disposed on the semiconductor substrate 10. The conductive film 12 is disposed on the insulating film 11. The semiconductor portion 13 is disposed on the conductive film 12. The semiconductor substrate 10 is, for example, a silicon substrate. The conductivity type of the semiconductor substrate 10 is, for example, p-type. A device separation region 10i is, for example, disposed on the front side of the semiconductor substrate 10. The device separation region 10i is, for example, an insulating region containing a silicon oxide film, defining an active region AA on the front side of the semiconductor substrate 10. The source and drain regions of a transistor Tr are disposed in the active region AA. The transistor Tr constitutes a CMOS (Complementary Metal Oxide Semiconductor) circuit as a control circuit for non-volatile memory. The insulating film 11 contains, for example, a silicon oxide film, and insulates the transistor Tr. A wiring 11a is disposed within the insulating film 11. The wiring 11a is electrically connected to the transistor Tr. The conductive film 12 contains a conductive metal, for example, tungsten (W). Semiconductor section 13 may, for example, contain n-type silicon. A portion of semiconductor section 13 may also contain undoped silicon.

[0065] The stacked layer 2 is positioned above the semiconductor section 13 in the Z-axis direction. The stacked layer 2 is constructed by alternately stacking multiple conductive layers 21 and multiple insulating layers 22 in the Z-axis direction. The conductive layers 21 contain conductive metals, such as tungsten. The insulating layers 22 contain, for example, silicon oxide. The insulating layers 22 insulate the conductive layers 21 from each other. The number of conductive layers 21 and insulating layers 22 stacked is arbitrary. The insulating layers 22 may also be gaps, for example. An insulating film 2g is provided between the stacked layer 2 and the semiconductor section 13, for example. The insulating film 2g may contain, for example, a silicon oxide film. The insulating film 2g may also contain a high dielectric material with a higher relative dielectric constant than silicon oxide. The high dielectric material may also be an oxide such as hafnium oxide.

[0066] The conductive layer 21 includes at least one source-side select gate (SGS), multiple word lines (WL), and at least one drain-side select gate (SGD). The source-side select gate (SGS) is the gate electrode of the source-side select transistor (STS). The word line (WL) is the gate electrode of the memory cell (MC). The drain-side select gate (SGD) is the gate electrode of the drain-side select transistor (STD). The source-side select gate (SGS) is disposed in the lower region of the stacked layer 2. The drain-side select gate (SGD) is disposed in the upper region of the stacked layer 2. The lower region refers to the region of the stacked layer 2 closest to the substrate portion 1, and the upper region refers to the region of the stacked layer 2 furthest from the substrate portion 1. The word line (WL) is disposed between the source-side select gate (SGS) and the drain-side select gate (SGD).

[0067] The thickness of the insulating layer 22 that insulates the source-side select gate SGS from the word line WL in the Z-axis direction can, for example, be thicker than the thickness of the insulating layer 22 that insulates the word lines WL from each other in the Z-axis direction. Furthermore, a cover insulating film can be provided on the uppermost insulating layer 22 furthest from the substrate 1. The cover insulating film may, for example, contain silicon oxide.

[0068] Semiconductor device 100 has multiple memory cells MC connected in series between a source-side selection transistor STS and a drain-side selection transistor STD. The structure formed by connecting the source-side selection transistor STS, memory cells MC, and drain-side selection transistor STD in series is called a "memory string" or "NAND string". The memory string is connected to a bit line BL, for example, via a contact Cb. The bit line BL is positioned above the stack 2 and extends along the Y-axis.

[0069] Within the stacked volume 2, such as Figure 3 As shown, multiple deep slits ST and multiple shallow slits SHE are provided. The slits ST extend along the X-axis in the planar layout. In addition, in the cross-section of the Z-direction (lamination direction), the slits ST penetrate from the upper end of the laminate 2 to the substrate 1 and are provided within the laminate 2. Figure 3 A plate-shaped portion 3 is disposed within the slit ST. The plate-shaped portion 3 is, for example, an insulating film such as a silicon oxide film. The plate-shaped portion 3 is made of a conductive metal such as a conductive material (e.g., tungsten, copper) that is electrically connected to the semiconductor portion 13, and is electrically insulated from the laminate 2 by the insulating film. In a planar layout, the slit SHE extends approximately parallel to the slit ST along the X-axis direction. Furthermore, in a cross-section along the Z-direction, the slit SHE extends from the top of the laminate 2 to the middle of the laminate 2. An insulator 4 is disposed within the slit SHE, for example. The insulator 4 is, for example, an insulating film such as a silicon oxide film.

[0070] like Figure 3As shown, the stacked layer 2 includes a stepped portion 2s and a memory cell array MCA. The stepped portion 2s is disposed at the edge of the stacked layer 2. The memory cell array MCA is sandwiched or surrounded by the stepped portion 2s. A slit ST extends from the stepped portion 2s at one end of the stacked layer 2 through the memory cell array MCA to the stepped portion 2s at the other end of the stacked layer 2. The slit ST is disposed at least in the memory cell array MCA.

[0071] The portion of the stack 2 sandwiched between two slits ST (plate-like portions 3) is called a block. A block, for example, constitutes the smallest unit for data erasure. A slit SHE (insulator 4) is disposed within the block. The stack 2 between the slits ST and SHE is called a finger. A drain-side select gate SGD is separated for each finger. Therefore, during data writing and reading, one finger within the block can be selected using the drain-side select gate SGD.

[0072] like Figure 6 As shown, the memory cell array MCA includes cell regions and tap regions. The stepped section 2s includes a staircase region. The tap region is, for example, located between the cell region and the staircase region. Although in Figure 6 Although not shown in the diagram, tap areas can also be located between unit areas. The stepped area is where multiple wirings 37a are located. The tap area is where wirings 37b and 37c are located. Wirings 37a to 37c extend, for example, along the Z-axis. Wirings 37a are, for example, electrically connected to conductive layer 21. Wiring 37b is, for example, electrically connected to wiring 11a to supply power to transistor Tr, etc. Wiring 37c is, for example, electrically connected to conductive film 12. Wirings 37a to 37c are, for example, made of low-resistance metals such as copper or tungsten.

[0073] Insulating films 36a to 36c are respectively provided around the wirings 37a to 37c. The insulating films 36a to 36c are positioned between the wirings 37a to 37c and the laminate 2, providing electrical insulation between them. Thus, the wirings 37a to 37c remain insulated from the laminate 2, allowing wirings above the laminate 2 to be electrically connected to wirings below the laminate 2. The insulating films 36a to 36c are, for example, silicon oxide films. Furthermore, the insulating film 36b and the wiring 37b constitute a contact C4 provided in the tap area.

[0074] Multiple columnar portions CL are respectively disposed within memory vias MH provided within the laminate 2. The memory vias MH extend from the top end of the laminate 2 along the stacking direction (Z-axis direction) and into the laminate 2 and the semiconductor portion 13. For example... Figure 4 and Figure 5As shown, multiple columnar portions CL each include a semiconductor body 210, a memory film 220, and a core layer 230. The semiconductor body 210 is electrically connected to the semiconductor section 13. The memory film 220 has a charge trapping section between the semiconductor body 210 and the conductive layer 21. Multiple columnar portions CL, selected one by one from each finger, are commonly connected to a bit line BL via a contact Cb. For example, the columnar portions CL are respectively provided in... Figure 6 The cell region.

[0075] like Figure 4 and Figure 5 As shown, the shape of the memory aperture MH in the XY plane is, for example, circular or elliptical. A barrier insulating film 21a, forming part of the memory film 220, may also be provided between the conductive layer 21 and the insulating layer 22. The barrier insulating film 21a may be, for example, a silicon oxide film or a metal oxide film. An example of a metal oxide is aluminum oxide. A barrier film 21b may also be provided between the conductive layer 21 and the insulating layer 22, and between the conductive layer 21 and the memory film 220. For example, if the conductive layer 21 is tungsten, the barrier film 21b may be, for example, a multilayer structure of titanium nitride and titanium. The barrier insulating film 21a inhibits charge tunneling from the conductive layer 21 to the memory film 220 side. The barrier film 21b improves the adhesion between the conductive layer 21 and the barrier insulating film 21a.

[0076] The semiconductor body 210 is, for example, cylindrical in shape. The semiconductor body 210 contains, for example, silicon. The silicon is, for example, polycrystalline silicon formed by crystallizing amorphous silicon. The semiconductor body 210 is, for example, undoped silicon. Alternatively, the semiconductor body 210 may also be p-type silicon. The semiconductor body 210 serves as the channel for the drain-side selection transistor (STD), the memory cell (MC), and the source-side selection transistor (STS).

[0077] A memory film 220 is disposed between the inner wall of the memory aperture MH and the semiconductor body 210. The memory film 220 is, for example, cylindrical. Multiple memory cells MC have storage regions between the semiconductor body 210 and the conductive layer 21 that will become word lines WL, and the layers are stacked in the Z-axis direction. The memory film 220 includes, for example, a covering insulating film 221, a charge trapping film 222, and a tunnel insulating film 223. The semiconductor body 210, the charge trapping film 222, and the tunnel insulating film 223 each extend along the Z-axis direction.

[0078] An insulating film 221 is disposed between the conductive layer 21 and the insulating layer 22 and the charge trapping film 222. The insulating film 221 is, for example, made of silicon oxide. The insulating film 221 protects the charge trapping film 222 from etching when the sacrificial film (not shown) is replaced with the conductive layer 21. The insulating film 221 can also be removed from between the conductive layer 21 and the memory film 220 during the replacement process. In this case, such as... Figure 4 and Figure 5 As shown, a barrier insulating film 21a is provided, for example, between the conductive layer 21 and the charge trapping film 222. Alternatively, if a replacement process is not used when forming the conductive layer 21, the covering insulating film 221 may not be provided.

[0079] A charge trapping film 222 is disposed between the covering insulating film 221 and the tunnel insulating film 223. The charge trapping film 222 may contain, for example, silicon nitride and has trapping portions within the film for trapping charges. The portion of the charge trapping film 222 sandwiched between the conductive layer 21, which will become the word line WL, and the semiconductor body 210 constitutes the storage region of the memory cell MC as a charge trapping section. The threshold voltage of the memory cell MC varies depending on whether there is charge in the charge trapping section or the amount of charge trapped in the charge trapping section. Thus, the memory cell MC is able to store information.

[0080] A tunnel insulating film 223 is disposed between the semiconductor body 210 and the charge trapping film 222. The tunnel insulating film 223 may be made of silicon oxide, or silicon oxide and silicon nitride, for example. The tunnel insulating film 223 acts as a potential barrier between the semiconductor body 210 and the charge trapping film 222. For example, when electrons are injected from the semiconductor body 210 into the charge trapping section (writing operation) and holes are injected from the semiconductor body 210 into the charge trapping section (erasing operation), the electrons and holes respectively pass through (tunnel) the potential barrier of the tunnel insulating film 223.

[0081] The core layer 230 fills the internal space of the cylindrical semiconductor body 210. The core layer 230 is, for example, columnar. The core layer 230 uses an insulating film such as silicon oxide film.

[0082] Multiple columnar portions CLHR are respectively disposed within holes provided in the laminate 2. The holes extend from the top end of the laminate 2 along the Z-axis into the laminate 2 and into the semiconductor portion 13. The columnar portions CLHR are made of an insulating material such as silicon oxide film. Alternatively, the columnar portions CLHR may have the same structure as the columnar portions CL. The columnar portions CLHR are respectively disposed in the staircase region and the tap region. The columnar portions CLHR function as support members to maintain the gaps formed in the staircase region and the tap region when the sacrificial film is replaced with the conductive layer 21 (replacement process).

[0083] like Figure 2 As shown, the semiconductor device 100 further includes a semiconductor section 14. The semiconductor section 14 is located between the multilayer 2 and the semiconductor section 13. The semiconductor section 14 is disposed between the insulating layer 22 closest to the semiconductor section 13 and the insulating film 2g. The conductivity type of the semiconductor section 14 is, for example, n-type. The semiconductor section 14 functions, for example, as a source-side selected gate (SGS).

[0084] Figure 7 This is a cross-sectional view illustrating an example of the structure of the chip region Rc and the dicing region Rd. For convenience, in... Figure 7 In the chip region Rc, the columnar portion CL, slit ST, and contact C4 contained in the memory cell array MCA are represented side by side. Figure 7 In the cut area Rd, the slits ST_teg and contacts C4_teg contained in the test pattern TEG are represented side by side.

[0085] In the chip region Rc, a transistor Tr, which is part of a CMOS circuit, is disposed on the substrate portion 1. A multilayer wiring structure, including wiring 11a, is disposed on the transistor Tr. A conductive film 12 and a semiconductor portion 13 are disposed on the wiring 11a.

[0086] Above the substrate 1, as described above, a stacked body 2 is disposed. In the stacked body 2 of the chip region Rc, the columnar portions CL extend from above the stacked body 2 to the semiconductor portion 13 in the stacking direction (Z direction) of the conductive layer 21 and the insulating layer 22. The semiconductor body 210 of the plurality of columnar portions CL within the same fingers ( Figure 4 Each bit is electrically connected to a different bit line BL via a contact Cb. Thus, when a word line WL is selected, data in the finger selected by the drain-side selection gate SGD is read via each bit line BL. Alternatively, data is written to the memory cell MC in the selected finger via each bit line BL.

[0087] The slit ST extends from the upper end of the laminate 2 through the laminate 2 to the matrix 1 and is disposed within the laminate 2.

[0088] Contact C4 extends within the laminate 2 along the stacking direction of the laminate 2, and passes through the laminate 2, semiconductor portion 13, and conductive film 12 from above to the wiring 11a of substrate portion 1. Contact C4 electrically connects the power wiring above the laminate 2 to wiring 11a, and via wiring 11a, electrically connects to the CMOS circuit containing transistor Tr. For example, contact C4 can be a power contact provided to supply power to the CMOS circuit. As described above, contact C4 is composed of wiring 37b and insulating film 36b. Insulating film 36b is disposed within the laminate 2 between conductive layer 21 and wiring 37b, and covers the periphery of wiring 37b. By covering the periphery of wiring 37b with insulating film 36b, the wiring 37b can be kept insulated from the laminate 2, and wiring above the laminate 2 can be electrically connected to wiring 11a below the laminate 2.

[0089] Within the substrate portion 1_teg in the dicing region Rd, a transistor Tr_teg, which is included in the test pattern TEG, is disposed. The transistor Tr_teg constitutes part of the CMOS circuitry of the test pattern TEG. On the transistor Tr_teg, a multilayer wiring structure including wiring 11a_teg is disposed. On the wiring 11a_teg, a conductive film 12 and a semiconductor portion 13 are disposed.

[0090] Above the substrate 1_teg, a stacked body 2_teg is disposed. The stacked body 2_teg has the same structure as the stacked body 2. That is, the stacked body 2_teg is disposed above the transistor Tr_teg and is constructed by alternately stacking multiple insulating layers 22 and multiple conductive layers 21. A slit ST_teg and a contact C4_teg are disposed on the stacked body 2_teg.

[0091] The slit ST_teg has the same structure as the slit ST. That is, the slit ST_teg extends from the upper end of the laminate 2_teg through the cutting region Rd to the substrate 1_teg, and is disposed within the laminate 2_teg. An insulating film, such as a silicon oxide film, is embedded within the slit ST_teg.

[0092] Contact C4_teg extends along the stacking direction of stack 2_teg in the dicing region Rd, and passes through the stack 2_teg, semiconductor portion 13, and conductive film 12 from above to the wiring 11a_teg of substrate portion 1_teg. Contact C4_teg is provided, for example, to electrically connect the power wiring above stack 2_teg to wiring 11a_teg and to supply power to the CMOS circuit containing transistor Tr_teg. Contact C4_teg has the same configuration as contact C4. That is, contact C4_teg is composed of wiring 37b and an insulating film 36b covering the wiring 37b. Thus, contact C4_teg can maintain the insulation of wiring 37b from stack 2_teg, and electrically connect the wiring above stack 2_teg to wiring 11a_teg below stack 2_teg.

[0093] According to this embodiment, such as Figure 7As shown, a stacked body 2_teg is also provided in the test pattern TEG of the cut region Rd. The stacked body 2_teg has the same structure as the stacked body 2 in the chip region Rc, and is provided around the contact C4_teg, which has the same structure as the contact C4. Therefore, the transistor Tr_teg of the test pattern TEG can be tested under approximately the same conditions as the transistor Tr in the chip region Rc. Therefore, by measuring the transistor Tr_teg, the characteristics of the transistor Tr located below the stacked body 2 (memory cell array MCA) can be detected. As a result, the influence of the stacked body 2 on the transistor Tr can be detected.

[0094] Next, the method of monolithically converting semiconductor wafer W into multiple chips will be explained.

[0095] Figures 8A to 8H This is a perspective view illustrating an example of a manufacturing method for the semiconductor device 100 according to the first embodiment. The semiconductor device 100 of the first embodiment, for example, includes a monolithically mounted semiconductor chip CH.

[0096] The semiconductor wafer W has a surface F1 and a surface F2 located on the opposite side of surface F1.

[0097] First, such as Figure 8A As shown, a groove (deep section) G is formed on the front side (surface F1) of the semiconductor wafer W. The groove G is formed, for example, by laser etching. Further details regarding the groove G will be provided in [reference needed]. Figures 9A to 9C This will be explained below.

[0098] Next, as Figure 8B As shown, protective tape is attached to the front side (face F1) of the semiconductor wafer W.

[0099] Next, as Figure 8C As shown, a light back-side grinding (pre-grinding) is performed to remove the back-side film on face F2. This is because the back-side film affects the absorption efficiency during subsequent laser cutting. Alternatively, this process may not be necessary. Figure 8C The process shown.

[0100] Next, as Figure 8D As shown, dicing is performed. That is, by irradiating a laser from the F2 side of the semiconductor wafer W, a modified portion (modified layer) LM is formed within the semiconductor wafer W along the dicing region Rd. The focal point of the laser during irradiation is positioned between the grooves and within the semiconductor wafer. The modified portion LM is formed, for example, within the semiconductor substrate 10. Furthermore, cracks Wc extend from the modified portion LM in a direction perpendicular to the surfaces F1 and F2. Additionally, cracks Wc can also extend through subsequent backside grinding.

[0101] Next, as Figure 8EAs shown, back-side grinding of semiconductor wafer W is performed. Grinding is performed on the surface F2 until the semiconductor wafer W is ground to a specified thickness. For example, back-side grinding is performed using CMP (Chemical Mechanical Polishing). The surface F2 of the semiconductor wafer W is ground, for example, until the modified portion LM is removed.

[0102] Next, as Figure 8F As shown, a semiconductor wafer W is mounted on a dicing tape with a loop. Then, the protective tape is peeled off.

[0103] Next, as Figure 8G As shown, a semiconductor wafer W is monolithically divided into multiple semiconductor chips CH. More specifically, the semiconductor wafer W is monolithically divided into multiple semiconductor chips CH by cleaving the semiconductor wafer W starting from the modified section LM. More specifically, this is achieved by using a pressing component (not shown) to... Figure 8G The cutting tape, which has an adhesive layer bonded to surface F2 of the semiconductor wafer W, is pushed upwards from below, thereby stretching (expanding) the cutting tape. Since each semiconductor chip CH is separated by being cleaved along the crack Wc within the cutting region Rd, the semiconductor wafer W is monolithically divided into multiple semiconductor chips. For example... Figure 8H The monolithic semiconductor chip 20 shown is disposed on the wiring substrate 30, and then the wiring substrate 30 and the semiconductor chip 20 are electrically connected by wire bonding 15, etc., and then sealed by molding resin 40.

[0104] Next, the relationship between groove G and crack Wc will be explained.

[0105] Figures 9A to 9C This is a cross-sectional view illustrating an example of a method for manufacturing the semiconductor device 100 according to the first embodiment. Figures 9A to 9C This represents a portion of the cross-section of the cutting region Rd. Figures 9A to 9C The processes shown respectively and Figure 8A , Figure 8D ,and Figure 8G The process shown corresponds to the steps.

[0106] like Figure 9A As shown, a functional film (device film) 110 is disposed on a semiconductor substrate 10. The semiconductor substrate 10 is disposed on the F2 side of the semiconductor wafer W. The functional film 110 is disposed on the F1 side of the semiconductor wafer W. The functional film 110 includes semiconductor elements and an interlayer insulating film 60. The semiconductor elements include, for example, a memory cell array (MCA) and control circuitry.

[0107] First, such as Figure 9A As shown, multiple grooves G are formed from the F1 side of the semiconductor wafer W along the cutting region Rd of the semiconductor wafer W. Figure 9AIn the example shown, two slots G are formed. Multiple slots G, for example, are formed along... Figure 1 The cut area Rd shown is in Figure 9A The paper extends vertically. Multiple slots G are arranged side by side. Figure 9A The left and right directions of the paper. That is to say, multiple slots G are not connected to each other and do not overlap. Furthermore, in Figure 9A In the example shown, the trench G reaches the semiconductor substrate 10. The width of the trench G is, for example, 10 μm, and the distance between the bottoms of the trenches G is, for example, 40 μm.

[0108] For example, groove G can be formed by laser grooving. Laser grooving can also be performed by laser ablation. Lasers with ablation effects can have wavelengths below 600 nm and pulse widths below 10 nm.

[0109] In addition, compressive stress 120 and crystallization defects 130 are generated during the formation of groove G. That is, compressive stress and crystallization defects corresponding to multiple grooves G are formed together.

[0110] Compressive stress 120 and crystallization defect 130 exist near the groove G. Crystallization defect 130 is formed, for example, extending downward from the groove G. Compressive stress 120 is formed, for example, below the groove G and away from the groove G, and at the leading edge of crystallization defect 130. Compressive stress 120 and crystallization defect 130 can be resolved, for example, by Raman imaging.

[0111] In addition, Figure 9A In the example shown, the two compressive stresses 120 are of different magnitudes. However, the compressive stresses 120 can also be of the same magnitude.

[0112] Next, as Figure 9B As shown, by irradiating a laser from the F2 side of the semiconductor wafer W, a modified portion LM is formed within the semiconductor wafer W along the cutting region Rd. Viewed from the Z direction, the position of the modified portion LM (the laser irradiation position) is formed between two grooves G. Alternatively, multiple modified portions LM can be formed in the Z direction. Here, "between two grooves G" refers to... Figure 9B The two ends of the groove G are shown to be between each other at a width T. That is, when viewed from above, the modified part LM may sometimes overlap with a certain groove G.

[0113] The wavelength of the transmissive laser used for cutting is, for example, 1000 nm to 1400 nm. Furthermore, the focus is set in the cutting area Rd during back-side grinding.

[0114] The crack Wc that develops from the modified part LM is induced to a specified position in the cutting region Rd by compressive stress 120 and crystallization defects 130.

[0115] Crack Wc propagates from the modified portion LM in a direction approximately perpendicular to surfaces F1 and F2. Crack Wc propagates in a manner avoiding compressive stress 120 and penetrates upwards along the fragile crystallization defect 130. Figure 9B In the example shown, the crack Wc changes its path of travel due to the compressive stress 120 below the groove G on the right. Figure 9B The crack Wc approaches the compressive stress 120 at a position slightly to the left of its center, and propagates from the compressive stress 120 toward the groove G on the left. Then, the crack Wc propagates in the Z-direction along the crystallization defect 130 of the groove G on the left. Figure 9B Wc2). That is, the movement path of the crack Wc is controlled by the compressive stress 120 and the crystallization defect 130, and the crack Wc progresses between the two grooves G.

[0116] Next, as Figure 9C As shown, the semiconductor wafer W is monolithically divided into multiple semiconductor chips CH by cleaving it with the modified section LM as the base point. Since each semiconductor chip CH is separated along the crack Wc, ​​it is monolithically divided into multiple semiconductor chips CH. The point where the crack Wc in surface F1 reaches is between two grooves G. The modified section LM appears along the side of the semiconductor chip CH.

[0117] The semiconductor chip CH has a surface F1, a surface F2, and a side surface Fs. Surface F1 is the surface on which semiconductor elements are disposed. Surface F2 is the surface opposite to surface F1. Side surface Fs is the side surface between surface F1 and surface F2. Side surface Fs corresponds to the cut surface during monolithization.

[0118] Furthermore, the semiconductor chip CH has a groove G on its front side (face F1) near the side Fs. Moreover, the crack Wc, ​​which does not necessarily extend along the cutting region Rd entirely between the two grooves G. That is, a portion of the crack Wc may also extend outwards from the multiple grooves G. Viewed from face F1, the groove G extends along the outer periphery of the semiconductor chip CH in at least a portion of its outer periphery.

[0119] Furthermore, the position of the groove G on surface F1 sometimes varies depending on the interval between the two grooves G when they are formed. The wider the interval, the greater the likelihood that the groove G will remain on surface F1. In addition, the two grooves G can also be connected when they are formed.

[0120] In addition, Figure 9C In the example shown, the groove is split at the point where it connects to the groove G. However, it can also be split inside the groove G. In this case, the step difference corresponding to the groove G forms a surface F1 near the side surface Fs.

[0121] Next, for Figure 9C The details of the functional membrane 110 near the groove G will be explained.

[0122] Figure 10A and Figure 10B This is a cross-sectional view showing an example of the configuration of the semiconductor device 100 according to the first embodiment. Figure 10A and Figure 10B yes Figure 9C An enlarged sectional view of the dashed box shown. Figure 10A and Figure 10B A cross-sectional view showing the functional membrane at different locations. Figure 10A This represents a cross-sectional view at the location containing the stacked volume 2_teg. Figure 10B This is a cross-sectional view showing the location where the stacked volume 2_teg is not included. Stacked volume 2_teg and... Figure 7 The layer shown corresponds to 2_teg.

[0123] The semiconductor chip CH has a semiconductor substrate 10, a semiconductor element, a multilayer 2_teg, an interlayer insulating film 60, and a protective film 70.

[0124] The functional film 110 has a semiconductor element, a laminate 2_teg, and an interlayer insulating film 60. Figure 10A The functional film 110 in the cut region Rd shown has a laminate 2_teg and an interlayer insulating film 60. Furthermore, the functional film 110 in the cut region Rd may also have... Figure 7 The transistor Tr_teg is shown.

[0125] The functional film 110 has, for example, a thickness of 3 μm or more and less than 5 μm. The thickness of the functional film 110 varies, for example, depending on the number of layers in the memory cell array (MCA). The thickness of the functional film 110 can also be 5 μm or more and less than 10 μm.

[0126] Semiconductor elements are disposed, for example, in the chip region Rc. These semiconductor elements include, for example, the memory cell array MCA and control circuitry. (See reference...) Figure 2 and Figure 7 As explained, the control circuitry is located below the memory cell array MCA. Viewed from a direction approximately perpendicular to plane F1 (Z direction), the semiconductor element is positioned at the center of the semiconductor chip CH.

[0127] The stack body 2_teg is, for example, set in the dicing region Rd. Viewed from the Z direction, the stack body 2_teg is located at the outer periphery of the semiconductor chip CH.

[0128] like Figure 10A As shown, the stacked volume 2_teg has multiple layers L1 and multiple layers L2 alternately stacked in the Z direction. (Refer to...) Figure 7As explained, the stacked structure of stack 2_teg corresponds to the stacked structure of the memory cell array (MCA). For example, layers L1 and L2 of stack 2_teg correspond to the conductive layer 21 and insulating layer 22 of the memory cell array (MCA), respectively. Furthermore, the stack is configured to extend through stack 2_teg. Figure 7 The slit ST_teg is shown.

[0129] Alternatively, a laminate consisting of alternating layers of two insulators can be used instead of laminate 2_teg.

[0130] The interlayer insulating film 60 is provided in a manner that covers the laminate 2_teg. The interlayer insulating film 60 is, for example, an insulating film. The interlayer insulating film 60 is, for example, a silicon oxide film, or a laminate containing a silicon oxide film and other insulating films (e.g., a silicon nitride film). The interlayer insulating film 60 is formed, for example, using TEOS (Tetraethoxysilane).

[0131] A protective film 70 is disposed on the upper surface of the interlayer insulating film 60. The material of the protective film 70 is, for example, PI (Polyimide).

[0132] like Figure 10B As shown, without the stacked body 2_teg, the interlayer insulating film 60 is set from the upper end to the lower end of the functional film.

[0133] As described above, according to the first embodiment, a plurality of grooves G are formed from the F1 side of the semiconductor wafer W, extending along the dicing region Rd of the semiconductor wafer W and arranged side by side. Furthermore, by irradiating the space between the plurality of grooves G from the F2 side of the semiconductor wafer W, a modified portion LM is formed within the semiconductor wafer W along the dicing region Rd. Additionally, by cleaving the semiconductor wafer W starting from the modified portion LM, the semiconductor wafer W is monolithically divided into a plurality of semiconductor chips CH. Thus, the movement path of the crack Wc is controlled by the compressive stress 120 and the crystallization defect 130, and the crack Wc progresses between the two grooves G. As a result, more suitable monolithicization is possible.

[0134] Figure 11A and Figure 11B This is a cross-sectional view illustrating an example of a manufacturing method for the comparative semiconductor device 100. The comparative example differs from the first embodiment in that a single groove G is formed. Furthermore, in... Figure 11B The modification section (LM) has been omitted.

[0135] The cutting laser irradiates the area below the groove G. In this case, the compressive stress 120 may hinder the propagation of crack Wc from the modified section LM. For example, when crack Wc stops at compressive stress 120, crack Wc will not propagate to surface F1 and will not propagate further. Figure 11BWc3). Additionally, when crack Wc bends due to compressive stress 120, crack Wc may meander or advance in a straight line, causing the crack to progress to a location far from groove G. Figure 11B (Wc4). If the crack Wc travels away from the groove G, it may lead to the risk of chip cracking. In addition, if the functional film 110 becomes more complex or thicker, laser ablation requires a higher output, which may easily produce the aforementioned defects.

[0136] In this regard, in the first embodiment, a modified portion LM is formed between the two grooves G. This prevents the cracks Wc from easily progressing between the two grooves G, thus suppressing the progression and meandering of the cracks Wc. As a result, it is possible to achieve more suitable monolithic construction. Furthermore, the more complex or thicker the functional film 110, the more preferable it is to form the modified portion LM between the two grooves G.

[0137] (Second Implementation)

[0138] Figure 12A and Figure 12B This is a perspective view illustrating an example of a manufacturing method for the semiconductor device 100 according to the second embodiment. The difference between the second embodiment and the first embodiment is that cutting is performed after backside grinding. Figure 12A and Figure 12B The process shown is in Figure 8B The process shown will be carried out after this step.

[0139] After applying protective tape to the front side (F1) of semiconductor wafer W (refer to...) Figure 8B ),like Figure 12A As shown, the back side of the semiconductor wafer W is ground.

[0140] Next, as Figure 12B As shown, proceed with the cutting.

[0141] Then, proceed with... Figure 8F and Figure 8G The same process.

[0142] As described in the second embodiment, cutting can also be performed after grinding the back side. In this case, the same effect as in the first embodiment can be obtained.

[0143] (Third Implementation)

[0144] Figure 13 This is a cross-sectional view illustrating an example of a method for manufacturing the semiconductor device 100 according to the third embodiment. The difference between the third embodiment and the first embodiment is that laser ablation is performed with high output.

[0145] In addition, Figure 13 The modification section (LM) has been omitted.

[0146] The formation conditions of the groove G are used to induce cracks Wc that propagate from the modified section LM. The formation conditions of the groove G include, for example, at least one of the position and number of grooves G on the cutting region Rd, and the irradiation conditions of the laser forming the groove G. The irradiation conditions include, for example, at least one of the output and number of laser ablation beams.

[0147] The magnitude of the compressive stress 120 and the depth of the crystallization defect 130 can be controlled by the output of the laser ablation, the irradiation spacing, the number of beams, or the focal position. Therefore, the movement path of the crack Wc can be controlled by adjusting the output of the laser ablation, the irradiation spacing, the number of beams, or the focal position.

[0148] exist Figure 13 In the example shown, the output when the right groove G is formed is greater than the output when the left groove G is formed. Therefore, the compressive stress 120 of the right groove G is greater than that of the left groove G. Furthermore, the crystallization defect 130 of the right groove G is deeper than that of the left groove G. As a result, the flexibility of the crack Wc can be improved. In addition, the compressive stress 120 and the crystallization defect 130 may vary depending on the irradiation spacing, the number of beams, or the focal point position. The focal point of the laser irradiated from surface F2 is preferably aimed at a distance of approximately 5 μm from the center of the region forming the compressive stress 120 toward the adjacent groove.

[0149] As described in the third embodiment, high-output laser ablation can also be performed. In this case, the same effect as in the first embodiment can be obtained. Furthermore, the compressive stress 120 and crystal defects 130 may vary depending on the irradiation spacing, the number of beams, or the focal point position.

[0150] (Fourth implementation)

[0151] Figure 14 This is a cross-sectional view illustrating an example of a method for manufacturing the semiconductor device 100 according to the fourth embodiment. The difference between the fourth embodiment and the first embodiment is that laser ablation is performed on the same location using multiple beams.

[0152] The depth of the crystallization defect 130 can be controlled by the laser ablation output, irradiation spacing, number of beams, or focal position. Therefore, the movement path of the crack Wc can be controlled by adjusting the laser ablation output, irradiation spacing, number of beams, or focal position.

[0153] exist Figure 14 In the example shown, the number of beams when the right-hand groove G is formed is greater than the number of beams when the left-hand groove G is formed. Therefore, the crystallization defect 130 of the right-hand groove G is deeper than that of the left-hand groove G. As a result, the meandering of the crack Wc can be suppressed. Furthermore, the crystallization defect 130 may also vary due to factors such as output, irradiation spacing, or focal spot position.

[0154] As described in the fourth embodiment, multiple beams can also be used to perform laser ablation on the same location. In this case, the same effect as in the first embodiment can be obtained. Furthermore, the crystallization defect 130 may vary depending on the output, irradiation spacing, or focal point position, etc.

[0155] (Fifth Embodiment)

[0156] Figure 15 This is a cross-sectional view illustrating an example of a manufacturing method for the semiconductor device 100 according to the fifth embodiment. The difference between the fifth embodiment and the first embodiment is that three slots G are formed.

[0157] exist Figure 15 In the example shown, three slots G are formed. Furthermore, in a portion of slots G, laser ablation with high output and multiple beams, as described in the third and fourth embodiments, is performed.

[0158] The modified section LM is located between the left-side groove G and the central groove G. Even if the crack Wc passes through the crystallization defect 130 of the central groove G, it will also pass through surface F1 along the crystallization defect 130 of the right-side groove G. Therefore, by increasing the number of grooves G, the propagation of the crack Wc can be easily stopped. Figure 15 The paper's lateral movement is thus prevented. This, in turn, inhibits the meandering of the cracked Wc. Consequently, cracked Wc can be easily induced.

[0159] Furthermore, the position of the modified section LM can also be between the left groove G and the right groove G. That is, during cutting, the laser irradiates the area between the outermost two grooves G of the three grooves G (or multiple grooves G).

[0160] In addition, depending on the location of the crack Wc, ​​the monolithic semiconductor chip CH can also have multiple slots G that extend along the outer periphery and are arranged side by side.

[0161] As described in the fifth embodiment, three slots G can also be formed. In this case, the same effect as in the first embodiment can be obtained.

[0162] (Sixth Embodiment)

[0163] Figure 16A and Figure 16B This is a cross-sectional view illustrating an example of a method for manufacturing the semiconductor device 100 according to the sixth embodiment. The difference between the sixth embodiment and the first embodiment is that the depth of the two trenches G extends into the interior of the functional film 110. Figure 16A and Figure 16B The process shown is the same as that in the first embodiment. Figure 9A and Figure 9B The process shown corresponds to the steps.

[0164] In addition, Figure 16A and Figure 16B The image shows compressive stress 120 and crystallization defect 130 together.

[0165] Two trenches G are formed. The two trenches G extend from the surface F1 into the interior of the functional film 110. That is, the two trenches G have a depth from the surface F1 that does not reach the semiconductor substrate 10.

[0166] Even if the direction of the crack Wc deviates from the center of the cutting area Rd, the groove G or the compressive stress 120 or crystallization defect 130 formed by laser ablation can prevent the crack Wc from deviating to the outside of the compressive stress 120 or crystallization defect 130.

[0167] Furthermore, the two grooves G have the same depth. Between the two grooves G, the position and magnitude of the crystallization defect 130 and the compressive stress 120 in the Z direction are the same. That is, the two grooves G are formed using the same conditions. However, the two grooves G can also be formed using different conditions. In addition, the width G1 of the grooves G is smaller than the spacing between them. In other words, the width of the ungrouted portion S between the grooves G is greater than the width G1 of the grooves G.

[0168] As described in the sixth embodiment, the depth of the two grooves G can also reach the interior of the functional membrane 110. In this case, the same effect as in the first embodiment can also be obtained.

[0169] (Seventh Embodiment)

[0170] Figure 17A and Figure 17B This is a cross-sectional view illustrating an example of a method for manufacturing the semiconductor device 100 according to the seventh embodiment. The difference between the seventh embodiment and the sixth embodiment is that a plurality of trenches G reach the semiconductor substrate 10.

[0171] The two grooves G have a depth that extends from the surface F1 through the functional film 110 to the semiconductor substrate 10.

[0172] The deeper the groove G, the easier it is to suppress the meandering of the crack Wc. However, a deeper groove G may be more difficult to excavate, and the excavation time may be longer. On the other hand, a shallower groove G may result in lower compressive stress 120, making it less likely for the crack Wc to meander. The depth of the groove G can also be set, for example, based on factors such as the ease of meandering of the actual crack Wc.

[0173] Furthermore, the two grooves G have the same depth. Between the two grooves G, the position and magnitude of the crystallization defect 130 and the compressive stress 120 in the Z direction are the same. That is, the two grooves G are formed under the same conditions. However, the two grooves G can also be formed under different conditions.

[0174] As described in the seventh embodiment, multiple trenches G can also reach the semiconductor substrate 10. In this case, the same effect as in the sixth embodiment can also be obtained.

[0175] (Eighth Embodiment)

[0176] Figure 18A and Figure 18B This is a cross-sectional view illustrating an example of a manufacturing method for the semiconductor device 100 according to the eighth embodiment. The difference between the eighth embodiment and the sixth embodiment is that three slots G are formed.

[0177] Three trenches G are formed. The three trenches G extend from the surface F1 into the interior of the functional film 110. That is, the three trenches G have a depth that does not reach the semiconductor substrate 10. Furthermore, the width G1 of each trench G is smaller than the spacing between the trenches. In other words, the width of the un-trenched portion S between the trenches G is greater than the width G1 of the trenches G.

[0178] With reference Figure 15 Similarly, in the fifth embodiment described, the greater the number of grooves G, the more effectively the meandering of the crack Wc can be suppressed. As a result, it is easier to induce crack Wc.

[0179] As described in embodiment 8, three slots G can also be formed. In this case, the same effect as in embodiment 6 can be obtained. Furthermore, with three slots G formed, when the chip is monolithically assembled, two slots G can be retained on either of two adjacent chips. When multiple slots are retained, the adhesion between the chip tip and the molding resin is improved.

[0180] (9th embodiment)

[0181] Figure 19A and Figure 19B This is a cross-sectional view illustrating an example of a method for manufacturing the semiconductor device 100 according to the ninth embodiment. The difference between the ninth embodiment and the eighth embodiment is that three trenches G reach the semiconductor substrate 10. In other words, the ninth embodiment is a combination of the seventh and eighth embodiments.

[0182] The three grooves G have a through-film 110 that reaches the depth of the semiconductor substrate 10.

[0183] As described in the ninth embodiment, the three trenches G can also reach the semiconductor substrate 10. In this case, the same effect as in the eighth embodiment can also be obtained.

[0184] (10th Embodiment)

[0185] Figure 20A and Figure 20BThis is a cross-sectional view illustrating an example of a manufacturing method for the semiconductor device 100 according to the tenth embodiment. The difference between the tenth embodiment and the sixth embodiment is that four slots G are formed.

[0186] Four trenches G are formed. The four trenches G extend from the surface F1 into the interior of the functional film 110. That is, the four trenches G have a depth that does not reach the semiconductor substrate 10. Furthermore, the width G1 of the trenches G is smaller than the spacing between the trenches. In other words, the width of the ungrooved portion S between the trenches G is greater than the width G1 of the trenches G.

[0187] As described in the 10th embodiment, four slots G can also be formed. In this case, the same effect as in the 6th embodiment can be obtained. Furthermore, with four slots G formed, when the chip is monolithically assembled, two to three slots G can be retained on any one of two adjacent chips. When multiple slots are retained, the adhesion between the chip tip and the molding resin is improved.

[0188] (11th Embodiment)

[0189] Figure 21A and Figure 21B This is a cross-sectional view illustrating an example of a method for manufacturing the semiconductor device 100 according to the 11th embodiment. The 11th embodiment differs from the 8th embodiment in that four trenches G reach the semiconductor substrate 10. In other words, the 11th embodiment is a combination of the 7th and 10th embodiments.

[0190] The four grooves G have a through-film 110 that reaches the depth of the semiconductor substrate 10.

[0191] As described in the 11th embodiment, the four trenches G can also reach the semiconductor substrate 10. In this case, the same effect as in the 10th embodiment can also be obtained.

[0192] (12th implementation)

[0193] Figure 22A and Figure 22B This is a cross-sectional view illustrating an example of a method for manufacturing the semiconductor device 100 according to the 12th embodiment. The difference between the 12th embodiment and the 6th embodiment is that five slots G are formed.

[0194] Five trenches G are formed. The five trenches G extend from the surface F1 into the interior of the functional film 110. That is, the five trenches G have a depth that does not reach the semiconductor substrate 10. Furthermore, the width G1 of each trench G is smaller than the spacing between the trenches. In other words, the width of the un-trenched portion S between the trenches G is greater than the width G1 of the trenches G.

[0195] As described in embodiment 12, five slots G can also be formed. In this case, the same effect as in embodiment 6 can be obtained. Furthermore, with five slots G formed, when the chip is monolithically assembled, two to four slots G can be retained on any one of two adjacent chips. When multiple slots are retained, the adhesion between the chip tip and the molding resin is improved.

[0196] (13th implementation)

[0197] Figure 23A and Figure 23B This is a cross-sectional view illustrating an example of a method for manufacturing the semiconductor device 100 according to the 13th embodiment. The difference between the 13th embodiment and the 12th embodiment is that five trenches G reach the semiconductor substrate 10. In other words, the 13th embodiment is a combination of the 7th and 12th embodiments.

[0198] The five grooves G have a through-film 110 that reaches the depth of the semiconductor substrate 10.

[0199] As described in embodiment 13, the five trenches G can also reach the semiconductor substrate 10. In this case, the same effect as in embodiment 12 can also be obtained.

[0200] (14th embodiment)

[0201] Figure 24A and Figure 24B This is a cross-sectional view illustrating an example of a manufacturing method for the semiconductor device 100 according to the 14th embodiment. The difference between the 14th embodiment and the 6th embodiment is that six slots G are formed.

[0202] Six trenches G are formed. The six trenches G extend from the surface F1 into the interior of the functional film 110. That is, the six trenches G have a depth that does not reach the semiconductor substrate 10. Furthermore, the width G1 of each trench G is greater than the spacing between the trenches. In other words, the width of the un-trenched portion S between the trenches G is smaller than the width G1 of the trenches G.

[0203] As described in embodiment 14, six slots G can also be formed. In this case, the same effect as in embodiment 6 can be obtained. Furthermore, with six slots G formed, when the chip is monolithically assembled, two to five slots G can be retained on any one of two adjacent chips. When multiple slots are retained, the adhesion between the chip tip and the molding resin is improved.

[0204] (15th implementation)

[0205] Figure 25A and Figure 25BThis is a cross-sectional view illustrating an example of a method for manufacturing the semiconductor device 100 according to the 15th embodiment. The difference between the 15th embodiment and the 14th embodiment is that six trenches G reach the semiconductor substrate 10. In other words, the 15th embodiment is a combination of the 7th and 14th embodiments.

[0206] The six grooves G have a through-film 110 that reaches the depth of the semiconductor substrate 10.

[0207] As described in embodiment 15, the six trenches G can also reach the semiconductor substrate 10. In this case, the same effect as in embodiment 14 can also be obtained.

[0208] (Sixteenth Embodiment)

[0209] Figure 26A and Figure 26B This is a cross-sectional view illustrating an example of a manufacturing method for the semiconductor device 100 according to the 16th embodiment. The difference between the 16th embodiment and the 6th embodiment is that seven slots G are formed.

[0210] Seven trenches G are formed. These seven trenches G extend from the surface F1 into the interior of the functional film 110. That is, the seven trenches G have a depth that does not reach the semiconductor substrate 10. Furthermore, the width G1 of each trench G is greater than the spacing between the trenches. In other words, the width of the un-trenched portion S between the trenches G is less than the width G1 of the trenches G.

[0211] As described in embodiment 16, seven slots G can also be formed. In this case, the same effect as in embodiment 6 can be obtained. Furthermore, with seven slots G formed, when the chip is monolithically assembled, two to six slots G can be retained on any one of two adjacent chips. Retaining multiple slots improves the adhesion between the chip ends and the molding resin.

[0212] (17th embodiment)

[0213] Figure 27A and Figure 27B This is a cross-sectional view illustrating an example of a method for manufacturing the semiconductor device 100 according to the 17th embodiment. The difference between the 17th and 16th embodiments is that the 7 trenches G reach the semiconductor substrate 10. In other words, the 17th embodiment is a combination of the 7th and 16th embodiments.

[0214] The seven grooves G have a through-film 110 that reaches the depth of the semiconductor substrate 10.

[0215] In addition, more than 8 slots G can be set.

[0216] As described in embodiment 17, the seven trenches G can also reach the semiconductor substrate 10. In this case, the same effect as in embodiment 16 can also be obtained.

[0217] As the width of the flat portion S decreases, the induction of cracks Wc becomes easier. However, when the number of grooves G is small, the focus of the laser in the XY direction irradiated from the surface F2 side tends to deviate from the grooves G. When the number of grooves G is large, the laser focus is less likely to deviate, but the grooves G require multiple processing steps. As the width of the flat portion S increases, cracks Wc tend to meander between the flat portions S. However, even with a small number of grooves G, the focus of the laser in the XY direction irradiated from the surface F2 side is less likely to deviate from the grooves G. The relationship between the number of grooves G and the flat portion S can be appropriately adjusted. For example, when the number of grooves G is 2 to 4, the width G1 of the grooves can be narrower than the width of the flat portion S. For example, when the number of grooves G is 5 or more, the width G1 of the grooves can be greater than the width of the flat portion S.

[0218] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways and can be omitted, substituted, or modified in various ways without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, as well as in the invention as described in the claims and its equivalents.

[0219] [Explanation of Symbols]

[0220] 100: Semiconductor devices

[0221] 10: Semiconductor substrate

[0222] 110: Functional membrane

[0223] 120: Compressive stress

[0224] 130: Crystallization defects

[0225] CH: Semiconductor chip

[0226] F1: Face

[0227] F2: Face

[0228] Fs: Side view

[0229] G: slot

[0230] LM: Quality Improvement Department

[0231] Rd: Cutting area

[0232] W: Semiconductor wafer

[0233] Wc: cracked.

Claims

1. A method for manufacturing a semiconductor device, comprising the following steps: A first trench and a second trench are formed on a first surface of a semiconductor wafer. The first trench and the second trench extend along a dicing region of the semiconductor wafer having the first surface and a second surface located on the opposite side of the first surface and are arranged side by side. A first laser is irradiated from the second surface of the semiconductor wafer between the first and second grooves when viewed from above, thereby forming a modified portion within the semiconductor wafer along the dicing region; and By cleaving the semiconductor wafer, the semiconductor wafer is monolithically divided into multiple semiconductor chips.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the step of cleaving the semiconductor wafer comprises: The semiconductor wafer is split open, starting from the modified part.

3. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the first trench and the second trench comprises: forming regions corresponding to the first trench and the second trench that generate compressive stress and crystal defects.

4. The method of manufacturing a semiconductor device according to claim 1, wherein a third groove extending along the dicing region is formed on the first surface of the semiconductor wafer. The third slot is located between the first slot and the second slot.

5. The method of manufacturing a semiconductor device according to claim 1, wherein the width of the portion formed between the first trench and the second trench is smaller than the width of the first trench.

6. The method of manufacturing a semiconductor device according to claim 1, wherein the width of the portion formed between the first trench and the second trench is greater than the width of the first trench.

7. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor wafer comprises: Semiconductor substrate, including the second surface; and The film includes the first surface and the semiconductor element; The first trench and the second trench are formed to penetrate the film from the first surface side to a depth reaching the semiconductor substrate.

8. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor wafer comprises: Semiconductor substrate, including the second surface; and The film includes the first surface and the semiconductor element; The first trench and the second trench are formed at a depth that does not reach the semiconductor substrate from the first surface side.

9. The method for manufacturing a semiconductor device according to claim 7 or 8, wherein the thickness of the film is 5 μm or more and less than 10 μm.

10. A method for manufacturing a semiconductor device according to any one of claims 1 to 8, wherein the first trench and the second trench are formed by laser ablation using a second laser.

11. The method of manufacturing a semiconductor device according to claim 10, wherein the wavelength of the first laser is from 1000 nm to 1400 nm. The wavelength of the second laser is below 600 nm and the pulse width is below 10 nm.

12. A semiconductor device having a first surface and a second surface opposite to the first surface. The semiconductor device further comprises: A semiconductor element, when viewed from a direction perpendicular to the first surface, is disposed at the center of the semiconductor device; At least two slots, when viewed from a direction perpendicular to the first surface, extend along at least a portion of the outer peripheral end of the semiconductor device; and A modified part is formed on the side of the semiconductor device.

13. The semiconductor device of claim 12, comprising regions generating compressive stress and crystal defects respectively corresponding to the at least two trenches.

14. The semiconductor device of claim 12, wherein the semiconductor device comprises: Semiconductor substrate, including the second surface; and The film includes the first surface and the semiconductor element; The depth of at least two of the trenches does not reach the semiconductor substrate.

15. The semiconductor device of claim 12, wherein the semiconductor device comprises: Semiconductor substrate, including the second surface; and The film includes the first surface and the semiconductor element; The depth of the at least two trenches reaches the semiconductor substrate.

16. The semiconductor device according to any one of claims 12 to 15, wherein the width of the portion formed between the two said trenches is less than the width of one of the at least two trenches.

17. The semiconductor device according to any one of claims 12 to 15, wherein the width of the portion formed between the two said trenches is greater than the width of one of the at least two trenches.

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