Package carrier unit and preparation method thereof
By indenting the sidewalls of the glass substrate unit and combining it with an edge protection layer and a protective structure, the problem of easy damage to the glass substrate unit after cutting is solved, thereby improving the reliability and performance of the packaging carrier unit.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SUZHOU GUOXIAN INNOVATION TECHNOLOGY CO LTD
- Filing Date
- 2026-04-15
- Publication Date
- 2026-05-12
AI Technical Summary
In traditional packaging substrates, the glass substrate units are easily damaged after cutting, affecting the reliability of the packaging.
By recessing the sidewalls of the glass substrate unit relative to the sidewalls of the dielectric layer unit, and combining an edge protection layer and a protective structure, the dielectric layer protects the glass substrate unit from damage during production, transportation, or use.
It improves the reliability and performance of the packaging carrier unit, prevents edge damage to the glass substrate unit, and enhances the overall packaging stability.
Smart Images
Figure CN122028757A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor packaging technology, and in particular to a packaging carrier unit and its preparation method. Background Technology
[0002] Compared to silicon substrates, glass substrates have advantages such as low loss, high mechanical stability, low cost, and the ability to achieve large-size and ultra-thin designs. Therefore, they have attracted widespread attention and have broad application prospects, and are used in fields such as optical communication, radio frequency modules, optoelectronic system integration, consumer electronics, electronic power amplifiers, and medical devices.
[0003] The performance of the current packaging substrate needs to be improved. Summary of the Invention
[0004] Based on this, this application provides a packaging carrier unit and its preparation method, which can effectively improve the performance of the packaging carrier unit.
[0005] In a first aspect, this application provides a packaging carrier unit, comprising: A glass substrate unit includes a glass through-hole disposed along the thickness direction and a conductive post filling the glass through-hole; A redistribution layer unit is disposed on at least one side of the glass substrate unit. The redistribution layer unit includes a conductive line layer and a dielectric layer unit. The conductive line layer passes through the dielectric layer unit and is electrically connected to the conductive pillar. The sidewall of the glass substrate unit is recessed relative to the sidewall of the dielectric layer unit in a direction parallel to the surface of the glass substrate unit and close to the center of the glass substrate unit.
[0006] In one embodiment, an edge protection layer is also included, which covers the sidewalls of the glass substrate unit.
[0007] In one embodiment, the edge protection layer at least partially covers the sidewalls of the dielectric layer; In one embodiment, the material of the edge protection layer includes at least one of organic epoxy materials, silane materials, or polyimide materials.
[0008] In one embodiment, the orthographic projection of the sidewall of the glass substrate unit onto the target plane does not overlap with the orthographic projection of the sidewall of the dielectric layer unit onto the target plane, and is located within the orthographic projection of the dielectric layer unit onto the target plane; wherein the target plane is parallel to the surface of the glass substrate unit.
[0009] In one embodiment, a protective structure is further included, the protective structure including an embedded portion and an extension portion, the embedded portion being disposed between the glass substrate unit and the dielectric layer unit, and the extension portion extending from the embedded portion in a direction parallel to the surface of the glass substrate unit and away from the center of the glass substrate unit, and extending beyond the sidewall of the glass substrate unit.
[0010] In one embodiment, the protective structure and the conductive circuit layer are made of the same material and are prepared using the same process.
[0011] In one embodiment, the materials of the protective structure and the conductive line layer include copper.
[0012] In one embodiment, the sidewall of the glass substrate unit is recessed by 50-200 μm relative to the sidewall of the dielectric layer unit in a direction parallel to the surface of the glass substrate unit and close to the center of the glass substrate unit.
[0013] In one embodiment, the packaging carrier unit further includes an ink layer disposed on the side of the redistribution layer away from the glass substrate, the ink layer having an opening exposing the conductive circuit layer, and conductive bumps disposed within the opening.
[0014] The second invention provides a method for preparing a packaged carrier unit, comprising: A packaging carrier is provided; wherein the packaging carrier includes a glass substrate and a redistribution layer, the glass substrate includes a glass via disposed through the thickness direction and a conductive post filling the glass via, the redistribution layer is disposed on at least one side of the glass substrate, the redistribution layer includes a conductive line layer and a dielectric layer, the conductive line layer passes through the dielectric layer and is electrically connected to the conductive post; Remove the dielectric layer on the dicing groove of the packaging substrate to form a plurality of dielectric layer units; The glass substrate is cut along the cutting path to form multiple glass substrate units; The sidewalls of the glass substrate unit are etched so that the sidewalls of the glass substrate unit are recessed relative to the sidewalls of the dielectric layer unit in a direction parallel to the surface of the glass substrate unit and close to the center of the glass substrate unit.
[0015] In one embodiment, after etching the sidewalls of the glass substrate unit to make the sidewalls of the glass substrate unit recessed relative to the sidewalls of the dielectric layer unit in a direction parallel to the surface of the glass substrate unit and close to the center of the glass substrate unit, the method further includes: An edge protection layer is formed on the sidewall of the glass substrate unit; Preferably, after cutting the glass substrate along the cutting path to form a plurality of glass substrate units; before etching the sidewalls of the glass substrate units so that the sidewalls of the glass substrate units are recessed relative to the sidewalls of the dielectric layer units in a direction parallel to the surface of the glass substrate units and close to the center of the glass substrate units, the method further includes: The glass substrate unit is modified.
[0016] In one embodiment, after etching the sidewalls of the glass substrate unit to make the sidewalls of the glass substrate unit recessed relative to the sidewalls of the dielectric layer unit in a direction parallel to the surface of the glass substrate unit and close to the center of the glass substrate unit, before forming an edge protection layer on the sidewalls of the glass substrate, the method further includes: An edge protection material layer is formed on the sidewall of the glass substrate unit and the sidewall of the dielectric layer unit; The edge protection material layer is trimmed to form the edge protection layer.
[0017] In one embodiment, the packaging substrate further includes an ink layer disposed on the side of the redistribution layer away from the glass substrate unit, the ink layer having an opening that exposes the conductive circuit layer; After cutting the glass substrate along the cutting path to form multiple glass substrate units; after etching the sidewalls of the glass substrate units, before the sidewalls of the glass substrate units are recessed relative to the sidewalls of the dielectric layer units in a direction parallel to the surface of the glass substrate units and close to the center of the glass substrate units, the method further includes: A first protective layer is formed on the ink layer and on the side of the opening away from the glass substrate unit.
[0018] The packaging substrate further includes an ink layer disposed on the side of the redistribution layer away from the glass substrate, and the ink layer has an opening that exposes the conductive circuit layer. In one embodiment, after etching the sidewalls of the glass substrate unit, and then causing the sidewalls of the glass substrate unit to be recessed relative to the sidewalls of the dielectric layer unit in a direction parallel to the surface of the glass substrate unit and close to the center of the glass substrate unit, the method further includes: Remove the first protective layer.
[0019] After cutting the glass substrate along the cutting path to form multiple glass substrate units; after etching the sidewalls of the glass substrate units, before the sidewalls of the glass substrate units are recessed relative to the sidewalls of the dielectric layer units in a direction parallel to the surface of the glass substrate units and close to the center of the glass substrate units, the method further includes: A first protective layer is formed on the ink layer and on the side of the opening away from the glass substrate unit, and a second protective layer is formed on the sidewall of the redistribution layer unit.
[0020] In one embodiment, after etching the sidewalls of the glass substrate unit, and then causing the sidewalls of the glass substrate unit to be recessed relative to the sidewalls of the dielectric layer unit in a direction parallel to the surface of the glass substrate unit and close to the center of the glass substrate unit, the method further includes: An edge protection layer is formed on the sidewall of the glass substrate unit and on the side of the second protective layer away from the dielectric layer unit; Remove the first protective layer and retain the second protective layer.
[0021] In one embodiment, after etching the sidewalls of the glass substrate unit to make the sidewalls of the glass substrate unit recessed relative to the sidewalls of the dielectric layer unit in a direction parallel to the surface of the glass substrate unit and close to the center of the glass substrate unit, the method further includes: Conductive bumps that are electrically connected to the conductive line layer are formed within the opening.
[0022] The packaging carrier unit provided in this application, by retracting the sidewall of the glass substrate unit relative to the sidewall of the dielectric layer unit in a direction parallel to the surface of the glass substrate unit and close to the center of the glass substrate unit, effectively protects the sidewall of the glass substrate unit with the dielectric layer, avoiding damage to the glass substrate unit during production, transportation or use, which helps to improve packaging reliability and improve the performance of the packaging carrier unit. Attached Figure Description
[0023] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0024] Figure 1 This is a cross-sectional structural diagram of a related packaging carrier board; Figure 2 This is a schematic diagram of the cross-sectional structure of a related packaging substrate after cutting. Figure 3 This is a cross-sectional structural schematic diagram of the encapsulation carrier unit in one embodiment of this application; Figure 4 This is a cross-sectional structural diagram of the encapsulation carrier board in one embodiment of this application; Figure 5 This is a cross-sectional structural schematic diagram of the encapsulation carrier unit in another embodiment of this application; Figure 6 This is a cross-sectional structural schematic diagram of the encapsulation carrier unit in another embodiment of this application; Figure 7 This is a cross-sectional structural schematic diagram of the encapsulation carrier unit in another embodiment of this application; Figure 8 This is a schematic diagram of the orthographic projection of the sidewall of the glass substrate unit and the sidewall of the dielectric layer unit onto the target plane in another embodiment of this application. Figure 9 This is a cross-sectional structural schematic diagram of the encapsulation carrier unit in another embodiment of this application; Figure 10 This is a cross-sectional structural schematic diagram of the encapsulation carrier unit in another embodiment of this application; Figure 11 This is a flowchart of a method for preparing a packaging carrier unit in another embodiment of this application; Figure 12 This is a schematic diagram of the process for preparing the encapsulation carrier unit in another embodiment of this application; Figure 13 This is a schematic diagram of the process for preparing the encapsulation carrier unit in another embodiment of this application; Figure 14 This is a schematic diagram of the process for preparing the encapsulation carrier unit in another embodiment of this application; Figure 15 This is a schematic diagram of the process for preparing the encapsulation carrier unit in another embodiment of this application; Figure 16 This is a schematic diagram of the process for preparing the encapsulation carrier unit in another embodiment of this application; Figure 17 This is a schematic diagram of the process for preparing the encapsulation carrier unit in another embodiment of this application; Figure 18 This is a schematic diagram of the process for preparing the encapsulation carrier unit in another embodiment of this application.
[0025] Marker explanation: 100. Encapsulation carrier; 10. Glass substrate; 11. Glass substrate unit; 20. Redundancy layer; 21. Dielectric layer; 22. Conductive circuit layer; 30. Cutting track; 40. Encapsulation carrier unit; 51. Conductive pillar; 60. Redundancy layer unit; 61. Dielectric layer unit; 70. Edge protection layer; 71. Edge protection material layer; 72. First protective layer; 73. Second protective layer; 80. Protective structure; 81. Embedded portion; 82. Extension portion; 90. Ink layer; 91. Opening; 92. Conductive bump. Detailed Implementation
[0026] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.
[0027] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0028] With the rapid development of information technology, the demands on chip computing power, bandwidth, energy efficiency, and integration density are increasing exponentially. Traditional organic packaging substrates face bottlenecks in handling ultra-high frequency signal transmission (e.g., >100GHz) and high-density interconnects due to their high dielectric loss and limited dimensional stability. Against this backdrop, glass core substrates stand out with their unique material properties and are considered the preferred substrate material for next-generation advanced packaging. Their core advantages include: extremely low dielectric constant and loss factor, which can significantly reduce signal transmission delay and attenuation, meeting the stringent requirements of artificial intelligence chips for ultra-high bandwidth and low-power interconnects; ultra-high surface flatness and dimensional stability, supporting the fabrication of submicron-level fine lines and multi-layer stacking alignment; excellent insulation resistivity, which can effectively isolate high-frequency signals and reduce crosstalk; adjustable coefficient of thermal expansion, which can achieve good matching with chip materials such as silicon and compound semiconductors, improving thermomechanical reliability; and optical transparency and compatibility with optical waveguide processes, which provide possibilities for optoelectronic co-packaging and embedding passive devices.
[0029] However, glass is a typical brittle material, with fracture toughness far lower than that of silicon or organic materials, and is extremely sensitive to defects and stress concentration. When subjected to mechanical or thermal stress impacts, it is highly susceptible to crack formation and rapid propagation, leading to overall failure.
[0030] Reference Figure 1 As shown, in the manufacturing process of a related encapsulation substrate 100, glass vias are first fabricated and metallized on a glass substrate 10. Then, a redistribution layer 20, consisting of a dielectric layer 21 and a conductive line layer 22, is formed on both sides of the substrate through lamination or other methods. Next, the dielectric layer 21 on the dicing groove 30 is removed. Finally, the entire encapsulation substrate 100 is cut along the dicing groove 30 into multiple encapsulation substrate units 40, as shown in the figure. Figure 2 As shown.
[0031] Through in-depth research and production practice, the inventors of this application have discovered that in the cut packaging carrier unit 40, the dielectric layer unit 61 is recessed within the glass substrate unit 11, causing the edges of the glass substrate unit 11 to be exposed. During production, transportation, or use, the edges of the glass substrate unit 11 are easily damaged, thereby affecting the packaging reliability.
[0032] Therefore, this application provides a packaging carrier unit solution to solve the above-mentioned technical problems.
[0033] like Figure 3 As shown, one embodiment of this application provides a packaging carrier unit 40, including a glass substrate unit 11 and a redistribution layer unit 60. The glass substrate unit 11 includes a glass through-hole disposed along the thickness direction and a conductive post 51 filling the glass through-hole. The redistribution layer unit 60 is disposed on at least one side of the glass substrate unit 11. The redistribution layer unit 60 includes a conductive line layer 22 and a dielectric layer unit 61. The conductive line layer 22 passes through the dielectric layer unit 61 and is electrically connected to the conductive post 51.
[0034] The sidewall S1 of the glass substrate unit 11 is recessed relative to the sidewall S2 of the dielectric layer unit 61 in a direction parallel to the surface of the glass substrate unit 11 and close to the center of the glass substrate unit 11 (as shown by the arrow in the figure).
[0035] The packaging carrier unit 40 provided in this embodiment reduces the sidewall S1 of the glass substrate unit 11 relative to the sidewall S2 of the dielectric layer unit 61 in a direction parallel to the surface of the glass substrate unit 11 and close to the center of the glass substrate unit 11. The dielectric layer 21 effectively protects the sidewall S1 of the glass substrate unit 11, preventing damage to the glass substrate unit 11 during production, transportation or use, which helps to improve packaging reliability and improve the performance of the packaging carrier unit 40.
[0036] Reference Figure 3 and4 As shown, the encapsulation carrier unit 40 is cut from the encapsulation carrier 100 along the cutting channel 30. The cutting is carried out in two steps. The first step is to remove the dielectric layer 21 in the area of the cutting channel 30 and divide the redistribution layer 20 into multiple redistribution layer units 60. The second step is to cut the glass substrate 10 along the cutting channel 30 and divide the glass substrate 10 into multiple glass substrate units 11.
[0037] Optionally, the sidewall S1 of the glass substrate unit 11 is etched inward relative to the sidewall S2 of the dielectric layer unit 61 in a direction parallel to the surface of the glass substrate unit 11 and close to the center of the glass substrate unit 11. Specifically, the glass substrate unit 11 is laterally etched using an etching solution.
[0038] Optionally, the redistribution layer unit 60 is disposed on both sides of the glass substrate unit 11, and the sidewall S1 of the glass substrate unit 11 is recessed inward in a direction parallel to the surface of the glass substrate unit 11 and close to the center of the glass substrate unit 11 relative to the sidewall S2 of the dielectric layer units 61 on both sides, thereby achieving better protection for the glass substrate unit 11.
[0039] The inward shrinkage should not be too small, so that the dielectric layer 21 can effectively protect the sidewalls of the glass substrate 10, preventing damage to the glass substrate unit 11 during production, transportation, or use, and thus improving packaging reliability. At the same time, the inward shrinkage should not be too large, to avoid increasing process complexity and wasting the glass substrate 10. Therefore, optionally, the sidewall S1 of the glass substrate unit 11 is 50-200 μm inward relative to the sidewall S2 of the dielectric layer unit 61 in a direction parallel to the surface of the glass substrate unit 11 and close to the center of the glass substrate unit 11.
[0040] For example, the sidewall of the glass substrate unit 11 is recessed by a dimension H relative to the sidewall of the dielectric layer unit 61 in a direction parallel to the surface of the glass substrate unit 11 and close to the center of the glass substrate unit 11. The specific size is not limited.
[0041] Reference Figure 5 As shown, in one embodiment, the packaging carrier unit 40 further includes an edge protection layer 70, which covers the sidewall S1 of the glass substrate unit 11. The edge protection layer 70 effectively protects the sidewall S1 of the glass substrate unit 11, preventing damage during production, transportation, or use, and improving packaging reliability.
[0042] Optionally, the edge protection layer 70 is made of at least one of organic epoxy materials, silane materials, or polyimide materials. These materials have properties such as low modulus and high temperature resistance, and can provide buffer protection for the sidewalls S1 of the glass substrate unit 11. For example, organic epoxy materials include bisphenol A type epoxy resin, epoxy laminated glass cloth, epoxy-modified Ajinomoto film, etc.; silane materials include epoxy-based silane coupling agents, amino-based silane coupling agents, vinyltrimethoxysilane, silane-modified epoxy coating agents, etc.; and polyimide materials include pyromellitic polyimide films, biphenyl polyimide films, thermosetting polyimide coating agents, etc.
[0043] Reference Figure 6 As shown, in one embodiment, the edge protection layer 70 protrudes from the sidewall S2 of the dielectric layer unit 61 in a direction parallel to the surface of the glass substrate unit 11 and close to the center of the glass substrate unit 11, that is, the thickness of the edge protection layer 70 is greater than H, thereby improving the protection effect on the glass substrate unit 11.
[0044] Reference Figure 7 As shown, in one embodiment, the edge protection layer 70 at least partially covers the sidewall S2 of the dielectric layer 21. The edge protection layer 70 effectively protects the connection between the dielectric layer 21 and the glass substrate unit 11, while also enhancing the adhesion of the edge protection layer 70 to prevent damage and detachment of the dielectric layer 21 during production, transportation, or use, thereby further improving packaging reliability.
[0045] Optionally, the edge protection layer 70 covers the entire sidewall S2 of the dielectric layer 21.
[0046] Reference Figure 8 As shown, in one embodiment, the orthographic projection of the sidewall S1 of the glass substrate unit 11 onto the target plane does not overlap with the orthographic projection of the sidewall S2 of the dielectric layer unit 61 onto the target plane, and is located within the orthographic projection of the dielectric layer unit 61 onto the target plane; wherein, the target plane is parallel to the surface of the glass substrate unit 11. This achieves effective circumferential protection of the sidewall S1 of the glass substrate unit 11 by the sidewall S2 of the dielectric layer 21.
[0047] Optionally, the orthographic projection of the sidewall S1 of the glass substrate unit 11 onto the target plane is a first rectangular ring, and the orthographic projection of the sidewall S2 of the dielectric layer unit 61 onto the target plane is a second rectangular ring. The first rectangular ring is located inside the second rectangular ring and forms an annular gap with the second rectangular ring.
[0048] Reference Figure 9As shown, in one embodiment, the packaging carrier unit 40 further includes a protective structure 80. The protective structure 80 includes an embedded portion 81 and an extension portion 82. The embedded portion 81 is disposed between the glass substrate unit 11 and the dielectric layer unit 61. The extension portion 82 extends from the embedded portion 81 in a direction parallel to the surface of the glass substrate unit 11 and away from the center of the glass substrate unit 11, and extends beyond the sidewall of the glass substrate unit 11. The protective structure 80 can effectively protect the glass substrate 10 when removing the dielectric layer 21 in the dicing area 30; and when etching the sidewall S1 of the glass substrate unit 11, the protective structure 80 can also effectively protect the dielectric layer unit 61, preventing the etching solution from corroding the dielectric layer unit 61. The protective structure 80 mainly protects the bottom of the dielectric layer unit 61.
[0049] Since the glass substrate 10 forms an inward-shrinking structure after etching, and the protective structure 80 forms an embedded portion 81 and an extension portion 82 after etching, it can prevent the bottom surface of the dielectric layer unit 61 from being exposed due to excessive etching, and prevent the etching solution from corroding the dielectric layer unit 61. At the same time, the glass substrate unit 11 effectively supports the bottom of the protective structure 80, ensuring the overall structural stability.
[0050] Furthermore, the orthographic projection of the extension 82 on the target plane overlaps with the orthographic projection of the edge protection layer 70 on the target plane.
[0051] Furthermore, the orthographic projection of the sidewall of the extension 82 onto the target plane lies within the orthographic projection of the edge protection layer 70 onto the target plane.
[0052] Furthermore, the sidewall of the extension 82 is flush with the sidewall of the edge protection layer 70.
[0053] Preferably, the protective structure 80 and the conductive circuit layer 22 are made of the same material and are prepared using the same process, which helps to simplify the preparation process and improve the preparation efficiency.
[0054] Furthermore, the protective structure 80 is spaced apart from the conductive post 51 to avoid affecting the signal of the conductive post 51.
[0055] Furthermore, the distance between the protective structure 80 and the conductive post 51 is greater than the distance between adjacent conductive posts 51.
[0056] Furthermore, the protective structure 80 is spaced apart from the conductive line layer 22.
[0057] Preferably, the materials of the protective structure 80 and the conductive line layer 22 include copper to ensure good conductivity and stability.
[0058] Reference Figure 9-10As shown, in one embodiment, the encapsulation carrier unit 40 further includes an ink layer 90, which is disposed on the side of the redistribution layer 20 away from the glass substrate 10. The ink layer 90 has an opening 91 that exposes the conductive line layer 22, and conductive bumps 92 are disposed in the opening 91.
[0059] The ink layer 90 serves as a protective layer for the redistribution layer 20, protecting it from external wear and moisture erosion. The conductive bumps 92 act as conductive connection media, enabling electrical signal transmission and mechanical fixation between the conductive circuit layer 22 and external chips and modules.
[0060] Reference Figure 11 As shown, another embodiment of this application provides a method for preparing a packaging carrier unit 40, which includes the following steps: Step S10: Provide a packaging substrate 100; wherein the packaging substrate 100 includes a glass substrate 10 and a redistribution layer 20, the glass substrate 10 includes a glass through-hole disposed along the thickness direction and a conductive post 51 filling the glass through-hole, the redistribution layer 20 is disposed on at least one side of the glass substrate 10, the redistribution layer 20 includes a conductive line layer 22 and a dielectric layer 21, the conductive line layer 22 passes through the dielectric layer 21 and is electrically connected to the conductive post 51; see reference Figure 12 As shown.
[0061] Step S20: Remove the dielectric layer 21 on the dicing groove 30 of the encapsulation substrate 100 to form a plurality of dielectric layer units 61; refer to Figure 4 As shown.
[0062] Step S30: Cut the glass substrate 10 along the cutting path 30 to form multiple glass substrate units 11; Refer to Figure 13 As shown.
[0063] Step S40: Etch the sidewalls of the glass substrate unit 11, so that the sidewall S1 of the glass substrate unit 11 is recessed relative to the sidewall S2 of the dielectric layer unit 61 in a direction parallel to the surface of the glass substrate unit 11 and close to the center of the glass substrate unit 11; Refer to Figure 3 As shown.
[0064] The method for preparing the packaging carrier unit 40 provided in this embodiment involves reducing the sidewall S1 of the glass substrate unit 11 relative to the sidewall S2 of the dielectric layer unit 61 inward in a direction parallel to the surface of the glass substrate unit 11 and close to the center of the glass substrate unit 11. The dielectric layer 21 effectively protects the sidewall S1 of the glass substrate unit 11, preventing damage to the glass substrate unit 11 during production, transportation, or use. This improves packaging reliability and enhances the performance of the packaging carrier unit 40.
[0065] In one embodiment, after etching the sidewall S1 of the glass substrate unit 11 so that the sidewall S1 of the glass substrate unit 11 is recessed relative to the sidewall S2 of the dielectric layer unit 61 in a direction parallel to the surface of the glass substrate unit 11 and close to the center of the glass substrate unit 11, step S40 further includes the following steps: Step S50: An edge protection layer 70 is formed on the sidewall S1 of the glass substrate unit 11; Refer to Figure 5 As shown. The edge protection layer 70 can effectively protect the sidewall S1 of the glass substrate unit 11, preventing damage to the glass substrate unit 11 during production, transportation or use, and improving the reliability of the packaging.
[0066] Optionally, an edge protection layer 70 is formed on the sidewall of the glass substrate unit 11 by coating.
[0067] Optionally, the edge protection layer 70 is made of at least one of organic epoxy materials, silane materials, or polyimide materials. These materials have properties such as low modulus and high temperature resistance, and can provide buffer protection for the sidewalls S1 of the glass substrate unit 11. For example, organic epoxy materials include bisphenol A type epoxy resin, epoxy laminated glass cloth, epoxy-modified Ajinomoto film, etc.; silane materials include epoxy-based silane coupling agents, amino-based silane coupling agents, vinyltrimethoxysilane, silane-modified epoxy coating agents, etc.; and polyimide materials include pyromellitic polyimide films, biphenyl polyimide films, thermosetting polyimide coating agents, etc.
[0068] In one embodiment, after step S30, cutting the glass substrate 10 along the cutting path 30 to form a plurality of glass substrate units 11; and after step S40, etching the sidewalls S1 of the glass substrate units 11 so that the sidewalls S1 of the glass substrate units 11 are recessed relative to the sidewalls S2 of the dielectric layer unit 61 in a direction parallel to the surface of the glass substrate units 11 and close to the center of the glass substrate units 11, the following steps are further included: Step S31: Modify the glass substrate unit 11. This facilitates precise control of the glass etching removal depth and accelerates the etching rate.
[0069] Optionally, the modification method can be chemical modification or physical modification. Chemical modification can employ silane coupling agents or hydrofluoric acid pretreatment to alter the activity of the sidewalls of the glass substrate unit 11, thereby accelerating the etching rate and improving etching uniformity. Physical modification can utilize laser pretreatment or plasma bombardment to create micro-defects on the sidewalls of the glass substrate unit 11, thereby precisely controlling the etching depth and avoiding over-etching or uneven etching.
[0070] In one embodiment, step S40 involves etching the sidewalls of the glass substrate unit 11 so that the sidewalls S1 of the glass substrate unit 11 are recessed relative to the sidewalls S2 of the dielectric layer unit 61 in a direction parallel to the surface of the glass substrate unit 11 and close to the center of the glass substrate unit 11; step S50, before forming the edge protection layer 70 on the sidewalls S1 of the glass substrate 10, further includes the following steps: Step S41: An edge protection material layer 71 is formed on the sidewall S1 of the glass substrate unit 11 and the sidewall S2 of the dielectric layer unit 61; Refer to Figure 14 As shown.
[0071] Step S42: Trim the edge protection material layer 71 to form the edge protection layer 70; refer to Figure 5 As shown.
[0072] An edge protection material layer 71 is formed on both the sidewall S1 of the glass substrate unit 11 and the sidewall S2 of the dielectric layer unit 61, which can be easily trimmed to form a smooth edge protection layer 70.
[0073] Optionally, the edge protection material layer 71 may be trimmed by grinding or other methods.
[0074] Optionally, in step S42, the edge protection material layer 71 is trimmed to form an edge protection layer 70 that at least partially covers the sidewall S2 of the dielectric layer 21. The edge protection layer 70 effectively protects the sidewall S2 of the dielectric layer 21, preventing damage to the dielectric layer 21 during production, transportation, or use, thereby further improving packaging reliability.
[0075] In one embodiment, the encapsulation substrate 100 further includes an ink layer 90, which is disposed on the side of the redistribution layer 20 away from the glass substrate unit 11, and has an opening 91 exposing the conductive line layer 22; after step S30, cutting the glass substrate along the dicing 30 to form a plurality of glass substrate units; after step S40, etching the sidewalls of the glass substrate unit 11, before the sidewalls of the glass substrate unit 11 are recessed relative to the sidewalls of the dielectric layer unit 61 in a direction parallel to the surface of the glass substrate unit 11 and close to the center of the glass substrate unit 11, the following steps are further included: Step S32: A first protective layer 72 is formed on the side of the ink layer 90 and the opening 91 away from the glass substrate unit 11; Refer to Figure 15 As shown. The first protective layer 72 is used to protect the ink layer 90 during the etching of the glass substrate unit 11, preventing the ink layer 90 and the conductive line layer 22 from being corroded, and to protect the ink layer 90 during the formation of the edge protective layer 70, preventing the ink layer 90 and the conductive line layer 22 from being contaminated.
[0076] Optionally, the first protective layer 72 can be formed by bonding. The first protective layer 72 is glass, silicon wafer, etc., and can serve as a load-bearing material. After the edge protection material layer 71 is formed on the sidewall S1 of the glass substrate unit 11 and the sidewall S2 of the dielectric layer unit 61 in step S41, the edge protection material layer 71 is trimmed and debonded before the edge protection layer 70 is formed in step S42 to remove the first protective layer 72.
[0077] Further, in step S40, after etching the sidewalls of the glass substrate unit 11 so that the sidewalls S1 of the glass substrate unit 11 are recessed relative to the sidewalls S2 of the dielectric layer unit 61 in a direction parallel to the surface of the glass substrate unit 11 and close to the center of the glass substrate unit 11, in step S50, before forming the edge protection layer 70 on the sidewalls S1 of the glass substrate unit 11, the following steps are also included: Step S401: Remove the first protective layer 72.
[0078] In one embodiment, the encapsulation substrate 100 further includes an ink layer 90, which is disposed on the side of the redistribution layer 20 away from the glass substrate unit 11, and has an opening 91 exposing the conductive line layer 22; after step S30, cutting the glass substrate along the dicing 30 to form a plurality of glass substrate units; after step S40, etching the sidewalls of the glass substrate unit 11, before the sidewalls of the glass substrate unit 11 are recessed relative to the sidewalls of the dielectric layer unit 61 in a direction parallel to the surface of the glass substrate unit 11 and close to the center of the glass substrate unit 11, the following steps are further included: Step S33: A first protective layer 72 is formed on the side of the ink layer 90 and the opening 91 away from the glass substrate unit 11, and a second protective layer 73 is formed on the sidewall of the redistribution layer 20; Refer to Figure 16 As shown. The first protective layer 72 protects the ink layer 90 during etching of the glass substrate unit 11, preventing corrosion of the ink layer 90 and the conductive line layer 22, and also protects the ink layer 90 during the formation of the edge protective layer 70, preventing contamination of the ink layer 90 and the conductive line layer 22. The second protective layer 73 protects the sidewall S2 of the dielectric layer unit 61 during etching of the glass substrate unit 11, preventing corrosion of the dielectric layer unit 61.
[0079] Optionally, the first protective layer 72 and the second protective layer 73 can be formed by coating. The first protective layer 72 and the second protective layer 73 can be inorganic materials (such as silicon dioxide) or acid and alkali resistant organic polymer materials (such as pyrene).
[0080] Further, after etching the sidewalls of the glass substrate unit 11 in step S40, so that the sidewalls S1 of the glass substrate unit 11 are recessed relative to the sidewalls S2 of the dielectric layer unit 61 in a direction parallel to the surface of the glass substrate unit 11 and close to the center of the glass substrate unit 11, the following steps are also included: Step S51: An edge protection layer 70 is formed on the sidewall of the glass substrate unit 11 and on the side of the second protective layer 73 away from the dielectric layer unit 61; Refer to Figure 17 As shown.
[0081] Step S52: Remove the first protective layer 72, retaining the second protective layer 73; refer to Figure 18 As shown.
[0082] The second protective layer 73 will be retained in the final product to protect the sidewall S2 of the dielectric layer unit 61. It can work together with the edge protective layer 70 to protect the dielectric layer unit 61, thereby improving the protective effect.
[0083] In one embodiment, after etching the sidewalls of the glass substrate unit 11 so that the sidewalls of the glass substrate unit 11 are recessed relative to the sidewalls of the dielectric layer unit 61 in a direction parallel to the surface of the glass substrate unit 11 and close to the center of the glass substrate unit 11, step S40 further includes the following steps: Step S60: Form conductive bumps 92 electrically connected to the conductive line layer 22 within the opening 91; corresponding to Figure 10 As shown.
[0084] It should be noted that the above description describes some embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
[0085] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the technical concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A packaging carrier unit, characterized in that, include: A glass substrate unit includes a glass through-hole disposed along the thickness direction and a conductive post filling the glass through-hole; A redistribution layer unit is disposed on at least one side of the glass substrate unit. The redistribution layer unit includes a conductive line layer and a dielectric layer unit. The conductive line layer passes through the dielectric layer unit and is electrically connected to the conductive pillar. The sidewall of the glass substrate unit is recessed relative to the sidewall of the dielectric layer unit in a direction parallel to the surface of the glass substrate unit and close to the center of the glass substrate unit.
2. The packaging carrier unit according to claim 1, characterized in that, The packaging carrier unit further includes an edge protection layer, which at least covers the sidewalls of the glass substrate unit; And / or, the orthographic projection of the sidewall of the glass substrate unit onto the target plane does not overlap with the orthographic projection of the sidewall of the dielectric layer unit onto the target plane, and is located within the orthographic projection of the dielectric layer unit onto the target plane; wherein, the target plane is parallel to the surface of the glass substrate unit.
3. The packaging carrier unit according to claim 1, characterized in that, The encapsulation carrier unit further includes a protective structure, which includes an embedded portion and an extension portion. The embedded portion is disposed between the glass substrate unit and the dielectric layer unit, and the extension portion extends from the embedded portion in a direction parallel to the surface of the glass substrate unit and away from the center of the glass substrate unit, and extends beyond the sidewall of the glass substrate unit.
4. A method for fabricating a packaging carrier unit, characterized in that, include: A packaging carrier is provided; wherein the packaging carrier includes a glass substrate and a redistribution layer, the glass substrate includes a glass via disposed through the thickness direction and a conductive post filling the glass via, the redistribution layer is disposed on at least one side of the glass substrate, the redistribution layer includes a conductive line layer and a dielectric layer, the conductive line layer passes through the dielectric layer and is electrically connected to the conductive post; Remove the dielectric layer on the dicing groove of the packaging substrate to form a plurality of dielectric layer units; The glass substrate is cut along the cutting path to form multiple glass substrate units; The sidewalls of the glass substrate unit are etched so that the sidewalls of the glass substrate unit are recessed relative to the sidewalls of the dielectric layer unit in a direction parallel to the surface of the glass substrate unit and close to the center of the glass substrate unit.
5. The method for preparing the packaging carrier unit according to claim 4, characterized in that, The etching of the sidewalls of the glass substrate unit, such that the sidewalls of the glass substrate unit are recessed relative to the sidewalls of the dielectric layer unit in a direction parallel to the surface of the glass substrate unit and close to the center of the glass substrate unit, further includes: An edge protection layer is formed on the sidewall of the glass substrate unit.
6. The method for preparing the packaging carrier unit according to claim 5, characterized in that, After etching the sidewalls of the glass substrate unit so that the sidewalls of the glass substrate unit are recessed relative to the sidewalls of the dielectric layer unit in a direction parallel to the surface of the glass substrate unit and close to the center of the glass substrate unit, before forming an edge protection layer on the sidewalls of the glass substrate, the method further includes: An edge protection material layer is formed on the sidewall of the glass substrate unit and the sidewall of the dielectric layer unit; The edge protection material layer is trimmed to form the edge protection layer.
7. The method for preparing the packaging carrier unit according to claim 4, characterized in that, The packaging substrate further includes an ink layer disposed on the side of the redistribution layer away from the glass substrate, and the ink layer has an opening that exposes the conductive circuit layer. After cutting the glass substrate along the cutting path to form multiple glass substrate units; after etching the sidewalls of the glass substrate units, before the sidewalls of the glass substrate units are recessed relative to the sidewalls of the dielectric layer units in a direction parallel to the surface of the glass substrate units and close to the center of the glass substrate units, the method further includes: A first protective layer is formed on the ink layer and on the side of the opening away from the glass substrate unit.
8. The method for preparing the packaging carrier unit according to claim 4, characterized in that, The packaging substrate further includes an ink layer disposed on the side of the redistribution layer away from the glass substrate, and the ink layer has an opening that exposes the conductive circuit layer. After cutting the glass substrate along the cutting path to form multiple glass substrate units; after etching the sidewalls of the glass substrate units, before the sidewalls of the glass substrate units are recessed relative to the sidewalls of the dielectric layer units in a direction parallel to the surface of the glass substrate units and close to the center of the glass substrate units, the method further includes: A first protective layer is formed on the ink layer and on the side of the opening away from the glass substrate unit, and a second protective layer is formed on the sidewall of the redistribution layer unit.
9. The method for preparing the packaging carrier unit according to claim 8, characterized in that, After etching the sidewalls of the glass substrate unit, and after causing the sidewalls of the glass substrate unit to be recessed relative to the sidewalls of the dielectric layer unit in a direction parallel to the surface of the glass substrate unit and close to the center of the glass substrate unit, the method further includes: An edge protection layer is formed on the sidewall of the glass substrate unit and on the side of the second protective layer away from the dielectric layer unit; Remove the first protective layer and retain the second protective layer.
10. The method for preparing the packaging carrier unit according to claim 4, characterized in that, After cutting the glass substrate along the cutting path to form multiple glass substrate units; before etching the sidewalls of the glass substrate units so that the sidewalls of the glass substrate units are recessed relative to the sidewalls of the dielectric layer units in a direction parallel to the surface of the glass substrate units and close to the center of the glass substrate units, the method further includes: The glass substrate unit is modified.