Bump packaging structure and bump packaging method

Abstract

This application provides a bump packaging structure and method, relating to the field of semiconductor packaging technology. The bump packaging structure includes a chip with pads, a buffer layer, and a wiring layer. Multiple spaced first conductive pillars are provided on the pads, and the first conductive pillars are electrically connected to the pads. The buffer layer covers the multiple first conductive pillars, and the wiring layer is connected to the buffer layer, which is electrically connected to at least one of the first conductive pillars and the pads. The buffer layer can absorb stress in the wiring layer, preventing structural delamination and breakage, and improving conductivity and structural reliability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a bump packaging structure and a bump packaging method. Background Technology

[0002] With the rapid development of the semiconductor industry, the wafer-level redistribution layer process involves coating a layer of photoresist onto the chip pad surface using a coating process, defining a new wiring pattern through exposure and development, and then using an electroplating process to create new metal lines, forming the redistribution layer. This allows for modification of the original chip wiring contact positions (I / O terminals) through wafer-level metal wiring and bumping processes, increasing the number of bumps and reducing the bump spacing to improve product performance. However, in this redistribution process, due to the inconsistent thermal expansion coefficients of the dielectric layer material, wiring layer, and chip material, solder delamination can easily occur at the chip pad opening contact points, leading to electrical failures. Alternatively, as the wiring layer thickness and linewidth decrease, the skin effect can easily occur on the wiring layer surface, causing current to flow only on the surface rather than being evenly distributed across the entire cross-sectional area of ​​the wiring layer, resulting in a decline in electrical performance. Summary of the Invention

[0003] The purpose of this invention is to provide a bump packaging structure and a bump packaging method, which can absorb the thermal stress of the material, prevent solder delamination, and improve conductivity and electrical connection reliability by forming a buffer layer at the contact point of the chip's solder pad opening.

[0004] In a first aspect, the present invention provides a bump packaging structure, comprising: A chip having pads, wherein the pads are provided with a plurality of spaced first conductive posts, and the first conductive posts are electrically connected to the pads; A buffer layer, wherein the buffer layer covers a plurality of the first conductive pillars; A wiring layer electrically connected to at least one of the first conductive post and the pad, and the wiring layer and the buffer layer are connected.

[0005] In an optional embodiment, the buffer layer is disposed between a plurality of first conductive pillars, and the buffer layer and the plurality of first conductive pillars together form a buffer body. The buffer body has an inwardly concave or outwardly convex arc-shaped surface, and the wiring layer is in contact with the arc-shaped surface.

[0006] In an optional embodiment, the buffer body is provided with a first groove, the wiring layer is in contact with the groove wall of the first groove, and is electrically connected to a plurality of first conductive pillars respectively.

[0007] In an optional embodiment, the first groove exposes the surface of the first conductive post, and among the plurality of first conductive posts, the height of the first conductive post closer to the center of the pad is lower than the height of the first conductive post farther from the center of the pad.

[0008] In an optional embodiment, the bottom of the first groove is arc-shaped.

[0009] In an optional embodiment, a first dielectric layer and a second dielectric layer are further included. The first dielectric layer has a first opening that exposes the pads. The buffer body is disposed in the first opening. The second dielectric layer covers the first dielectric layer and fills the first opening. A second opening is formed on the second dielectric layer to expose the buffer body. The wiring layer is disposed in the second opening.

[0010] In an optional embodiment, the buffer layer includes a plurality of buffer pillars, each of the first conductive pillars being covered by one of the buffer pillars; the plurality of buffer pillars are spaced apart to form a first gap; the wiring layer fills the first gap, and the wiring layer is electrically connected to the pad.

[0011] In an optional embodiment, the buffer pillar has a second groove on the side away from the pad.

[0012] In an optional embodiment, the wiring layer is disposed along the groove wall of the second groove at the second groove, and forms a third groove.

[0013] In an optional embodiment, a sidewall buffer pillar is further included, the sidewall buffer pillar being located around the buffer pillar and connected to the pad; a fourth groove is provided on the side of the sidewall buffer pillar facing the buffer pillar, and the wiring layer fills the fourth groove.

[0014] In an optional embodiment, a first dielectric layer and a second dielectric layer are further included. The first dielectric layer has a first opening that exposes the pads. A plurality of the buffer pillars and the sidewall buffer pillars are disposed within the first opening. The second dielectric layer covers the first dielectric layer and fills the first opening. A second opening is formed on the second dielectric layer to expose the pads, the buffer pillars and the sidewall buffer pillars. The wiring layer is disposed within the second opening.

[0015] In an optional embodiment, the wiring layer further fills the space between the sidewall buffer pillar and the second dielectric layer.

[0016] In an optional embodiment, the wiring layer is recessed at the pads.

[0017] In an optional embodiment, a third dielectric layer is further included, which covers the wiring layer and has a third opening that exposes the wiring layer; The third opening is provided with a second conductive post and a bump connected in sequence, and the second conductive post is electrically connected to the wiring layer.

[0018] Secondly, the present invention provides a bump encapsulation method, comprising: Multiple spaced first pillars are formed on the chip's pads; A buffer layer is formed that covers multiple first pillars; A wiring layer is formed connected to the buffer layer, and the wiring layer and the pad are electrically connected; if the first pillar is metal, the wiring layer is electrically connected to at least one of the first pillar and the pad.

[0019] In an optional implementation, the step of forming a buffer layer covering the plurality of first pillars includes: A first dielectric layer with a first opening is formed on the surface of the chip, the first opening exposing the pads; A photosensitive layer with a third opening is formed inside the first opening. The cross-section of the third opening is smaller than that of the first opening, and the third opening exposes the pad and the first pillar. A buffer layer is formed within the third opening to cover the plurality of the first pillars.

[0020] In an optional implementation, after the step of forming the buffer layer covering the plurality of first pillars, the method includes: A portion of the photosensitive layer within the first opening is removed, forming a second gap between the remaining photosensitive layer and the first dielectric layer; A second dielectric layer is formed to fill the second gap and cover the first dielectric layer, the second dielectric layer having a second opening that exposes the buffer layer; Remove the remaining photosensitive layer in the first opening to form a third gap between the buffer layer and the second dielectric layer; In the step of forming a wiring layer connected to the buffer layer: the wiring layer fills the third gap.

[0021] In an optional implementation, after the step of forming the buffer layer covering the plurality of first pillars, the method includes: The first pillar is a first conductive pillar; the buffer layer and the plurality of first conductive pillars together form a buffer body, and a first groove is formed in the buffer body; In the step of forming a wiring layer connected to the buffer layer: the wiring layer is arranged along the first groove.

[0022] In an optional implementation, after the step of forming the buffer layer covering the plurality of first pillars, the method includes: Multiple spaced buffer pillars and sidewall buffer pillars are formed on the buffer layer, with each buffer pillar covering one of the first pillars; a first gap is formed between adjacent buffer pillars and between the buffer pillars and the sidewall buffer pillars. In the step of forming a wiring layer connected to the buffer layer: the wiring layer fills the first gap.

[0023] In an optional embodiment, after the step of forming a plurality of spaced buffer pillars on the buffer layer and sidewall buffer pillars located around the plurality of buffer pillars, the method includes: A second groove is formed on the buffer support; And / or, a fourth groove is formed on the sidewall buffer post; In the step of forming a wiring layer connected to the buffer layer: the wiring layer fills the fourth groove, the wiring layer is disposed along the groove wall of the second groove, and a third groove is formed on the surface of the wiring layer.

[0024] In an optional embodiment, after the step of forming a plurality of spaced buffer pillars on the buffer layer and sidewall buffer pillars located around the plurality of buffer pillars, the method includes: Remove the first column and form a fifth groove at the end of the buffer support near the pad; In the step of forming a wiring layer connected to the buffer layer: the wiring layer fills the fifth groove to form a first conductive pillar in the fifth groove, the first conductive pillar being electrically connected to the pad and the wiring layer respectively.

[0025] The bump encapsulation structure and bump encapsulation method provided by this invention have the following advantages: Multiple first conductive pillars are placed on the chip's pads to increase electrical connection reliability and improve conductivity. A buffer layer is then coated over these first conductive pillars to absorb thermal stress during the manufacturing process, preventing structural delamination or electrical connection failure. A wiring layer is then formed to connect with the first conductive pillars, thus redistributing the pads. In this process, the buffer layer absorbs stress, prevents structural delamination, and improves structural reliability and electrical performance. Attached Figure Description

[0026] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of a first type of bump packaging structure provided in an embodiment of the present invention; Figure 2 for Figure 1 A magnified view of a portion of point A in the middle; Figure 3 A schematic diagram of the first groove formed on the buffer body in the bump encapsulation structure provided in the embodiment of the present invention; Figure 4 This is a schematic diagram of a second type of bump packaging structure provided in an embodiment of the present invention; Figure 5 for Figure 4 A magnified view of a portion of point B in the middle; Figure 6 A schematic diagram of a bump packaging structure provided in an embodiment of the present invention, in which the wiring layer is arranged along the second groove of the buffer pillar to form a third groove; Figure 7 This is a schematic diagram of a third type of bump packaging structure provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of the wafer structure provided in the bump packaging method according to an embodiment of the present invention; Figure 9 One of the process diagrams for the first bump encapsulation method provided in the embodiment of the present invention; Figure 10 A second schematic diagram of the manufacturing process of the first bump encapsulation method provided in an embodiment of the present invention; Figure 11 The third schematic diagram of the manufacturing process of the first bump encapsulation method provided in the embodiment of the present invention; Figure 12 Fourth schematic diagram of the manufacturing process of the first bump encapsulation method provided in the embodiments of the present invention; Figure 13 Fifth schematic diagram of the manufacturing process of the first bump encapsulation method provided in the embodiments of the present invention; Figure 14 A sixth schematic diagram of the manufacturing process of the first bump encapsulation method provided in an embodiment of the present invention; Figure 15 The seventh schematic diagram of the manufacturing process of the first bump encapsulation method provided in the embodiments of the present invention; Figure 16Eighth schematic diagram of the manufacturing process of the first bump encapsulation method provided in the embodiments of the present invention; Figure 17 This is one of the process diagrams for the second bump packaging method provided in an embodiment of the present invention; Figure 18 This is a second process diagram of the second bump packaging method provided in an embodiment of the present invention; Figure 19 This is a schematic diagram of the process for forming the fifth groove in the third bump encapsulation method provided in the embodiments of the present invention.

[0028] Icons: 100-Chip; 110-Pad; 120-First conductive pillar; 130-Buffer layer; 131-Buffer body; 132-First groove; 141-Buffer support; 142-First gap; 143-Second groove; 144-Sidewall buffer pillar; 145-Fourth groove; 146-Fifth groove; 150-Wiring layer; 151-Third groove; 161-First dielectric layer; 162-First opening; 163-Second dielectric layer; 164-Second opening; 165-Third dielectric layer; 166-Fourth opening; 171-Second conductive pillar; 172-Bump; 173-Metal layer; 180-Photosensitive layer; 181-Third opening; 182-Second gap; 183-Third gap; 191-Protective adhesive layer. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0030] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0031] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0032] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this invention is in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention. In addition, the terms "first," "second," and "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0033] Furthermore, terms such as "horizontal," "vertical," and "sag" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal relative to "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0034] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0035] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0036] Please combine Figures 1 to 3 This invention discloses a bump package structure, including a chip 100 with pads 110, a buffer layer 130, and a wiring layer 150. The pads 110 have a plurality of spaced first conductive posts 120, which are electrically connected to the pads 110. The buffer layer 130 covers the plurality of first conductive posts 120, and the wiring layer 150 is electrically connected to at least one of the first conductive posts 120 and the pads 110. It can be understood that the wiring layer 150 can be connected to the pads 110, connected to the first conductive posts 120, or connected to both the pads 110 and the first conductive posts 120. The connection between the wiring layer 150 and the buffer layer 130 allows the buffer layer 130 to better absorb thermal stress and prevent delamination or breakage of the wiring layer 150.

[0037] It can be understood that the buffer layer 130 covers multiple first conductive pillars 120. This can be achieved by a single buffer layer 130 covering multiple first conductive pillars 120 simultaneously, forming a single unit. Alternatively, multiple buffer layers 130 can each cover a corresponding first conductive pillar 120, with gaps between the buffer layers 130. No specific limitations are specified here.

[0038] Combination Figure 3 A buffer layer 130 covering multiple first conductive posts 120 forms a whole. The buffer layer 130 is disposed between the multiple first conductive posts 120, and the buffer layer 130 and the multiple first conductive posts 120 together form a buffer body 131. The side of the buffer body 131 away from the pads 110 exposes the end face of the first conductive posts 120, and the wiring layer 150 is electrically connected to the end face of the first conductive posts 120. The buffer body 131 has an inwardly recessed or outwardly convex arc-shaped surface, and the wiring layer 150 contacts the arc-shaped surface.

[0039] Optionally, the buffer body 131 is provided with a first groove 132, which exposes the end face of the first conductive post 120. The wiring layer 150 contacts the groove wall of the first groove 132 and is electrically connected to multiple first conductive posts 120 respectively. By providing the first groove 132, the contact area between the wiring layer 150 and the buffer body 131 can be increased, improving the bonding and preventing structural delamination. The buffer layer 130 can better absorb the stress of the wiring layer 150, the first conductive posts 120, etc., improving the reliability of electrical connections and enhancing conductivity.

[0040] Optionally, the first groove 132 is an arc-shaped groove. After the wiring layer 150 fills the arc-shaped groove, the surface of the wiring layer 150 in contact with the buffer body 131 is a curved arc surface, which can prevent breakage due to excessive stress. The curved arc surface has a certain buffering effect, and the wiring layer 150 can absorb stress using its own curved arc surface structure at the bottom. The material of the buffer layer 130 includes, but is not limited to, at least one of silicon nitride or silicon nitride, and does not use polyimide (PI material). Optionally, the bottom and sidewalls of the first groove 132 are arc-shaped.

[0041] It is understood that after the first groove 132 is formed on the buffer body 131, the first groove 132 exposes the surfaces of multiple first conductive pillars 120. Among the multiple first conductive pillars 120, the height of the first conductive pillar 120 closer to the center of the pad 110 is lower than the height of the first conductive pillar 120 farther from the center of the pad 110, forming a concave arc surface. The surface of the first conductive pillar 120 also has a corresponding arc surface. The wiring layer 150 formed in this way is thicker, which is beneficial to reducing the skin effect of current. It is understood that the arc-shaped wiring layer 150 can change the direction of current flow, allowing the current to flow along the cross-section, thereby reducing the skin effect on the wiring layer 150. The skin effect refers to the current flowing only along the surface of the circuit layer, rather than flowing evenly across the entire cross-sectional area of ​​the circuit layer.

[0042] Of course, in some other embodiments, an upwardly convex arc surface can be formed on the buffer body 131, that is, the height of the first conductive post 120 near the center of the pad 110 is higher than the height of the first conductive post 120 far from the center of the pad 110. In this way, when the wiring layer 150 contacts the convex arc surface of the buffer body 131, a curved arc surface can also be formed at the bottom of the wiring layer 150 to absorb stress, and to improve heat dissipation performance and connection reliability, and prevent structural delamination or breakage.

[0043] It is understood that the arc-shaped surface on the buffer body 131 can be wavy, that is, it can have convex arc surfaces or concave arc surfaces. Or it can be any other cross-sectional shape of protrusions or depressions. The number of protrusions or depressions is not limited. The first groove 132 can be an arc-shaped groove, that is, the bottom of the first groove 132 is arc-shaped, or it can be a groove of other cross-sectional shapes, which is not specifically limited here.

[0044] In some embodiments, one or more grooves may be formed on the buffer layer 130 to enhance the bonding force between the buffer layer 130 and the wiring layer 150, better absorb the stress of the wiring layer 150, prevent the wiring layer 150 from warping or delaminating, and improve structural reliability.

[0045] Optionally, the bump package structure further includes a first dielectric layer 161 and a second dielectric layer 163. The first dielectric layer 161 has a first opening 162 exposing the pads 110. A buffer body 131 is disposed within the first opening 162. The second dielectric layer 163 covers the first dielectric layer 161 and fills the first opening 162. A second opening 164 is formed on the second dielectric layer 163 to expose the buffer body 131. A wiring layer 150 is disposed in the second opening 164. It is understood that there is a gap between the sidewall of the first opening 162 and the buffer body 131. The second dielectric layer 163 can fill this gap, thereby protecting the buffer body 131 and the wiring layer 150. The second dielectric layer 163 can be made of the same material as the first dielectric layer 161. The buffer layer 130 can absorb the stress of the second dielectric layer 163, the first dielectric layer 161, and the wiring layer 150, preventing structural delamination.

[0046] Optionally, there is a gap between the second dielectric layer 163 and the buffer body 131, which the wiring layer 150 can fill. This can improve the bonding force between the wiring layer 150 and the second dielectric layer 163 and the buffer body 131 respectively, and enable the buffer body 131 to better absorb stress, alleviate the warping deformation of the structure, prevent delamination, and improve the reliability of the structure.

[0047] Please combine Figures 4 to 6 Multiple buffer layers 130 respectively cover multiple first conductive pillars 120. In this embodiment, the buffer layer 130 includes multiple buffer supports 141, and each first conductive pillar 120 is covered by a buffer support 141; the multiple buffer supports 141 are spaced apart to form a first gap 142; the first gap 142 exposes a portion of the pad 110. The wiring layer 150 fills the first gap 142, and the wiring layer 150 and the pad 110 are electrically connected. This configuration can increase the thickness of the wiring layer 150 and reduce the skin effect of current. Furthermore, the wiring layer 150 filling the first gap 142 helps to improve the bonding force between the wiring layer 150 and the pad 110 and the buffer support 141 respectively, fully utilizes the stress absorption function of the buffer support 141, and prevents structural delamination.

[0048] Optionally, the periphery of the multiple buffer pillars 141 is provided with sidewall buffer pillars 144, which are connected to the pads 110. The multiple buffer pillars 141 and sidewall buffer pillars 144 help to partition the structure of the pads 110, thereby reducing the contact area between the wiring layer 150 and the pads 110, reducing the stress between the dielectric layer and the wiring layer 150, and preventing the wiring layer 150 from being pulled and broken.

[0049] Optionally, a second groove 143 is provided on the side of the buffer pillar 141 away from the pad 110. The second groove 143 helps to improve the bonding force between the wiring layer 150 and the buffer pillar 141. In this embodiment, the buffer pillar 141 completely covers the first conductive pillar 120, and the height of the buffer pillar 141 is greater than the height of the first conductive pillar 120. The depth of the second groove 143 is not limited; it may expose the first conductive pillar 120 or not. Taking the illustration as an example, the end face of the first conductive pillar 120 is not exposed. The wiring layer 150 is disposed along the groove wall of the second groove 143 at the second groove 143, so that the surface of the formed wiring layer 150 has a third groove 151. This arrangement helps to improve the bonding performance between the wiring layer 150 and the third dielectric layer 165, as well as improve heat dissipation performance. Furthermore, the third groove 151 can serve as a buffer structure, which helps to prevent the wiring layer 150 from breaking under stress.

[0050] Optionally, the bump package structure also includes a sidewall buffer pillar 144, located around the buffer pillar 141, and connected to the pad 110. A fourth groove 145 is provided on the side of the sidewall buffer pillar 144 facing the buffer pillar 141. The wiring layer 150 fills the fourth groove 145 and the gap between the sidewall buffer pillar 144 and the buffer pillar 141. The fourth groove 145 helps improve the bonding force between the sidewall buffer pillar 144 and the wiring layer 150, prevents structural delamination, and better absorbs stress in the wiring layer 150.

[0051] In this embodiment, the first dielectric layer 161 has a first opening 162 exposing the pads 110, and multiple buffer pillars 141 and sidewall buffer pillars 144 are disposed within the first opening 162. The second dielectric layer 163 covers the first dielectric layer 161 and fills the first opening 162, that is, fills the space between the first dielectric layer 161 and the sidewall buffer pillars 144. The second dielectric layer 163 protects the wiring layer 150 and the buffer layer 130. The second dielectric layer 163 has a second opening 164 to expose the pads 110, the buffer pillars 141 and the sidewall buffer pillars 144, and the wiring layer 150 is disposed within the second opening 164.

[0052] Optionally, the wiring layer 150 also fills the gap between the sidewall buffer pillars 144 and the second dielectric layer 163. The sidewall buffer pillars 144 absorb the stress on the sidewalls of the wiring layer 150, protect the sidewalls of the wiring layer 150, and help reduce the stress impact of the second dielectric layer 163 on the sidewalls of the wiring layer 150. It is understood that a gap exists between the sidewall buffer pillars 144 and the first dielectric layer 161, which is filled with the second dielectric layer 163 and the wiring layer 150. The presence of the sidewall buffer pillars 144 can reduce the sidewall filling thickness of the second dielectric layer 163 and the sidewall thickness of the wiring layer 150, thereby reducing stress. Optionally, the cross-section of the first opening 162 is trapezoidal. The inclination angle of the sidewall buffer pillars 144 is consistent with the inclination angle of the sidewall of the first opening 162, and the inclination angle is between 15 degrees and 75 degrees.

[0053] In this embodiment, the wiring layer 150 is recessed at the pad 110, which helps to reduce the skin effect of the current and improve the bonding force between the wiring layer 150 and the dielectric layer, buffer layer 130, pad 110, etc., thereby improving the electrical connection performance.

[0054] Optionally, in some embodiments, a second groove 143 or flow channel may be formed on the sidewall of the buffer support 141. When forming the wiring layer 150, the wiring layer 150 fills the second groove 143 or flow channel to further improve the bonding between the wiring layer 150 and the buffer layer 130, fully utilize the function of the buffer layer 130 in absorbing the stress of the wiring layer 150, and achieve higher structural reliability. Of course, in some embodiments, the sidewall buffer support 144 may also be omitted.

[0055] Please combine Figure 7 It should be noted that the first conductive post 120 can be formed before or after the step of forming the buffer pillar 141. Optionally, after forming the buffer pillar 141 on the pad 110, a fifth groove 146 is formed on the buffer pillar 141 near the pad 110. When forming the filling metal of the wiring layer 150, the fifth groove 146 can be filled at the same time, thereby forming the first conductive post 120 electrically connected to the pad 110 and the wiring layer 150 respectively in the fifth groove 146. Alternatively, the first conductive post 120 and the wiring layer 150 are integrally formed. The shape and number of the first conductive posts 120 are not limited. Using an integral forming method is beneficial to increasing the contact area between the wiring layer 150 and the pad 110, thereby improving conductivity, bonding force between the wiring layer 150 and the pad 110, and heat dissipation performance.

[0056] In this embodiment, if the first conductive post 120 is made of graphene, the conductivity and heat dissipation performance of the pad 110 can be improved by using graphene.

[0057] Optionally, the bump package structure further includes a third dielectric layer 165, which covers the wiring layer 150 and has a third opening 181 exposing the wiring layer 150. The third opening 181 has a second conductive post 171 and a bump 172 connected in sequence, and the second conductive post 171 is electrically connected to the wiring layer 150. Optionally, a metal layer 173 is provided within the third opening 181, covering the sidewall of the third opening 181. The metal layer 173 may selectively extend to cover a portion of the third dielectric layer 165, or extend to cover a portion of the wiring layer 150, or cover both a portion of the third dielectric layer 165 and a portion of the wiring layer 150. The second conductive post 171 is electrically connected to the metal layer 173 and the wiring layer 150. The bump 172 may be a solder ball, connected to the side of the conductive post away from the wiring layer 150.

[0058] This invention also provides a bump encapsulation method, which can be used to prepare the above-mentioned bump encapsulation structure, and generally includes the following main steps: To better illustrate the process diagram at pad 110 Figures 9 to 14 This is only a partial schematic diagram of the pad 110 of chip 100.

[0059] Please combine Figure 8 and Figure 9 Step S1: Form a plurality of spaced first pillars on the pads 110 of the chip 100. Optionally, the first pillars are first conductive pillars 120. The chip 100 can be a substrate or other devices. In wafer-level packaging processes, the wafer can be used as the substrate. The pads 110 can be aluminum pads 110 or other metal materials.

[0060] Optionally, a wafer substrate is selected, and a metal layer is deposited on the pad 110 to form a first conductive pillar 120 using any one of the following processes: electroplating, sputtering, electroless plating, physical vapor deposition (PVD), chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), or low-pressure chemical vapor deposition (LPCVD). Multiple first conductive pillars 120 are spaced apart on the pad 110. The deposited metal layer is not limited to any type of metal and is used to improve the conductivity of the pad 110. Graphene can also be used instead of a metal layer to improve the conductivity and heat dissipation of the pad 110.

[0061] Step S2: Form a buffer layer 130 covering the plurality of the first pillars.

[0062] Optionally, a first dielectric layer 161 with a first opening 162 is formed on the surface of the chip 100, the first opening 162 exposing the pad 110.

[0063] A liquid dielectric layer, such as polyimide, is uniformly coated onto the wafer using a spin coater to form a first dielectric layer 161. The first dielectric layer 161 is then soft-baked on a hot plate to set its shape. A photomask is then used in a proximity method to shield the predetermined openings of the first dielectric layer 161 from light exposure. The unexposed areas are then removed by spraying developer to form the first opening 162 that exposes the pads 110. Finally, an oven is used to accelerate the curing of the first dielectric layer 161 to a fully cured and stable state.

[0064] Optionally, a plasma descum machine can be used to remove organic contaminants from the surface of the first dielectric layer 161 or residues within the first opening 162.

[0065] Step S3: A buffer layer 130 is formed within the first opening 162, covering a plurality of first conductive pillars 120.

[0066] by Figures 4 to 6 Taking the buffer layer 130 structure shown as an example, the buffer layer 130 includes a plurality of spaced-apart buffer pillars 141 and sidewall buffer pillars 144. One optional method of forming it includes: Please combine Figure 10 Step S31: A photosensitive layer 180 with a third opening 181 is formed in the first opening 162. The cross-section of the third opening 181 is smaller than the cross-section of the first opening 162. The third opening 181 exposes the pad 110 and the first pillar.

[0067] A liquid photosensitive material (such as at least one of decahydrogenated phthalate and thermoplastic elastomer) is uniformly coated into the first opening 162 using a spin coating machine. The material can be coated only into the first opening 162 or applied to the entire surface of the first dielectric layer 161, filling the first opening 162, to form a photosensitive layer 180. This is then set by a hot plate soft bake. Through an exposure process, using an image mask layer, the pads 110 are exposed and developed, forming a third opening 181 on the photosensitive layer 180 that exposes the pads 110. The cross-section of the third opening 181 is smaller than that of the first opening 162, meaning that a portion of the photosensitive layer 180 remains within the first opening 162.

[0068] Step S32: Form a buffer layer 130 within the third opening 181.

[0069] A liquid buffer medium is uniformly coated onto the wafer using a spin coater to form a buffer layer 130. The material of the buffer layer 130 includes, but is not limited to, at least one of silicon nitride or silicon nitride, but does not use polyimide (PI material). The film is then baked and set using a hot plate. Please refer to... Figure 11 The buffer layer 130 is shielded from light by a photomask using a proximity method with an exposure machine. The unexposed areas are then removed by spraying developer to form multiple buffer pillars 141 covering the first conductive pillar 120 in the third opening 181. Sidewall buffer pillars 144, connected to the photosensitive layer 180, are formed around the buffer pillars 141. The multiple buffer pillars 141 are spaced apart to form a first gap 142. The first gap 142 exposes the pad 110.

[0070] Step S33: Remove the photosensitive layer 180 from the first opening 162. Optionally, an edge-removal process is performed. Using a photomask process, the photosensitive layer 180 is decomposed, and a cleaning process is performed again to remove the remaining photosensitive layer 180 on the sidewall of the second opening 164, forming a second gap 182 between the sidewall buffer pillar 144 and the first dielectric layer 161. Here, the remaining photosensitive layer 180 can be completely removed or partially removed. In this embodiment, a portion of the remaining photosensitive layer 180 is removed along the thickness direction, so that the second gap 182 is formed between the first dielectric layer 161 and the remaining photosensitive layer 180.

[0071] Please combine Figure 12 In step S34, optionally, a second groove 143 is formed on the buffer pillar 141 and a fourth groove 145 is formed on the sidewall buffer pillar 144 using a dry etching process.

[0072] Step S4: Form the second dielectric layer 163.

[0073] Please combine Figure 13 A liquid medium layer (such as polyimide) is uniformly coated onto the first medium layer 161 using a spin coating machine to form the second medium layer 163. The film is then set by a hot plate baking process. Using a proximity method, a photomask is used to shield the predetermined opening positions of the second medium layer 163 from light exposure. The unexposed areas are then removed by spraying developer to form a second opening 164 on the second medium layer 163, exposing the buffer pillars 141 and the sidewall buffer pillars 144.

[0074] Optionally, a chemical cleaning process is performed using chemical agents, including but not limited to at least one of N-methylcyclopropionyl ketone and amine mixtures. All remaining photosensitive layer 180 within the first opening 162 is removed, forming a third gap 183 between the sidewall buffer pillar 144 and the second dielectric layer 163.

[0075] Step S5: Form a wiring layer 150 connected to the buffer layer 130.

[0076] Please combine Figure 14 Optionally, a first photoresist or protective adhesive is coated on the surface of the second dielectric layer 163, and a photolithography process (exposure, development, baking) is performed using a mask to form a patterned layer opening on the first photoresist. Metal is electroplated into the patterned layer opening using an electroplating process to form a wiring layer 150, which is a copper layer. The wiring layer 150 fills the second opening 164, specifically filling the first gap 142 between multiple buffer pillars 141, the gap between the buffer pillars 141 and the sidewall buffer pillars 144, and the third gap 183, etc. The second groove 143, the fourth groove 145, and the third gap 183 can improve the adhesion of the wiring layer 150. A third groove 151 is formed along the second groove 143 on the surface of the wiring layer 150. The first photoresist is removed. The wiring layer 150 is electrically connected to the pad 110 and the first conductive pillar 120, respectively.

[0077] Step S6: Form the third dielectric layer 165.

[0078] Please combine Figure 15 , Figure 16 Optionally, a liquid dielectric layer (polyimide) is uniformly coated onto the second dielectric layer 163 using a spin coating machine, covering the wiring layer 150 to form a third dielectric layer 165. Then, the layer is set by hot-plate baking, and a fourth opening 166 is formed on the third dielectric layer 165 using a photomask and photolithography (exposure, development, baking). Metal is then electroplated into the fourth opening 166 to form a second conductive pillar 171. The second conductive pillar 171 is a copper pillar. Optionally, metal is first electroplated into the fourth opening 166 to form a metal layer 173, a titanium layer is formed on the metal layer 173, and then a copper pillar is formed on the titanium layer. The steps for forming the copper pillar include: A protective adhesive layer 191 is formed on the third dielectric layer 165. A fifth opening is formed on the protective adhesive layer 191 using an exposure and development process. The fifth opening is connected to the fourth opening 166. Metal is electroplated into the fifth opening to form a copper pillar, namely the second conductive pillar 171. The copper pillar is electrically connected to the metal layer 173. Subsequently, a plasma descumber is used to remove the protective adhesive layer 191, forming the copper pillar structure.

[0079] Step S7: Form metal layer bumps 172 on the copper pillar.

[0080] Optionally, a second photoresist with a sixth opening is formed, exposing the copper pillar. Solder is filled into the sixth opening using electroplating or printing processes, with solder filling controlled by adjusting electroplating parameters or printing thickness. The second photoresist is removed using a plasma descummer, forming a copper pillar with solder, i.e., bump 172. After reflow, the solder forms solder balls, completing the process. Finally, the wafer is diced into individual chips using a dicing process. The solder can be at least one of nickel, vanadium, or their alloys, acting as a barrier layer to prevent tin atoms from the top solder balls from diffusing onto the second conductive pillar 171 (copper pillar).

[0081] Please combine Figures 17 to 18 If you want to prepare Figures 1 to 3 The structure shown has similar steps S1 and S2. In step S3, step S31 is performed to form a third opening 181 on the photosensitive layer 180, exposing the pad 110. A portion of the photosensitive layer 180 is retained within the first opening 162. A buffer layer 130 is filled into the third opening 181, covering the first conductive pillar 120. The buffer layer 130 and the multiple first conductive pillars 120 together form a buffer body 131. A first groove 132 is formed on the buffer body 131, which can be achieved by laser grooving or etching. In this embodiment, the first groove 132 is an arc-shaped groove, and the wiring layer 150 is electrically connected to the pad 110 and the first conductive pillar 120, respectively.

[0082] Remove the remaining portion of the photosensitive layer 180 within the first opening 162, and form a second gap 182 between the first dielectric layer 161 and the photosensitive layer 180.

[0083] A second dielectric layer 163 is formed to fill the second gap 182, and a second opening 164 is formed in the second dielectric layer 163 to expose the buffer body 131. The remaining photosensitive layer 180 in the first opening 162 is removed, forming a third gap 183 between the second dielectric layer 163 and the buffer body 131. Metal is electroplated into the second opening 164 to form a wiring layer 150, and the wiring layer 150 fills the third gap 183. Subsequent steps S5 to S7 are similar in process.

[0084] Please combine Figure 19 Optionally, the wiring layer 150 and the first conductive post 120 can be integrally formed: In step S1, when forming the first pillar, the material of the first pillar is selected to be a removable material, such as a removable adhesive layer. In step S34, an additional step of cleaning the removable adhesive is added, which forms a fifth groove 146 at the end of the buffer pillar 141 near the pad 110. The remaining steps are similar to those described in S1 to S7. The wiring layer 150 and the first conductive pillar 120 are integrally formed.

[0085] Alternatively, in step S34, a second groove 143 is formed on the buffer pillar 141, a third groove 151 is formed on the sidewall buffer pillar 144, and a fifth groove 146 is formed below the buffer pillar 141 using a dry etching process. The remaining steps are similar to those described in S1 to S7.

[0086] The bump encapsulation structure and bump encapsulation method provided in this invention have the following beneficial effects: Multiple first conductive pillars 120 are disposed on the pads 110 of chip 100 to increase electrical connection reliability and improve conductivity. A buffer layer 130 is covered on the multiple first conductive pillars 120. The buffer layer 130 is connected to the pads 110, wiring layer 150, etc., to absorb thermal stress during the manufacturing process, prevent structural delamination or electrical connection failure, and then form wiring layer 150 connected to the first conductive pillars 120 to complete the redistribution of pads 110. In this process, the buffer layer 130 absorbs stress to prevent structural delamination and improves structural reliability and electrical connection capability.

[0087] This bump encapsulation method is simple in steps and easy to operate. It helps to fully absorb thermal stress, prevent the wiring layer 150 from delamination or breakage, reduce the skin effect of current, and improve connection reliability and electrical connection performance.

[0088] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; any modifications, equivalent substitutions, improvements, etc., should be included within the protection scope of the present invention.

Claims

1. A bump encapsulation structure, characterized in that, include: A chip having pads, wherein the pads are provided with a plurality of spaced first conductive posts, and the first conductive posts are electrically connected to the pads; A buffer layer, wherein the buffer layer covers a plurality of the first conductive pillars; A wiring layer, the wiring layer being electrically connected to at least one of the first conductive post and the pad, the wiring layer being connected to the buffer layer; The buffer layer includes a plurality of buffer pillars, each of the first conductive pillars being covered by one of the buffer pillars; the plurality of buffer pillars are spaced apart to form a first gap; the wiring layer fills the first gap, and the wiring layer is electrically connected to the pads.

2. The bump encapsulation structure according to claim 1, characterized in that, The buffer layer is disposed between the plurality of first conductive pillars, and the buffer layer and the plurality of first conductive pillars together form a buffer body. The buffer body has an inwardly concave or outwardly convex arc-shaped surface, and the wiring layer is in contact with the arc-shaped surface.

3. The bump encapsulation structure according to claim 2, characterized in that, The buffer body is provided with a first groove, the wiring layer is in contact with the groove wall of the first groove, and is electrically connected to a plurality of first conductive pillars respectively.

4. The bump encapsulation structure according to claim 3, characterized in that, The first groove exposes the surface of the first conductive post. Among the plurality of first conductive posts, the height of the first conductive post closer to the center of the pad is lower than the height of the first conductive post farther from the center of the pad.

5. The bump encapsulation structure according to claim 3, characterized in that, The bottom of the first groove is arc-shaped.

6. The bump encapsulation structure according to claim 2, characterized in that, It also includes a first dielectric layer and a second dielectric layer. The first dielectric layer has a first opening that exposes the pads. The buffer body is disposed in the first opening. The second dielectric layer covers the first dielectric layer and fills the first opening. A second opening is formed on the second dielectric layer to expose the buffer body. The wiring layer is disposed in the second opening.

7. The bump encapsulation structure according to claim 1, characterized in that, The buffer support has a second groove on the side away from the solder pad.

8. The bump encapsulation structure according to claim 7, characterized in that, The wiring layer is disposed along the groove wall of the second groove at the second groove, and forms a third groove.

9. The bump encapsulation structure according to claim 1, characterized in that, It also includes a sidewall buffer pillar, which is located around the buffer pillar and connected to the pad; the sidewall buffer pillar has a fourth groove on the side facing the buffer pillar, and the wiring layer fills the fourth groove.

10. The bump encapsulation structure according to claim 9, characterized in that, It also includes a first dielectric layer and a second dielectric layer. The first dielectric layer has a first opening that exposes the pads. A plurality of the buffer pillars and the sidewall buffer pillars are disposed in the first opening. The second dielectric layer covers the first dielectric layer and fills the first opening. A second opening is formed on the second dielectric layer to expose the pads, the buffer pillars and the sidewall buffer pillars. The wiring layer is disposed in the second opening.

11. The bump encapsulation structure according to claim 10, characterized in that, The wiring layer also fills the space between the sidewall buffer pillar and the second dielectric layer.

12. The bump encapsulation structure according to claim 1, characterized in that, The wiring layer is recessed at the pads.

13. The bump encapsulation structure according to any one of claims 1-12, characterized in that, It also includes a third dielectric layer that covers the wiring layer and has a third opening that exposes the wiring layer; The third opening is provided with a second conductive post and a bump connected in sequence, and the second conductive post is electrically connected to the wiring layer.

14. A bump encapsulation method, characterized in that, include: Multiple spaced first pillars are formed on the chip's pads; A buffer layer is formed that covers multiple first pillars; A wiring layer is formed connected to the buffer layer, and the wiring layer and the pad are electrically connected; if the first pillar is metal, the wiring layer is electrically connected to at least one of the first pillar and the pad; The step of forming a buffer layer covering the plurality of first pillars includes: A first dielectric layer with a first opening is formed on the surface of the chip, the first opening exposing the pads; A photosensitive layer with a third opening is formed inside the first opening. The cross-section of the third opening is smaller than that of the first opening, and the third opening exposes the pad and the first pillar. A buffer layer covering multiple first pillars is formed within the third opening; After the step of forming a buffer layer covering the plurality of first pillars, the method includes: A portion of the photosensitive layer within the first opening is removed, forming a second gap between the remaining photosensitive layer and the first dielectric layer; A second dielectric layer is formed to fill the second gap and cover the first dielectric layer, the second dielectric layer having a second opening that exposes the buffer layer; Remove the remaining photosensitive layer in the first opening to form a third gap between the buffer layer and the second dielectric layer; In the step of forming a wiring layer connected to the buffer layer: the wiring layer fills the third gap.

15. The bump encapsulation method according to claim 14, characterized in that, After the step of forming a buffer layer covering the plurality of first pillars, the method includes: The first pillar is a first conductive pillar; the buffer layer and the plurality of first conductive pillars together form a buffer body, and a first groove is formed in the buffer body; In the step of forming a wiring layer connected to the buffer layer: the wiring layer is arranged along the first groove.

16. The bump encapsulation method according to claim 14, characterized in that, After the step of forming a buffer layer covering the plurality of first pillars, the method includes: Multiple spaced buffer pillars and sidewall buffer pillars are formed on the buffer layer, with each buffer pillar covering one of the first pillars; a first gap is formed between adjacent buffer pillars and between the buffer pillars and the sidewall buffer pillars. In the step of forming a wiring layer connected to the buffer layer: the wiring layer fills the first gap.

17. The bump encapsulation method according to claim 16, characterized in that, Following the step of forming a plurality of spaced buffer pillars on the buffer layer and sidewall buffer pillars located around the plurality of buffer pillars, the method includes: A second groove is formed on the buffer support; And / or, a fourth groove is formed on the sidewall buffer post; In the step of forming a wiring layer connected to the buffer layer: the wiring layer fills the fourth groove, the wiring layer is disposed along the groove wall of the second groove, and a third groove is formed on the surface of the wiring layer.

18. The bump encapsulation method according to claim 16, characterized in that, Following the step of forming a plurality of spaced buffer pillars on the buffer layer and sidewall buffer pillars located around the plurality of buffer pillars, the method includes: Remove the first column and form a fifth groove at the end of the buffer support near the pad; In the step of forming a wiring layer connected to the buffer layer: the wiring layer fills the fifth groove to form a first conductive pillar in the fifth groove, the first conductive pillar being electrically connected to the pad and the wiring layer respectively.

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