Parallel data interface circuit, chip, electronic device, parallel data transmission method

Abstract

A parallel data interface circuit, chip, electronic device, and parallel data transmission method are disclosed, applicable to the field of data communication. The parallel data interface circuit is used for parallel conversion and transmission between signals in the digital domain and signals in the analog domain within the chip. The parallel data interface circuit includes a digital-to-analog conversion interface and a first circuit located in the analog domain. The digital-to-analog conversion interface is configured to perform parallel conversion between N analog signals and N digital signals. The first circuit includes N data lines, configured to transmit N analog signals in parallel through the N data lines. At least one of the N data lines is divided into multiple data traces, and a buffer is provided between every two adjacent data traces to drive the transmission of analog signals in the first data line. The data traces farther from the digital-to-analog conversion interface have a wider line width. This parallel data interface circuit can improve data transmission speed and achieve high-speed communication.

Description

Technical Field

[0001] The embodiments of this disclosure are applied to the field of data communication, specifically relating to a parallel data interface circuit, a chip, an electronic device, a parallel data transmission method, and a non-transitory computer-readable storage medium. Background Technology

[0002] High-speed parallel interfaces, including digital-to-analog conversion or analog-to-digital conversion, consist of multiple parallel data paths (signal lines). Multiple bits of data (e.g., 8-bit / 16-bit / 32-bit) are transmitted simultaneously through these parallel signal lines, offering advantages such as high bandwidth and large data transmission capacity. The PHY (Physical Layer) is the underlying hardware for high-speed communication, responsible for converting digital signals into high-speed analog electrical signals (transmission) and converting analog signals back into digital signals (reception). The PHY can be integrated into the die of a System-on-Chip (SoC), serving as a core peripheral module and one of the core underlying modules for implementing communication functions within the SoC. The PHY's high-speed signal pins and pads are located on the die edge, forming the physical interface area for signal interaction between the PHY and external components (or other modules within the SoC).

[0003] High-speed parallel interfaces require multiple signal lines to achieve high-speed communication, but the die edge is relatively small to facilitate on-chip system integration. Therefore, the parallel signal lines of a high-speed parallel interface and the small die edge create a design contradiction: the high-speed parallel interface needs more space to accommodate the parallel signal lines, but the physical space at the die edge is limited. Summary of the Invention

[0004] This invention application provides at least one embodiment of a parallel data interface circuit for parallel conversion and transmission between signals in the digital domain and signals in the analog domain within a chip. The parallel data interface circuit includes a digital-to-analog conversion interface and a first circuit located in the analog domain. The digital-to-analog conversion interface is configured to perform parallel conversion between N analog signals and N digital signals, where N is a positive integer greater than 1. The first circuit includes N data lines configured to transmit the N analog signals in parallel through the N data lines. Each data line is configured to transmit one analog signal. At least one of the N data lines is divided into multiple data traces. For each first data line, a buffer is provided between every two adjacent data traces. The buffer is configured to drive the transmission of the analog signal in the first data line. The linewidth of each data trace is a fixed value, and the linewidth of the data trace is related to the distance between the data trace and the digital-to-analog conversion interface; the data trace farther from the digital-to-analog conversion interface has a wider linewidth.

[0005] For example, in at least one embodiment of the present invention, a parallel data interface circuit is provided, wherein the first data line is divided into multiple data traces, including the first data trace closest to the digital-to-analog conversion interface, the line width of the first data trace is the minimum value among the line widths of the multiple data traces, the length of the first data trace is determined according to the signal transmission speed requirements of the parallel data interface circuit, and the line width of the first data trace is determined according to N and the length of the die edge allocated to the first circuit.

[0006] For example, in at least one embodiment of the present invention, a parallel data interface circuit is provided, wherein the multiple data traces further include a second data trace adjacent to the first data trace. When the first quantity and the second quantity are the same, the line widths of the first data trace and the second data trace are the same, wherein the first quantity is N, and the second quantity is the number of the at least one first data line; when the first quantity and the second quantity are different, the line width of the first data trace is smaller than the line width of the second data trace.

[0007] For example, in at least one embodiment of the present invention, a parallel data interface circuit is provided, wherein the first data line is divided into multiple data lines according to the length of the first data line. When the length of the first data line cannot be divided into multiple segments according to the length of the first data line, the length of the third data line is less than the length of the first data line. The third data line is the data line that is farthest from the digital-to-analog conversion interface among the multiple data lines.

[0008] For example, in at least one embodiment of the present invention, a parallel data interface circuit is provided, wherein the length of the other data lines among the N data lines, excluding the at least one first data line, is less than the length of the first data trace, and at least one segment of the data trace has a consistent line width, wherein the distance between the first position of each of the at least one segment of the data trace and the digital-to-analog conversion interface is the same.

[0009] For example, in at least one embodiment of the present invention, a parallel data interface circuit is provided, wherein each data line is provided with a trigger for transmitting analog signals, and the trigger uses a clock signal as a trigger signal.

[0010] For example, in at least one embodiment of the present invention, a parallel data interface circuit is provided. For each first data line, the trigger is set at the signal output terminal of the target data trace among the multiple data traces included in the first data line, wherein the target data trace is determined according to the data jitter value corresponding to the first data line. For the other data lines among the N data lines other than the at least one first data line, the trigger is set at the signal output terminal of each of the other data lines.

[0011] For example, in at least one embodiment of the present invention, a parallel data interface circuit is provided, wherein the target data trace is the i-th data trace among the multiple data traces, where i is a positive integer and equal to P is the maximum value among the total number of N data traces corresponding to the N data lines. The total number of data traces corresponding to each first data line is the total number of data traces divided into the first data line. The total number of data traces corresponding to each of the other data lines is 1. This indicates a floor function. When the total number of data traces corresponding to a data line is less than or equal to i, the trigger is set at the output of the data line.

[0012] For example, in at least one embodiment of the present invention, a parallel data interface circuit is provided, wherein the total lengths of the N data lines are different from each other, and the spacing between at least one data line arranged in parallel at a position farther away from the digital-to-analog conversion interface is larger.

[0013] For example, in at least one embodiment of this application, a parallel data interface circuit is provided, wherein the parallel data interface circuit is a physical layer circuit (PHY) and is disposed at the edge of the die of the chip.

[0014] For example, in at least one embodiment of this application, a parallel data interface circuit is provided, wherein the digital-to-analog conversion interface is a digital-to-analog conversion interface, the digital-to-analog conversion interface is configured to convert the N digital signals received by the digital-to-analog conversion interface into the N analog signals in parallel, and the first circuit is configured to transmit the N analog signals to an analog circuit transmitter through the N data lines, so as to transmit them to the physical output interface of the chip through the analog circuit transmitter.

[0015] For example, in at least one embodiment of the present invention, a parallel data interface circuit is provided. When the digital-to-analog conversion interface is an analog-to-digital conversion interface, the analog-to-digital conversion interface is configured to convert the N analog signals output by the first circuit into the N digital signals in parallel, and the analog signals input by the physical input interface of the chip are processed by the analog circuit receiver and transmitted to the first circuit, and transmitted to the analog-to-digital conversion interface through the N data lines.

[0016] This application provides at least one embodiment of a chip, including a parallel data interface circuit as described in any embodiment of this application.

[0017] This application provides at least one embodiment of an electronic device, including a chip as described in any embodiment of this application.

[0018] This invention application provides at least one embodiment of a parallel data transmission method for performing parallel conversion and transmission between signals in the digital domain and signals in the analog domain within a chip. The parallel data transmission method includes: transmitting N analog signals in parallel via N data lines; and performing parallel conversion between the N analog signals and N digital signals via a digital-to-analog conversion interface. Specifically, at least one of the N data lines is divided into multiple data traces. For each first data line, a buffer is provided between every two adjacent data traces within the multiple data traces included in the first data line. The buffer is used to drive the transmission of the analog signals in the first data line. The linewidth of each data trace is a fixed value, and the linewidth of the data trace is related to the distance between the data trace and the digital-to-analog conversion interface; the data trace farther from the digital-to-analog conversion interface has a wider linewidth.

[0019] This application provides at least one embodiment of a non-transitory computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the parallel data transmission method according to at least one embodiment of this application.

[0020] The parallel data interface provided by this invention application can reduce the jitter and delay generated by a single data line as a whole. Furthermore, due to the reduced delay of each data line, the signal skew between multiple data lines can be further reduced, thereby further reducing data jitter and improving data transmission speed to support and realize a high-speed parallel interface. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0022] Figure 1 A signal line layout diagram of a high-speed parallel interface including digital-to-analog conversion is shown.

[0023] Figure 2 A schematic diagram of a parallel data interface circuit provided for at least one embodiment of this disclosure;

[0024] Figure 3A A schematic structural diagram of a parallel data interface circuit including a digital-to-analog conversion interface provided for at least one embodiment of the present disclosure;

[0025] Figure 3B A schematic structural diagram of a parallel data interface circuit including an analog-to-digital conversion interface provided for at least one embodiment of the present disclosure;

[0026] Figure 4 A schematic structural diagram of a chip provided for at least one embodiment of this disclosure;

[0027] Figure 5 This is a schematic structural diagram of a general-purpose graphics processor;

[0028] Figure 6 A schematic structural diagram of an electronic device provided for at least one embodiment of this disclosure;

[0029] Figure 7 A schematic block diagram of an electronic device provided in one embodiment of this disclosure;

[0030] Figure 8 A schematic flowchart illustrating a parallel data transmission method provided in at least one embodiment of this disclosure;

[0031] Figure 9 A schematic diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0033] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components are omitted.

[0034] Figure 1 A signal line layout diagram of a high-speed parallel interface including digital-to-analog conversion is shown.

[0035] Figure 1 The image shows a high-speed parallel interface, including a digital-to-analog converter. This high-speed parallel interface is an important peripheral module within the chip, which can also include further circuitry. Figure 1 Only the parts related to the high-speed parallel interface are shown in the text.

[0036] A digital-to-analog converter interface is used to convert digital signals into analog signals.

[0037] Figure 1 In the diagram, the gray area represents digital circuits (digital domain), where data lines (or signal lines) transmit digital signals, while the white area represents analog circuits (analog domain), where data lines transmit analog signals.

[0038] exist Figure 1 In the example, the digital signal output by the digital circuit serves as the input signal of the high-speed parallel interface, and is represented as follows: Figure 1Inputs 0, 1, 2, ..., 7 are processed through a digital-to-analog converter interface. These input signals are converted from digital signals to analog signals and output through multiple data lines. These output analog signals are represented as follows: Figure 1 The outputs are 0, 1, 2, ..., 7. Figure 1 In the example provided, the high-speed parallel interface includes eight parallel data lines, enabling the parallel transmission of eight signals. Of course, in other examples, the high-speed parallel interface may include more or fewer parallel signal lines, which will not be discussed further here.

[0039] Typically, in the physical layer design of high-speed parallel signal lines, the lengths of each signal line (also called a data line) are likely to be different, which is reflected in... Figure 1 In analog circuits, the signal lines have varying lengths. The analog circuitry needs to be evenly distributed across the analog domain, and one end of each signal line must be fixed at the digital-to-analog interface, resulting in different positions for the other end. This leads to the problems described below in such high-speed parallel interface circuits.

[0040] refer to Figure 1 The layout shown has the longest signal line for output 0, which has limited signal driving capability. This limits the transmission speed of the signal line. Since all signals from the parallel signal lines need to be received before further processing, the limited transmission speed of output 0 will affect the overall transmission speed of the high-speed parallel signal lines.

[0041] Furthermore, signal jitter is directly proportional to the length of the signal line and inversely proportional to the width and spacing of the signal line. Therefore, the signal line with an output of 0 is the longest and has the largest jitter, which will further limit the transmission speed of the signal line.

[0042] Signal delay is directly proportional to the length of the signal line and inversely proportional to the width and spacing of the signal line. Therefore, the signal line with the output 0 is the longest and has the largest delay. However, the output requires 8 signals to be received simultaneously, which will affect the overall transmission speed of the high-speed parallel signal line.

[0043] Since each signal line has a different length, its jitter and delay also differ. This difference can cause signal skew, which in turn affects the overall signal jitter and limits the transmission speed of the signal lines.

[0044] In addition, such as Figure 1 As shown, in the analog circuit area, in addition to the layout of 8 signal lines, there is an empty area shown as "Area 1". The shape of this empty area is irregular and it is difficult to continue to use, resulting in a waste of hardware resources and a reduction in area utilization.

[0045] At least one embodiment of this disclosure provides a parallel data interface circuit for parallel conversion and transmission between signals in the digital domain and signals in the analog domain within a chip. The parallel data interface circuit includes a digital-to-analog conversion interface and a first circuit located in the analog domain. The digital-to-analog conversion interface is configured to perform parallel conversion between N analog signals and N digital signals, where N is a positive integer greater than 1. The first circuit includes N data lines configured to transmit N analog signals in parallel through the N data lines. Each data line is configured to transmit one analog signal. At least one of the N data lines is divided into multiple data traces. For each first data line, a buffer is provided between every two adjacent data traces in the multiple data traces included in the first data line. The buffer is used to drive the transmission of the analog signal in the first data line. The line width of each data trace is a fixed value, with the line width increasing the distance from the digital-to-analog conversion interface.

[0046] In the parallel data interface provided in at least one embodiment of this disclosure, a single data line can be divided into multiple data traces, and a buffer is added between two adjacent data traces. Each data trace can then be driven by the buffer, effectively improving signal transmission speed to support high-speed transmission. Furthermore, the data traces farther from the digital-to-analog conversion interface have a wider line width. When the data traces are wider, their jitter and latency are reduced. Therefore, compared to the current scheme of setting the width of the entire data line to be the same, the parallel data interface circuit provided in at least one embodiment of this disclosure can reduce the jitter and latency generated by a single data line overall. Moreover, the latency of data traces farther from the digital-to-analog conversion interface is lower, reducing the transmission latency difference between data lines and further reducing signal skew between multiple data lines. This further reduces data jitter and improves data transmission speed to support and implement a high-speed parallel interface.

[0047] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings, but this disclosure is not limited to these specific embodiments.

[0048] Figure 2 A schematic diagram of a parallel data interface circuit provided for at least one embodiment of this disclosure.

[0049] Figure 2 A schematic structural diagram of a parallel data interface circuit 100 is shown. This parallel data interface circuit 100 is used for parallel conversion and transmission between signals in the digital domain and signals in the analog domain within the chip.

[0050] A die, after being packaged and tested, is the final product that can be called a chip. A die is a single, complete, but unpackaged integrated circuit unit cut from a manufactured wafer. For example, the parallel data interface circuit 100 can be the physical layer circuit (PHY) of the chip and is located at the edge of the die. That is, the parallel data interface circuit 100 is arranged in the peripheral area of ​​the die, which facilitates direct pin routing, reduces trace interference, and is beneficial for high-speed signals.

[0051] Of course, the parallel interface data circuit can also be arranged in other suitable locations in the integrated circuit as needed, and no further examples will be given. This disclosure does not impose any specific restrictions.

[0052] like Figure 2 As shown, the gray area represents the digital domain, which processes digital signals and performs functions such as arithmetic, control, protocol processing, data storage, and signal processing. The white area represents the analog domain, which processes analog signals and performs functions such as signal amplification and equalization, and signal transmission and reception. The analog domain is generally located at the edge of the die, close to the pins and pads, facilitating the transmission and reception of analog or high-speed signals; the digital domain is located in the middle of the chip, with a large and regular area, facilitating layout and routing.

[0053] like Figure 2 As shown, the parallel data interface circuit 100 includes a digital-to-analog conversion interface 101 and a first circuit 102 located in the analog domain.

[0054] The digital-to-analog conversion interface 101 is configured to perform parallel conversion between N analog signals and N digital signals, where N is a positive integer greater than 1. For example, in Figure 1 In the example, N=8. Of course, N can be set to other values, such as 16, 32, etc., depending on the actual needs.

[0055] Digital-to-analog conversion interfaces can include digital-to-analog conversion interfaces or analog-to-digital conversion interfaces.

[0056] The digital-to-analog converter (DAC) is configured to convert N digital signals received by the DAC into N analog signals in parallel, and the analog-to-digital converter (ADC) is configured to convert N analog signals output by the first circuit into N digital signals in parallel. The signal transmission directions of the two are different, but their circuit structures are basically the same. The parallel data interface circuit provided in at least one embodiment of this disclosure can be applied to both digital-to-analog conversion and analog-to-digital conversion processes. Specific examples can be found below. Figure 3A and Figure 3B The description will not be repeated here.

[0057] The first circuit includes N data lines, for example Figure 2The data lines 0 to 7 are shown. The first circuit is configured to transmit N analog signals in parallel via N data lines, with each data line configured to transmit one analog signal.

[0058] As mentioned earlier, in Figure 1 In the example, data lines 0 and 1 are relatively long, resulting in greater signal delay and jitter. Furthermore, longer data lines slow down signal transmission, weaken amplitude, and may cause timing errors. Therefore, as... Figure 2 As shown, in at least one embodiment of this disclosure, at least one of the N data lines is divided into multiple data traces, for example... Figure 2 Data lines 0 through 5 can all be used as the first data line. Each first data line can be divided into multiple data traces, for example... Figure 2 Data line 0 in the diagram can be used as the first data line, which includes four data traces, for example... Figure 2 The first data trace, the second data trace, the third data trace, etc.

[0059] For each first data line, a buffer is provided between every two adjacent data traces in the multiple data traces included in the first data line. This buffer is used to drive the transmission of analog signals in the first data line. For example, as Figure 2 As shown, data lines 0 through 5 are divided into multiple data traces, and a buffer is placed between every two adjacent data traces. The buffer is represented as... Figure 2 The middle element is a square connecting the two data traces. Buffers are typically directional, with the direction differing between analog-to-digital and digital-to-analog conversions, as described in the relevant embodiments below.

[0060] A buffer can act as a dedicated driver amplifier, compensating for delays, correcting timings, isolating noise, preventing crosstalk, adjusting drive strength, and enhancing signal drive capability, enabling high-speed signal transmission and effectively improving signal transmission speed. For data lines, especially those with long lengths, using multiple data traces and adding buffers can effectively enhance signal drive capability, increase signal transmission speed, and achieve high-speed signal transmission.

[0061] like Figure 2 As shown, taking data line 0 as an example, it is divided into 4 data traces. A buffer is set between each pair of adjacent data traces, and a total of 3 buffers are set. So when the signal is transmitted to the buffer through the data trace, it can be driven by the buffer again to maintain high-speed transmission and improve the signal transmission speed.

[0062] The number of data cable segments, and whether to divide them into multiple segments, depends on the length of the data cable itself. For example, data cables 6 and 7 are relatively short, and their transmission speed is already sufficient to meet the data transmission requirements, so there is no need to divide them into multiple segments.

[0063] like Figure 2 As shown, the line width of each data trace is a fixed value, meaning that the line width of a single data trace is uniform and constant. The line width of a data trace is related to the distance between the data trace and the digital-to-analog conversion interface; the farther the data trace is from the digital-to-analog conversion interface, the wider its line width.

[0064] The distance between the data trace and the digital-to-analog conversion interface can be set as the distance between a predetermined position of the data trace and the digital-to-analog conversion interface. The predetermined position can be the end of the data trace closer to the digital-to-analog conversion interface, the end farther from the digital-to-analog conversion interface, or the midpoint of the data trace, etc. This disclosure does not impose specific limitations on this.

[0065] like Figure 2 As shown, taking data line 0 as the first data line as an example, it includes four data traces. The first data trace, which is closest to the digital-to-analog conversion interface, has the narrowest line width. The second data trace has a line width greater than that of the first data trace. The third data trace, which is farthest from the digital-to-analog conversion interface, has the widest line width.

[0066] As mentioned earlier, currently Figure 1 The illustrated scheme maintains consistent data line width and spacing. Longer-distance traces exhibit greater delay and jitter, with a significant delay difference between long and short data lines, increasing overall signal skew. The overall data transmission speed is limited by the worst jitter or delay, making high-speed transmission difficult. Since signal delay and jitter are inversely proportional to trace width, in the parallel data interface circuit provided in at least one embodiment of this disclosure, data traces farther from the digital-to-analog conversion interface have wider trace widths and lower parasitic resistance. The spacing between data traces farther from the digital-to-analog conversion interface is also larger, resulting in lower parasitic capacitance. Therefore, signal delay and jitter can be effectively reduced. The overall transmission delay and jitter of longer data lines decrease, thus improving data transmission speed and supporting high-speed signal transmission. Furthermore, the reduced delay and jitter of longer traces reduces the delay difference between long and short data lines, effectively minimizing overall signal skew.

[0067] Furthermore, due to the inconsistent lengths of the data cables, the number of parallel data cables decreases the further away from the digital-to-analog conversion interface, such as... Figure 2As shown, eight data lines or data traces are arranged side-by-side closest to the digital-to-analog converter interface 101, and two data traces, namely data line 0 and data line 1, are arranged side-by-side furthest from the digital-to-analog converter interface 101. Figure 2 As shown, when there are many data traces arranged in parallel, the trace width and spacing are relatively small, while when there are few data traces arranged in parallel, the trace width and spacing are relatively large. Therefore, data traces farther from the digital-analog interface experience less signal delay and jitter.

[0068] The larger the spacing between data traces, the lower the jitter and latency. Therefore, while making full use of the trace area, it can effectively reduce data jitter and latency and reduce overall signal skew. Furthermore, setting wider data traces can still maintain a neat layout and avoid generating irregularly shaped remaining area that is difficult to utilize, thus effectively improving the utilization rate of on-chip resources.

[0069] For any given first data line, the multiple data traces divided into the first data trace include the first data trace closest to the digital-to-analog conversion interface, and the line width of the first data trace is the minimum value among the line widths of the multiple data traces. For example, Figure 2 As shown, for data line 0, the first data trace among its four data traces has the narrowest width.

[0070] The length of the first data trace is determined based on the signal transmission speed requirements of the parallel data interface circuit, and the trace width of the first data trace is determined based on N and the length of the die edge allocated to the first circuit.

[0071] Since the number of data lines closest to the digital-to-analog conversion interface is always maximum (N), and as mentioned earlier, the length of the die edge is finite, the linewidth of the data lines is also finite, and the spacing between the data lines is relatively small. The linewidth is determined based on N and the length of the die edge allocated to the first circuit. Based on the signal transmission speed requirements of the parallel data interface circuit, and combined with the linewidth, an upper limit threshold for the data traces is determined to meet these requirements. The length of the first data trace should be less than or equal to this upper limit threshold to satisfy the signal transmission speed requirements. Therefore, the length of the first data trace can be determined.

[0072] For data lines whose length is already less than the length of the first data trace, their signal transmission speed can meet the requirements, so there is no need to divide them into multiple data traces.

[0073] For data lines longer than the first data trace, they need to be divided into multiple data traces. For example, the lengths of other data traces can be the same as the length of the first data trace. In this case, the buffer capacity and settings can be handled uniformly, reducing the processing burden and ensuring better layout matching. This allows two or more critical data traces to run with exactly the same length, path, and environment, guaranteeing consistent electrical characteristics. Furthermore, since the first data trace has the narrowest width, if the first data trace meets the signal transmission speed requirements, subsequent data traces will inevitably meet the speed requirements without needing to be verified again.

[0074] For example, the first data line can be divided into multiple data lines based on its length. If it cannot be divided equally, the length of the third data line, which is furthest from the digital-to-analog conversion interface, can be shorter than the length of the first data line. Figure 2 As shown, the third data trace has the widest width, and its length is shorter than that of the first data trace. The lengths of the other data traces in the first data trace are the same as those of the first data trace.

[0075] Of course, in other embodiments, it is also possible to configure multiple data traces included in a first data line, with each data trace having a different length, or some data traces having the same length while others have different lengths, etc. This disclosure does not impose specific limitations on this.

[0076] To facilitate layout and routing, a group of data traces arranged side-by-side can be configured to have the same trace width. For example, taking a first data trace and a second data trace as examples, when the first quantity and the second quantity are the same, the first data trace and the second data trace have the same trace width, where the first quantity is N and the second quantity is the number of at least one first data trace; when the first quantity and the second quantity are different, the trace width of the first data trace is smaller than the trace width of the second data trace.

[0077] The length of the data line may vary in different chips; for example, in... Figure 2 In one example, the first quantity is 8 and the second quantity is 6, so the line width of the first data trace is smaller than the line width of the second data trace. In other examples, the lengths of the data traces may be such that the first and second quantities are the same. In this case, the line widths of the first and second data traces are the same to ensure neat layout and avoid irregular excess area.

[0078] In other words, along the direction from the digital-to-analog conversion interface to away from it, as the number of parallel data traces decreases, the trace width increases. For example, the previous group of data traces (e.g.) Figure 2The number of the eight first data traces arranged side-by-side with the first data trace is greater than the number of data traces in the current group (e.g., ...). Figure 2 The number of data traces arranged in parallel with the second data trace; when the number of data traces arranged in parallel remains unchanged, for example, the number of data traces in the previous group is equal to the number of data traces in the current group, the line width of the data traces also remains unchanged, thereby ensuring that the layout and wiring are neat and avoiding the generation of irregular remaining areas.

[0079] For example, among the N data lines, the length of all data lines except for at least one first data line is less than the length of the first data trace, and at least one segment of the data trace has a consistent line width. The distance between the first position of each of these at least one data trace and the digital-to-analog conversion interface is the same. For example, the first position could be an endpoint or midpoint of the data trace, etc., without specific limitations.

[0080] For example, Figure 2 As shown, for the first group of data traces closest to the digital-to-analog conversion interface among data lines 0-7, namely the first data trace among data lines 0-5, as well as data lines 6 and 7, the first position (e.g., the right endpoint or the midpoint) of these data traces is the same distance from the digital-to-analog conversion interface, and the line width of these data traces is the same.

[0081] For the second group of data traces adjacent to the first group of data traces, namely the second data traces in data lines 0 to 5, the first position (e.g., the right endpoint) of these data traces is the same distance from the digital-to-analog conversion interface, and the line widths between the second group of data traces are also the same, and are all greater than the line widths of the data traces in the first group of data traces.

[0082] Because the number of data traces in the second group is less than the number of data traces in the first group, the trace width of the second group increases. If the number of data traces in the second group remains N, then the trace width of the second group remains unchanged.

[0083] Because the length of the die edge is limited, crosstalk can occur when the spacing between data traces is small, resulting in significant signal jitter at the output and making it difficult to support high speeds. In the parallel data interface circuit provided in at least one embodiment of this disclosure, a flip-flop can be further provided in each data line for transmitting analog signals. The flip-flop uses a clock signal as the trigger signal, represented as... Figure 2 The "DFF" in the text.

[0084] Clock signals are relatively clean signals. Using clock signals can resynchronize analog signals, effectively reducing crosstalk and signal jitter, improving signal transmission speed, and enabling high-speed signal transmission.

[0085] Setting triggers in data lines incurs some overhead. Therefore, placing triggers in appropriate locations can mitigate the negative impact of this overhead and ensure their effective function. For example, for each first data line, a trigger can be set at the signal output terminal of the target data trace among the multiple data traces included in the first data line, where the target data trace is determined based on the data jitter value corresponding to the first data line; for the other data lines among the N data lines excluding at least one first data line, triggers can be set at the signal output terminals of each of the other data lines.

[0086] like Figure 2 As shown, each data line is equipped with a trigger to maintain timing consistency.

[0087] For shorter data lines, such as those shorter than the length of the first data trace and therefore not configured as multi-segment data traces, triggers are set at the outputs of these data lines. For example, data lines 6 and 7 can be considered as containing a single data trace, and triggers are set at the outputs of data lines 6 and 7.

[0088] For data lines divided into multiple data segments, a trigger is set at the signal output terminal of the target data segment. The target data segment is determined based on the data jitter value corresponding to the first data line. For example, in one embodiment, the data segment corresponding to the median value of the overall data jitter value of the first data line can be determined as the target data segment, and a trigger is set at the output terminal of the target data segment. The purpose of setting the trigger is to reduce signal jitter; therefore, setting it near the median jitter value allows the segments before and after the trigger to offset the effect of signal jitter to the greatest extent possible.

[0089] For example, in some embodiments, the median value can be determined based on the jitter value, and the data trace corresponding to the median value can be identified as the target data trace.

[0090] For example, in some embodiments, since the data traces near the digital-to-analog conversion interface have small spacing and small line width, their signal jitter value is relatively large, so they can be set at the output end of the data traces closer to the digital-to-analog conversion interface.

[0091] For example, in one embodiment, the target data trace is the i-th data trace in a set of multiple data traces, where i is a positive integer and equal to P is the maximum value among the total number of data traces corresponding to the N data lines. The total number of data traces corresponding to each first data line is the total number of data traces divided by that first data line. The total number of data traces corresponding to each of the other data lines is 1. This represents the floor function.

[0092] Here, with Figure 2 For example, the first data trace is the first data trace segment, and the third data trace is the Pth data trace segment. The total number of data traces corresponding to data lines 6 and 7 is 1, the total number of data traces corresponding to data lines 4 and 5 is 2, the total number of data traces corresponding to data lines 3 and 2 is 3, the total number of data traces corresponding to data lines 0 and 1 is 4, and P is the maximum value among the total number of data traces corresponding to the 8 data lines, i.e., P is 4. For example, for Figure 2 In the example shown, P=4, therefore the target data trace can be the second data trace in each data trace segment, that is... Figure 2 The second data trace in the diagram has a trigger set at the output of the second data trace of each data trace. For example, refer to... Figure 2 For data lines 0 through 3, each includes at least 3 data traces, and a trigger is set at the output of the second data trace.

[0093] For example, when the total number of data traces corresponding to a data line is less than or equal to i, a trigger is set at the output of that data line. For example, refer to... Figure 2 For data lines 4 and 5, which include two data traces, a trigger is set at the output end of the data line; for data lines 6 and 7, which include one data trace, a trigger is set at the output end of the data line.

[0094] Triggers can use relatively clean clock signals to resynchronize data, reducing signal jitter and effectively improving speed. Furthermore, triggers are set at the output of specific target data traces, which are determined by the jitter value corresponding to the data line. For example, the data trace corresponding to the median jitter value can be used as the target data trace. This maximizes the ability to handle signal jitter on two signal lines segmented by the trigger with just one trigger (reducing jitter), effectively improving signal transmission speed and achieving high-speed signal transmission.

[0095] Digital-to-analog conversion interfaces include digital-to-analog conversion interfaces and analog-to-digital conversion interfaces.

[0096] Figure 3A This is a schematic structural diagram of a parallel data interface circuit including a digital-to-analog conversion interface, provided for at least one embodiment of the present disclosure.

[0097] exist Figure 3A In the example, the digital domain processes the digital signal, which is then used as input to the digital-to-analog converter (DAC) and converted into N analog signals. These signals are then transmitted via the N data lines of the first circuit in the analog domain.

[0098] exist Figure 3AIn the example, the analog domain also includes an analog circuit transmitter, which is coupled to N data lines in the first circuit and configured to transmit the analog signals in the chip to the chip's physical output interface after signal amplification and other processing.

[0099] like Figure 3A As shown, the buffer is represented by a triangle with its sharp corner pointing to the left. It can drive the analog signal output from the previous data trace to the next data trace along the analog signal transmission direction, thereby improving the transmission speed of the analog signal.

[0100] like Figure 3A As shown, the line width of each data trace is a fixed value. The line width of the data trace is related to the distance between the data trace and the digital-to-analog converter interface. The farther the data trace is from the digital-to-analog converter interface, the wider the line width.

[0101] like Figure 3A As shown, when there are many data traces arranged side-by-side along a direction perpendicular to the data line, the trace width and spacing are relatively small. For example, the eight data traces closest to the digital-to-analog converter interface have relatively small trace widths and spacings. Conversely, when there are fewer data traces arranged side-by-side, the trace width and spacing are relatively large. For example, the two data traces furthest from the digital-to-analog converter interface have relatively large trace widths and spacings. Therefore, data traces farther from the digital-to-analog converter interface experience less signal delay and jitter, reducing the overall signal delay and jitter of long-distance data lines, improving signal transmission speed, and reducing signal skew between data lines of different lengths, further reducing signal jitter caused by signal skew and improving signal transmission speed.

[0102] about Figure 3A For a more detailed description of the parallel data interface circuit shown, please refer to [reference needed]. Figure 2 The relevant content will not be repeated here.

[0103] Figure 3B This is a schematic structural diagram of a parallel data interface circuit including an analog-to-digital conversion interface, provided for at least one embodiment of the present disclosure.

[0104] exist Figure 3B In the example, the analog domain also includes an analog circuit receiver. The analog signal input from the chip's physical input interface is processed by the analog circuit receiver and then transmitted to N data lines in the first circuit. The N data lines then transmit the signal to the analog-to-digital conversion interface, which is configured to convert the N analog signals output from the first circuit into N digital signals in parallel. These digital signals then enter the digital domain for further processing.

[0105] like Figure 3BAs shown, the buffer is represented by a triangle with its sharp right corner. It can drive the analog signal output from the previous data trace to the next data trace along the analog signal transmission direction, thereby improving the transmission speed of the analog signal.

[0106] like Figure 3B As shown, the line width of each data trace is a fixed value. The line width of the data trace is related to the distance between the data trace and the analog-to-digital conversion interface. The farther the data trace is from the analog-to-digital conversion interface, the wider its line width.

[0107] like Figure 3B As shown, when there are many data traces arranged side-by-side along a direction perpendicular to the data line, the trace width and spacing are relatively small. For example, the eight data traces closest to the analog-to-digital converter interface have small trace widths and spacings. Conversely, when there are fewer data traces arranged side-by-side, such as the two data traces furthest from the analog-to-digital converter interface, the trace width and spacing are relatively large. Therefore, data traces farther from the analog-to-digital converter interface experience less signal delay and jitter, reducing the overall signal delay and jitter of long-distance data lines, improving signal transmission speed, and reducing signal skew between data lines of different lengths, further reducing signal jitter caused by signal skew and improving signal transmission speed.

[0108] about Figure 3B For a more detailed description of the parallel data interface circuit shown, please refer to [reference needed]. Figure 2 The relevant content will not be repeated here.

[0109] Of course, in Figure 3A and 3B In the example, the simulation domain can also include other circuits or units, and the connection relationship between the various circuits or units is unrestricted and can be determined according to actual needs.

[0110] It should be noted that, in at least one embodiment of this disclosure, the parallel data interface circuit may include more or fewer circuits or units, and the connection relationship between the various circuits or units is not limited and can be determined according to actual needs. The specific configuration of each circuit or unit is not limited; it can be constructed from analog devices, digital chips, or other suitable methods according to circuit principles.

[0111] For example, parallel data interface circuits can be implemented in hardware or a combination of hardware and software, and this disclosure does not impose any specific restrictions on this.

[0112] This disclosure also provides a chip in at least one embodiment. Figure 4 This is a schematic structural diagram of a chip provided for at least one embodiment of the present disclosure.

[0113] like Figure 4As shown, the chip 200 includes a parallel data interface circuit 100.

[0114] For more detailed information about the parallel data interface circuit 100, please refer to the relevant descriptions in the foregoing embodiments, which will not be repeated here.

[0115] For example, the parallel data interface circuit 100 can be a physical layer circuit (PHY circuit). The chip integrates a digital processing module and the physical layer circuit. The digital processing module is used to implement digital logic functions such as data encoding, decoding, timing control, and protocol processing. The physical layer circuit, including the first circuit and the digital-to-analog conversion interface, is used to complete high-speed signal transmission and reception between the digital and analog domains within the chip. The physical layer circuit is usually located at the edge area of ​​the chip die to facilitate direct connection with external pins, reduce high-speed signal transmission paths, and reduce noise interference.

[0116] In addition to the physical layer circuits, the analog domain of a chip can also include clock generation circuits, analog receivers, analog transmitters, etc., undertaking functions such as high-speed signal driving, reception equalization, and level matching.

[0117] For example, the chip provided in at least one embodiment of this disclosure may specifically be a Graphic Processing Unit (GPU), a General-Purpose Graphic Processing Unit (GPGPU), a Tensor Processing Unit (TPU), a Data Processing Unit (DPU), a Neural Processing Unit (NPU), etc., and this disclosure does not impose any specific limitations on it.

[0118] The following is based on Figure 5 For example, this illustrates the structure when the chip is a graphics processor or a general-purpose graphics processor.

[0119] Figure 5 This is a schematic diagram of a general-purpose graphics processing unit (GPGPU).

[0120] like Figure 5 As shown, a graphics processing unit (GPU) is actually an array of programmable multiprocessors. For example, a programmable multiprocessor can be a streaming processor cluster (SPC), such as including... Figure 5The diagram shows multiple streaming processor clusters. In a graphics processing unit (GPU), one streaming processor cluster handles one computational task, or multiple streaming processor clusters handle one computational task. Multiple streaming processor clusters share data through a global cache or global memory.

[0121] like Figure 5 As shown, a streaming processor cluster includes multiple computing units (CUs). Each computing unit (CU) is used to perform arithmetic and logical operations, such as accumulation, reduction, and regular addition, subtraction, multiplication, and division.

[0122] A computing unit comprises multiple cores (also called computing kernels or computing cores). Each computing core includes an arithmetic logic unit (ALU), a floating-point unit, etc., and is used to execute specific computational tasks. In addition, the computing unit also includes registers (e.g., ... Figure 5 The register file and shared memory in a computing unit are used to store source and destination data related to computing tasks in a hierarchical manner. The shared memory in a computing unit is used to share data between the cores of that computing unit.

[0123] like Figure 5 As shown, each computing unit also provides a tensor core for performing tensor-related computations, such as tensor shrinking operations. Tensor cores can accelerate tensor operations such as matrix multiplication. Tensor cores in multiple computing units can be scheduled and controlled uniformly.

[0124] In parallel computing, computational tasks are typically executed by multiple threads. These threads are divided into multiple thread blocks before execution in the graphics processing unit (or parallel computing processor), and then dispatched via a thread block distribution module. Figure 5 (Not shown in the image) Multiple thread blocks are distributed to various computation units. All threads in a thread block must be assigned to the same computation unit for execution. Simultaneously, thread blocks are broken down into minimum execution thread bundles (or simply warps), each containing a fixed number (or less than this fixed number) of threads, for example, 32 threads. Multiple thread blocks can execute in the same computation unit or in different computation units.

[0125] In each computing unit, the thread beam scheduling / distribution module ( Figure 5(Not shown in the diagram) Thread bundles are scheduled and allocated so that multiple computing cores within the computing unit can run thread bundles. Depending on the number of computing cores in the computing unit, multiple thread bundles within a thread block can execute concurrently or in a time-sharing manner. Multiple threads within each thread bundle execute the same instructions. Memory-executed instructions are issued to shared memory within the computing unit or further issued to intermediate-level caches, global caches, or global memory (e.g., [example cache]). Figure 5 High Bandwidth Memory (HBM) is used for read and write operations.

[0126] At least one embodiment of this disclosure also provides an electronic device. Figure 6 A schematic structural diagram of an electronic device provided for at least one embodiment of this disclosure.

[0127] like Figure 6 As shown, the electronic device 300 includes a chip 200. Further description of the chip 200 can be found in the relevant descriptions of the foregoing embodiments, and will not be repeated here.

[0128] For example, the electronic device could be a multi-GPU system, which integrates multiple GPU cards and works together to complete large-scale parallel computing tasks. This architecture is commonly used for tasks such as artificial intelligence training, scientific computing, and high-performance graphics rendering.

[0129] For example, in some embodiments, the electronic device 300 provided in at least one embodiment of this disclosure can be a single-machine multi-card form, where multiple GPU cards are integrated in a single server or workstation, and inter-card communication is achieved through a bus (such as PCIe bus, AMD bus, etc.). For example, the electronic device 300 can also be a multi-machine multi-card form, where multiple single-machine multi-card servers are interconnected through a high-speed network to form a cluster, and each card can not only communicate with other cards in its own machine, but also interact with cards in other groups through the network.

[0130] For example, electronic device 300 can also be a TPU cluster, a multi-FPGA accelerator card system, etc., and this disclosure does not impose specific limitations on it.

[0131] For example, this electronic device 300 overcomes the limitations of single-card computing power or memory through parallel computing, and is therefore widely used in scenarios requiring large-scale data processing, high-throughput computing, or low-latency parallel tasks. Examples include deep learning and large model training, high-performance computing, large-scale data processing and AI inference, real-time rendering and visualization, and it can be applied to fields such as large model training, scientific computing, high-concurrency AI services, and real-time rendering.

[0132] Figure 7 This is a schematic block diagram of an electronic device provided in one embodiment of the present disclosure.

[0133] like Figure 7 As shown, Figure 7 The components of the electronic device 300 shown are merely exemplary and not limiting. The electronic device 300 may have other components as needed for the actual application.

[0134] like Figure 7 As shown, the electronic device 300 may include a processing device 301 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to non-transitory computer-readable instructions stored in memory to achieve various functions.

[0135] For example, the processing device 301 may adopt the structure or function of the aforementioned chip 200.

[0136] For example, the memory may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) 303 and / or cache memory, etc., whereby computer-readable instructions can be loaded from storage device 308 into RAM 303 to execute. Non-volatile memory may include, for example, read-only memory (ROM) 302, hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB storage, flash memory, etc. Various applications and various data, such as various data used and / or generated by applications, may also be stored in the computer-readable storage medium.

[0137] For example, the processing device 301, the read-only memory (ROM) 302, and the random access memory (RAM) 303 are interconnected via a bus 304. The input / output (I / O) interface 305 is also connected to the bus 304.

[0138] Typically, the following devices can be connected to the input / output (I / O) interface 305: input devices 306 including, for example, a touchscreen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; output devices 307 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage devices 308 including, for example, magnetic tape, hard disk, flash memory, etc.; and communication devices 309. Communication device 309 allows electronic device 300 to communicate wirelessly or wiredly with other electronic devices to exchange data. Although Figure 7An electronic device 300 with various devices is shown, but it should be understood that it is not required to implement or possess all of the devices shown, and the electronic device 300 may alternatively implement or possess more or fewer devices. For example, a processing device 301 can control other components in the electronic device 300 to perform desired functions. The processing device 301 may be a device with data processing capabilities and / or program execution capabilities, such as a central processing unit (CPU), a tensor processor (TPU), or a graphics processing unit (GPU). The central processing unit (CPU) may be an x86, ARM, RISC-V architecture, etc. The GPU may be directly integrated into the SOC, directly integrated onto the motherboard, or built into the northbridge chip of the motherboard.

[0139] At least one embodiment of this disclosure also provides a parallel data transmission method. Figure 8 This is a schematic flowchart illustrating a parallel data transmission method provided in at least one embodiment of the present disclosure.

[0140] like Figure 8 As shown, the parallel data transmission method includes steps S10 and S20.

[0141] In step S10, N analog signals are transmitted in parallel through N data lines.

[0142] In step S20, parallel conversion between N analog signals and N digital signals is performed through a digital-to-analog conversion interface.

[0143] At least one of the N data lines is divided into multiple data traces. For each first data line, a buffer is provided between every two adjacent data traces in the multiple data traces included in the first data line. The buffer is used to drive the transmission of analog signals in the first data line.

[0144] The line width of each data trace is a fixed value. The line width of the data trace is related to the distance between the data trace and the digital-to-analog conversion interface. The farther the data trace is from the digital-to-analog conversion interface, the wider the line width.

[0145] For more details on the digital-to-analog conversion interface and the N data lines, please refer to the aforementioned description of the parallel data interface circuit; it will not be repeated here.

[0146] The parallel data transmission method provided in at least one embodiment of this disclosure divides a single data line into multiple data traces and adds a buffer between two adjacent data traces, so that each data trace can be driven by the buffer, effectively improving the signal transmission speed and enabling high-speed transmission.

[0147] Furthermore, the data traces farther from the digital-to-analog conversion interface have wider trace widths. When the data traces are wider, their jitter and latency are reduced. Therefore, compared to the current approach of setting the width of the entire data line to be the same, the parallel data transmission method provided in at least one embodiment of this disclosure can reduce the jitter and latency generated by a single data line as a whole. Moreover, the latency of data traces farther from the digital-to-analog conversion interface is lower, reducing the transmission latency difference between data lines and further reducing signal skew between multiple data lines, thereby further reducing data jitter and improving data transmission speed to support and realize high-speed parallel interfaces.

[0148] The parallel data transmission method provided in at least one embodiment of this disclosure can achieve similar technical effects to the aforementioned parallel data interface circuit, and will not be described again here.

[0149] Figure 9 A schematic diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of this disclosure. For example, such as Figure 9 As shown, storage medium 400 can be a non-transitory computer-readable storage medium on which one or more computer-readable instructions 401 can be stored non-transitory. For example, when the computer-readable instructions 401 are executed by a processor, one or more steps in the parallel data transfer method described above can be performed.

[0150] For example, the storage medium 400 can be used in an electronic device 300, such as the storage medium 400 including the storage device 308 in the electronic device 300.

[0151] For example, a storage device may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB storage, flash memory, etc. One or more computer-readable instructions may be stored on the computer-readable storage medium, and a processor may execute these instructions to perform various functions of the processor. Various application programs and various data may also be stored in the storage medium.

[0152] For example, the storage medium may include a memory card for a smartphone, a cache component for a tablet computer, a hard disk for a personal computer, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), flash memory, or any combination of the above storage media, or other suitable storage media.

[0153] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0154] The units described in the embodiments of this disclosure can be implemented in software or hardware. The names of the units are not, in some cases, intended to limit the specific unit.

[0155] The functions described above in this document can be performed at least in part by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SoCs), complex programmable logic devices (CPLDs), and so on.

[0156] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

[0157] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0158] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

[0159] The following points should be noted regarding this disclosure:

[0160] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0161] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0162] The above description is only a specific embodiment of this disclosure, but the protection scope of this disclosure is not limited thereto. The protection scope of this disclosure should be determined by the protection scope of the claims.

Claims

1. A parallel data interface circuit, characterized in that, Used for parallel conversion and transmission between signals in the digital domain and signals in the analog domain within the chip. The parallel data interface circuit includes a digital-to-analog conversion interface and a first circuit located in the analog domain. The digital-to-analog conversion interface is configured to perform parallel conversion between N analog signals and N digital signals, where N is a positive integer greater than 1; The first circuit includes N data lines configured to transmit the N analog signals in parallel through the N data lines, with each data line configured to transmit one analog signal. At least one of the N data lines is divided into multiple data traces. For each first data line, a buffer is provided between every two adjacent data traces in the multiple data traces included in the first data line. The buffer is configured to drive the transmission of analog signals in the first data line. The line width of each data trace is a fixed value. The line width of the data trace is related to the distance between the data trace and the digital-to-analog conversion interface. The data trace farther away from the digital-to-analog conversion interface has a wider line width.

2. The parallel data interface circuit according to claim 1, characterized in that, The first data line is divided into multiple data traces, including the first data trace closest to the digital-to-analog conversion interface. The line width of the first data trace is the minimum value among the line widths of the multiple data traces. The length of the first data trace is determined according to the signal transmission speed requirements of the parallel data interface circuit, and the trace width of the first data trace is determined according to N and the length of the die edge allocated to the first circuit.

3. The parallel data interface circuit according to claim 2, characterized in that, The multiple data traces also include a second data trace adjacent to the first data trace. When the first quantity and the second quantity are the same, the line width of the first data trace and the second data trace are the same, wherein the first quantity is N, and the second quantity is the number of the at least one first data trace; When the first quantity and the second quantity are different, the line width of the first data trace is smaller than the line width of the second data trace.

4. The parallel data interface circuit according to claim 2, characterized in that, The first data line is divided into multiple data lines according to the length of the first data trace. When the length of the first data line cannot be divided into multiple segments according to the length of the first data trace, the length of the third data trace is less than the length of the first data trace, and the lengths of the other data traces in the first data line are the same as the length of the first data trace. The third data trace is the data trace that is farthest from the digital-to-analog conversion interface among the multiple data trace segments.

5. The parallel data interface circuit according to claim 2, characterized in that, Of the N data lines, the length of the other data lines besides the at least one first data line is less than the length of the first data trace. At least one data trace has a consistent line width, wherein the distance between the first position of each of the at least one data trace and the digital-to-analog conversion interface is the same, and the first position includes the endpoint or midpoint of each data trace.

6. The parallel data interface circuit according to claim 1, characterized in that, Each data line is equipped with a trigger for transmitting analog signals, and the trigger uses a clock signal as the trigger signal.

7. The parallel data interface circuit according to claim 6, characterized in that, For each first data line, the trigger is set at the signal output terminal of the target data trace among the multiple data traces included in the first data line, wherein the target data trace is determined according to the data jitter value corresponding to the first data line. For the N data lines other than the at least one first data line, the trigger is set at the signal output terminal of each of the other data lines.

8. The parallel data interface circuit according to claim 7, characterized in that, The target data trace is the i-th data trace among the multiple data traces. Where i is a positive integer and equal to P is the maximum value among the total number of data traces corresponding to the N data lines. The total number of data traces corresponding to each first data line is the total number of data traces divided into the first data line. The total number of data traces corresponding to each of the other data lines is 1. This represents the floor function. When the total number of data traces corresponding to a data line is less than or equal to i, the trigger is set at the output terminal of the data line.

9. The parallel data interface circuit according to claim 1, characterized in that, The total lengths of the N data lines are different from each other, and the spacing between at least one data line arranged in parallel at a location farther away from the digital-to-analog conversion interface is larger.

10. The parallel data interface circuit according to any one of claims 1-9, characterized in that, The parallel data interface circuit is a physical layer circuit and is located at the edge of the die of the chip.

11. The parallel data interface circuit according to any one of claims 1-9, characterized in that, The digital-to-analog conversion interface is a digital-to-analog conversion interface, configured to convert the N digital signals received by the digital-to-analog conversion interface into the N analog signals in parallel. The first circuit is configured to transmit the N analog signals to an analog circuit transmitter via the N data lines, so that the signals can be transmitted to the physical output interface of the chip via the analog circuit transmitter.

12. The parallel data interface circuit according to any one of claims 1-9, characterized in that, When the digital-to-analog conversion interface is an analog-to-digital conversion interface, the analog-to-digital conversion interface is configured to convert the N analog signals output by the first circuit into the N digital signals in parallel, and The analog signal input from the physical input interface of the chip is processed by the analog circuit receiver and then transmitted to the first circuit, and then transmitted to the analog-to-digital conversion interface through the N data lines.

13. A chip, characterized in that, Includes the parallel data interface circuit as described in any one of claims 1-12.

14. An electronic device, characterized in that, Includes the chip as described in claim 13.

15. A parallel data transmission method, characterized in that, Used for parallel conversion and transmission between signals in the digital domain and signals in the analog domain within the chip. The parallel data transmission method includes: N analog signals are transmitted in parallel through N data lines; Parallel conversion between the N analog signals and the N digital signals is performed through a digital-to-analog conversion interface; Among them, at least one of the N data lines is divided into multiple data traces. For each first data line, a buffer is provided between every two adjacent data traces in the multiple data traces included in the first data line. The buffer is used to drive the transmission of analog signals in the first data line. The line width of each data trace is a fixed value. The line width of the data trace is related to the distance between the data trace and the digital-to-analog conversion interface. The data trace farther away from the digital-to-analog conversion interface has a wider line width.

16. A non-transitory computer-readable storage medium, characterized in that, The non-transitory computer-readable storage medium stores computer-executable instructions. When the computer-executable instructions are executed by the processor, the parallel data transmission method according to claim 15 is implemented.

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