Simulation method, device and system for offset voltage of comparator
By employing a phased simulation and confidence-weighted fusion method, the problems of slow simulation speed and insufficient accuracy of comparator offset voltage are solved, achieving efficient and accurate simulation results that are suitable for offset voltage evaluation of dynamic comparators.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING TSINGTENG MICROSYSTEM CO LTD
- Filing Date
- 2026-01-21
- Publication Date
- 2026-05-15
AI Technical Summary
Existing comparator offset voltage simulation methods are slow, resource-intensive, and lack accuracy, failing to meet the requirements of high-resolution and high-bandwidth ADCs.
By determining the initial search interval, initial bias voltage, and step size, simulations are performed in stages. Combining confidence judgment and weighted fusion improves simulation speed and accuracy.
It reduces simulation time, lowers resource consumption, improves the accuracy and reliability of simulation results, and adapts to different comparators and operating conditions.
Smart Images
Figure CN122047136A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and for example to a simulation method, apparatus, and system for comparator offset voltage. Background Technology
[0002] The dynamic comparator is a crucial analog module in an ADC (Analog-to-Digital Converter), and its offset voltage can affect the overall performance of the ADC, even leading to malfunction. Therefore, evaluating the offset voltage of the dynamic comparator is essential during design simulation. In recent years, with the rapid iteration of communication protocols, various communication chips have increasingly higher requirements for ADC resolution and bandwidth. This means that the dynamic comparator circuit in the ADC needs to resolve weaker signals under faster clock signals, making the evaluation of the dynamic comparator's offset voltage paramount.
[0003] In related technologies, a comparator offset voltage simulation circuit is disclosed, combined with Figure 1 As shown, under the operating clock, a slow ramp signal is input to one end of the dynamic comparator, while the other end is a fixed reference level. The voltage difference between the two ends is observed at the instant of the output transition. The absolute value of the voltage difference is the comparator's offset voltage, and the sign represents the polarity of the offset voltage. The input ramp signal needs to be slow enough to ensure that the signal change between two adjacent operating clock cycles is less than the least significant bit of the ADC, and a sufficiently large voltage drop is required to ensure that the input signal can cover the offset voltage under all mismatch conditions.
[0004] In the process of implementing the embodiments of this disclosure, at least the following problems were found in the related art: Simulation methods in related technologies are limited by simulation speed, which is determined by the comparator's operating clock frequency and the least significant bit of the ADC. Under the same simulation accuracy, it takes longer and consumes more simulation resources.
[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0006] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.
[0007] This disclosure provides a method, apparatus, and system for simulating comparator offset voltage, thereby improving the simulation speed of comparator offset voltage.
[0008] In some embodiments, the simulation method for comparator offset voltage includes: determining an initial search interval, an initial bias voltage, a step size, and a current operating stage, and entering the current operating stage when the comparator is in a steady state; if the current operating stage is a first stage, determining the voltage range at which the comparator output first flips within the initial search interval based on the initial bias voltage, and entering a second stage; if the current operating stage is a second stage, converging the voltage range and reducing the step size based on the comparator operating state to determine the offset voltage and confidence level in the current polarity direction; and weightedly fusing the first offset voltage and first confidence level in the positive polarity direction, and the second offset voltage and second confidence level in the reverse polarity direction to obtain the target offset voltage.
[0009] Optionally, the comparator is determined to be in a steady state as follows: the current bias voltage is maintained at the falling edge of each comparator clock, and the comparator output is sampled multiple times to obtain the multiple sampling results and their confidence levels, and the number of toggles is counted; if the number of toggles exceeds a first threshold or the confidence level is lower than a second threshold, the comparator is determined to be in a metastable state; if the number of toggles does not exceed the first threshold and the confidence level is not lower than the second threshold, the comparator is determined to be in a steady state.
[0010] Optionally, the simulation method for comparator offset voltage further includes: when the comparator is in a metastable state, reducing the current step size, backing up the current bias voltage along the current polarity direction, and then re-evaluating whether the comparator is in a steady state.
[0011] Optionally, determining the voltage range at which the comparator output first flips within the initial search interval based on the initial bias voltage includes: increasing the initial bias voltage in the current polarity direction to determine the voltage range at which the comparator output first flips.
[0012] Optionally, the voltage interval is converged and the step size is reduced based on the comparator's operating state to determine the offset voltage and confidence level in the current polarity direction. This includes: determining the comparator's operating state based on the midpoint bias voltage of the voltage interval to obtain a determination result; determining the assignment of one side of the voltage interval based on the determination result and converging the voltage interval; continuing to determine the comparator's operating state and converge the voltage interval based on the midpoint bias voltage of the converged voltage interval, and reducing the step size; and determining the offset voltage and confidence level in the current polarity direction when the width of the converged voltage interval is less than a third threshold and the comparator is in a steady state.
[0013] Optionally, the simulation method for the comparator offset voltage further includes feeding back the current bias voltage to the comparator input at the end of each clock edge of the comparator clock.
[0014] Optionally, the simulation method for comparator offset voltage also includes: in the case of hot start, determining the initial bias voltage, step size and hot start voltage range based on the hot start parameters, and entering the second stage when the comparator is in a steady state.
[0015] In some embodiments, the simulation apparatus for comparator offset voltage includes a processor and a memory storing program instructions, the processor being configured to execute the simulation method for comparator offset voltage as described above when the program instructions are executed.
[0016] In some embodiments, a simulation system for comparator offset voltage includes: a comparator under test; a simulation device equipped with the simulation apparatus for comparator offset voltage as described above; the simulation device having a non-inverting input, an inverting input, an output, and a clock signal; the non-inverting input is connected to the output of the comparator under test, the inverting input is grounded, and the clock signal is connected to the clock signal of the comparator under test; and a balun device having a first input, a second input, a first output, and a second output; the first input is connected to the output of the simulation device, the second input is connected to a reference voltage, the first output is connected to the positive input of the comparator under test, and the second output is connected to the negative input of the comparator under test.
[0017] Optionally, the simulation apparatus for the comparator offset voltage is implemented by compiling Verilog-A code and encapsulating it into an IP implementation of an ahdl that can be called in virtuoso; and / or, by reducing the upper limit of the scan voltage of the simulation apparatus, the speed of determining the voltage range in the first stage can be improved.
[0018] The simulation method, apparatus, and system for comparator offset voltage provided in this disclosure can achieve the following technical effects: In this embodiment, parameters such as the initial search interval, initial bias voltage, and step size are determined before simulation begins, and the tasks for different working stages are defined. The first stage determines a voltage interval when the comparator output first flips. Then, in the second stage, by combining voltage interval convergence and step size reduction, the voltage interval is progressively refined and the offset voltage is precisely located. Compared to methods in related technologies, this embodiment does not require slow input signals to ensure simulation accuracy, thus reducing simulation time, increasing the simulation speed of the comparator offset voltage, and consuming fewer simulation resources. Furthermore, by measuring both positive and negative offset voltages, the comprehensiveness of the measurement results is ensured. Weighted fusion of the positive and negative measurement results using confidence levels results in a more accurate and reliable target offset voltage, further improving the accuracy of the simulation results.
[0019] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description
[0020] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein: Figure 1 This is a circuit diagram of a comparator offset voltage simulation circuit in related technologies; Figure 2 This is a schematic diagram of a simulation method for comparator offset voltage provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram of a method for determining whether a comparator is in a steady state, provided in an embodiment of this disclosure; Figure 4 This is a schematic diagram of another simulation method for comparator offset voltage provided in an embodiment of this disclosure; Figure 5 This is a schematic diagram of a simulation device for comparator offset voltage provided in an embodiment of this disclosure; Figure 6 This is a schematic diagram of a simulation system for comparator offset voltage provided in an embodiment of this disclosure. Detailed Implementation
[0021] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.
[0022] The terms "first," "second," etc., used in the technical solutions described in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.
[0023] Unless otherwise stated, the term "multiple" means two or more.
[0024] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.
[0025] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.
[0026] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.
[0027] Combination Figure 2 As shown, this disclosure provides a simulation method for comparator offset voltage. The execution entity of this simulation method can be a processor, and the simulation method includes: S201, the processor determines the initial search range, initial bias voltage, step size and current operating stage, and enters the current operating stage when the comparator is in a steady state.
[0028] S202, when the processor is in the first working stage, it determines the voltage range at which the comparator output first flips in the initial search range based on the initial bias voltage, and then enters the second stage.
[0029] S203, when the processor is in the second stage of operation, it converges the voltage range and reduces the step size according to the comparator's operating state to determine the offset voltage and confidence level in the current polarity direction.
[0030] S204, the processor performs weighted fusion of the first offset voltage and first confidence level of the positive polarity, and the second offset voltage and second confidence level of the reverse polarity, to obtain the target offset voltage.
[0031] In this embodiment, parameters such as the initial search interval, initial bias voltage, and step size are determined before simulation begins, and the tasks for different working stages are defined. The first stage determines a voltage interval when the comparator output first flips. Then, in the second stage, by combining voltage interval convergence and step size reduction, the voltage interval is progressively refined and the offset voltage is precisely located. Compared to methods in related technologies, this embodiment does not require slow input signals to ensure simulation accuracy, thus reducing simulation time, increasing the simulation speed of the comparator offset voltage, and consuming fewer simulation resources. Furthermore, by measuring both positive and negative offset voltages, the comprehensiveness of the measurement results is ensured. Weighted fusion of the positive and negative measurement results using confidence levels results in a more accurate and reliable target offset voltage, further improving the accuracy of the simulation results.
[0032] Optionally, the comparator is determined to be in a steady state as follows: the current bias voltage is maintained at the falling edge of each comparator clock, and the comparator output is sampled multiple times to obtain the multiple sampling results and their confidence levels, and the number of toggles is counted; if the number of toggles exceeds a first threshold or the confidence level is lower than a second threshold, the comparator is determined to be in a metastable state; if the number of toggles does not exceed the first threshold and the confidence level is not lower than the second threshold, the comparator is determined to be in a steady state.
[0033] In this embodiment, by maintaining the current bias voltage at the falling edge of each comparator clock and sampling the comparator output multiple times, it is possible to accurately determine whether the comparator is in a steady state. By considering two key indicators—the number of toggles and the confidence level—the steady-state and metastable state of the comparator can be accurately distinguished. The stability of the comparator output can be determined by counting the number of toggles in multiple samplings. If the number of toggles exceeds a set first threshold, it indicates that the comparator output is unstable and in a metastable state. The reliability of the comparator output can be determined by calculating the confidence level of the majority vote. If the confidence level is lower than a set second threshold, it indicates that the comparator output lacks stability and is in a metastable state.
[0034] Optionally, the simulation method for comparator offset voltage further includes: when the comparator is in a metastable state, reducing the current step size, backing up the current bias voltage along the current polarity direction, and then re-evaluating whether the comparator is in a steady state.
[0035] In this embodiment, when the comparator is in a metastable state, the comparator state is reassessed by reducing the step size and backing up the bias voltage. This effectively handles the metastability problem and avoids simulation misjudgments and inaccurate results caused by metastability. By reducing the step size, the accurate value of the offset voltage can be searched more precisely, reducing misjudgments caused by excessively large step sizes. Backing up the bias voltage along the current polarity direction avoids skipping the true offset point due to excessively large step sizes, thereby improving simulation accuracy.
[0036] Combination Figure 3 As shown, this disclosure provides a method for determining whether a comparator is in a steady state, including: S301: The processor maintains the current bias voltage on the falling edge of each comparator clock, samples the comparator output multiple times, obtains the sampling results and their confidence levels, and counts the number of toggles.
[0037] S302, the processor determines whether the number of flips exceeds the first threshold or the confidence level is lower than the second threshold. If not, S303 is executed; if so, S304 is executed.
[0038] S303, the processor determines that the comparator is in a steady state.
[0039] S304, the processor determines that the comparator is in a metastable state.
[0040] S305, the processor decreases the current step size, rolls back the current bias voltage along the current polarity direction, and executes S301.
[0041] In one specific embodiment, to determine whether the comparator is in a steady state, an iteration is performed at the falling edge of each comparator clock. Each iteration samples for several cycles while maintaining the same bias voltage `cur_offset`. At this fixed bias voltage point, the majority result `maj_bit` of the comparator response, its consistency confidence `conf`, and the number of flips (`flips`) of the response bit between these samples are counted to measure the stability of the decision corresponding to that bias voltage point. If the current bias voltage point is determined to be metastable (the number of flips exceeds a first threshold or the confidence is below a second threshold), the decision is considered unreliable. When the comparator is metastable, the step size `step` is reduced, and a small backtrack is performed along the current search direction `dir` to maintain direction consistency. Then, the sampling counter is reset to zero, and resampling is performed in that vicinity.
[0042] Optionally, determining the voltage range at which the comparator output first flips within the initial search interval based on the initial bias voltage includes: increasing the initial bias voltage in the current polarity direction to determine the voltage range at which the comparator output first flips.
[0043] In this embodiment, by increasing the initial bias voltage in the current polarity direction and determining the voltage range when the comparator output first flips, the approximate range of the offset voltage can be quickly located. Using a unidirectional coarse scan, the boundary of the comparator output flip is quickly found, thus locking in the range where the offset voltage is located. By unidirectionally increasing the bias voltage, the point of comparator output flip can be quickly found in fewer iterations, thereby determining the approximate range of the offset voltage and reducing search time. Determining the initial flip point provides a clear boundary for subsequent fine-grained searches, allowing the second-stage search to be performed within a smaller range, improving overall search efficiency.
[0044] In one specific embodiment, in the first stage, the bias voltage cur_offset is unidirectionally advanced in a fixed direction until the first flip of the comparator output from 0 to 1 or from 1 to 0 is detected, thereby locking a voltage range containing the actual offset voltage point, and switching to the second stage.
[0045] Optionally, the voltage interval is converged and the step size is reduced based on the comparator's operating state to determine the offset voltage and confidence level in the current polarity direction. This includes: determining the comparator's operating state based on the midpoint bias voltage of the voltage interval to obtain a determination result; determining the assignment of one side of the voltage interval based on the determination result and converging the voltage interval; continuing to determine the comparator's operating state and converge the voltage interval based on the midpoint bias voltage of the converged voltage interval, and reducing the step size; and determining the offset voltage and confidence level in the current polarity direction when the width of the converged voltage interval is less than a third threshold and the comparator is in a steady state.
[0046] In this embodiment, the voltage range is gradually narrowed through successive approximations, ultimately leading to a precise determination of the offset voltage value. The comparator's operating state is used to determine the midpoint bias voltage within the voltage range, ensuring that each iteration gets closer to the true offset voltage value. Each iteration, by determining the comparator's output state at the midpoint bias voltage, gradually narrows the voltage range, eventually converging to a value very close to the true offset voltage. When the width of the voltage range is less than a set third threshold, a sufficiently accurate offset voltage value can be considered to have been found, thus ensuring high measurement accuracy.
[0047] In a specific embodiment, in the second stage, the current decision result is taken as the assignment to one side of the interval. The voltage interval [lo, hi] is continuously narrowed using this decision, and the midpoint of the voltage interval, mid, is taken as the new bias voltage, cur_offset, and the test continues. The step size is gradually reduced. When the voltage interval width converges to the set tolerance eps and the confidence level conf meets the stability threshold stability_req, the offset voltage in the current polarity direction is considered to have been located. If the current scan direction is positive (dir=+1), the result is recorded as the first offset voltage off_pos and its first confidence level conf_pos. Then, the search direction is flipped to dir=-1, the current working stage is reset to the first stage, and the same process is repeated with the opposite polarity. When the reverse scan is also completed, the second offset voltage off_neg and its second confidence level conf_neg can be obtained. The positive and reverse results are weighted and fused according to the confidence level to obtain the target offset voltage. At the same time, phase is set to 4 to indicate completion.
[0048] Combination Figure 4 As shown, this disclosure provides another simulation method for comparator offset voltage, including: S401, the processor determines the initial search range, initial bias voltage, step size, and current operating stage.
[0049] S402, the processor enters the current working phase when the comparator is in a steady state.
[0050] S403, when the processor is in the first stage of operation, it determines the voltage range at which the comparator output first flips in the initial search range based on the initial bias voltage, and then enters the second stage.
[0051] S404: When the processor is currently in the second stage of operation, it converges the voltage range and reduces the step size according to the comparator's operating state to determine the offset voltage and confidence level in the current polarity direction.
[0052] S405, the processor determines whether the offset voltages of the positive and negative polarities have been determined. If yes, it executes S406; otherwise, it executes S407.
[0053] S406, the processor performs weighted fusion of the first offset voltage and first confidence level of the positive polarity, and the second offset voltage and second confidence level of the reverse polarity, to obtain the target offset voltage.
[0054] S407, the processor flips the search direction, resets the current working stage to the first stage, and executes S402.
[0055] Optionally, the target offset voltage V is calculated according to the following formula.t :
[0056] In this embodiment, confidence-weighted scalar calculation more accurately reflects the reliability of each offset voltage. Offset voltages with higher confidence levels have a greater weight in the final result, thereby improving the reliability of the target offset voltage. Offset voltages with positive and negative polarities may differ; weighted fusion can comprehensively consider both cases, avoiding errors caused by measurements in a single direction.
[0057] Optionally, the simulation method for the comparator offset voltage further includes feeding back the current bias voltage to the comparator input at the end of each clock edge of the comparator clock.
[0058] In this embodiment, by feeding back the current bias voltage to the comparator input at the end of each clock edge, real-time dynamic adjustment of the comparator input can be achieved. This allows the simulation process to dynamically adjust subsequent bias voltages based on the current bias voltage and the comparator output state, thereby more accurately approximating the offset voltage. Real-time feedback allows the simulation process to dynamically adjust the bias voltage according to the current comparator state, ensuring that each iteration gets closer to the true offset voltage value and adapting to changes in the comparator under different operating states, thus improving the simulation's adaptability to different comparators and operating conditions.
[0059] In one specific embodiment, at the end of each clock edge, the current bias voltage is driven to the output port offset through the transition function and fed back to the comparator input, so that the comparator continues to receive the next round of stimulation.
[0060] Optionally, the simulation method for comparator offset voltage also includes: in the case of hot start, determining the initial bias voltage, step size and hot start voltage range based on the hot start parameters, and entering the second stage when the comparator is in a steady state.
[0061] In this embodiment, the warm-start mechanism allows the simulation to quickly enter the second stage based on pre-set parameters, without having to start the first stage with a unidirectional coarse traversal from the full range, reducing the search time in the early stages of the simulation and improving the overall simulation efficiency. By directly entering the second stage through warm-start parameters, the coarse traversal process starting from the full range is avoided, significantly reducing the search time in the early stages of the simulation. The warm-start parameters can quickly locate the approximate range of the offset voltage, providing a starting point closer to the true value for subsequent fine-tuning searches.
[0062] In one specific embodiment, at the start of the simulation, an initialization phase is entered to determine the initial search interval [lo, hi], initial bias voltage cur_offset, step size, and current operating phase (phase) based on whether warm start (init_with_seed) is enabled. If warm start is not enabled, the first phase is entered, and phase is set to 0; if warm start is enabled, the second phase is entered, and phase is set to 2.
[0063] Combination Figure 5 As shown, this disclosure provides a simulation device 500 for comparator offset voltage, including a processor 501 and a memory 502. Optionally, the device may further include a communication interface 503 and a bus 504. The processor 501, communication interface 503, and memory 502 can communicate with each other via the bus 504. The communication interface 503 can be used for information transmission. The processor 501 can call logic instructions in the memory 502 to execute the simulation method for comparator offset voltage described in the above embodiment.
[0064] Furthermore, the logic instructions in the aforementioned memory 502 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.
[0065] The memory 502, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this disclosure. The processor 501 executes functional applications and data processing by running the program instructions / modules stored in the memory 502, that is, it implements the simulation method for comparator offset voltage in the above embodiments.
[0066] The memory 502 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 502 may include high-speed random access memory and may also include non-volatile memory.
[0067] Combination Figure 6As shown, this disclosure provides a simulation system 600 for comparator offset voltage, including: a comparator under test 601, a simulation device 602, and a balun device 603. The simulation device 602 is equipped with the simulation device for comparator offset voltage as described above. The installation relationship described herein is not limited to placement within the simulation device 602, but also includes installation connections with other components of the simulation device 602, including but not limited to physical connections, electrical connections, or signal transmission connections. Those skilled in the art will understand that the simulation device for comparator offset voltage can be adapted to a feasible simulation device 602 body to achieve other feasible embodiments. The simulation device 602 is provided with a non-inverting input terminal inp, an inverting input terminal inn, an output terminal vos, and a clock signal terminal clk1; the non-inverting input terminal inp is connected to the output terminal Q of the comparator under test 601, the inverting input terminal inn is grounded, and the clock signal terminal clk1 is connected to the clock signal terminal clk2 of the comparator under test 601. The balun device 603 is provided with a first input terminal, a second input terminal, a first output terminal, and a second output terminal; the first input terminal is connected to the output terminal of the simulation device 602, the second input terminal is connected to the reference voltage VREF, the first output terminal is connected to the positive input terminal of the comparator under test 601, and the second output terminal is connected to the negative input terminal of the comparator under test 601.
[0068] Optionally, the simulation apparatus for the comparator offset voltage is implemented by compiling Verilog-A code and encapsulating it into an IP implementation of an ahdl that can be called in virtuoso; and / or, by reducing the upper limit of the scan voltage of the simulation apparatus, the speed of determining the voltage range in the first stage can be improved.
[0069] In this embodiment, Verilog-A code is compiled and encapsulated into an AHDL IP that can be called in Virtuoso by using simulation device 602. The input of simulation device 602 is in pseudo-differential form, with the non-inverting input connected to the comparator's output and the inverting input grounded. The output is the dynamic comparator offset voltage calculated by the algorithm at that clock frequency. In the simulation, this IP is defined as a Veriloga file, and... Figure 6 The comparator under test 601 and the simulation device 602 are connected as shown. The input of the dynamic comparator uses an ideal balun device 603 to convert the single-ended signal into a differential signal. Running the transient simulation requires no additional precision settings. The simulation report will display the current offset signal voltage value at each falling edge of the clock. The offset voltage can also be obtained from the waveform graph of the offset to arrive at the final calculated and evaluated offset voltage.
[0070] The simulation method, apparatus, and system for comparator offset voltage using embodiments of this disclosure achieve superior performance in terms of simulation speed, accuracy, and portability. Specifically, the improved simulation speed is achieved by defining the upper and lower limits of the scan voltage and the cycle period of the Verilog-A-based simulation device. This allows for rapid iteration of simulation results to accurate values, calculating only the falling edge of each clock cycle. Furthermore, lowering the upper limit of the scan voltage of the simulation device accelerates the first-stage traversal time, thereby speeding up the simulation iteration. Secondly, the improved simulation accuracy stems from the binary search and feedback loop of the successive approximation algorithm. The iteration results are fed back to the comparator input in real time for comparison with the comparator's intrinsic offset voltage. Within the clock window, the algorithm can rapidly traverse and search for values infinitely close to the intrinsic offset voltage, oscillating around that value. Finally, the operating state of the comparator can be determined based on the voting confidence level, thereby deciding the direction of code execution. This addresses the issue of the comparator being in a metastable state, which can lead to errors in the simulator's offset voltage calculation, thus improving the stability of the simulation results.
[0071] This disclosure provides a computer-readable storage medium storing computer-executable instructions configured to perform the above-described simulation method for comparator offset voltage.
[0072] The technical solutions of this disclosure can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in this disclosure. The aforementioned storage medium can be a non-transitory storage medium, including: a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and other media capable of storing program code.
[0073] The foregoing description and accompanying drawings fully illustrate embodiments of this disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terminology used in this application is for describing embodiments only and is not intended to limit the technical solutions described herein. As used in the technical solutions described herein, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used herein refers to any and all possible combinations of one or more of the associated listed elements. Additionally, when used in this application, the term "comprise" and its variations "comprises" and / or "comprising" refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Without further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes said element. In this document, each embodiment may focus on the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, the relevant parts can be referred to the description of the method section.
[0074] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.
[0075] The methods and products disclosed in the embodiments herein (including but not limited to devices and equipment) can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to implement this embodiment according to actual needs. In addition, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
[0076] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.
Claims
1. A simulation method for comparator offset voltage, characterized in that, include: Determine the initial search range, initial bias voltage, step size, and current operating stage, and enter the current operating stage when the comparator is in a steady state; When the current working stage is the first stage, the voltage range at which the comparator output first flips is determined in the initial search interval based on the initial bias voltage, and then the second stage is entered. When the current working stage is the second stage, the voltage range is converged and the step size is reduced according to the comparator's working state to determine the offset voltage and confidence level in the current polarity direction. The target offset voltage is obtained by weighted fusion of the first offset voltage and the first confidence level of the positive polarity, and the second offset voltage and the second confidence level of the reverse polarity.
2. The simulation method according to claim 1, characterized in that, Determine whether the comparator is in a steady state as follows: The current bias voltage is maintained at the falling edge of each comparator clock, and the comparator output is sampled multiple times to obtain the multiple sampling results and their confidence levels, and the number of toggles is counted. If the number of flips exceeds the first threshold or the confidence level is lower than the second threshold, the comparator is determined to be in a metastable state. If the number of flips does not exceed the first threshold and the confidence level is not lower than the second threshold, the comparator is determined to be in a steady state.
3. The simulation method according to claim 2, characterized in that, Also includes: If the comparator is in a metastable state, reduce the current step size and back the current bias voltage along the current polarity direction, then re-evaluate whether the comparator is in a stable state.
4. The simulation method according to claim 1, characterized in that, The voltage range at which the comparator output first flips is determined within the initial search interval based on the initial bias voltage, including: Increase the initial bias voltage in the current polarity direction, and determine the voltage range when the comparator output first flips.
5. The simulation method according to claim 1, characterized in that, Based on the comparator's operating state, the voltage range is converged and the step size is reduced to determine the offset voltage and confidence level in the current polarity direction, including: The determination result is obtained by comparing the operating state of the comparator based on the midpoint bias voltage of the voltage range; The attribution of one side of the voltage range is determined based on the judgment result, and the voltage range is then converged. Based on the midpoint bias voltage of the converged voltage range, continue to determine the operating state of the comparator and the convergence of the voltage range, and reduce the step size. If the width of the converged voltage range is less than the third threshold and the comparator is in a steady state, determine the offset voltage and confidence level in the current polarity direction.
6. The simulation method according to any one of claims 1 to 5, characterized in that, Also includes: At the end of each clock edge of the comparator clock, the current bias voltage is fed back to the comparator input.
7. The simulation method according to any one of claims 1 to 5, characterized in that, Also includes: When using a hot start, the initial bias voltage, step size, and hot start voltage range are determined based on the hot start parameters, and the second stage is entered when the comparator is in a steady state.
8. A simulation device for comparator offset voltage, comprising a processor and a memory storing program instructions, characterized in that, The processor is configured to, when running the program instructions, execute the simulation method for comparator offset voltage as described in any one of claims 1 to 7.
9. A simulation system for comparator offset voltage, characterized in that, include: Comparator under test; The simulation equipment is equipped with the simulation device for comparator offset voltage as described in claim 8; The simulation equipment is equipped with a non-inverting input terminal, an inverting input terminal, an output terminal, and a clock signal terminal; the non-inverting input terminal is connected to the output terminal of the comparator under test, the inverting input terminal is grounded, and the clock signal terminal is connected to the clock signal terminal of the comparator under test; The balun device is provided with a first input terminal, a second input terminal, a first output terminal, and a second output terminal; The first input terminal is connected to the output terminal of the simulation device, the second input terminal is connected to the reference voltage, the first output terminal is connected to the positive input terminal of the comparator under test, and the second output terminal is connected to the negative input terminal of the comparator under test.
10. The simulation system according to claim 9, characterized in that, The simulation setup for comparator offset voltage is implemented by compiling Verilog-A code and encapsulating it into an ahdl IP that can be called in Virtuoso; and / or, By lowering the upper limit of the scanning voltage of the simulation equipment, the speed of determining the voltage range in the first stage can be improved.