Layout link tracking efficiency optimization method based on through hole embedded index

Abstract

The invention discloses a layout link tracking efficiency optimization method based on a through hole embedded index, belongs to the field of integrated circuit electronic design automation (EDA), and particularly relates to a data organization and index construction method for layout link tracking. The method comprises the following steps: performing uniform grid division on a layout region, and constructing an R *-tree index structure in a metal layer in each grid; by utilizing the characteristic that the through holes need to be wrapped by upper and lower layers of metal under a process rule, screening and accurately judging metal polygons containing the through holes in the indexes of the upper and lower layers of metal corresponding to the through holes, and establishing an embedded index relationship between the through holes and the metal polygons; on the basis, the link tracking process is based on embedded through hole information, connected metal is positioned in a cross-layer mode, and constant overhead traversal of layout links is achieved; according to the method, the construction frequency of the spatial index structure is reduced, the cross-layer query overhead in the link tracking process is greatly reduced, and the overall efficiency of super-large-scale integrated circuit layout link tracking can be effectively improved.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design and EDA (Electronics Design Automation), specifically relating to a layout link tracing efficiency optimization method based on via embedded index, which is used to improve the link tracing efficiency between cross-layer metals in integrated circuit layout. Background Technology

[0002] With the continuous evolution of integrated circuit manufacturing processes, the number of back end-of-line (BEOL) layers continues to increase, significantly enhancing the quantity and complexity of metal interconnects and via structures in the layout. In electronic design automation (EDA) tools, layout link tracing serves as a fundamental function in processes such as physical verification, parasitic parameter extraction, and layout analysis, and its execution efficiency has a significant impact on the overall design flow.

[0003] In existing integrated circuit layouts, especially in BEOL layouts, electrical connections are primarily achieved through multiple layers of metal and vias. Compared to direct interconnections within the same metal layer, cross-layer interconnections vias constitute the majority of the overall connectivity structure, while direct electrical connections between metals on the same layer are relatively rare. Consequently, during layout link tracing, a large number of tracing operations are concentrated on cross-layer connectivity paths between metal layers and via layers, i.e., frequent switching and searching between metal-via-metal.

[0004] On the other hand, due to the design rules of integrated circuit manufacturing process, vias usually adopt a regular rectangular geometry. In order to ensure the reliability of electrical connection and reduce connection resistance, vias usually need to be surrounded by metal polygons of the adjacent metal layers above and below in the layout. That is, the via is located in the internal area of ​​the metal polygons of the upper and lower layers in terms of geometric position, and the metal polygons have a certain extension range around the via.

[0005] In existing technologies, layout link tracing typically employs a method of constructing separate spatial index data structures for each metal layer and via layer. For example, R-trees or their variants are created for metal layers and via layers respectively to support spatial queries and connectivity determination during link tracing. However, when the number of vias in a BEOL layout is far greater than the number of metal interconnects on the same layer, constructing a separate spatial index structure for the via layer not only increases the overhead of data structure construction and storage but also requires frequent cross-layer queries between the metal layer index and the via layer index during link tracing, thus limiting the efficiency of cross-layer link tracing.

[0006] Furthermore, existing technologies typically determine the spatial inclusion or intersection relationships between vias and upper / lower layer metal polygons during the link tracing process, lacking pre-organization and indexing of the connectivity relationships between vias and metal polygons. When the layout is large and the number of cross-layer connections is high, this dynamic determination method further increases the computational complexity of the link tracing process, affecting the overall efficiency of cross-layer link tracing.

[0007] Therefore, in the BEOL layout, how to combine the inherent geometric inclusion relationship between vias and metal polygons under the process rules to organize cross-layer connectivity more efficiently, thereby reducing the number of cross-layer queries during link tracing and improving the execution efficiency of cross-layer link tracing, has become a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0008] To address the aforementioned issues, this invention discloses a layout link tracing efficiency optimization method based on via embedded indexes. The method "embeds" the via index into its corresponding upper and lower metal layers, using the geometrically contained metal polygon to index the via. This eliminates the overhead of constructing separate spatial indexes for each via layer. During link tracing, the method utilizes the container maintained by the metal polygon containing all vias within that metal layer, and the container maintained by the via containing the upper and lower metal layers, to achieve rapid cross-layer jumps, significantly improving query speed and overall link tracing efficiency.

[0009] To achieve the above objectives, the technical solution of the present invention is as follows: The layout link tracing efficiency optimization method based on via embedding index includes the following steps: Step 1: Read the integrated circuit layout file to obtain the number of polygons, geometric information, inter-layer connection relationships, and overall spatial range of the layout for each layer. Step 2: Based on the overall spatial range of the layout, the layout area is divided into uniform grids with a size of 10 micrometers × 10 micrometers, and the polygons in the layout are stored in the corresponding grid index containers according to their spatial positions. Step 3: Within each grid index container, construct an R*-tree spatial index data structure for the polygons in the metal layer to support spatial queries of polygons within the metal layer; Step 4: For the through-hole polygons in each grid index container, instead of constructing an independent through-hole layer spatial index structure, we select the metal polygons whose minimum bounding rectangle (MBR) contains the through-hole in the upper and lower metal layer spatial index data structures corresponding to the through-hole, and then make a precise determination through geometric inclusion relationships. Step 5: Based on the precise determination result, establish an embedded index relationship of "through hole-metal" between the through hole and the corresponding upper and lower layer metal polygons, and store the identification information of each other in the through hole and the metal polygon respectively; Step 6: Based on the established "via-metal" embedded index relationship and the metal layer spatial index data structure, perform link tracing starting from the initial metal polygon until the traversal of the metal polygons electrically connected to it is completed.

[0010] This method consists of two phases: steps one through five belong to the data structure construction phase, and step six belongs to the link tracing phase.

[0011] As a supplement to the present invention, the method for reading the layout file in step one is as follows: The vertex coordinates of each layer of polygons are read and stored line by line. During reading, the maximum and minimum values ​​of the vertex x and y coordinates are counted to obtain the bounding rectangle (MBR) of the polygon. At the same time, the number of polygons in each layer and the horizontal axis coordinate range of the layout are recorded. The rule file is parsed and the interconnection relationship between each metal layer and via layer is recorded. For example, M3 is interconnected with Via3, Via3 is interconnected with M4, and M3 and M4 are not directly interconnected.

[0012] As a supplement to the present invention, the method for constructing the uniform grid index container in step two is as follows: Based on the map's extent, divide the length and width by 10 micrometers to obtain the number of horizontal and vertical blocks, and construct an array. Based on the bounding rectangle of a given polygon, calculate which grid it falls on or spans. Store the polygon's pointer in an array corresponding to the indices of the covered grids.

[0013] As a supplement to the present invention, the method for constructing the metal layer polygonal spatial index data structure in step three is as follows: For all polygons of a metal layer in the corresponding mesh, the metal layer spatial index data structure is directly constructed using the RTree constructor in the Boost open-source library based on the pre-calculated bounding rectangle.

[0014] As a supplement to the present invention, the method for screening metal polygons including through holes in step four is as follows: Based on the bounding box of the through-hole, query the covered grid area. For the R*-tree data structure of the upper and lower metal layers in each grid, use the bounding box of the through-hole to query, and further refine the inclusion judgment of all initially queried metal polygons. Specifically, determine whether all four vertices of the through-hole polygon are inside the candidate metal polygon.

[0015] As a supplement to the present invention, the method for establishing the "through hole-metal" embedded index relationship in step five is as follows: Based on the precise determination results obtained in step four, new containers are created for the information structures of vias and metals that have an inclusion relationship. The containers in the metal polygon structure store the structure pointers of all the vias it contains. Similarly, the contained vias also store the structure pointers pointing to their corresponding metal polygons. Based on this, the contained vias can be quickly found from the metal layer polygon, and the metals of other layers can be quickly found from these vias.

[0016] As a supplement to the present invention, the link tracing execution method in step six is ​​as follows: Starting with the polygon in the initial metal layer, the system quickly locates the connected vias based on the pointer information in its via index container. Then, using the pointer information in the index containers of these vias, it quickly retrieves metal polygons in other metal layers. After the upper and lower layer metal polygon query steps are completed, the system searches for metal polygons that spatially intersect with the polygon within the same layer, based on the spatial index data structure of the layer to which the polygon belongs. These new polygons are then stored in a breadth-first search (BFS) queue.

[0017] Based on the R*-tree spatial index data structure of the starting metal layer, the bounding boxes of the starting metal polygons are used for searching. After finding candidate polygons whose bounding boxes intersect, further precise intersection judgment is performed. New polygons that pass the precise intersection judgment are also stored in the BFS queue.

[0018] Each time, a polygon is retrieved from the BFS queue, and the above steps are repeated until the queue is empty. This completes one link tracing process. The polygons retrieved during this process have an electrical connection with the starting polygon, which are the link tracing search results.

[0019] The beneficial effects of this invention are as follows: (1) Reduce the number of spatial indexes to build: By not building additional data structures such as R-trees for the via layers, the index building time and memory usage are significantly reduced, especially in the later BEOL layout where the number of vias is much greater than the number of metals.

[0020] (2) Directness of cross-layer jump: By directly maintaining a list containing via pointers in the information structure of the metal polygon, cross-layer positioning is simplified from "index query (metal → via layer spatial index data structure → metal)" to "direct reading", saving one or more index queries and result filtering.

[0021] (3) Improve link tracing throughput: In breadth-first search, the cross-layer expansion of each metal node becomes a direct operation of O(nlogn), thereby significantly reducing link tracing latency and CPU overhead in typical metal cross-layer interconnection-dominated connectivity scenarios.

[0022] (4) Uniform grid + local R*-tree natural collaboration: The method combines uniform grid + local R*-tree to take into account the problem of segmenting long metal strips and the local density of hot spots, improve the query efficiency of R*-tree, and further accelerate link tracing.

[0023] (5) Good compatibility: This method does not rely on a specific R-tree or other specific data structure for implementation, nor does it change the layout semantics, and is easy to integrate with existing EDA pipelines. Attached Figure Description

[0024] Figure 1 This is a flowchart of the layout link tracing efficiency optimization method based on via embedded indexes according to the present invention.

[0025] Figure 2 This is a schematic diagram of the polygonal bounding box and layout mesh division proposed in this invention.

[0026] Figure 3 This is a schematic diagram of the via distribution in the BEOL layout of this invention.

[0027] Figure 4 This is a schematic diagram of the cross-layer metal interconnect structure of the present invention. Detailed Implementation

[0028] The present invention will be further illustrated below with reference to the accompanying drawings and specific embodiments. It should be understood that the following specific embodiments are for illustrative purposes only and are not intended to limit the scope of the invention.

[0029] like Figure 1 As shown, the layout link tracing efficiency optimization method based on via embedded index described in this invention includes five main steps.

[0030] 1. Input layout file (GDS format), parse and store the vertex coordinates of each layer of polygons. During reading, count the maximum and minimum values ​​of the vertex x and y coordinates to obtain the polygon bounding rectangle (MBR). Simultaneously record the number of polygons in each layer and the range of the layout's x-axis coordinates. Parse the rule file and record the interconnection relationships between each metal layer and via layer.

[0031] 2. Based on the layout area, divide the length and width by 10 micrometers respectively to obtain the number of horizontal and vertical blocks, and construct an array. For example... Figure 2 As shown, the minimum bounding box (MBR) of a polygon is determined based on the maximum and minimum values ​​of its x and y coordinates. The vertices of the bounding box are used to calculate which grid cells it falls on or spans, and the pointer of the polygon is stored in an array of indices corresponding to the covered grid cells. For example... Figure 2 As shown, assuming the map is divided into 20 grids, with the bottom left grid index being 0, the pointer of the polygon will be stored simultaneously in the grid arrays with indices 5, 6, 9, and 10, depending on the polygon's coverage.

[0032] 3. For all polygons of a certain metal layer in the corresponding grid, the spatial index data structure of the metal layer is directly constructed using the RTree constructor in the Boost open source library based on the pre-calculated bounding rectangle of the polygon. Each metal layer of each grid maintains a local R*-tree data structure.

[0033] 4. For example Figure 3 As shown, according to the layout process rules, to improve the reliability of electrical connections, vias are generally fixed-shape rectangles and are contained within the geometry of the upper and lower layer metal polygons. Based on the bounding box range of the via's rectangle, the covered grid area is queried. In the R*-tree data structure of the upper and lower layer metals of the via in each grid, an intersection query is performed using the via's rectangular bounding box. Further precise inclusion judgments are made on all initially queried candidate metal polygons. Specifically, it is determined whether all four vertices of the via polygon are contained within the candidate metal polygons.

[0034] Once a precise determination result is obtained, it can be determined that the metal contains the via. A new container is created within the structure storing the information about the via and the metal. The container in the metal polygon structure stores pointers to the vias it contains; similarly, the contained vias also store pointers to the structure of the metal polygon. Based on this, the "via-metal" embedding index can be constructed incrementally. After construction, the vias contained in the metal layer polygon can be quickly found, and the metals in other layers can be quickly found from these vias.

[0035] 5. Starting with the polygon in the initial metal layer, quickly locate the connected vias based on the pointer information in its via index container. Then, use the pointer information in the index containers of these vias to quickly find metal polygons in other metal layers. Store these new polygons in a breadth-first search (BFS) queue. For example... Figure 4 As shown, metal 1 points to vias 1 and 2, via 1 points to metals 1 and 2, and via 2 points to metals 1 and 3. At the same time, metal 2 points to a new via 3, and via 3, in addition to pointing to metal 2, points to a new metal 4. Thus, based on the "via-metal" embedded index, metals 2, 3, and 4 are quickly found from metal 1, moving from M3 to M4, and finally to M5.

[0036] The next step is to find intersecting metals on the same layer as the starting metal. Based on the R*-tree spatial index data structure of the starting metal layer, the bounding boxes of the starting metal polygons are used for searching. After finding candidate polygons whose bounding boxes intersect, further precise intersection checks are performed. New polygons that pass the precise intersection check are also stored in the BFS queue.

[0037] Each time, a polygon is retrieved from the BFS queue, and the above steps are repeated until the queue is empty. This completes one link tracing process. The polygons retrieved during this process have an electrical connection with the starting polygon, which are the link tracing search results.

[0038] It should be noted that the above content merely illustrates the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. For those skilled in the art, various improvements and modifications can be made without departing from the principle of the present invention, and all such improvements and modifications fall within the scope of protection of the claims of the present invention.

Claims

1. A layout link tracing efficiency optimization method based on via embedding indexes, applied to link tracing in integrated circuit layouts, characterized in that, The method includes the following steps: Step 1: Read the integrated circuit layout file to obtain the number of polygons, geometric information, inter-layer connection relationships, and overall spatial range of the layout for each layer. Step 2: Based on the spatial range of the layout, the layout area is divided into uniform grids, and the polygons in the layout are stored in the corresponding grid index containers according to their spatial positions. Step 3: Within each grid index container, construct an R*-tree spatial index data structure for the polygons in the metal layer to support spatial queries of polygons within the metal layer; Step 4: For through-hole polygons, instead of constructing an independent through-hole layer spatial index structure, we select metal polygons whose smallest bounding rectangle contains the through-hole from the upper and lower metal layer spatial index data structures corresponding to the through-hole, and then make a precise determination through geometric inclusion relationships. Step 5: Based on the accurate determination result, establish an "through hole-metal" embedded index relationship between the through hole and the corresponding upper and lower layer metal polygons, and store each other's identification information in the through hole and the metal polygon respectively; Step 6: Based on the established "via-metal" embedded index relationship and the metal layer spatial index data structure, perform link tracing starting from the initial metal polygon until the traversal of the metal polygons electrically connected to it is completed.

2. The layout link tracing efficiency optimization method based on via embedded index as described in claim 1, characterized in that, In step two, the uniform grid division of the map area is a fixed-size two-dimensional grid division method, and each grid cell is used to store the polygon information falling within the grid range.

3. The layout link tracing efficiency optimization method based on via embedding index as described in claim 2, characterized in that, The uniform grid has a size of 10 micrometers × 10 micrometers.

4. The layout link tracing efficiency optimization method based on via embedding index as described in claim 1, characterized in that, In step four, the process of screening metal polygons includes: using the circumscribed rectangle of the through hole to perform a spatial query in the spatial index data structure of the upper and lower metal layers corresponding to the through hole, so as to obtain a set of candidate metal polygons.

5. The layout link tracing efficiency optimization method based on via embedding index as described in claim 4, characterized in that, The precise determination in step four is: determining whether the through hole is geometrically completely contained by the candidate metal polygon.

6. The layout link tracing efficiency optimization method based on via embedding index as described in claim 1, characterized in that, The "through-hole-metal" embedded index relationship established in step five includes: storing the identification information of all through holes contained in the metal polygon structure, and storing the identification information of the metal polygons that contain it in the corresponding upper and lower layers geometrically.

7. The layout link tracing efficiency optimization method based on via embedded index as described in claim 1, characterized in that, The link tracing process in step six includes: starting from the initial metal polygon, locating the upper and lower layer metal polygons electrically connected to it through the embedded via index relationship.

8. The layout link tracing efficiency optimization method based on via embedded index as described in claim 7, characterized in that, After the step of searching and locating the upper and lower layer metal polygons is completed, based on the spatial index data structure of the layer to which the metal polygon belongs, the search is conducted for metal polygons that spatially intersect with it in the same layer.

9. The layout link tracing efficiency optimization method based on via embedded index as described in claim 7, characterized in that, The link tracing process uses a breadth-first traversal approach, searching layer by layer for metal polygons that are electrically connected to the starting metal polygon until no new connected metal polygons exist.

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