Piezoelectric driver circuit, piezoelectric driving method thereof, medium and equipment

Abstract

The embodiment of the invention provides a piezoelectric driver circuit with an energy recovery function, and the piezoelectric driver circuit comprises a voltage selection unit which is used for obtaining a first output voltage VHIGH according to a first input voltage VOUT + and a second input voltage VOUT-, the first output voltage VHIGH is the larger one of the first input voltage VOUT + and the second input voltage VOUT-; the voltage coarse adjustment unit is connected with the voltage selection unit and used for roughly adjusting the first output voltage VHIGH through open-loop control to obtain a second output voltage VHVREG; and the low-voltage linear voltage regulator is connected with the voltage coarse adjustment unit and used for accurately adjusting the second output voltage VHVREG to obtain a third output voltage V 'OUT + and a fourth output voltage V' OUT-. The embodiment of the invention further provides a piezoelectric driving method of the piezoelectric driver circuit, a computer readable storage medium and electronic equipment.

Description

Technical Field

[0001] This invention relates to the field of chip technology, particularly to the field of large-scale mixed-signal integrated circuit chips and power management chips, and more specifically, to piezoelectric driver circuits with energy recovery. Background Technology

[0002] A capacitive drive circuit converts the energy of the input voltage Vin into a capacitive load through level conversion. Driving methods include boost and buck conversion, similar to a DC-DC converter. The control of a capacitive drive circuit is also divided into open-loop and closed-loop control: Open-loop control means that in the level converter, voltage and current are controlled directly by the controller controlling the switching state of the power transistor. Closed-loop control means that in the level converter, the output voltage or current is monitored and fed back, and the switching state of the power transistor is adjusted according to the error, thereby adjusting the inductor current and controlling the output to achieve the target voltage.

[0003] In realizing the concept of this invention, the inventors discovered at least the following problems in the related technologies: While open-loop control has the advantages of simple structure and low cost, it cannot eliminate the influence of external disturbances, nor can it achieve precise output voltage control, easily leading to large fluctuations and low accuracy in the output voltage. Although closed-loop control can eliminate the influence of external disturbances, resulting in higher stability and accuracy of the output voltage and current, its circuit design is complex and its cost is high.

[0004] Therefore, those skilled in the art urgently need to develop a capacitor-type drive circuit that improves output stability while reducing circuit complexity. Summary of the Invention

[0005] In view of this, the technical problem to be solved by the present invention is to provide a piezoelectric driver circuit with energy recovery, which solves the problems of low output accuracy or complex circuit design of related capacitive drive circuits.

[0006] To address the aforementioned technical problems, a specific embodiment of the present invention provides a piezoelectric actuator circuit with energy recovery, comprising: a voltage selection unit, configured to select based on a first input voltage V. OUT+ Second input voltage V OUT- The first output voltage V is obtained HIGH Wherein, the first output voltage V HIGH The first input voltage V OUT+ and the second input voltage V OUT- The larger of the two; a voltage coarse adjustment unit, connected to the voltage selection unit, is used to coarsely adjust the first output voltage V through open-loop control. HIGH The second output voltage V is obtainedHV REG ; and a low-voltage linear regulator, connected to the voltage coarse adjustment unit, for precisely adjusting the second output voltage V. HV_REG The third output voltage V' is obtained OUT+ and the fourth output voltage V' OUT- .

[0007] Another aspect of the present invention provides a method for piezoelectric driving of a piezoelectric driver circuit, comprising: using a voltage selection unit to select the larger of a first input voltage and a second input voltage as a first output voltage; using a voltage coarse adjustment unit to coarsely adjust the first output voltage to a second output voltage through open-loop control; and using a low-voltage linear regulator to precisely adjust the second output voltage through closed-loop control to obtain a third output voltage and a fourth output voltage.

[0008] Another aspect of the present invention provides an electronic device, including one or more processors and a storage device, wherein the storage device is used to store executable instructions, which, when executed by the processor, implement the method of the present invention.

[0009] Another aspect of the present invention provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the method of the present invention.

[0010] Another aspect of the present invention provides a computer program, which includes computer-executable instructions that, when executed, implement the method of the present invention.

[0011] According to the above embodiments of the present invention, the boost function is achieved by using open-loop control, and the precise control is set at the low dropout linear regulator in the subsequent stage. This can at least partially solve the problems of low output accuracy or complex circuit design in related technologies, and thus achieve the technical effect of improving control accuracy while reducing circuit complexity.

[0012] It should be understood that the above general description and the following specific embodiments are merely exemplary and illustrative, and do not limit the scope of the invention. Attached Figure Description

[0013] The accompanying drawings, which are part of the specification of this invention, illustrate exemplary embodiments of the invention. The drawings, together with the description in the specification, serve to illustrate the principles of the invention.

[0014] Figure 1 This is a schematic circuit diagram of a capacitor-type driver in related technologies.

[0015] Figure 2This is a schematic diagram of a piezoelectric actuator circuit with energy recovery provided for a specific embodiment of the present invention.

[0016] Figure 3 This is a schematic diagram of a boost module and a voltage comparator provided for a specific embodiment of the present invention.

[0017] Figure 4 This is a schematic diagram of the structure of a logic controller provided in a specific embodiment of the present invention.

[0018] Figure 5 This is a schematic diagram of a current comparator provided in a specific embodiment of the present invention.

[0019] Figure 6 This is a schematic diagram of the structure of an energy recovery module provided in a specific embodiment of the present invention.

[0020] Figure 7 This is a schematic diagram of an error amplifier provided for a specific embodiment of the present invention.

[0021] Figure 8 This is a schematic diagram of the structure of a first transconductance stage provided for a specific embodiment of the present invention.

[0022] Figure 9 This is a schematic diagram of the structure of a first current mirror provided in a specific embodiment of the present invention.

[0023] Figure 10 This is a schematic flowchart illustrating a piezoelectric driving method for a piezoelectric actuator circuit provided in a specific embodiment of the present invention.

[0024] Figure 11 This is a schematic flowchart illustrating the precise adjustment of the second output voltage to obtain the third and fourth output voltages, provided for a specific embodiment of the present invention.

[0025] Explanation of reference numerals in the attached figures:

[0026] 1. Voltage selection unit; 2. Voltage coarse adjustment unit

[0027] 3 Low-voltage linear regulator 4 First resistor

[0028] 5 Second resistor 21 boost module

[0029] 22 Voltage comparator 23 Logic controller

[0030] 24 switching transistors, 25 current comparators

[0031] 26 First Inductor 27 First Diode

[0032] 28 First capacitor 29 Second capacitor

[0033] 31 First current mirror 32 First switch

[0034] 33 Second current mirror 34 Third current mirror

[0035] 35 First transconductance stage 36 Second transconductance stage

[0036] 37 Fourth Current Mirror 38 Second Switch

[0037] 39 Fifth Current Mirror 310 Sixth Current Mirror

[0038] 311 Third switch 312 Fourth switch

[0039] 313 Error Amplifier 314 Energy Recovery Module

[0040] 315 Load Capacitor Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the spirit of the contents disclosed in the present invention will be clearly explained below with reference to the accompanying drawings and detailed description. After understanding the embodiments of the present invention, any person skilled in the art can make changes and modifications based on the technology taught in the present invention without departing from the spirit and scope of the present invention.

[0042] The illustrative embodiments and descriptions of the present invention are used to explain the invention, but are not intended to limit the invention. Furthermore, elements / components using the same or similar reference numerals in the drawings and embodiments are used to represent the same or similar parts.

[0043] The terms "first," "second," etc., used in this document are not intended to specifically refer to order or sequence, nor are they intended to limit the invention. They are merely used to distinguish elements or operations described using the same technical terms.

[0044] The directional terms used in this article, such as up, down, left, right, front, or back, are for reference only when referring to the accompanying drawings. Therefore, the use of directional terms is for illustrative purposes and not to limit this work.

[0045] The terms “include,” “including,” “have,” “contain,” etc., used in this article are all open-ended terms, meaning that they include but are not limited to.

[0046] The term "and / or" as used herein includes any or all of the things mentioned.

[0047] The term "multiple" in this article includes "two" and "more than two"; the term "multiple groups" in this article includes "two groups" and "more than two groups".

[0048] The terms "approximately," "about," etc., used herein are intended to modify any quantity or error that may vary slightly, but these slight variations or errors do not change the essence of the quantity or error. Generally, the range of slight variations or errors modified by such terms may be 20% in some embodiments, 10% in others, 5% in still others, or other values. Those skilled in the art should understand that the aforementioned values ​​can be adjusted according to actual needs and are not limited thereto.

[0049] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0050] When expressions such as "at least one of A, B, and C" are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (e.g., "a system having at least one of A, B, and C" should include, but is not limited to, systems having A alone, having B alone, having C alone, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.). When expressions such as "at least one of A, B, or C" are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (e.g., "a system having at least one of A, B, or C" should include, but is not limited to, systems having A alone, having B alone, having C alone, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.). Those skilled in the art should also understand that any conjunction and / or phrase that substantially arbitrarily indicates two or more optional items, whether in the specification, claims, or drawings, should be understood to indicate the possibility of including one of these items, either of these items, or both items. For example, the phrase “A or B” should be understood as including the possibility of “A” or “B”, or “A and B”.

[0051] Figure 1 This is a schematic circuit diagram of a capacitor-type driver in related technologies.

[0052] like Figure 1 As shown, L is an inductor, Q1 and Q2 are power transistors, which together form a bidirectional current boost circuit. Q3, Q4, Q5 and Q6 are switching transistors, which together form the output stage. Cap is the load capacitor. By controlling the sequential on and off of the four switching transistors, the desired output waveform can be achieved.

[0053] Capacitive drivers are widely used in piezoelectric ceramic actuators in force generating devices, robots, impact motors, optical scanning, and other fields, requiring high resolution, fast response, and high thrust. In high-efficiency, low-power electronic devices, different loads require different driving methods and performance characteristics. For example, piezoelectric haptic drivers used in mobile phones, tablets, laptops, keyboards and mice, and touch-enabled devices need to be compatible with both low input voltage and high output voltage, and have fast haptic response times. Audio drivers, on the other hand, require power amplifier circuitry, low EMI (electromagnetic interference) across the entire bandwidth, and high linearity. Figure 1 The capacitor-type driver shown has at least the following drawbacks:

[0054] (1) The closed-loop control loop is placed in the step-up and step-down circuit. Since the output load capacitor range is large and the output voltage range is wide, it has a bidirectional energy transmission requirement. Therefore, the control logic is more complex and requires customers to manually set PID parameters (proportional, integral and derivative parameters) to achieve the best configuration. This is not conducive to customers expanding the application range of capacitor-type drivers.

[0055] (2) The loop control adopts the peak current control mode and feeds back the output voltage and inductor current to form a double feedback loop of voltage outer loop and current inner loop. However, the switching frequency and peak current cannot adapt to the load voltage magnitude and load voltage slope, resulting in the loss of switching frequency. Under low load conditions, the proportion of the total loss is larger, which reduces the efficiency under low load conditions.

[0056] (3) The energy recovery function is integrated into the step-up / step-down level conversion section, which requires the switching control logic of the power transistor. However, controlling the conduction of the power transistor also requires a large voltage signal to be applied to its gate, resulting in additional energy loss in the control section and further reducing the efficiency under low load.

[0057] (4) The H-bridge of the expansion stage adopts a four-switch mode. When the switches are switched, a large voltage difference will be generated, which has no obvious suppression effect on the ripple of the boost output. Therefore, the output distortion is not effectively suppressed.

[0058] Figure 2 This is a schematic diagram of a piezoelectric actuator circuit with energy recovery provided for a specific embodiment of the present invention.

[0059] like Figure 2 As shown, a piezoelectric driver circuit with energy recovery may include a voltage selection unit 1, a voltage coarse adjustment unit 2, and a low-voltage linear regulator 3.

[0060] Specifically, the voltage selection unit 1 is used to select the voltage based on the first input voltage V. OUT+ Second input voltage V OUT- The first output voltage V is obtainedHIGH Wherein, the first output voltage V HIGH The first input voltage V OUT+ and the second input voltage V OUT- The larger of the two. The voltage coarse adjustment unit 2 is connected to the voltage selection unit 1, and is used to coarsely adjust the first output voltage V through open-loop control. HIGH The second output voltage V is obtained HV_REG The low-voltage linear regulator 3 is connected to the voltage coarse adjustment unit 2, and the low-voltage linear regulator 3 is used to precisely adjust the second output voltage V. HV_REG The third output voltage V' is obtained OUT+ and the fourth output voltage V' OUT- .

[0061] In an optional embodiment of the present invention, the piezoelectric driver circuit employs open-loop control to achieve the boost function, increasing the second output voltage V. HV_REG Directly with the target voltage V HV The system compares the output voltage with the target voltage and then controls the switching of the power transistor (switching transistor) to obtain a coarse follower voltage that is not lower than the target voltage. Precise control of the output voltage is handled by the subsequent LDO (low dropout linear regulator). This circuit layout simplifies the control logic, maintains system stability, and, in low-load capacitor mode, enhances efficiency through its simple control method. Furthermore, this control architecture allows users to adjust any desired output waveform in real time and expand its capabilities.

[0062] In an optional embodiment of the present invention, the piezoelectric driver circuit with energy recovery may further include a first resistor 4 and a second resistor 5. Specifically, one end of the first resistor 4 is connected to the low-voltage linear regulator 3, and the other end of the first resistor 4 is connected to the first input voltage. One end of the second resistor 5 is connected to the low-voltage linear regulator 3, and the other end of the second resistor 5 is connected to the second input voltage.

[0063] In optional specific embodiments of the present invention, such as Figure 3 As shown, voltage selection unit 1 includes a first PMOS transistor and a second PMOS transistor. Specifically, the drain of the first PMOS transistor is connected to the first input voltage, the source of the first PMOS transistor is connected to the gate of the first PMOS transistor, and the gate of the first PMOS transistor is connected to the voltage coarse adjustment unit 2. The drain of the second PMOS transistor is connected to the second input voltage, the source of the second PMOS transistor is connected to the gate of the second PMOS transistor, and the gate of the second PMOS transistor is connected to the voltage coarse adjustment unit 2. The larger of the first input voltage and the second input voltage is the first output voltage.

[0064] In optional specific embodiments of the present invention, such as Figure 2 As shown, the voltage coarse adjustment unit 2 may include: a boost module 21, a voltage comparator 22, a logic controller 23, a switching transistor 24, a current comparator 25, a first inductor 26, and a first diode 27. Specifically, the input terminal of the boost module 21 is connected to the voltage selection unit 1, and the boost module 21 is used to boost the first output voltage to the second output voltage. One input terminal of the voltage comparator 22 is connected to the output terminal of the boost module 21, and the other input terminal of the voltage comparator 22 is connected to the following voltage V. HV A voltage comparator 22 is connected to the output of the voltage comparator 22 based on the second output voltage and the following voltage. An input of the logic controller 23 is connected to the output of the voltage comparator 22. The gate of the switch 24 is connected to the output of the logic controller 23, and the drain of the switch 24 is grounded. The switch 24 is used to output a first current under the control of the output signal from the logic controller 23. One input of the current comparator 25 is connected to the drain of the switch 24, and the other input of the current comparator 25 is connected to a first preset current threshold I. ZTC The current comparator 25 is connected to another input of the logic controller 23. The current comparator 25 outputs a second predetermined signal CLIM based on the first current and the first preset current threshold, so that the logic controller 23 controls the switching transistor 24 to turn on and off according to the first predetermined signal and the second predetermined signal. The input of the first inductor 26 is connected to the supplementary voltage V. IN The output terminal of the first inductor 26 is connected to the source of the switching transistor 24. The input terminal of the first diode 27 is connected to the output terminal of the first inductor 26, and the output terminal of the first diode 27 is connected to the low-voltage linear regulator 3. The first diode 27 is used to supply energy to the low-voltage linear regulator 3. Optionally, the first diode 27 is a high-voltage diode.

[0065] In optional specific embodiments of the present invention, such as Figure 2 As shown, the voltage coarse adjustment unit 2 may further include a first capacitor 28 and a second capacitor 29. Specifically, one end of the first capacitor 28 is connected to the input terminal of the first inductor 26, and the other end of the first capacitor 28 is grounded. One end of the second capacitor 29 is connected to the output terminal of the first diode 27, and the other end of the second capacitor 29 is grounded.

[0066] In an optional embodiment of the present invention, the piezoelectric driver circuit employs open-loop control to achieve the boost function, increasing the second output voltage V. HV_REG Directly with the target voltage V HVThe system compares the output voltage with the target voltage and then controls the switching of the power transistor (switching transistor) to obtain a coarse follower voltage that is not lower than the target voltage. Precise control of the output voltage is handled by the subsequent LDO (low dropout linear regulator). This circuit layout simplifies the control logic, maintains system stability, and, in low-load capacitor mode, enhances efficiency through its simple control method. Furthermore, this circuit control architecture allows users to adjust any desired output waveform in real time and expand its capabilities.

[0067] Figure 3 This is a schematic diagram of a boost module and a voltage comparator provided for a specific embodiment of the present invention.

[0068] In optional specific embodiments of the present invention, such as Figure 3 As shown, the boost module 21 may include: a third PMOS transistor, a second diode, a fourth PMOS transistor, a second resistor, a fifth PMOS transistor, a sixth PMOS transistor, and the third diode. Specifically, the drain of the third PMOS transistor is connected to the voltage selection unit, and the drain of the third PMOS transistor is grounded. The anode of the second diode is connected to the gate of the third PMOS transistor, and the cathode of the second diode is connected to the drain of the third PMOS transistor. The source of the fourth PMOS transistor is connected to the source of the third PMOS transistor, and the gate of the fourth PMOS transistor is connected to the source of the fourth PMOS transistor. One end of the second resistor is connected to the drain of the fourth PMOS transistor. The source of the fifth PMOS transistor is connected to the other end of the second resistor, and the gate of the fifth PMOS transistor is connected to the source of the fifth PMOS transistor. The gate of the sixth PMOS transistor is connected to the gate of the fifth PMOS transistor, the drain of the sixth PMOS transistor is connected to the drain of the fifth PMOS transistor, and the source of the sixth PMOS transistor is connected to the voltage comparator. The anode of the third diode is connected to the anode of the second diode, and the cathode of the third diode is connected to the drain of the fifth PMOS transistor and the drain of the sixth PMOS transistor. Optionally, the boost module 21 can boost the first output voltage to a second output voltage, where the second output voltage is 2V higher than the first output voltage.

[0069] In optional specific embodiments of the present invention, such as Figure 3 As shown, the voltage comparator 22 may include: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, an eleventh NMOS transistor, a ninth PMOS transistor, a twelfth NMOS transistor, a tenth PMOS transistor, and a thirteenth NMOS transistor.

[0070] Specifically, the source of the first NMOS transistor is connected to the source of the sixth PMOS transistor, the gate of the first NMOS transistor is connected to its source, and the drain of the first NMOS transistor is grounded. The drain of the second NMOS transistor is connected to the drain of the first NMOS transistor, the gate of the second NMOS transistor is connected to its source, and the source of the second NMOS transistor is connected to a fixed bias current I3 (i.e., the fixed bias current generated by the reference source module). The drain of the third NMOS transistor is connected to the drain of the second NMOS transistor, and the gate of the third NMOS transistor is connected to its gate. The drain of the fourth NMOS transistor is connected to the drain of the third NMOS transistor, and the gate of the fourth NMOS transistor is connected to its gate. The drain of the fifth NMOS transistor is connected to the drain of the fourth NMOS transistor, and the gate of the fifth NMOS transistor is connected to its gate. The drain of the sixth NMOS transistor is connected to the drain of the fifth NMOS transistor, and the gate of the sixth NMOS transistor is connected to its gate. The drain of the seventh NMOS transistor is connected to the source of the third NMOS transistor, and its gate is connected to the first trigger signal TRIM1. The source of the eighth NMOS transistor is connected to the source of the seventh NMOS transistor, its drain is connected to the source of the fourth NMOS transistor, and its gate is connected to the second trigger signal TRIM2. The source of the ninth NMOS transistor is connected to the source of the eighth NMOS transistor, its drain is connected to the source of the fifth NMOS transistor, and its gate is connected to the third trigger signal TRIM3. The source of the tenth NMOS transistor is connected to the source of the ninth NMOS transistor, its drain is connected to the source of the sixth NMOS transistor, and its gate is connected to the power supply voltage VCC (i.e., the overall circuit power supply voltage). The source of the seventh PMOS transistor is connected to the source of the tenth NMOS transistor, and its gate is connected to the source of the seventh PMOS transistor. The gate of the eighth PMOS transistor is connected to the gate of the seventh PMOS transistor, and the drain of the eighth PMOS transistor is connected to the drain of the seventh PMOS transistor. The drain of the eleventh NMOS transistor is connected to the source of the eighth PMOS transistor, the gate of the eleventh NMOS transistor is connected to the gate of the first NMOS transistor, and the drain of the eleventh NMOS transistor is connected to the drain of the sixth NMOS transistor. The gate of the ninth PMOS transistor is connected to the source of the eighth PMOS transistor, and the drain of the ninth PMOS transistor is connected to the drain of the eighth PMOS transistor. The source of the twelfth NMOS transistor is connected to the source of the ninth PMOS transistor, the drain of the twelfth NMOS transistor is connected to the drain of the eleventh NMOS transistor, and the gate of the twelfth NMOS transistor is connected to the source of the eighth PMOS transistor and the gate of the ninth PMOS transistor.The gate of the tenth PMOS transistor is connected to the source of the ninth PMOS transistor, the drain of the tenth PMOS transistor is connected to the drain of the ninth PMOS transistor, and the source of the tenth PMOS transistor is connected to the logic controller. The source of the thirteenth NMOS transistor is connected to the source of the tenth PMOS transistor, the drain of the thirteenth NMOS transistor is connected to the drain of the twelfth NMOS transistor, and the gate of the thirteenth NMOS transistor is connected to the gate of the tenth PMOS transistor and the source of the twelfth NMOS transistor.

[0071] See Figure 2 , Figure 3 The function of voltage selection unit 1 is to select V OUT+ and V OUT- The higher voltage branch is used as the first output voltage V. HIGH Then shift the voltage level by 2V to V. HIGH +2V is used as the input of the voltage comparator, which converts the input voltage into current, i.e., I. HV REG The signal, the current signal, is input to the current comparator and compared with a first preset current threshold I. ZTC The comparison is then made, and the switching of the power transistor (switching transistor) is controlled in an open-loop manner.

[0072] Figure 3 In this diagram, I1 and I2 are fixed currents obtained by mirroring the bias current source and the current mirror. The gate and source of transistors PM1 and PM2 (PMOS transistors) are connected, and their body electrodes are also connected. At this point, looking from the drain towards the body electrode of the MOS transistor, it appears as a forward-biased diode. Therefore, current can only flow from the high-voltage drain to the low-voltage source, and cannot flow in the reverse direction, thus preventing reverse current flow. OUT+ and V OUT- At the same time, only one is charging, while the other is at zero. Therefore, due to the pull-down effect of current I2, only V... OUT+ and V OUT- A current will flow through the branch with the higher voltage, thus generating a voltage V. HIGH Its value is approximately equal to V OUT+ or V OUT- PM5 and PM6 form a current mirror, whose main current is determined by the voltage difference across resistor R2. At this time, PM3 operates in the saturation region, and its on-resistance is negligible. Therefore, the main current I flowing through R2 is approximately:

[0073]

[0074] In the above formula, V GS3 This represents the gate-source voltage of MOSFET PM5, V. BD5This represents the forward voltage drop of the body diode in PM4, because PM4 also acts as a reverse current preventer. In this formula, the bus current I and V... HIGH The correlation is linear; the mother current I is obtained by mirroring the image through a current mirror. HV_REG And it is used as a comparison signal in the comparison. By appropriately adjusting the parameters of the resistors and MOSFETs in the module, the magnitude of the bus current I can be proportional to V. HIGH The +2V relationship is then converted into a current signal I. HV_REG Output.

[0075] In an optional specific embodiment of the present invention, due to V HV The voltage can reach up to 95V, making it impossible to use a voltage comparator structure; therefore, V... HIGH +2V is converted into the corresponding current I. HV_REG Then it is compared with the fixed bias current I3 generated by the reference source module. HV_REG Current flows into current mirrors NM1 and NM11. I3 is the fixed bias current generated by the reference source module. NM2, NM3, NM4, NM5, and NM6 form the current mirror, while NM7, NM8, NM9, and NM10 are switches composed of MOSFETs. NM10's gate is connected to the supply voltage VCC and is in a fixed on state. The gates of NM7, NM8, and NM9 are connected to TRIM1, TRIM2, and TRIM3, respectively, and their conduction can be controlled externally. The ratio of the three MOSFETs NM3, NM4, and NM5 to NM6 is 4:8:16:12, thus allowing for flexible control of I3. HV_REG The magnitude of the current being compared is sufficient to raise V. HV The purpose of the amplitude is to determine the comparison result. PM8 and NM11 form a push-pull output stage, which generates the comparison result and then outputs it as a NEEDSWON signal through a buffer stage. When I HV_REG When the current is lower than the fixed bias current I3 generated by the reference source module, NEEDSWON is low, requiring the power transistor to be turned on to charge C2; ​​when I... HV_REG When the current exceeds the set current, NEEDSWON is at a high level, and the power transistor needs to be turned off.

[0076] Figure 4 This is a schematic diagram of the structure of a logic controller provided in a specific embodiment of the present invention.

[0077] In optional specific embodiments of the present invention, such as Figure 4As shown, the logic controller 23 may include: a first AND logic unit, a first D flip-flop, a second AND logic unit, a first inverter, a second D flip-flop, a third D flip-flop, a second inverter, an eleventh PMOS transistor, a third resistor, a fourteenth NMOS transistor, a third capacitor, a third inverter, a first NAND logic unit, a fourth inverter, a twelfth PMOS transistor, a fifteenth NMOS transistor, a fourth resistor, a fourth capacitor, a fifth inverter, a second NAND logic unit, a third AND logic unit, a third NAND logic unit, a fourth NAND logic unit, a thirteenth PMOS transistor, a sixteenth NMOS transistor, a fifth resistor, a fifth capacitor, a sixth inverter, a first OR logic unit, a seventh inverter, an eighth inverter, a ninth inverter, a second OR logic unit, a tenth inverter, a third OR logic unit, and an eleventh inverter.

[0078] Specifically, one input of the first AND logic unit is connected to the continuous conduction mode fixed switching time flag signal TIME_OPEN, and the other input is connected to the continuous conduction mode flag signal CCM_OPEN. The clock port CK of the first D flip-flop is connected to the first AND logic unit, the D input port of the first D flip-flop is connected to the voltage comparator, the set port SET of the first D flip-flop is connected to the continuous conduction mode hold flag signal delay signal CCM_KKEP_DELAY, and the reset port CLR of the first D flip-flop is connected to the power supply voltage VCC. One input of the second AND logic unit is connected to the bias module normal operation flag signal BIAS_READY, and the other input is connected to the Q output of the first D flip-flop. The input of the first inverter is connected to the second AND logic unit. The reset port CLR of the second D flip-flop is connected to the output of the first inverter, the set port SET of the second D flip-flop is connected to the power supply voltage VCC, and the D input port of the second D flip-flop is connected to the power supply voltage VCC. The Q output of the third D flip-flop is connected to the clock port CK of the second D flip-flop. The set port SET of the third D flip-flop is connected to the supply voltage VCC. The clock port CK of the third D flip-flop is connected to the minimum off-time flag signal BLANK_TIME in discontinuous conduction mode. The reset port CLR of the third D flip-flop is connected to the inverted delay signal CCM_TRIGGERB_DELAY in continuous conduction mode. The D input port of the third D flip-flop is connected to the voltage comparator. The Q output of the third D flip-flop is connected to the inverted signal CCM_TRIGGERB in continuous conduction mode. The input of the second inverter is connected to the switching transistor. The gate of the eleventh PMOS transistor is connected to the output of the second inverter, and the drain of the eleventh PMOS transistor is connected to the supply voltage VCC. One end of the third resistor is connected to the source of the eleventh PMOS transistor. The source of the fourteenth NMOS transistor is connected to the other end of the third resistor, the gate of the fourteenth NMOS transistor is connected to the gate of the eleventh PMOS transistor, and the drain of the fourteenth NMOS transistor is grounded. One end of the third capacitor is connected to the source of the eleventh PMOS transistor, and the other end of the third capacitor is grounded. The input of the third inverter is connected to the source of the eleventh PMOS transistor. One input of the first NAND logic unit is connected to the output of the third inverter, and the other input of the first NAND logic unit is connected to the Q output of the second D flip-flop. The input of the fourth inverter is connected to the switching transistor. The gate of the twelfth PMOS transistor is connected to the output of the fourth inverter, and the drain of the twelfth PMOS transistor is connected to the supply voltage VCC. The gate of the fifteenth NMOS transistor is connected to the gate of the twelfth PMOS transistor, and the drain of the fifteenth NMOS transistor is grounded. One end of the fourth resistor is connected to the source of the twelfth PMOS transistor, and the other end of the fourth resistor is connected to the source of the fifteenth NMOS transistor.One end of the fourth capacitor is connected to the source of the twelfth PMOS transistor, and the other end of the fourth capacitor is grounded. The input of the fifth inverter is connected to the source of the twelfth PMOS transistor. One input of the second NAND logic unit is connected to the output of the fifth inverter, and the other input of the second NAND logic unit is connected to the voltage comparator. One input of the third AND logic unit is connected to the output of the first NAND logic unit, and the other input of the third AND logic unit is connected to the output of the second NAND logic unit. One input of the third NAND logic unit is connected to the output of the third AND logic unit. One input of the fourth NAND logic unit is connected to the output of the third NAND logic unit, and the output of the fourth NAND logic unit is connected to the other input of the third NAND logic unit. The gate of the thirteenth PMOS transistor is connected to the power transistor turn-on completion flag signal SW_DONE_FLAG, and the drain of the thirteenth PMOS transistor is connected to the supply voltage VCC. The gate of the sixteenth NMOS transistor is connected to the gate of the thirteenth PMOS transistor, and the drain of the sixteenth NMOS transistor is grounded. One end of the fifth resistor is connected to the source of the thirteenth PMOS transistor, and the other end is connected to the source of the sixteenth NMOS transistor. One end of the fifth capacitor is connected to the source of the thirteenth PMOS transistor, and the other end is grounded. The input of the sixth inverter is connected to the source of the thirteenth PMOS transistor. One input of the first OR logic is connected to the output of the sixth inverter, and the other input of the first OR logic is connected to the current comparator. The input of the seventh inverter is connected to the output of the first OR logic, and the output of the seventh inverter is connected to the other input of the fourth NAND logic. The input of the eighth inverter is connected to the digital-to-analog converter (DAC) operating flag signal DAC_ON. The input of the ninth inverter is connected to the inverted sensor function operating flag signal SENSE_ON_VINB. One input of the second OR logic is connected to the output of the eighth inverter, and one input of the second OR logic is connected to the output of the ninth inverter. The other input of the second OR logic is connected to the circuit stop operating flag signal SHUTDOWN. The input of the tenth inverter is connected to the BOOST_ON signal, the operating flag of the boost module. One input of the third OR logic is connected to the output of the second OR logic, another input of the third OR logic is connected to the output of the tenth inverter, and the other input of the third OR logic is connected to the output of the fourth NAND logic. The input of the eleventh inverter is connected to the output of the third OR logic, and the output of the eleventh inverter is connected to the switching transistor.

[0079] In an optional embodiment of the present invention, the logic controller determines the switching state of the power transistor through a series of logical operations on signals, and controls the switching of the voltage coarse adjustment unit between CCM (Continuous On-Mode) and DCM (Discontinuous On-Mode) operating modes. Its internal logic effects are mainly divided into three parts:

[0080] ① When the input voltage of voltage comparator CMP1 reaches the threshold (V) HIGH The power transistor is turned on when the input voltage of the voltage comparator CMP1 exceeds the threshold voltage (V) or when the power transistor's turn-off time reaches the set minimum turn-off time. HIGH The power transistor is turned off when the voltage reaches +2V or the power transistor's on-time reaches the set maximum on-time.

[0081] ② The minimum turn-off time or maximum switching time involved in the voltage coarse adjustment unit is controlled by adjusting the inverter with added delay to ensure that all logic operates reasonably.

[0082] ③ When the voltage coarse adjustment unit is in DCM mode, whenever the minimum turn-off time is reached, i.e., the rising edge of the BLANK_TIME signal, it checks whether the NEEDSWON signal is high. If it is high (even when operating in DCM mode, the turn-on time of the power transistor is insufficient to make it proportional to V), it will be checked. HIGH When the +2V bus current I reaches the set peak current, it enters CCM mode. In CCM mode, each time the fixed turn-off time in CCM mode is reached (i.e., the rising edge of TIME_OPEN), the NEEDSWON signal is checked for low. If low, it indicates that the power transistor's turn-on time is sufficient to make the current proportional to V... HIGH The +2V bus current I reaches the set peak current, so there is no need to operate in CCM mode, and thus it exits CCM and enters DCM state.

[0083] The rightmost SWON signal in the diagram is the signal that controls the power transistor to turn on. When it is high, the power transistor is on. If SWON needs to be high, the output of OR3 should be low, therefore all three inputs of OR3 should be low. BOOST_ON indicates the start signal of the voltage coarse adjustment unit, so it should be high under normal circumstances. After passing through inverter INV10, the output BOOST_ONB is low. SHUTDOWN is the circuit stop operation flag signal, given externally by the logic controller, and is low under normal circumstances. SENSE_ON_VINB being low indicates that the sensing function is working, and it should be high when the power transistor (switching transistor 24) is on. DAC_ON being high indicates that the DAC module is working, and it should be high when the power transistor is on. In summary, except for the top input of OR3, the other two being low indicates that the voltage coarse adjustment unit is working normally and has not received the circuit stop operation flag signal, the sensing function is not working, and the DAC module is working.

[0084] NAND gates NAND3 and NAND4 form the SR latch. As mentioned earlier, for SWON to be high, all inputs to OR3 should be low. Therefore, the output of NAND gate NAND4 is low. Working backwards, we know that all inputs to NAND4 must be high, and all inputs to NAND3 must be low. Therefore, SW_OFF should be low; when it is high, the power transistor is off. For SW_OFF to be low, all inputs to the OR gate must be low. CRESETX is a signal used to determine whether the current flowing through the power transistor in the voltage coarse adjustment unit has reached its peak current. When the current reaches its peak current, it is high. SW_DONE_FLAG is the power transistor turn-on completion flag signal. PM13 and NM16 form an inverter. Resistor R5 and capacitor C1 apply a delay to the inverter formed by PM13 and NM16. When SW_DONE_FLAG changes from low to high, the charge stored in C1 needs to be discharged to ground through NM16 before the input of inverter INV6 becomes low. Resistor R5 reduces the discharge rate, thus creating a delay at the falling edge. By changing the value of R5 and the value of C1, the time of this delay can be changed. In this circuit design, this delay time is the maximum turn-on time, the purpose of which is to prevent the power transistor from being turned on for too long, leading to overcharging.

[0085] As described above, for SWON to be high, all inputs to NAND3 must be low. Therefore, not all inputs to AND3 should be high. One input connected to NAND1 is the control branch for CCM mode, and the other input connected to NAND2 is the control branch for DCM mode. SWON outputs TIME_OPEN after passing through inverters INV2, PM11, and NM14 (forming inverters INV2 and INV3). R3 and C3 generate a delay, forming timing logic; this delay is the power-off time in CCM mode. The CCM_OPEN signal indicates entry or exit from CCM mode; when it is high, it indicates the need to enter CCM mode. It is generated by D flip-flop DF2, and the clock signal of DF2 is the output of DF3. The clock signal of DF3 is BLANK_TIME, which represents the signal generated after the minimum turn-off time of SWON in DCM mode. When BLANK_TIME is high, the NEEDSWON signal is passed to CCM_TRIGGER. The essence of this process is that when the circuit is working in DCM mode, the NEEDSWON signal is checked every minimum turn-off time. If it is high, it means that V is not turned off at this time. HV Once charged sufficiently, the power transistor still needs to remain on, so CCM_TRIGGER goes high, transmitting the supply voltage VCC to CCM_OPEN, and the circuit enters CCM mode. CCM_TRIGGERB_DELAY is the inverted signal of CCM_TRIGGERB, used to reset DF3. The reset signal for DF3 is generated by DF1. When both TIME_OPEN and CCM_OPEN, the inputs of AND3, are high, and the circuit is in CCM mode and the transistor shutdown process is complete, the output of AND1 goes high. At this point, it checks if NEEDSWON is low. If it is low, it means the circuit does not need to be in CCM mode to complete the charging process, so CCM_KEEP goes low. BIAS_READY is the bias module's normal operating indicator signal, which defaults to high. After passing through AND2 and INV1, it goes high, resetting DF2. CCM_OPEN goes low, indicating that the circuit exits CCM mode and enters DCM mode.

[0086] Figure 5 This is a schematic diagram of a current comparator provided in a specific embodiment of the present invention.

[0087] In optional specific embodiments of the present invention, Figure 5As shown, the current comparator 25 may include: a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a sixth resistor, a seventh resistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor, a nineteenth NMOS transistor, a twentieth NMOS transistor, a twenty-first NMOS transistor, a twenty-second NMOS transistor, a twenty-third NMOS transistor, a seventeenth PMOS transistor, a twenty-fourth NMOS transistor, an eighteenth PMOS transistor, a twenty-fifth NMOS transistor, a nineteenth PMOS transistor, a twenty-sixth NMOS transistor, a twentieth PMOS transistor, and a twenty-seventh NMOS transistor.

[0088] Specifically, the gate and source of the fourteenth PMOS transistor are connected. The gate of the fifteenth PMOS transistor is connected to the gate of the fourteenth PMOS transistor, and the drain of the fifteenth PMOS transistor is connected to the drain of the fourteenth PMOS transistor. The gate of the sixteenth PMOS transistor is connected to the gate of the fifteenth PMOS transistor, and the drain of the sixteenth PMOS transistor is connected to the drain of the fifteenth PMOS transistor. One end of the sixth resistor is connected to the source of the fifteenth PMOS transistor. One end of the seventh resistor is connected to the other end of the sixth resistor, and the other end of the seventh resistor is connected to the source of the sixteenth PMOS transistor. The source of the seventeenth NMOS transistor is connected to the source of the fifteenth PMOS transistor, and the gate of the seventeenth NMOS transistor is connected to the other end of the sixth resistor. The source of the eighteenth NMOS transistor is connected to the drain of the seventeenth NMOS transistor and connected to the first preset current threshold. The gate of the eighteenth NMOS transistor is connected to the power supply voltage VCC. The source of the nineteenth NMOS transistor is connected to the drain of the eighteenth NMOS transistor, the gate of the nineteenth NMOS transistor is connected to the power supply voltage VCC, and the drain of the nineteenth NMOS transistor is grounded. The source of the twentieth NMOS transistor is connected to the source of the sixteenth PMOS transistor, and the gate of the twentieth NMOS transistor is connected to the gate of the seventeenth NMOS transistor. The source of the twenty-first NMOS transistor is connected to the drain of the twentieth NMOS transistor, and the gate of the twenty-first NMOS transistor is connected to the power supply voltage VCC. The source of the twenty-second NMOS transistor is connected to the drain of the twenty-first NMOS transistor, the gate of the twenty-second NMOS transistor is connected to the minimum turn-on time flag signal BLANK, and the drain of the twenty-second NMOS transistor is grounded. The source of the twenty-third NMOS transistor is connected to the source of the twenty-second NMOS transistor, the gate of the twenty-third NMOS transistor is connected to the inverted minimum turn-on time flag signal BLANK_B, and the drain of the twenty-third NMOS transistor is connected to the voltage signal SW at the node where the first inductor and the switch are connected. The drain of the seventeenth PMOS transistor is connected to the drain of the sixteenth PMOS transistor, and the gate of the seventeenth PMOS transistor is connected to the source of the seventeenth PMOS transistor. The source of the twenty-fourth NMOS transistor is connected to the source of the seventeenth PMOS transistor, and the gate of the twenty-fourth NMOS transistor is connected to the source of the sixteenth PMOS transistor. The drain of the eighteenth PMOS transistor is connected to the drain of the seventeenth PMOS transistor, and the gate of the eighteenth PMOS transistor is connected to the source of the eighteenth PMOS transistor. The source of the twenty-fifth NMOS transistor is connected to the source of the eighteenth PMOS transistor, the gate of the twenty-fifth NMOS transistor is connected to the source of the fifteenth PMOS transistor, and the drain of the twenty-fifth NMOS transistor is connected to the drain of the twenty-fourth NMOS transistor. The gate of the nineteenth PMOS transistor is connected to the gate of the eighteenth PMOS transistor, and the drain of the nineteenth PMOS transistor is connected to the drain of the eighteenth PMOS transistor.The source of the 26th NMOS transistor is connected to the source of the 19th PMOS transistor, the gate of the 26th NMOS transistor is connected to the source of the 26th NMOS transistor, and the drain of the 26th NMOS transistor is grounded. The drain of the 20th PMOS transistor is connected to the drain of the 19th PMOS transistor, the gate of the 20th PMOS transistor is connected to the gate of the 17th PMOS transistor, and the source of the 20th PMOS transistor is connected to the gate of the switching transistor. The source of the 27th NMOS transistor is connected to the source of the 20th PMOS transistor, the gate of the 27th NMOS transistor is connected to the gate of the 26th NMOS transistor, and the drain of the 27th NMOS transistor is connected to the drain of the 26th NMOS transistor.

[0089] In an optional specific embodiment of the present invention, the inductor current (the current flowing through the first inductor 26 from left to right) is sampled and compared with a first preset peak current I. ZTC The comparison is performed, and the current comparator output logic CRESETX (i.e., CLIM current) is passed to the logic controller. In this circuit design, the current sampling circuit and the peak current comparator are integrated, converting the sampled current information into voltage information at points A and B in the diagram, which serves as the common-gate input voltage of the current comparator. Current I A It consists of two parts, namely the bias current I. BIASA and the first preset peak current I ZTC Current I B Only by bias current I BIASB Composed of, and related to I A The bias currents in the NM17 to NM21 are equal, and they are used as switches.

[0090] The voltage signals V at points A and B A V B Containing all information about the peak current and control signals, the current comparator starts working when the BLANK signal is low and the BLANK_B signal is high. The BLANK signal indicates the minimum turn-off time of the circuit in DCM mode. The on-resistances of NM18 to NM23 are defined to be the same, all being R. M1-5 The on-resistance of switch 24 is R. POWER_NMOS Then the voltages at points A and B are respectively:

[0091] V A =2R M1-5 ·(I BIASA +I ZTC )

[0092] V B =2R M1-5 ·I BIASB +V SW =2RM1-5 ·I BIASB +R POWER_NMOS ·I IND

[0093] In the above formula, V SW I represents the node voltage between the first inductor L1 and the first diode D1; IND This represents the current flowing through the first inductor; the voltage at point A is V. A and the voltage V at point B B As a common-gate input of the current comparator, the inversion point of the comparator output is V. A and V B When the voltages are equal, according to the above formula, the following current relationship exists:

[0094] 2R M1-5 ·(I BIASB +I ZTC ) = 2R M1-5 ·I BIASB +R POWER_NMOS ·I IND

[0095] After sorting, we can get I IND :

[0096]

[0097] According to the above formula, when the inductor current is less than αI ZTC When the current comparator output is low, meaning the inductor current is still rising, the inductor current will decrease. When the inductor current is greater than αI... ZTC When the current comparator outputs a high level, it means the inductor current has reached the first preset peak current I of the loop control. ZTC The current comparator output is sent to the logic controller to control the switching transistor 24 to turn off.

[0098] The current comparator consists of a common-gate amplifier and a comparator. Its input is a voltage signal V converted from a current signal by a sampling circuit. A and V B The comparator employs a current mirror structure to convert the output to a rail-to-rail voltage, allowing direct connection to an inverter without any follow-through current. Furthermore, the comparator requires a BLANK signal to control the switch. Comparison only begins when the BLANK signal is low, skipping the unstable voltage state during the power transistor's turn-on process. Comparison only starts after the voltage at point SW (the node connecting the first inductor and the switching transistor) stabilizes. The duration of a high BLANK signal corresponds to the minimum turn-on time of the power transistor.

[0099] In optional specific embodiments of the present invention, see again Figure 2The low-voltage linear regulator 3 may include: a first current mirror 31, a first switch 32, a second current mirror 33, a third current mirror 34, a first transconductance stage 35, a second transconductance stage 36, a fourth current mirror 37, a second switch 38, a fifth current mirror 39, a sixth current mirror 310, a third switch 311, a fourth switch 312, and an error amplifier 313.

[0100] Specifically, the two input terminals of the first current mirror 31 are connected to the output terminal of the first diode 27. One contact of the first switch 32 is connected to one output terminal of the first current mirror 31. The two input terminals of the second current mirror 33 are connected, and one output terminal of the second current mirror 33 is connected to the other contact of the first switch 32. One input terminal of the third current mirror 34 is connected to the other output terminal of the second current mirror 33, and the two output terminals of the third current mirror 34 are grounded. The positive terminal of the first transconductance stage 35 is connected to the common point of the first switch 32, and the negative terminal of the first transconductance stage 35 is grounded. The positive terminal of the second transconductance stage 36 is connected to the negative terminal of the first transconductance stage 35, and the negative terminal of the second transconductance stage 36 is connected to the positive terminal of the first transconductance stage 35, and the negative terminal of the second transconductance stage 36 is grounded. The two input terminals of the fourth current mirror 37 are connected to the output terminal of the first diode 27, and one output terminal of the fourth current mirror 37 is connected to the other input terminal of the third current mirror 34. One contact of the second switch 38 is connected to the other output terminal of the fourth current mirror 37, and the common point of the second switch 38 is connected to the positive terminal of the second transconductance stage 36. The two input terminals of the fifth current mirror 39 are connected, and one output terminal of the fifth current mirror 39 is connected to the other contact of the second switch 38. One input terminal of the sixth current mirror 310 is connected to the other output terminal of the fifth current mirror 39, and the other input terminal of the sixth current mirror 310 is connected to the other output terminal of the first current mirror 31. The two output terminals of the sixth current mirror 310 are grounded. The common point of the third switch 311 is connected to the other output terminal of the first current mirror 31, and the contact of the third switch 311 is grounded. The common point of the fourth switch 312 is connected to the other output terminal of the fourth current mirror 37, and the contact of the fourth switch 312 is grounded. The negative input terminal of the error amplifier 313 is connected to the negative terminal of the second transconductance stage 36, the positive input terminal of the error amplifier 313 is connected to the positive terminal of the second transconductance stage 36, the positive output terminal of the error amplifier 313 is connected to the first resistor 4, and the negative output terminal of the error amplifier 313 is connected to the second resistor 5. The error amplifier 313 is used to output a pull-down differential current.

[0101] In an optional embodiment of the present invention, the low-voltage linear regulator 3 may further include an energy recovery module 314 and a load capacitor 315 (i.e., a PIEZO capacitor). Specifically, one end of the energy recovery module 314 is connected to the other output terminal of the first current mirror 31, and the other end of the energy recovery module 314 is connected to the other output terminal of the fourth current mirror 37. One end of the load capacitor 315 (i.e., the PIEZO capacitor) is connected to one end of the energy recovery module 314, and the other end of the load capacitor 315 (i.e., the PIEZO capacitor) is connected to the other end of the energy recovery module 314.

[0102] In an optional embodiment of the present invention, the energy recovery module 314 is placed in the subsequent H-bridge low-voltage linear regulator 3. Therefore, this circuit design uses a high-voltage diode instead of a high-side power transistor, avoiding energy loss caused by the control section of the power transistor and significantly improving the driving efficiency of small capacitor loads. Furthermore, by placing the energy recovery module 314 in the subsequent H-bridge low-voltage linear regulator 3, during the output signal decline process, logic control switches enable partial recovery of energy during the output voltage decline process, and during the output voltage rise phase, the recovered energy is used to replenish the load capacitor, reducing overall energy loss and improving efficiency.

[0103] Figure 6 This is a schematic diagram of the structure of an energy recovery module provided in a specific embodiment of the present invention.

[0104] In optional specific embodiments of the present invention, such as Figure 6As shown, the energy recovery module 314 may include: a 21st PMOS transistor, a 22nd PMOS transistor, a 23rd PMOS transistor, a 28th NMOS transistor, a 29th NMOS transistor, a 30th NMOS transistor, a 31st NMOS transistor, a 32nd NMOS transistor, a 33rd NMOS transistor, a 24th PMOS transistor, a 25th PMOS transistor, a 26th PMOS transistor, a 27th PMOS transistor, a sixth capacitor, and a 34th PMOS transistor. S-channel MOSFET, PMOS transistor number 35, PMOS transistor number 36, PMOS transistor number 37, PMOS transistor number 38, PMOS transistor number 39, PMOS transistor number 40, PMOS transistor number 41, PMOS transistor number 42, PMOS transistor number 43, NMOS transistor number 37, NMOS transistor number 38, NMOS transistor number 39, PMOS transistor number 44, PMOS transistor number 45, PMOS transistor number 46, PMOS transistor number 40, NMOS transistor number 41, NMOS transistor number 42, NMOS transistor number 47, PMOS transistor number 48, NMOS transistor number 43, NMOS transistor number 44, NMOS transistor number 49, PMOS transistor number 50, and PMOS transistor number 51.

[0105] Specifically, the source and gate of the 21st PMOS transistor are connected, and the source of the 21st PMOS transistor is connected to the first input voltage. The source of the 22nd PMOS transistor is connected to the drain of the 21st PMOS transistor. The gate of the 23rd PMOS transistor is connected to the gate of the 22nd PMOS transistor, the drain of the 23rd PMOS transistor is connected to the drain of the 22nd PMOS transistor, and the source of the 23rd PMOS transistor is connected to the gate of the 23rd PMOS transistor. The source of the 28th NMOS transistor is connected to the source of the 23rd PMOS transistor, and the gate of the 28th NMOS transistor is connected to the charging flag signal MID_RIGHT_ON on the OUT+ side of the load capacitor. The drain of the 29th NMOS transistor is connected to the drain of the 28th NMOS transistor, and the gate of the 29th NMOS transistor is connected to the ground flag signal LEFT_ON on the OUT+ side of the load capacitor. The drain of the 30th NMOS transistor is connected to the source of the 29th NMOS transistor, and the gate of the 30th NMOS transistor is connected to the charging flag signal MID_SIDE on the load capacitor. The drain of the 31st NMOS transistor is connected to the drain of the 29th NMOS transistor, and the gate of the 31st NMOS transistor is connected to a second fixed voltage. The drain of the 32nd NMOS transistor is connected to the drain of the 29th NMOS transistor, and the gate of the 32nd NMOS transistor is connected to the ORI_RIGHT_ON signal, which follows the voltage across the OUT+ side of the load capacitor. The drain of the 33rd NMOS transistor is connected to the source of the 29th NMOS transistor, and the gate of the 33rd NMOS transistor is connected to the power supply V, which follows the voltage across the load capacitor. INThe charging flag signal is ORL_SIDE. The source of the 24th PMOS transistor is connected to the source of the 30th NMOS transistor, and the source and gate of the 24th PMOS transistor are connected. The source of the 25th PMOS transistor is connected to the drain of the 24th PMOS transistor, and the source and gate of the 25th PMOS transistor are connected. The drain of the 26th PMOS transistor is connected to the drain of the 25th PMOS transistor, and the gate of the 26th PMOS transistor is connected to the gate of the 25th PMOS transistor. The drain of the 27th PMOS transistor is connected to the source of the 26th PMOS transistor, and the gate and source of the 27th PMOS transistor are connected. One end of the sixth capacitor is connected to the source of the 27th PMOS transistor, and the other end of the sixth capacitor is grounded. The source of the 28th PMOS transistor is connected to the source of the 27th PMOS transistor, and the gate and source are connected. The source of the 29th PMOS transistor is connected to the drain of the 28th PMOS transistor. The drain of the 30th PMOS transistor is connected to the drain of the 29th PMOS transistor, the gate of the 30th PMOS transistor is connected to the gate of the 29th PMOS transistor, and the gate of the 30th PMOS transistor is connected to its source. The drain of the 31st PMOS transistor is connected to the source of the 30th PMOS transistor, and the gate of the 31st PMOS transistor is connected to its source. The source of the 32nd PMOS transistor is connected to the source of the 31st NMOS transistor, and the gate of the 32nd PMOS transistor is connected to its source. The drain of the 33rd PMOS transistor is connected to the drain of the 32nd PMOS transistor, and the gate of the 33rd PMOS transistor is connected to its gate. The source of the 34th NMOS transistor is connected to the source of the 33rd PMOS transistor, and the source of the 34th NMOS transistor is connected to its gate. The drain of the 34th NMOS transistor is grounded. The gate of the 35th NMOS transistor is connected to the gate of the 34th NMOS transistor, and the drain of the 35th NMOS transistor is connected to the drain of the 33rd NMOS transistor. The source of the 36th NMOS transistor is connected to the source of the 35th NMOS transistor, and the drain of the 36th NMOS transistor is connected to the drain of the 35th NMOS transistor. The gate of the 36th NMOS transistor is connected to the RIGHT_ON ground flag signal of the load capacitor OUT side. The source of the 34th PMOS transistor is connected to the source of the 33rd NMOS transistor, and the gate of the 34th PMOS transistor is connected to the source of the 34th PMOS transistor. The source of the 35th PMOS transistor is connected to the drain of the 34th PMOS transistor, the drain of the 35th PMOS transistor is connected to the source of the 36th NMOS transistor, and the source of the 35th PMOS transistor is connected to the gate of the 35th PMOS transistor.The gate of the 36th PMOS transistor is connected to the gate of the 35th PMOS transistor, and the drain of the 36th PMOS transistor is connected to the drain of the 35th PMOS transistor. The drain of the 37th PMOS transistor is connected to the source of the 36th PMOS transistor, and the source of the 37th PMOS transistor is connected to its gate. The source of the 38th PMOS transistor is connected to the source of the 37th PMOS transistor, and the source of the 38th PMOS transistor is connected to its gate. The source of the 39th PMOS transistor is connected to the drain of the 38th PMOS transistor. The source of the 40th PMOS transistor is connected to the source of the 32nd NMOS transistor, and the source of the 40th PMOS transistor is connected to its gate. The gate of the 41st PMOS transistor is connected to the gate of the 40th PMOS transistor, the drain of the 41st PMOS transistor is connected to its drain, and the source of the 41st PMOS transistor is connected to the drain of the 39th PMOS transistor. The drain of the 42nd PMOS transistor is connected to the source of the 41st PMOS transistor, the gate of the 42nd PMOS transistor is connected to the gate of the 39th PMOS transistor, and the gate of the 42nd PMOS transistor is connected to the source of the 42nd PMOS transistor. The drain of the 43rd PMOS transistor is connected to the source of the 42nd PMOS transistor, and the gate of the 43rd PMOS transistor is connected to the source of the 43rd PMOS transistor. The source of the 37th NMOS transistor is connected to the drain of the 42nd PMOS transistor, and the drain of the 37th NMOS transistor is connected to the drain of the 35th NMOS transistor. The gate of the 37th NMOS transistor is connected to the LEFT_ON ground flag signal on the OUT+ side of the load capacitor. The source of the 38th NMOS transistor is connected to the source of the 37th NMOS transistor, and the drain of the 38th NMOS transistor is connected to the drain of the 37th NMOS transistor. The gate of the 39th NMOS transistor is connected to the gate of the 38th NMOS transistor, the drain of the 39th NMOS transistor is connected to the drain of the 38th NMOS transistor, and the source of the 39th NMOS transistor is connected to its gate. The source of the 44th PMOS transistor is connected to the source of the 39th NMOS transistor. The drain of the 45th PMOS transistor is connected to the drain of the 44th PMOS transistor, the gate of the 45th PMOS transistor is connected to the gate of the 44th PMOS transistor, and the gate of the 45th PMOS transistor is connected to its source. The source of the 46th PMOS transistor is connected to the source of the 45th PMOS transistor, and its gate is connected to a second fixed voltage. The source of the 40th NMOS transistor is connected to the source of the 43rd PMOS transistor, the drain of the 40th NMOS transistor is connected to the drain of the 46th PMOS transistor, and its gate is connected to a load capacitor connected to a power supply V. INThe charging flag signal ORI_SIDE. The source of the 41st NMOS transistor is connected to the drain of the 40th NMOS transistor, and its gate is connected to the load capacitor OUT-side grounding flag signal RIGHT_ON. The source of the 42nd NMOS transistor is connected to the source of the 31st PMOS transistor, and its drain is connected to the source of the 41st NMOS transistor. The gate of the 42nd NMOS transistor is connected to the load capacitor, and its charging flag signal MID_SIDE is connected to the energy recovery capacitor. The drain of the 47th PMOS transistor is connected to the drain of the 41st PMOS transistor, and its source is connected to the drain of the 36th PMOS transistor. The gate of the 48th PMOS transistor is connected to the gate of the 47th PMOS transistor, its drain is connected to the drain of the 47th PMOS transistor, and its gate is connected to the source of the 48th PMOS transistor. The source of the 43rd NMOS transistor is connected to the source of the 48th PMOS transistor, and the drain of the 43rd NMOS transistor is connected to the drain of the 41st NMOS transistor. The gate of the 43rd NMOS transistor is connected to the ORI_LEFT_ON signal, which tracks the charging flag of the load capacitor OUT side following the voltage. The drain of the 44th NMOS transistor is connected to the drain of the 43rd NMOS transistor, and the gate of the 44th NMOS transistor is connected to the MID_LEFT_ON signal, which tracks the charging flag of the energy recovery capacitor OUT side following the load capacitor. The source of the 49th PMOS transistor is connected to the source of the 44th NMOS transistor, and the gate of the 49th PMOS transistor is connected to the source of the 49th PMOS transistor. The drain of the 50th PMOS transistor is connected to the drain of the 49th PMOS transistor, and the gate of the 50th PMOS transistor is connected to the gate of the 49th PMOS transistor. The source of the 51st PMOS transistor is connected to the source of the 50th PMOS transistor, the gate of the 51st PMOS transistor is connected to the drain of the 51st PMOS transistor, and the drain of the 51st PMOS transistor is connected to the second input voltage. Wherein, the first output voltage and V... MID The larger of the voltages is the MID_SIDE signal, which is the inverse of the ORI_SIDE signal. The ORI_SIDE signal is logically ANDed with the LEFT_ON signal to obtain the ORI_LEFT_ON signal; the MID_SIDE signal is logically ANDed with the LEFT_ON signal to obtain the MID_LEFT_ON signal; the ORI_SIDE signal is logically ANDed with the RIGHT_ON signal to obtain the ORI_RIGHT_ON signal; and the MID_SIDE signal is logically ANDed with the RIGHT_ON signal to obtain the MID_RIGHT_ON signal.

[0106] In an optional embodiment of the present invention, the alternating charging and discharging of the load capacitor PIEZO is achieved by alternately opening and closing the switch. Since an energy recovery process is involved, the following description is based on the circuit's stable operating state after a period of time.

[0107] See Figure 6 The logical judgment is mainly composed of voltage comparators CMP3 and CMP4. Both voltage comparators are related to V. HIGH and V MID The comparisons are performed, but the inputs are reversed, where V... MID This is the voltage across the energy recovery capacitor C6. The function of CMP3 is to output V... OUT+ or V OUT- During the descent, determine whether it is related to V. MID Charging begins when V MID Less than V HIGH When MID_SIDE is high and ORI_SIDE is low, the corresponding switch is turned on, charging the energy recovery capacitor C6. When V MID Charge until the voltage is greater than V HIGH When this happens, the CMP3 output toggles, ORI_SIDE goes high, and the output V is controlled. OUT+ or V OUT- For V IN Charging is performed, a process that is also energy recovery. The CMP4's function is to output V... OUT+ or V OUT- Determine whether it passes V during the upward movement. MID For V OUT+ or V OUT- Charging begins when V MID Greater than V HIGH When either LEFT_ON or RIGHT_ON is high, the corresponding MID_LEFT_ON or MID_RIGHT_ON will also be high, controlling the corresponding switch to open, via V. MID For V OUT+ or V OUT- Charging begins. When V HIGH Rise to V MID When ORI_LEFT_ON or ORI_RIGHT_ON is high, the comparator toggles. HV For V OUT+ or V OUT- Charge it.

[0108] I OUTP and I OUTN This refers to the current generated by the transconductance stage. Firstly, when a sine wave needs to be output in the first quadrant, i.e., V... OUT+When the output rises, the recovery capacitor C6 stores the charge stored during the circuit's stable operation before this stage. Therefore, the charge stored in C6 is preferentially used to adjust V. OUT+ Charging. At this time, V... HIGH Below V MID And in order to make V OUT- With grounded, RIGHT_ON is high, and switch NM36 is open. Therefore, after passing through an AND gate, MID_RIGHT_ON is high, controlling switch NM44 to open. Current I OUTN V is made by using current mirrors PM22-PM23 MID For V OUT+ During charging, PM21 is the anti-reverse current transistor mentioned earlier, preventing V... OUT+ Higher than V MID Time to V MID Reverse charging.

[0109] When V OUT+ (i.e. V) HIGH Rise to above V MID When the comparator CMP4 flips, the AND gate ORI_RIGHT_ON becomes high, controlling the NM32 switch to open, and the current I... OUTN V was made using current mirrors PM40-PM41 HV For V OUT+ Charging completes the first quadrant of the output sine wave.

[0110] V OUT+ After reaching its maximum value, it enters the second quadrant of the sine wave, i.e., V. OUT+ The descent process. This process consists of three stages: V OUT+ Decrease to V MID The voltage is the same; V OUT+ Decrease to V IN The voltage is the same; V OUT+ The voltage drops to zero. Firstly, in the first stage, since V... HIGH Voltage higher than V MID The voltage comparator CMP3 outputs MID_SIDE high, opening switch NM42. Simultaneously, because VOUT+ is being charged and discharged during this phase, RIGHT_ON remains high, opening switch NM41. Since the preset MID_SIDE voltage is higher than the gate voltage of control NM46 by 1.8V, the current I... OUTP The current flows through NM42 and then through the current mirrors PM29-PM30, causing V to... OUT+ The capacitor C6 is charged to perform the first stage of energy recovery. PM28 and PM31 are both anti-backflow transistors.

[0111] When V OUT+ Drop below VMID When the comparator CMP3 flips, the output MID_SIDE is low and ORI_SIDE is high, and the voltage is also greater than 1.8V. Therefore, NM42 is turned off and NM40 is turned on, and the current I... OUTP The current flowing through NM40 through current mirrors PM36, PM38, PM39, and PM42 causes V to... OUT+ For V IN During charging, the second stage of energy recovery process begins. Both PM38 and PM43 are anti-backflow transistors.

[0112] When V OUT+ Drop below V IN When, current I OUTP The current flows through NM46 and then through current mirrors PM44-PM45 and NM38-NM39 to transfer V OUT+ The discharge to the ground completes the V process. OUT+ The charging and discharging process.

[0113] For V OUT- During the charging and discharging process, corresponding to the third and fourth quadrants of the output sine wave, the relationship with the aforementioned V... OUT- The charging and discharging process is completely symmetrical. In the third quadrant, V OUT+ When grounded, MID_LEFT_ON is initially high, and the current I... OUTP V is made through a current mirror MID For V OUT- Charging. When V OUT- Rise above V MID After that, ORI_LEFT_ON is high, V HV Start with V OUT- Charge until V OUT- It rises to its maximum value. Then it enters the fourth quadrant, V. OUT- The current begins to decrease; MID_SIDE is initially high, and the current I... OUTN V was obtained by using a current mirror PM25-PM29 OUT- Charge capacitor C6. V OUT- Drop below V MID Afterwards, ORI_SIDE is high, VOUT- to V IN Charge, finally V OUT- Drop below V IN After that, the current I OUTN Overcurrent mirrors PM32-PM33 and NM34-NM35 will V OUT- The discharge to the ground completes the V process. OUT- The charging and discharging process.

[0114] Figure 7 This is a schematic diagram of an error amplifier provided for a specific embodiment of the present invention.

[0115] In optional specific embodiments of the present invention, such as Figure 7 As shown, the error amplifier 313 may include: an eighth resistor, a ninth resistor, a fifty-second PMOS transistor, a fifty-third PMOS transistor, a forty-fifth NMOS transistor, a forty-sixth NMOS transistor, a tenth resistor, an eleventh resistor, a fifty-fourth PMOS transistor, a fifty-fifth PMOS transistor, a fifty-sixth PMOS transistor, a fifty-seventh PMOS transistor, a fifty-eighth PMOS transistor, a fifty-ninth PMOS transistor, a twelfth resistor, a forty-seventh NMOS transistor, a forty-eighth NMOS transistor, a forty-ninth NMOS transistor, and a fiftieth NMOS transistor.

[0116] Specifically, one end of the eighth resistor is connected to the positive terminal of the first transconductance stage. One end of the ninth resistor is connected to the other end of the eighth resistor, and the other end of the ninth resistor is connected to the positive terminal of the second transconductance stage. The source of the fifty-second PMOS transistor is connected to the second transconductance stage. The source of the fifty-third PMOS transistor is connected to the first transconductance stage, and the drain of the fifty-third PMOS transistor is connected to the drain of the fifty-second PMOS transistor. The source of the forty-fifth NMOS transistor is connected to the first transconductance stage, the gate of the forty-fifth NMOS transistor is connected to the other end of the eighth resistor, and the drain of the forty-fifth NMOS transistor is grounded. The source of the forty-sixth NMOS transistor is connected to the second transconductance stage, the gate of the forty-sixth NMOS transistor is connected to the gate of the forty-fifth NMOS transistor, and the drain of the forty-sixth NMOS transistor is grounded. One end of the tenth resistor is connected to the gate of the fifty-second PMOS transistor, and the other end of the tenth resistor is connected to the drain of the forty-fifth NMOS transistor. One end of the eleventh resistor is connected to the gate of the fifty-third PMOS transistor, and the other end of the eleventh resistor is connected to the drain of the forty-sixth NMOS transistor. The source of the 54th PMOS transistor is connected to the first resistor. The source of the 55th PMOS transistor is connected to the drain of the 54th PMOS transistor, and the drain of the 55th PMOS transistor is connected to the circuit power supply voltage VDD. The drain of the 56th PMOS transistor is connected to the drain of the 55th PMOS transistor, and the gate of the 56th PMOS transistor is connected to the gate of the 55th PMOS transistor. The drain of the 57th PMOS transistor is connected to the source of the 56th PMOS transistor, the source of the 57th PMOS transistor is connected to the gate of the 56th PMOS transistor, and the gate of the 57th PMOS transistor is connected to the gate of the 54th PMOS transistor. The drain of the 58th PMOS transistor is connected to the drain of the 56th PMOS transistor, and the gate of the 58th PMOS transistor is connected to the gate of the 56th PMOS transistor. The drain of the 59th PMOS transistor is connected to the source of the 58th PMOS transistor, the gate of the 59th PMOS transistor is connected to the gate of the 57th PMOS transistor, and the source of the 59th PMOS transistor is connected to the second resistor. One end of the twelfth resistor is connected to the source of the fifty-seventh PMOS transistor, and the other end is connected to the gate of the fifty-ninth PMOS transistor. The source of the forty-seventh NMOS transistor is connected to the twelfth resistor. The gate of the forty-eighth NMOS transistor is connected to the gate of the forty-seventh NMOS transistor, and the source of the forty-eighth NMOS transistor is connected to the current I7 flowing through the sixtieth PMOS transistor. The gate of the forty-ninth NMOS transistor is connected to the source of the forty-eighth NMOS transistor, and the drain of the forty-ninth NMOS transistor is grounded.The source of the fiftieth NMOS transistor is connected to the drain of the forty-seventh NMOS transistor, the gate of the fiftieth NMOS transistor is connected to the gate of the forty-ninth NMOS transistor, and the drain of the fiftieth NMOS transistor is connected to the drain of the forty-ninth NMOS transistor.

[0117] In an optional embodiment of the present invention, the error amplifier functions by receiving the pull-down current I generated by the digital-to-analog converter. DAC_OUTP and I DAC_OUTN The voltage difference generated by the current difference passing through the resistor, when amplified, controls the transconductance level G in the control diagram. m1 and G m2 Generates current, which in turn affects V OUT+ and V OUT- The charging and discharging process is repeated until the input differential voltage of the error amplifier is equal.

[0118] Current source I1 first mirrors the current through low-voltage current mirrors NM47-NM50 to a current mirror composed of PM44-PM49. This current is a fixed bias current with a constant magnitude. The current I is obtained by mirroring through PM54 and PM55. L The current I is obtained by mirroring PM58 and PM59. R And respectively merged into V OUT+ and V OUT- A side road leading to the destination. DAC_OUTP with I DAC_OUTN The current drawn from the digital-to-analog converter contains the final output waveform information, and its output current is the waveform played by the desired drive circuit. As shown in the diagram, the current I flowing through the left-hand R10... LP for:

[0119] I LP =I L -I DAC_OUTP

[0120] Where, I L Represented as the total pull-down current generated by the OUT+ port; I DAC_OUTP This represents the positive phase current generated by the digital-to-analog converter.

[0121] The current I flowing through R11 on the right side RN for:

[0122] I RN =I R -I DAC_OUTN

[0123] Where, I R Indicates the total pull-down current generated by the OUT- port; I DAC_OUTN This represents the inverting current generated by the digital-to-analog converter.

[0124] The gates of transistors PM52 and PM53 are the differential input terminals of error amplifier EA1. LP Voltage V is generated after flowing through R10 DAC_OUTP for:

[0125] V DAC_OUTP =V OUT+ -I RLP ·R 10

[0126] Where, I RLP Indicates current I L With current I DAC_OUTP The difference.

[0127] I RN Voltage V is generated after flowing through R11 DAC_OUTN for:

[0128] V DAC_OUTN =V OUT- -I RN ·R 11

[0129] Where, I RN Indicates current I R With current I DAC_OUTN The difference.

[0130] Voltage V DAC_OUTP and voltage V DAC_OUTN These two inputs serve as the two inputs to the error amplifier, with the higher input producing a lower output. The two output voltages then drive G. m1 and G m2 Generates current. When V is needed... OUT+ When rising, I DAC_OUTP There is current, and I DAC_OUTN If V is 0, then DAC_OUTP As the non-inverting input of the error amplifier, and because I DAC_OUTN If the value is 0, then the current flowing through R11 is only the static bias current I. R ,at this time:

[0131] I RN =-I R

[0132] therefore,

[0133] V DAC_OUTN =V OUT- +-I R R 11

[0134] As shown in the figure, V is compared via EA1. EAP <V EAN Therefore, transconductance Gm1 A large current is generated, and G m2 A very small current is generated. Switch SW1 is connected to A, and switch SW3 is closed. V HV Start through current mirror C M1 Give V OUT+ Charging makes V OUT+ rise.

[0135] When V OUT+ The opposite is true when a decrease is needed, V DAC_OUTP <V DAC_OUTN Therefore, V EAP >V EAN This makes the transconductance stage G m2 Generates a large current, while G m1 A small current is generated; switch SW2 is connected to B, V OUT+ The voltage is discharged to ground through current mirrors CM5 and CM6, thus completing the voltage drop, V OUT- The rise and fall of V OUT+ The principle is the same.

[0136] Figure 8 This is a schematic diagram of the structure of a first transconductance stage provided for a specific embodiment of the present invention.

[0137] In optional specific embodiments of the present invention, such as Figure 8 As shown, the first transconductance stage 35 may include: the 60th PMOS transistor, the 61st PMOS transistor, the 51st NMOS transistor, the 52nd NMOS transistor, the 62nd PMOS transistor, the 63rd PMOS transistor, the 64th PMOS transistor, the 53rd NMOS transistor, the 65th PMOS transistor, the 66th PMOS transistor, the 13th resistor, the 54th NMOS transistor, the 67th PMOS transistor, the 68th PMOS transistor, the 55th NMOS transistor, the 69th PMOS transistor, the 56th NMOS transistor, and the 57th NMOS transistor.

[0138] Specifically, the gate of the 60th PMOS transistor is connected to the negative input terminal of the error amplifier. The drain of the 61st PMOS transistor is connected to the drain of the 60th PMOS transistor, and the gate of the 61st PMOS transistor is connected to the positive input terminal of the error amplifier. The gate of the 51st NMOS transistor is connected to the source of the 60th PMOS transistor, and the source of the 51st NMOS transistor is connected to the pull-down current I generated by the transconductance stage. OUTN(Used for charging the PIEZO capacitor), the drain of the 51st NMOS transistor is grounded. The gate of the 52nd NMOS transistor is connected to the gate of the 51st NMOS transistor, the source of the 52nd NMOS transistor is connected to the source of the 60th PMOS transistor, and the drain of the 52nd NMOS transistor is connected to the drain of the 51st NMOS transistor. The gate of the 62nd PMOS transistor is connected to the enable signal ENABLE. The drain of the 63rd PMOS transistor is connected to the drain of the 62nd PMOS transistor. The drain of the 64th PMOS transistor is connected to the source of the 63rd PMOS transistor, and the gate of the 64th PMOS transistor is connected to the source of the 64th PMOS transistor. The gate of the 53rd NMOS transistor is connected to the gate of the 52nd NMOS transistor, the source of the 53rd NMOS transistor is connected to the source of the 64th PMOS transistor, and the drain of the 53rd NMOS transistor is connected to the drain of the 52nd NMOS transistor. The drain of the 65th PMOS transistor is connected to the drain of the 63rd PMOS transistor, and the gate of the 65th PMOS transistor is connected to the gate of the 63rd PMOS transistor. The drain of the 66th PMOS transistor is connected to the source of the 65th PMOS transistor, the gate of the 66th PMOS transistor is connected to the gate of the 64th PMOS transistor, and the source of the 66th PMOS transistor is connected to the source of the 62nd PMOS transistor. One end of the 13th resistor is connected to the source of the 66th PMOS transistor. The source of the 54th NMOS transistor is connected to the other end of the 13th resistor, the drain of the 54th NMOS transistor is connected to the drain of the 53rd NMOS transistor, and the gate of the 54th NMOS transistor is connected to the enable signal ENABLE. The drain of the 67th PMOS transistor is connected to the drain of the 65th PMOS transistor, and the gate of the 67th PMOS transistor is connected to the gate of the 65th PMOS transistor. The drain of the 68th PMOS transistor is connected to the source of the 67th PMOS transistor, the gate of the 68th PMOS transistor is connected to the gate of the 66th PMOS transistor, and the source of the 68th PMOS transistor is connected to the gate of the 67th PMOS transistor. The source of the 55th NMOS transistor is connected to the source of the 68th PMOS transistor, the gate of the 55th NMOS transistor is connected to the gate of the 53rd NMOS transistor, and the drain of the 55th NMOS transistor is connected to the drain of the 53rd NMOS transistor. The drain of the 69th PMOS transistor is connected to the drain of the 67th PMOS transistor, the gate of the 69th PMOS transistor is connected to the source of the 66th PMOS transistor, and the source of the 69th PMOS transistor is connected to the drain of the 61st PMOS transistor.The source of the 56th NMOS transistor is connected to the source of the 61st PMOS transistor, the gate of the 56th NMOS transistor is connected to the gate of the 55th NMOS transistor, and the drain of the 56th NMOS transistor is connected to the drain of the 55th NMOS transistor. The gate and source of the 56th NMOS transistor are connected. The gate of the 57th NMOS transistor is connected to the gate of the 56th NMOS transistor, and the drain of the 57th NMOS transistor is connected to the drain of the 56th NMOS transistor. The source of the 57th NMOS transistor is connected to the charging current I on the high-voltage rail HV to the load capacitor OUT- side. OUTP .

[0139] In optional specific embodiments of the present invention, see [reference needed]. Figure 8 The first and second transconductance stages are used to compare the differential output of error amplifier EA1 and produce two effects: (1) the larger the difference between the differential inputs of EA1, the larger the current generated by the transconductance stage; (2) the differential output of EA1 generates two signals—EAP and EAN, and the difference between these two signals is used as the input of the two transconductance stages with two opposite polarities. The transconductance stage with the larger differential signal generates a smaller current, while the transconductance stage with the smaller differential output generates a larger current. Under different differential inputs, one of the PMOS transistors in PM65 and PM66 will act as a switch, and the other PMOS transistor will feed back the smaller current in PM60 and PM61. The negative feedback will modulate the side with the smaller current in PM60 and PM61 to the magnitude of the current flowing through resistor R13.

[0140] The transistors PM62 and NM54, controlled by the ENABLE signal, act as switches. The error amplifier module generates the signal V. EAN and V EAP As input, connect differential transistors PM60 and PM61. When V EAP Greater than V EAN When the current flowing through PM61 is less than the current flowing through PM60, the current mirrors formed by NM55-NM56 and NM52-NM53 replicate the current. At the top of the module, PM64, PM66, PM68, and PM63, PM65, PM67 form a current mirror. Since the current flowing through PM64 is greater than the current flowing through PM68, after mirroring, PM66 is pushed into the linear region to generate a small current mirrored from PM67 to PM65. The current flowing through R13 is determined by the smaller current between PM60 and PM61, and a voltage drop is generated at the gate of PM69. When the differential input difference is large, the current flowing through R13 is smaller, corresponding to a smaller gate voltage of PM69 (i.e., the voltage difference across R13), resulting in a larger current generated by PM69. Furthermore, most of the current generated by PM69, after being shunt, flows into the smaller differential input, such as V. EAP >V EANWhen the current flowing through PM69 mainly flows through PM60, the differential output of EA1 is larger, resulting in a smaller current being generated, and vice versa. The final generated current is then replicated as current I through a current mirror composed of NM55, NM53, NM52, NM55, NM56 and NM52, NM53, NM55, NM54, NM51. OUTP and I OUTN

[0141] Figure 9 This is a schematic diagram of the structure of a first current mirror provided in a specific embodiment of the present invention.

[0142] In optional specific embodiments of the present invention, such as Figure 9 As shown, the first current mirror 31 may include: the 58th NMOS transistor, the 14th resistor, the 59th NMOS transistor, the 15th resistor, the 60th NMOS transistor, the 16th resistor, the 61st NMOS transistor, the 17th resistor, the 62nd NMOS transistor, the 63rd NMOS transistor, the 64th NMOS transistor, the 18th resistor, the 65th NMOS transistor, the 19th resistor, the 66th NMOS transistor, the 20th resistor, the 67th NMOS transistor, the 21st resistor, the 68th NMOS transistor, and the 69th NMOS transistor.

[0143] Specifically, the source of the fifty-eighth NMOS transistor is connected to the current I flowing through the sixtieth PMOS transistor. mirror1The drain of the transistor is grounded. One end of the fourteenth resistor is connected to the source of the fifty-eighth NMOS transistor. The source of the fifty-ninth NMOS transistor is connected to the other end of the fourteenth resistor, the gate of the fifty-ninth NMOS transistor is connected to the gate of the fifty-eighth NMOS transistor, and the drain of the fifty-ninth NMOS transistor is connected to the drain of the fifty-eighth NMOS transistor. One end of the fifteenth resistor is connected to the source of the fifty-eighth NMOS transistor. The source of the sixtieth NMOS transistor is connected to the other end of the fifteenth resistor, the gate of the sixtieth NMOS transistor is connected to the gate of the fifty-ninth NMOS transistor, and the drain of the sixtieth NMOS transistor is connected to the drain of the fifty-ninth NMOS transistor. One end of the sixteenth resistor is connected to the source of the fifty-sixth NMOS transistor. The source of the sixty-first NMOS transistor is connected to the other end of the sixteenth resistor, the gate of the sixty-first NMOS transistor is connected to the gate of the sixty-first NMOS transistor, and the drain of the sixty-first NMOS transistor is connected to the drain of the sixty-sixth NMOS transistor. One end of the seventeenth resistor is connected to the source of the fifty-sixth NMOS transistor. The source of the 62nd NMOS transistor is connected to the other end of the 17th resistor, the gate of the 62nd NMOS transistor is connected to the gate of the 61st NMOS transistor, and the drain of the 62nd NMOS transistor is connected to the drain of the 61st NMOS transistor. The gate of the 63rd NMOS transistor is connected to the gate of the 62nd NMOS transistor, and the drain of the 63rd NMOS transistor is connected to the drain of the 62nd NMOS transistor. The source of the 63rd NMOS transistor is connected to the high-voltage rail HV and the charging current I5 on the OUT+ side of the load capacitor. The source of the 64th NMOS transistor is connected to the current I flowing through the 61st PMOS transistor. mirror2The drain of the 64th NMOS transistor is grounded. One end of the 18th resistor is connected to the source of the 64th NMOS transistor. The source of the 65th NMOS transistor is connected to the other end of the 18th resistor, the gate of the 65th NMOS transistor is connected to the gate of the 64th NMOS transistor, and the drain of the 65th NMOS transistor is connected to the drain of the 64th NMOS transistor. One end of the 19th resistor is connected to the source of the 64th NMOS transistor. The source of the 66th NMOS transistor is connected to the other end of the 19th resistor, the gate of the 66th NMOS transistor is connected to the gate of the 65th NMOS transistor, and the drain of the 66th NMOS transistor is connected to the drain of the 65th NMOS transistor. One end of the 20th resistor is connected to the source of the 64th NMOS transistor. The source of the 67th NMOS transistor is connected to the other end of the 20th resistor, the gate of the 67th NMOS transistor is connected to the gate of the 66th NMOS transistor, and the drain of the 67th NMOS transistor is connected to the drain of the 66th NMOS transistor. One end of the twenty-first resistor is connected to the source of the sixty-fourth NMOS transistor. The source of the sixty-eighth NMOS transistor is connected to the other end of the twenty-first resistor, the gate of the sixty-eighth NMOS transistor is connected to the gate of the sixty-seventh NMOS transistor, and the drain of the sixty-eighth NMOS transistor is connected to the drain of the sixty-seventh NMOS transistor. The gate of the sixty-ninth NMOS transistor is connected to the gate of the sixty-eighth NMOS transistor, and the drain of the sixty-ninth NMOS transistor is connected to the drain of the sixty-eighth NMOS transistor. The source of the sixty-ninth NMOS transistor is connected to the charging current I6 on the load capacitor OUT side of the voltage rail HV. Optionally, the structure and composition of the second current mirror 33 are similar to those of the first current mirror 31, and will not be described again here.

[0144] In optional specific embodiments of the present invention, see [reference needed]. Figure 9 A resistor is added to the drain terminal of each transistor on the current mirror side. Its function is that as the current flowing through the current mirror gradually increases, the voltage drop across the resistor also gradually increases, and the drain voltage of the transistor gradually decreases until the transistor is pushed into the deep linear region, thereby achieving the purpose of continuously changing the magnification of the current mirror.

[0145] In the diagram, I1 and I2 are the external inflow currents. Analyzing the left half of the circuit, NM58 and NM63 form a fixed current mirror, while NM59 to NM62 are transistors identical to NM58, but the resistances of R14 to R17 increase proportionally, with a ratio of R14:R15:R16:R17 = 1:2:3:4. As the current I1 gradually increases, since R17 has the largest resistance, its voltage drop is also the largest. Therefore, NM62 is the first to be pushed into the deep linear region and lose its current mirror function. As the current I1 continues to increase, the voltage drop across R16 also gradually increases until NM61 loses its current mirror function. This process continues until only NM58 remains in normal operation. Thus, the current mirror replication ratio changes continuously from 5:1 to 1:1. The right half of the circuit works similarly. This structure avoids the situation where the input current increases too much when the current mirror replication ratio is large, leading to excessively rapid changes in the replicated current.

[0146] In optional embodiments of the present invention, the circuit structure described above can produce at least the following significant effects:

[0147] (1) An open-loop control is used to achieve the boost function. The output voltage is directly compared with the target voltage, and then the switching of the power transistor is controlled to obtain a coarse follower voltage that is not lower than the target voltage. The precise control of the output voltage is handled by the low-voltage linear regulator in the later stage. This circuit structure makes the control logic simpler and more direct, always maintaining the stability of the system. In the small load capacitor mode, the simple control method makes the efficiency higher. Furthermore, this control architecture allows users to adjust any desired output waveform in a timely manner and expand its functionality.

[0148] (2) The voltage coarse adjustment unit can adaptively and flexibly switch between continuous conduction mode (CCM) and discontinuous conduction mode (DCM) according to the size of the load capacitance. When the drive is under heavy load, it automatically enters the DCM working mode, while when the drive is under light load, it enters CCM, which greatly improves the efficiency of the circuit. The switching process is smooth and without dead zones, and the output waveform accuracy is not affected.

[0149] (3) The energy recovery section is placed in the downstream H-bridge low-voltage linear regulator. Therefore, the present invention uses a high-voltage diode instead of a high-side power transistor, which avoids the energy loss caused by the control section of the upper power transistor and significantly improves the driving efficiency of small capacitor loads.

[0150] (4) The low-voltage linear regulator of the output stage adopts a hybrid architecture of a core error amplifier and two switches. The coarse follower voltage after boosting is used to achieve high-precision output through LDO (low dropout linear regulator). It has a good suppression effect on output ripple, low output signal distortion, and higher linearity.

[0151] (5) The energy recovery module is placed in the low-voltage linear regulator. During the output signal decline, the energy of the output voltage during the decline is partially recovered by the logic control switch. During the output voltage rise, the recovered energy is used to replenish the load capacitor, which reduces the overall energy loss and improves efficiency.

[0152] Figure 10 This is a schematic flowchart illustrating a piezoelectric driving method for a piezoelectric actuator circuit provided in a specific embodiment of the present invention.

[0153] In optional specific embodiments of the present invention, such as Figure 10 As shown, the method for piezoelectric driving by the piezoelectric actuator circuit may include the following operations S101 to S103:

[0154] In operation S101: the voltage selection unit selects the larger of the first input voltage and the second input voltage as the first output voltage.

[0155] Then, in operation S102: the first output voltage is coarsely adjusted to the second output voltage by using the voltage coarse adjustment unit through open-loop control.

[0156] Next, in operation S103: the second output voltage is precisely adjusted through closed-loop control using a low-voltage linear regulator to obtain the third and fourth output voltages.

[0157] In an optional embodiment of the present invention, open-loop control is used to achieve the boost function. The output voltage is directly compared with the target voltage, and the switching of the switching transistor is controlled to obtain a coarsely approximate following voltage that is not lower than the target voltage. Precise control of the output voltage is handled by the subsequent low-voltage linear regulator. This circuit structure makes the control logic simpler and more direct, maintaining system stability at all times. In small load capacitor mode, the simple control method results in higher efficiency. Furthermore, this control architecture allows users to adjust any desired output waveform in real time and expand its functionality.

[0158] Figure 11 This is a schematic flowchart illustrating the precise adjustment of the second output voltage to obtain the third and fourth output voltages, provided for a specific embodiment of the present invention.

[0159] In optional specific embodiments of the present invention, such as Figure 11 As shown, operation S103 uses a low-voltage linear regulator to precisely adjust the second output voltage to obtain the third and fourth output voltages, and may include the following operations S1031 to S1032:

[0160] In operation S1031: During the output voltage drop process, the energy recovery module is used to recover the energy released by the load capacitor.

[0161] Then, in operation S1032: during the output voltage rise, the energy recovered by the energy recovery module is used to replenish the load capacitor.

[0162] In an optional embodiment of the present invention, the energy recovery module is placed inside the low-voltage linear regulator. During the output signal decline, the energy of the output voltage during the decline is partially recovered through logic control of the switch. During the output voltage rise phase, the recovered energy is used to replenish the load capacitor, thereby reducing overall energy loss and improving efficiency.

[0163] In an optional embodiment of the present invention, when the piezoelectric driver circuit drives a heavy load, the load capacitor of the low-voltage linear regulator is in discontinuous conduction mode; when the piezoelectric driver circuit drives a light load, the load capacitor of the low-voltage linear regulator is in continuous conduction mode. When driving a heavy load, the system operates in CCM mode, where the inductor current is greater than 0 at the end of each cycle and remains continuous in the next cycle. When driving a light load, it operates in DCM mode, where the inductor current drops to 0 at the end of each cycle, resulting in discontinuous inductor current and significantly improving circuit efficiency.

[0164] The piezoelectric driver circuit with energy recovery provided in this invention replenishes energy to the low-voltage linear regulator through a voltage coarse adjustment unit, and then charges and discharges the PIEZO capacitor through an H-bridge type low-dropout linear regulator structure under the HV power rail, achieving arbitrary waveform (including sine wave) output. Taking a sine wave as an example, one cycle involves charging and discharging the positive and negative output ports of the PIEZO capacitor, thus it can be divided into four stages, corresponding to the four quadrants of the output sine half-wave. The specific process is as follows:

[0165] (1) When the output sine wave is in the first quadrant, V OUT- Ground, V OUT+ As the circuit rises, switch SW1 connects to point A, and SW3 disconnects accordingly. At this time, the digital-to-analog converter generates a pull-down differential current (IA). DAC_OUTP I DAC_OUTN A differential voltage is generated through R1 and R2, amplified by the first stage of error amplifier EA1, and then passed through the second stage transconductance stage G. m1 A large current is generated, eventually at V HV The voltage rail is supplied with V through the current mirror CM1. OUT+ Charging. Conversely, the transconductance level G... m2 A very small fixed current is generated, and SW4 is closed, causing V to... OUT- Grounding. V OUT+ The voltage is fed back to the input of the error amplifier EA1 through resistor R1, thus forming negative feedback in the entire loop. During this stage, when V... OUT+ When the voltage is low, the energy recovery module (ERM) prioritizes V.OUT+ Charging begins when V OUT+ When the voltage is charged to a level higher than the voltage on the energy recovery capacitor inside the energy recovery module, then through V... HV For V OUT+ Charge it to improve efficiency.

[0166] (2) When the output sine wave is in the second quadrant, V OUT- Ground, V OUT+ Descend, SW2 connects to B. At this time, G... m1 A small current is generated, and SW3 is disconnected accordingly. The pull-down current I... DAC_OUTP and I DAC_OUTN The voltage difference is generated by R1 and R2, amplified by error amplifier EA1, and then applied to the transconductance stage G. m2 A large current is generated, which is then passed through current mirrors CM5 and CM6 to V. OUT+ Discharge occurs, but SW4 remains grounded. V OUT+ The voltage is fed back to the input of error amplifier EA1 through resistor R1, and the output of EA1 controls G. m2 The current forms a negative feedback loop. During this stage, V... OUT+ When the voltage is high, the energy discharged is first stored in the energy recovery module (ERM). OUT+ Charge V when the voltage is low IN Finally, it was released onto the ground.

[0167] (3) When the output sine wave is in the third quadrant, V OUT+ Ground, V OUT- As the plane rises, switch SW2 is connected to point A, and SW4 is disconnected. At this time, G... m1 A small current is generated, SW3 closes, and the pull-down current I... DAC_OUTP and I DAC_OUTN The voltage difference is generated by R1 and R2, amplified by error amplifier EA1, and makes the transconductance stage G... m2 A large current is generated, eventually at V HV The voltage rail is supplied with V through the current mirror CM4. OUT- Charging. V OUT- The voltage is fed back to the input of error amplifier EA1 through resistor R2, and the output of EA1 controls G. m2 The current forms a negative feedback loop. During this stage, when V... OUT+ When the voltage is low, the energy recovery module (ERM) prioritizes V. OUT- Charging begins when V OUT- When the voltage is charged to a level higher than the voltage on the energy recovery capacitor inside the energy recovery module, then through V... HV For V OUT- Charge it.

[0168] (4) When the output sine wave is in the fourth quadrant, V OUT+ Ground, V OUT- Decrease. Pull-down current I DAC_OUTP and I DAC_OUTN The voltage difference generated by R1 and R2 is amplified by error amplifier EA1 and then makes the transconductance stage G... m1 A large current is generated, SW1 is connected to point B, SW3 is closed, V OUT- Discharge is achieved through the current mirror CM3. At this time, G... m2 A small current is generated, and SW4 is disconnected. V OUT- The voltage is fed back to the input of error amplifier EA1 through resistor R2, and the output of EA1 controls G. m1 The current forms a negative feedback loop. V OUT+ The voltage is fed back to the input of error amplifier EA1 through resistor R1, and the output of EA1 controls G. m2 The current forms a negative feedback loop. During this stage, V... OUT- When the voltage is high, the energy from the discharge first charges the energy recovery capacitor inside the energy recovery module. OUT+ Charge V when the voltage is low IN Finally, it was released onto the ground.

[0169] According to embodiments of the present invention, the method flow according to embodiments of the present invention can be implemented as a computer software program. For example, embodiments of the present invention include a computer program product comprising a computer program carried on a computer-readable storage medium, the computer program containing program code for performing the method shown in the flowchart. According to embodiments of the present invention, the electronic devices, devices, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0170] The present invention also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into the device / apparatus / system. The computer-readable storage medium carries one or more programs, which, when executed, implement the method according to the embodiments of the present invention.

[0171] According to embodiments of the present invention, the computer-readable storage medium may be a non-volatile computer-readable storage medium, such as including, but not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In the present invention, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0172] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0173] Those skilled in the art will understand that the features described in the various embodiments and / or claims of the present invention can be combined or combined in various ways, even if such combinations or combinations are not explicitly described in the present invention. In particular, the features described in the various embodiments and / or claims of the present invention can be combined or combined in various ways without departing from the spirit and teachings of the present invention. All such combinations and / or combinations fall within the scope of the present invention.

[0174] The embodiments of the present invention have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of the invention. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of the invention is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A piezoelectric actuator circuit with energy recovery, characterized in that, The piezoelectric actuator circuit includes: Voltage selection unit (1), used to select voltage based on first input voltage V OUT+ Second input voltage V OUT- The first output voltage V is obtained HIGH Wherein, the first output voltage V HIGH The first input voltage V OUT+ and the second input voltage V OUT- The larger one; The voltage coarse adjustment unit (2), connected to the voltage selection unit (1), is used to coarsely adjust the first output voltage V through open-loop control. HIGH The second output voltage V is obtained HV_REG ;as well as A low-voltage linear regulator (3) is connected to the voltage coarse adjustment unit (2) for precisely adjusting the second output voltage V. HV_REG The third output voltage V' is obtained OUT+ and the fourth output voltage V' OUT- .

2. The piezoelectric actuator circuit with energy recovery according to claim 1, characterized in that, The piezoelectric driver circuit also includes: A first resistor (4), one end of which is connected to the low-voltage linear regulator (3), and the other end of which is connected to the first input voltage; and The second resistor (5) has one end connected to the low-voltage linear regulator (3) and the other end connected to the second input voltage.

3. The piezoelectric actuator circuit with energy recovery according to claim 2, characterized in that, The voltage selection unit (1) includes: The first PMOS transistor has its drain connected to the first input voltage, its source connected to its gate, and its gate connected to the voltage coarse adjustment unit (2); and The second PMOS transistor has its drain connected to the second input voltage, its source connected to its gate, and its gate connected to the voltage coarse adjustment unit (2). The larger of the first input voltage and the second input voltage is the first output voltage.

4. The piezoelectric actuator circuit with energy recovery according to claim 2, characterized in that, The voltage coarse adjustment unit (2) includes: A boost module (21) is connected to the voltage selection unit (1) at its input terminal, and is used to boost the first output voltage to the second output voltage; A voltage comparator (22) has one input terminal connected to the output terminal of the boost module (21), and the other input terminal connected to the following voltage V. HV A connection is provided for outputting a first predetermined signal NEEDSWON based on the second output voltage and the following voltage; A logic controller (23) has one input terminal connected to the output terminal of the voltage comparator (22); The switching transistor (24) has its gate connected to the output terminal of the logic controller (23) and its drain grounded. It is used to output a first current under the control of the output signal of the logic controller (23). The current comparator (25) has one input terminal connected to the drain of the switching transistor (24), and the other input terminal connected to the first preset peak current I. ZTC The output terminal of the switch is connected to another input terminal of the logic controller (23) to output a second predetermined signal CLIM according to the first current and the first preset current threshold, so that the logic controller (23) controls the switching transistor (24) to turn on and off according to the first predetermined signal and the second predetermined signal. The first inductor (26), its input terminal is connected to the supplementary voltage V IN The output terminal is connected to the source of the switching transistor (24); and The first diode (27) has its input terminal connected to the output terminal of the first inductor (26) and its output terminal connected to the low-voltage linear regulator (3) to provide energy to the low-voltage linear regulator (3).

5. The piezoelectric actuator circuit with energy recovery according to claim 4, characterized in that, The voltage coarse adjustment unit (2) also includes: A first capacitor (28), one end of which is connected to the input terminal of the first inductor (26), and the other end is grounded; and The second capacitor (29) has one end connected to the output terminal of the first diode (27) and the other end grounded.

6. The piezoelectric actuator circuit with energy recovery according to claim 4, characterized in that, The boost module (21) includes: The drain of the third PMOS transistor is connected to the voltage selection unit and grounded; The positive terminal of the second diode is connected to the gate of the third PMOS transistor, and the negative terminal is connected to the drain of the third PMOS transistor. The fourth PMOS transistor has its source connected to the source of the third PMOS transistor, and its gate connected to its source. The second resistor has one end connected to the drain of the fourth PMOS transistor; The fifth PMOS transistor has its source connected to the other end of the second resistor, and its gate connected to the source. The sixth PMOS transistor has its gate connected to the gate of the fifth PMOS transistor, its drain connected to the drain of the fifth PMOS transistor, and its source connected to the voltage comparator; and The anode of the third diode is connected to the anode of the second diode, and the cathode is connected to the drain of the fifth PMOS transistor and the drain of the sixth PMOS transistor, respectively.

7. The piezoelectric actuator circuit with energy recovery according to claim 6, characterized in that, The voltage comparator (22) includes: The first NMOS transistor has its source connected to the source of the sixth PMOS transistor, its gate connected to its source, and its drain grounded. The drain of the second NMOS transistor is connected to the drain of the first NMOS transistor, and the gate is connected to the source. The source is connected to a fixed bias current I3. The drain of the third NMOS transistor is connected to the drain of the second NMOS transistor, and the gate is connected to the gate of the second NMOS transistor. The fourth NMOS transistor has its drain connected to the drain of the third NMOS transistor and its gate connected to the gate of the third NMOS transistor. The fifth NMOS transistor has its drain connected to the drain of the fourth NMOS transistor and its gate connected to the gate of the fourth NMOS transistor. The sixth NMOS transistor has its drain connected to the drain of the fifth NMOS transistor and its gate connected to the gate of the fifth NMOS transistor. The seventh NMOS transistor has its drain connected to the source of the third NMOS transistor, and its gate connected to the first trigger signal TRIM1. The eighth NMOS transistor has its source connected to the source of the seventh NMOS transistor, its drain connected to the source of the fourth NMOS transistor, and its gate connected to the second trigger signal TRIM2. The ninth NMOS transistor has its source connected to the source of the eighth NMOS transistor, its drain connected to the source of the fifth NMOS transistor, and its gate connected to the third trigger signal TRIM3. The tenth NMOS transistor has its source connected to the source of the ninth NMOS transistor, its drain connected to the source of the sixth NMOS transistor, and its gate connected to the power supply voltage VCC. The seventh PMOS transistor has its source connected to the source of the tenth NMOS transistor, and its gate connected to its source. The eighth PMOS transistor has its gate connected to the gate of the seventh PMOS transistor and its drain connected to the drain of the seventh PMOS transistor. The eleventh NMOS transistor has its drain connected to the source of the eighth PMOS transistor, its gate connected to the gate of the first NMOS transistor, and its drain connected to the drain of the sixth NMOS transistor. The ninth PMOS transistor has its gate connected to the source of the eighth PMOS transistor and its drain connected to the drain of the eighth PMOS transistor. The twelfth NMOS transistor has its source connected to the source of the ninth PMOS transistor, its drain connected to the drain of the eleventh NMOS transistor, and its gate connected to the source of the eighth PMOS transistor and the gate of the ninth PMOS transistor, respectively. The tenth PMOS transistor has its gate connected to the source of the ninth PMOS transistor, its drain connected to the drain of the ninth PMOS transistor, and its source connected to the logic controller; and The thirteenth NMOS transistor has its source connected to the source of the tenth PMOS transistor, its drain connected to the drain of the twelfth NMOS transistor, and its gate connected to the gate of the tenth PMOS transistor and the source of the twelfth NMOS transistor.

8. The piezoelectric actuator circuit with energy recovery according to claim 4, characterized in that, The logic controller (23) includes: The first AND logic unit has one input connected to the continuous conduction mode fixed switch time flag signal TIME_OPEN, and the other input connected to the continuous conduction mode flag signal CCM_OPEN. The first D flip-flop has its clock port CK connected to the first AND logic unit, its D input port connected to the voltage comparator, its set port SET connected to the continuous conduction mode hold flag delay signal CCM_KKEP_DELAY, and its reset port CLR connected to the power supply voltage VCC. The second logic unit has one input connected to the bias module working properly flag signal BIAS_READY, and the other input connected to the Q output of the first D flip-flop. The first inverter has its input connected to the second AND logic unit; The second D flip-flop has its reset port CLR connected to the output of the first inverter, its set port SET connected to the power supply voltage VCC, and its D input port connected to the power supply voltage VCC. The third D flip-flop has its Q output connected to the clock port CK of the second D flip-flop, its set port SET connected to the supply voltage VCC, its clock port CK connected to the minimum turn-off time flag signal BLANK_TIME in discontinuous conduction mode, its reset port CLR connected to the inverted delay signal CCM_TRIGGERB_DELAY in continuous conduction mode, and its D input port connected to the voltage comparator. The output terminal is connected to the inverted signal of the continuous conduction mode trigger flag, CCM_TRIGGERB; The second inverter has its input terminal connected to the switching transistor; The eleventh PMOS transistor has its gate connected to the output of the second inverter and its drain connected to the power supply voltage VCC. The third resistor has one end connected to the source of the eleventh PMOS transistor; The fourteenth NMOS transistor has its source connected to the other end of the third resistor, its gate connected to the gate of the eleventh PMOS transistor, and its drain grounded. The third capacitor has one end connected to the source of the eleventh PMOS transistor and the other end grounded. The third inverter has its input terminal connected to the source of the eleventh PMOS transistor; The first NAND logic unit has one input connected to the output of the third inverter and the other input connected to the Q output of the second D flip-flop. The fourth inverter has its input terminal connected to the switching transistor; The twelfth PMOS transistor has its gate connected to the output terminal of the fourth inverter and its drain connected to the power supply voltage VCC. The gate of the fifteenth NMOS transistor is connected to the gate of the twelfth PMOS transistor, and its drain is grounded. The fourth resistor has one end connected to the source of the twelfth PMOS transistor and the other end connected to the source of the fifteenth NMOS transistor. The fourth capacitor has one end connected to the source of the twelfth PMOS transistor and the other end grounded. The fifth inverter has its input terminal connected to the source of the twelfth PMOS transistor; The second NAND logic unit has one input connected to the output of the fifth inverter and the other input connected to the voltage comparator. The third AND logic unit has one input terminal connected to the output terminal of the first AND-NOT logic unit, and the other input terminal connected to the output terminal of the second AND-NOT logic unit. A third NAND logic device, one of its input terminals is connected to the output terminal of the third NAND logic device; The fourth NAND logic device has one input connected to the output of the third NAND logic device and its output connected to the other input of the third NAND logic device. The thirteenth PMOS transistor has its gate connected to the power transistor turn-on completion flag signal SW_DONE_FLAG and its drain connected to the power supply voltage VCC. The sixteenth NMOS transistor has its gate connected to the gate of the thirteenth PMOS transistor, and its drain is grounded. The fifth resistor has one end connected to the source of the thirteenth PMOS transistor and the other end connected to the source of the sixteenth NMOS transistor. The fifth capacitor has one end connected to the source of the thirteenth PMOS transistor and the other end grounded. The sixth inverter has its input terminal connected to the source of the thirteenth PMOS transistor; The first OR logic unit has one input terminal connected to the output terminal of the sixth inverter and the other input terminal connected to the current comparator. The seventh inverter has its input connected to the output of the first OR logic unit and its output connected to the other input of the fourth NAND logic unit. The eighth inverter has its input connected to the digital-to-analog converter (DAC) operating flag signal DAC_ON. The ninth inverter has its input connected to the inverted signal SENSE_ON_VINB, which is the indicator signal for sensor operation. The second OR logic unit has one input connected to the output of the eighth inverter, one input connected to the output of the ninth inverter, and the other input connected to the circuit stop working flag signal SHUTDOWN. The tenth inverter has its input connected to the boost module's BOOST_ON signal. A third OR logic unit, one input of which is connected to the output of the second OR logic unit, one input of which is connected to the output of the tenth inverter, and another input of which is connected to the output of the fourth NAND logic unit; and The eleventh inverter has its input connected to the output of the third OR logic unit, and its output connected to the switching transistor.

9. The piezoelectric actuator circuit with energy recovery according to claim 4, characterized in that, The current comparator (25) includes: The fourteenth PMOS transistor has its gate and source connected; The gate of the fifteenth PMOS transistor is connected to the gate of the fourteenth PMOS transistor, and the drain is connected to the drain of the fourteenth PMOS transistor. The gate of the sixteenth PMOS transistor is connected to the gate of the fifteenth PMOS transistor, and the drain is connected to the drain of the fifteenth PMOS transistor. The sixth resistor has one end connected to the source of the fifteenth PMOS transistor; The seventh resistor has one end connected to the other end of the sixth resistor and the other end connected to the source of the sixteenth PMOS transistor. The source of the seventeenth NMOS transistor is connected to the source of the fifteenth PMOS transistor, and its gate is connected to the other end of the sixth resistor. The source of the eighteenth NMOS transistor is connected to the drain of the seventeenth NMOS transistor and connected to the first preset current threshold, while the gate is connected to the power supply voltage VCC. The source of the nineteenth NMOS transistor is connected to the drain of the eighteenth NMOS transistor, the gate is connected to the power supply voltage VCC, and the drain is grounded. The twentieth NMOS transistor has its source connected to the source of the sixteenth PMOS transistor and its gate connected to the gate of the seventeenth NMOS transistor. The source of the twenty-first NMOS transistor is connected to the drain of the twentieth NMOS transistor, and its gate is connected to the power supply voltage VCC. The source of the 22nd NMOS transistor is connected to the drain of the 21st NMOS transistor, the gate is connected to the minimum turn-on time flag signal BLANK, and the drain is grounded. The source of the 23rd NMOS transistor is connected to the source of the 22nd NMOS transistor, the gate is connected to the inverted signal BLANK_B of the minimum turn-on time flag, and the drain is connected to the voltage signal SW of the node where the first inductor and the switch are connected. The drain of the seventeenth PMOS transistor is connected to the drain of the sixteenth PMOS transistor, and the gate is connected to the source. The source of the twenty-fourth NMOS transistor is connected to the source of the seventeenth PMOS transistor, and its gate is connected to the source of the sixteenth PMOS transistor. The drain of the eighteenth PMOS transistor is connected to the drain of the seventeenth PMOS transistor, and the gate is connected to the source. The source of the 25th NMOS transistor is connected to the source of the 18th PMOS transistor, the gate is connected to the source of the 15th PMOS transistor, and the drain is connected to the drain of the 24th NMOS transistor. The nineteenth PMOS transistor has its gate connected to the gate of the eighteenth PMOS transistor and its drain connected to the drain of the eighteenth PMOS transistor. The source of the twenty-sixth NMOS transistor is connected to the source of the nineteenth PMOS transistor, the gate is connected to the source, and the drain is grounded. The twentieth PMOS transistor has its drain connected to the drain of the nineteenth PMOS transistor, its gate connected to the gate of the seventeenth PMOS transistor, and its source connected to the gate of the switching transistor; and The source of the twenty-seventh NMOS transistor is connected to the source of the twentieth PMOS transistor, the gate is connected to the gate of the twenty-sixth NMOS transistor, and the drain is connected to the drain of the twenty-sixth NMOS transistor.

10. The piezoelectric actuator circuit with energy recovery according to claim 4, characterized in that, The low-voltage linear regulator (3) includes: The first current mirror (31) has its two input terminals connected to the output terminal of the first diode (27); The first switch (32) has one contact connected to an output terminal of the first current mirror (31); The second current mirror (33) has two input terminals connected and one output terminal connected to another contact of the first switch (32); The third current mirror (34) has one input terminal connected to the other output terminal of the second current mirror (33), and both output terminals are grounded. The first transconducting stage (35) has its positive terminal connected to the common point of the first switch (32) and its negative terminal grounded. The positive terminal of the second transconducting stage (36) is connected to the negative terminal of the first transconducting stage (35), the negative terminal is connected to the positive terminal of the first transconducting stage (35), and the negative terminal is grounded. The fourth current mirror (37) has two input terminals connected to the output terminal of the first diode (27) and one output terminal connected to the other input terminal of the third current mirror (34); The second switch (38) has one contact connected to the other output terminal of the fourth current mirror (37), and the common point is connected to the positive terminal of the second transconductance stage (36); The fifth current mirror (39) has two input terminals connected and one output terminal connected to another contact of the second switch (38); The sixth current mirror (310) has one input terminal connected to the other output terminal of the fifth current mirror (39), and the other input terminal connected to the other output terminal of the first current mirror (31). Both output terminals are grounded. The third switch (311) has its common point connected to the other output terminal of the first current mirror (31), and its contact is grounded; The fourth switch (312), whose common point is connected to the other output terminal of the fourth current mirror (37), and whose contact is grounded; and An error amplifier (313) has its negative input terminal connected to the negative terminal of the second transconductance stage (36), its positive input terminal connected to the positive terminal of the second transconductance stage (36), its positive output terminal connected to the first resistor (4), and its negative output terminal connected to the second resistor (5). The error amplifier (313) is used to output a pull-down differential current.

11. The piezoelectric actuator circuit with energy recovery according to claim 10, characterized in that, The low-voltage linear regulator (3) also includes: An energy recovery module (314) has one end connected to the other output terminal of the first current mirror (31) and the other end connected to the other output terminal of the fourth current mirror (37); and A load capacitor (315) is connected at one end to one end of the energy recovery module (314) and at the other end to the other end of the energy recovery module (314).

12. The piezoelectric actuator circuit with energy recovery according to claim 11, characterized in that, The energy recovery module (314) includes: The twenty-first PMOS transistor has its source and gate connected together, and is connected to the first input voltage; The source of the twenty-second PMOS transistor is connected to the drain of the twenty-first PMOS transistor. The gate of the 23rd PMOS transistor is connected to the gate of the 22nd PMOS transistor, the drain is connected to the drain of the 22nd PMOS transistor, and the source is connected to the gate. The source of the 28th NMOS transistor is connected to the source of the 23rd PMOS transistor, and the gate is connected to the energy recovery capacitor and the charging flag signal MID_RIGHT_ON on the OUT+ side of the load capacitor. The drain of the 29th NMOS transistor is connected to the drain of the 28th NMOS transistor, and the gate is connected to the load capacitor OUT+ side grounding flag signal LEFT_ON; The drain of the thirtieth NMOS transistor is connected to the source of the twenty-ninth NMOS transistor, and the gate is connected to the load capacitor to the energy recovery capacitor charging flag signal MID_SIDE. The drain of the thirty-first NMOS transistor is connected to the drain of the twenty-ninth NMOS transistor, and the gate is connected to the second fixed voltage. The drain of the thirty-second NMOS transistor is connected to the drain of the twenty-ninth NMOS transistor, and its gate is connected to the ORI_RIGHT_ON signal. The drain of the thirty-third NMOS transistor is connected to the source of the twenty-ninth NMOS transistor, and its gate is connected to the load capacitor relative to the power supply V. IN The charging indicator signal ORL_SIDE; The source of the twenty-fourth PMOS transistor is connected to the source of the thirtieth NMOS transistor, and the source is connected to the gate. The source of the 25th PMOS transistor is connected to the drain of the 24th PMOS transistor, and the source is connected to the gate. The drain of the 26th PMOS transistor is connected to the drain of the 25th PMOS transistor, and the gate is connected to the gate of the 25th PMOS transistor. The drain of the twenty-seventh PMOS transistor is connected to the source of the twenty-sixth PMOS transistor, and the gate is connected to the source. The sixth capacitor has one end connected to the source of the twenty-seventh PMOS transistor and the other end grounded. The source of the twenty-eighth PMOS transistor is connected to the source of the twenty-seventh PMOS transistor, and the gate is connected to the source. The source of the twenty-ninth PMOS transistor is connected to the drain of the twenty-eighth PMOS transistor; The thirtieth PMOS transistor has its drain connected to the drain of the twenty-ninth PMOS transistor, its gate connected to the gate of the twenty-ninth PMOS transistor, and its gate connected to its source. The drain of the thirty-first PMOS transistor is connected to the source of the thirtieth PMOS transistor, and the gate is connected to the source. The source of the thirty-second PMOS transistor is connected to the source of the thirty-first NMOS transistor, and the gate is connected to the source. The drain of the thirty-third PMOS transistor is connected to the drain of the thirty-second PMOS transistor, and the gate is connected to the gate of the thirty-second PMOS transistor. The source of the thirty-fourth NMOS transistor is connected to the source of the thirty-third PMOS transistor, the source is connected to the gate, and the drain is grounded. The gate of the thirty-fifth NMOS transistor is connected to the gate of the thirty-fourth NMOS transistor, and the drain is connected to the drain of the thirty-third NMOS transistor. The source of the 36th NMOS transistor is connected to the source of the 35th NMOS transistor, the drain is connected to the drain of the 35th NMOS transistor, and the gate is connected to the load capacitor OUT-side grounding flag signal RIGHT_ON. The source of the thirty-fourth PMOS transistor is connected to the source of the thirty-third NMOS transistor, and the gate is connected to the source. The source of the thirty-fifth PMOS transistor is connected to the drain of the thirty-fourth PMOS transistor, the drain of the thirty-sixth NMOS transistor is connected to the source of the thirty-sixth NMOS transistor, and the source is connected to the gate. The gate of the thirty-sixth PMOS transistor is connected to the gate of the thirty-fifth PMOS transistor, and the drain is connected to the drain of the thirty-fifth PMOS transistor. The drain of the thirty-seventh PMOS transistor is connected to the source of the thirty-sixth PMOS transistor, and the source is connected to the gate. The source of the thirty-eighth PMOS transistor is connected to the source of the thirty-seventh PMOS transistor, and the source is connected to the gate. The source of the thirty-ninth PMOS transistor is connected to the drain of the thirty-eighth PMOS transistor; The source of the fortieth PMOS transistor is connected to the source of the thirty-second NMOS transistor, and the source is connected to the gate. The gate of the forty-first PMOS transistor is connected to the gate of the fortieth PMOS transistor, the drain is connected to the drain of the fortieth PMOS transistor, and the source is connected to the drain of the thirty-ninth PMOS transistor. The drain of the forty-second PMOS transistor is connected to the source of the forty-first PMOS transistor, and its gate is connected to the gate of the thirty-ninth PMOS transistor. The gate is also connected to the source. The drain of the forty-third PMOS transistor is connected to the source of the forty-second PMOS transistor, and the gate is connected to the source. The source of the 37th NMOS transistor is connected to the drain of the 42nd PMOS transistor, and the drain of the 35th NMOS transistor is connected to the drain of the load capacitor OUT+ side grounding flag signal LEFT_ON. The source of the thirty-eighth NMOS transistor is connected to the source of the thirty-seventh NMOS transistor, and the drain is connected to the drain of the thirty-seventh NMOS transistor. The gate of the thirty-ninth NMOS transistor is connected to the gate of the thirty-eighth NMOS transistor, the drain is connected to the drain of the thirty-eighth NMOS transistor, and the source is connected to the gate. The source of the forty-fourth PMOS transistor is connected to the source of the thirty-ninth NMOS transistor; The drain of the forty-fifth PMOS transistor is connected to the drain of the forty-fourth PMOS transistor, the gate is connected to the gate of the forty-fourth PMOS transistor, and the gate is connected to the source. The source of the forty-sixth PMOS transistor is connected to the source of the forty-fifth PMOS transistor, and the gate is connected to a second fixed voltage. The source of the fortieth NMOS transistor is connected to the source of the forty-third PMOS transistor, and its drain is connected to the drain of the forty-sixth PMOS transistor. Its gate is connected to the load capacitor relative to the power supply V. IN The charging indicator signal is ORI_SIDE; The source of the forty-first NMOS transistor is connected to the drain of the fortieth NMOS transistor, and the gate is connected to the load capacitor OUT-side grounding flag signal RIGHT_ON. The source of the forty-second NMOS transistor is connected to the source of the thirty-first PMOS transistor, the drain is connected to the source of the forty-first NMOS transistor, and the gate is connected to the load capacitor to the energy recovery capacitor charging flag signal MID_SIDE. The drain of the forty-seventh PMOS transistor is connected to the drain of the forty-first PMOS transistor, and the source is connected to the drain of the thirty-sixth PMOS transistor. The gate of the forty-eighth PMOS transistor is connected to the gate of the forty-seventh PMOS transistor, the drain is connected to the drain of the forty-seventh PMOS transistor, and the gate is connected to the source. The source of the forty-third NMOS transistor is connected to the source of the forty-eighth PMOS transistor, the drain is connected to the drain of the forty-first NMOS transistor, and the gate is connected to the ORI_LEFT_ON signal, which follows the voltage to charge the load capacitor OUT-side. The drain of the forty-fourth NMOS transistor is connected to the drain of the forty-third NMOS transistor, and the gate is connected to the energy recovery capacitor to the load capacitor OUT-side charging flag signal MID_LEFT_ON. The source of the forty-ninth PMOS transistor is connected to the source of the forty-fourth NMOS transistor, and the gate is connected to the source. The 50th PMOS transistor has its drain connected to the drain of the 49th PMOS transistor, and its gate connected to the gate of the 49th PMOS transistor; and The source of the fifty-first PMOS transistor is connected to the source of the fiftieth PMOS transistor, and its gate and drain are connected. The drain is connected to the second input voltage. Wherein, the first output voltage and V MID The larger of the voltages is the MID_SIDE signal, which is the inverse of the ORI_SIDE signal. The ORI_SIDE signal is logically ANDed with the LEFT_ON signal to obtain the ORI_LEFT_ON signal; the MID_SIDE signal is logically ANDed with the LEFT_ON signal to obtain the MID_LEFT_ON signal; the ORI_SIDE signal is logically ANDed with the RIGHT_ON signal to obtain the ORI_RIGHT_ON signal; and the MID_SIDE signal is logically ANDed with the RIGHT_ON signal to obtain the MID_RIGHT_ON signal.

13. The piezoelectric actuator circuit with energy recovery according to claim 10, characterized in that, The error amplifier (313) includes: The eighth resistor has one end connected to the positive terminal of the first transconductance stage; The ninth resistor has one end connected to the other end of the eighth resistor and the other end connected to the positive terminal of the second transconductance stage. The source of the fifty-second PMOS transistor is connected to the second transconductance stage; The source of the fifty-third PMOS transistor is connected to the first transconductance stage, and its drain is connected to the drain of the fifty-second PMOS transistor. The forty-fifth NMOS transistor has its source connected to the first transconductance stage, its gate connected to the other end of the eighth resistor, and its drain grounded. The source of the forty-sixth NMOS transistor is connected to the second transconductance stage, the gate is connected to the gate of the forty-fifth NMOS transistor, and the drain is grounded. The tenth resistor has one end connected to the gate of the fifty-second PMOS transistor and the other end connected to the drain of the forty-fifth NMOS transistor. The eleventh resistor has one end connected to the gate of the fifty-third PMOS transistor and the other end connected to the drain of the forty-sixth NMOS transistor. The source of the fifty-fourth PMOS transistor is connected to the first resistor; The source of the fifty-fifth PMOS transistor is connected to the drain of the fifty-fourth PMOS transistor, and the drain is connected to the circuit power supply voltage VDD. The drain of the fifty-sixth PMOS transistor is connected to the drain of the fifty-fifth PMOS transistor, and the gate is connected to the gate of the fifty-fifth PMOS transistor. The drain of the fifty-seventh PMOS transistor is connected to the source of the fifty-sixth PMOS transistor, the source is connected to the gate of the fifty-sixth PMOS transistor, and the gate is connected to the gate of the fifty-fourth PMOS transistor. The drain of the fifty-eighth PMOS transistor is connected to the drain of the fifty-sixth PMOS transistor, and its gate is connected to the gate of the fifty-sixth PMOS transistor. The drain of the fifty-ninth PMOS transistor is connected to the source of the fifty-eighth PMOS transistor, the gate is connected to the gate of the fifty-seventh PMOS transistor, and the source is connected to the second resistor. The twelfth resistor has one end connected to the source of the fifty-seventh PMOS transistor and the other end connected to the gate of the fifty-ninth PMOS transistor. The forty-seventh NMOS transistor has its source connected to the twelfth resistor; The gate of the forty-eighth NMOS transistor is connected to the gate of the forty-seventh NMOS transistor, and its source is connected to the first fixed current I1; The forty-ninth NMOS transistor has its gate connected to the source of the forty-eighth NMOS transistor, and its drain grounded; and The source of the fiftieth NMOS transistor is connected to the drain of the forty-seventh NMOS transistor, the gate is connected to the gate of the forty-ninth NMOS transistor, and the drain is connected to the drain of the forty-ninth NMOS transistor.

14. The piezoelectric actuator circuit with energy recovery according to claim 10, characterized in that, The first transconductance stage (35) includes: The gate of the sixtieth PMOS transistor is connected to the negative input terminal of the error amplifier; The sixty-first PMOS transistor has its drain connected to the drain of the sixtieth PMOS transistor, and its gate connected to the positive input terminal of the error amplifier. The fifty-first NMOS transistor has its gate connected to the source of the sixtieth PMOS transistor, and its source is connected to the high-voltage rail HV and the charging current I on the load capacitor OUT+ side. OUTN Drain grounded; The gate of the fifty-second NMOS transistor is connected to the gate of the fifty-first NMOS transistor, the source is connected to the source of the sixtieth PMOS transistor, and the drain is connected to the drain of the fifty-first NMOS transistor. The sixty-second PMOS transistor has its gate connected to the enable signal ENABLE. The drain of the sixty-third PMOS transistor is connected to the drain of the sixty-second PMOS transistor; The drain of the sixty-fourth PMOS transistor is connected to the source of the sixty-third PMOS transistor, and the gate is connected to the source. The gate of the fifty-third NMOS transistor is connected to the gate of the fifty-second NMOS transistor, the source is connected to the source of the sixty-fourth PMOS transistor, and the drain is connected to the drain of the fifty-second NMOS transistor. The drain of the sixty-fifth PMOS transistor is connected to the drain of the sixty-third PMOS transistor, and the gate is connected to the gate of the sixty-third PMOS transistor. The drain of the sixty-sixth PMOS transistor is connected to the source of the sixty-fifth PMOS transistor, the gate is connected to the gate of the sixty-fourth PMOS transistor, and the source is connected to the source of the sixty-second PMOS transistor. The thirteenth resistor has one end connected to the source of the sixty-sixth PMOS transistor; The source of the fifty-fourth NMOS transistor is connected to the other end of the thirteenth resistor, the drain is connected to the drain of the fifty-third NMOS transistor, and the gate is connected to the enable signal ENABLE. The drain of the sixty-seventh PMOS transistor is connected to the drain of the sixty-fifth PMOS transistor, and the gate is connected to the gate of the sixty-fifth PMOS transistor. The drain of the sixty-eighth PMOS transistor is connected to the source of the sixty-seventh PMOS transistor, the gate is connected to the gate of the sixty-sixth PMOS transistor, and the source is connected to the gate of the sixty-seventh PMOS transistor. The source of the fifty-fifth NMOS transistor is connected to the source of the sixty-eighth PMOS transistor, the gate is connected to the gate of the fifty-third NMOS transistor, and the drain is connected to the drain of the fifty-third NMOS transistor. The drain of the sixty-ninth PMOS transistor is connected to the drain of the sixty-seventh PMOS transistor, the gate is connected to the source of the sixty-sixth PMOS transistor, and the source is connected to the drain of the sixty-first PMOS transistor. The source of the fifty-sixth NMOS transistor is connected to the source of the sixty-first PMOS transistor, its gate is connected to the gate of the fifty-fifth NMOS transistor, its drain is connected to the drain of the fifty-fifth NMOS transistor, and its gate is connected to its source; and The gate of the fifty-seventh NMOS transistor is connected to the gate of the fifty-sixth NMOS transistor, and its drain is connected to the drain of the fifty-sixth NMOS transistor. Its source is connected to the high-voltage rail HV and the charging current I on the load capacitor OUT side. OUTP .

15. The piezoelectric actuator circuit with energy recovery according to claim 10, characterized in that, The first current mirror (31) includes: The source of the fifty-eighth NMOS transistor is connected to the current I flowing through the sixtieth PMOS transistor. mirror1 Drain grounded; The fourteenth resistor has one end connected to the source of the fifty-eighth NMOS transistor; The source of the fifty-ninth NMOS transistor is connected to the other end of the fourteenth resistor, the gate is connected to the gate of the fifty-eighth NMOS transistor, and the drain is connected to the drain of the fifty-eighth NMOS transistor. The fifteenth resistor has one end connected to the source of the fifty-eighth NMOS transistor; The source of the sixtieth NMOS transistor is connected to the other end of the fifteenth resistor, the gate is connected to the gate of the fifty-ninth NMOS transistor, and the drain is connected to the drain of the fifty-ninth NMOS transistor. The sixteenth resistor has one end connected to the source of the fifty-sixth NMOS transistor; The source of the sixty-first NMOS transistor is connected to the other end of the sixteenth resistor, the gate is connected to the gate of the sixtieth NMOS transistor, and the drain is connected to the drain of the sixtieth NMOS transistor. The seventeenth resistor has one end connected to the source of the fifty-sixth NMOS transistor; The source of the sixty-second NMOS transistor is connected to the other end of the seventeenth resistor, the gate is connected to the gate of the sixty-first NMOS transistor, and the drain is connected to the drain of the sixty-first NMOS transistor. The gate of the sixty-third NMOS transistor is connected to the gate of the sixty-second NMOS transistor, the drain is connected to the drain of the sixty-second NMOS transistor, and the source is connected to the high-voltage rail HV to charge the load capacitor OUT+ side current I5. The source of the sixty-fourth NMOS transistor is connected to the current I flowing through the sixty-first PMOS transistor. mirror2 Drain grounded; The eighteenth resistor has one end connected to the source of the sixty-fourth NMOS transistor; The source of the sixty-fifth NMOS transistor is connected to the other end of the eighteenth resistor, the gate is connected to the gate of the sixty-fourth NMOS transistor, and the drain is connected to the drain of the sixty-fourth NMOS transistor. The nineteenth resistor has one end connected to the source of the sixty-fourth NMOS transistor; The source of the sixty-sixth NMOS transistor is connected to the other end of the nineteenth resistor, the gate is connected to the gate of the sixty-fifth NMOS transistor, and the drain is connected to the drain of the sixty-fifth NMOS transistor. The twentieth resistor has one end connected to the source of the sixty-fourth NMOS transistor; The source of the sixty-seventh NMOS transistor is connected to the other end of the twentieth resistor, the gate is connected to the gate of the sixty-sixth NMOS transistor, and the drain is connected to the drain of the sixty-sixth NMOS transistor. The twenty-first resistor has one end connected to the source of the sixty-fourth NMOS transistor; The source of the sixty-eighth NMOS transistor is connected to the other end of the twenty-first resistor, its gate is connected to the gate of the sixty-seventh NMOS transistor, and its drain is connected to the drain of the sixty-seventh NMOS transistor; and The gate of the sixty-ninth NMOS transistor is connected to the gate of the sixty-eighth NMOS transistor, the drain is connected to the drain of the sixty-eighth NMOS transistor, and the source is connected to the high-voltage rail HV to the charging current I6 on the OUT- side of the load capacitor.

16. A method for piezoelectric driving using the piezoelectric actuator circuit according to any one of claims 1 to 15, characterized in that, The method includes: The voltage selection unit selects the larger of the first input voltage and the second input voltage as the first output voltage. The first output voltage is coarsely adjusted to the second output voltage using an open-loop control unit via a voltage coarse adjustment unit; and The second output voltage is precisely adjusted using a low-voltage linear regulator through closed-loop control to obtain the third and fourth output voltages.

17. The method for piezoelectric actuation according to claim 16, characterized in that, The steps for precisely adjusting the second output voltage using a low-voltage linear regulator to obtain the third and fourth output voltages include: During the output voltage drop, the energy recovery module recovers the energy released by the load capacitor; and During the output voltage rise, the energy recovered by the energy recovery module is used to replenish the load capacitor.

18. The method for piezoelectric actuation according to claim 16, characterized in that, When the piezoelectric actuator circuit drives a heavy load, the load capacitor of the low-voltage linear regulator is in intermittent conduction mode; when the piezoelectric actuator circuit drives a light load, the load capacitor of the low-voltage linear regulator is in continuous conduction mode.

19. A computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, implement the method according to any one of claims 16 to 18.

20. An electronic device, comprising: One or more processors; A storage device for storing executable instructions, which, when executed by the processor, implement the method according to any one of claims 16 to 18.

Images