Level shifter for power converter

Abstract

The invention relates to a level shifter for a power converter. A level shifter for a power converter includes: a differential detector; a first transistor having a drain, a gate, and a source, the drain being electrically connected to the first node of the differential detector; a second transistor having a drain, a gate, and a source, the drain being electrically connected to the second node of the differential detector; and a circuit configured to simultaneously apply the same voltage to the sources of the first transistor and the second transistor based on the digital signal input to the level shifter. The circuit is further configured to apply different gate voltages as a function of the input digital signal to select which side of the level shifter draws current to the differential detector. The differential detector is configured to convert the digital signal to different voltage levels based on a differential current between the first transistor and the second transistor.

Description

Technical Field

[0001] This disclosure relates to a level shifter for use in a power converter. Background Technology

[0002] Power converters (such as half-bridge and full-bridge converters) typically employ bootstrap techniques, which involve bootstrapping capacitors to create a floating voltage domain to drive one or more high-side power switches of the power converter. In typical DC-DC buck converter applications, there exists a dead time between the active high-side and low-side power switches, during which all power switches are turned off. During this dead time, the output inductor forces current to flow, thus forcing the switching node of the power converter to a negative value. If silicon transistors are used to implement the power switches, the low-side power switch has a parasitic / body diode in place, and the negative voltage at the switching node is approximately -0.7V. If GaN transistors (or gallium nitride high electron mobility transistors - GaN HEMTs) are used to implement the low-side power switches, the low-side power switches do not have a body diode, but current can be conducted if the voltage between the drain and gate creates a channel. In this case, the switching node of the power converter is forced to a more negative voltage, such as in the range of -2V to -5V. Due to the presence of the bootstrap capacitor, the bootstrap node (which is the positive supply voltage of the high-side driver) follows the switching node of the power converter, dropping to a level close to ground. To exit dead-time mode, the input control of the high-side driver switches, sending the signal from the low-voltage input domain to the high-side domain via a level shifter, and ultimately switching the driver used for the high-side power switch. Since both the switching node of the power converter and the low-voltage input domain are close to 0V in this situation, there is insufficient headroom for the level shifter architecture to propagate the current signal.

[0003] Therefore, there is a need for a level shifter design with improved voltage headroom for power converter applications. Summary of the Invention

[0004] According to an embodiment of a level shifter, the level shifter includes: a differential detector; a first transistor having a gate, a source, and a drain electrically connected to a first node of the differential detector; a second transistor having a gate, a source, and a drain electrically connected to a second node of the differential detector; and circuitry configured to simultaneously apply the same voltage to the sources of the first and second transistors based on a digital signal input to the level shifter, wherein the differential detector is configured to convert the digital signal into different voltage levels based on a differential current between the first and second transistors.

[0005] According to another embodiment of the level shifter, the level shifter includes: a differential detector; a first transistor having a gate, a source, and a drain electrically connected to a first node of the differential detector; a second transistor having a gate, a source, and a drain electrically connected to a second node of the differential detector; a common capacitor having a first terminal and a second terminal; a first switching device electrically connected between a first DC power supply voltage or a local ground reference and the first terminal of the common capacitor; a second switching device electrically connected between the first terminal of the common capacitor and a ground or bootstrap node; and a third switching device electrically connected between the second terminal of the common capacitor and the ground or bootstrap node, wherein the second terminal of the common capacitor is electrically connected to the source of the first transistor and the second transistor.

[0006] According to an embodiment of a power converter, the power converter includes: a high-side power switching device; a gate driver configured to drive the gate of the high-side power switching device; and a level shifter. The level shifter includes: a differential detector; a first transistor having a gate, a source, and a drain electrically connected to a first node of the differential detector; a second transistor having a gate, a source, and a drain electrically connected to a second node of the differential detector; and circuitry configured to simultaneously apply the same voltage to the sources of the first and second transistors based on a digital signal input to the level shifter, wherein the differential detector is configured to shift the digital signal to the voltage domain of the gate driver based on a differential current between the first and second transistors.

[0007] Those skilled in the art will recognize the additional features and advantages after reading the following detailed description and reviewing the accompanying drawings. Attached Figure Description

[0008] The elements in the accompanying drawings are not necessarily proportional to each other. Similar reference numerals denote corresponding similar parts. Features of the various illustrated embodiments can be combined unless they are mutually exclusive. Embodiments are depicted in the accompanying drawings and are described in detail below.

[0009] Figure 1A The figure shows a circuit diagram of an up-level shifter according to an embodiment.

[0010] Figure 1B The diagram illustrates the on / off states of various switching devices included in the up-level shifter during operation, as well as the gate-source voltage (Vgs) of the high-voltage transistor included in the up-level shifter.

[0011] Figure 2 The figure shows a circuit diagram of an up-level shifter according to another embodiment.

[0012] Figure 3The figure shows a circuit diagram of an up-level shifter according to another embodiment.

[0013] Figure 4 The figure shows a circuit diagram of a low-level shifter according to an embodiment.

[0014] Figure 5 The illustration shows a circuit diagram of a common switching network included in an up-level shifter according to an embodiment.

[0015] Figure 6 The diagram illustrates the relationship between... Figure 5 Various waveforms associated with the operation of the up-level shifter.

[0016] Figure 7 The illustration shows a circuit diagram of a common switching network included in a lower-level shifter according to an embodiment.

[0017] Figure 8 The figure illustrates a circuit diagram of a switching device included in a gate potential switching network of a level shifter according to an embodiment.

[0018] Figure 9 An embodiment of a power converter is illustrated, which includes an up-level shifter or a down-level shifter as described herein. Detailed Implementation

[0019] The embodiments described herein provide level shifters with improved voltage headroom. Level shifters can be used in power converter applications (e.g., half-bridge and full-bridge converters). Level shifters use high-voltage transistors and differential circuitry to send digital information from a low-side domain to a high-side domain. The high-voltage transistors are controlled at their source terminals rather than their gate terminals. The gate terminals of the high-voltage transistors are connected to ground or a DC voltage, such as near ground. The same voltage is simultaneously applied to the sources of the high-voltage transistors, where the applied source voltage corresponds to a low or high level of the input digital signal. The gates of the high-voltage transistors are controlled separately to set different Vgs (gate-source voltages) for the two high-voltage devices.

[0020] For example, a shared capacitor and a shared switching network can be used to simultaneously apply the same voltage to the source of a high-voltage transistor. In response to a digital signal transition, the shared switching network can connect the shared capacitor to the source of the high-voltage transistor, such that a negative voltage is simultaneously applied to the transistor's source. After a transition in the digital signal, the shared switching network can then pre-charge the shared capacitor for the next transition in the digital signal. In another example, a shared diode can be part of a circuit that simultaneously applies the same voltage to the source of a high-voltage transistor. Using shared components (such as a shared capacitor and a shared switching network and / or a shared diode) to simultaneously apply the same voltage to the source of a high-voltage transistor reduces component count and size, shares high-voltage isolation, and eliminates the need for additional high-voltage devices.

[0021] Exemplary embodiments of a level shifter and a power converter using a level shifter are described below with reference to the accompanying drawings.

[0022] Figure 1A A circuit diagram of a level shifter 100 according to an embodiment is illustrated. The level shifter 100 includes: a differential detector 102; a first (high-voltage) transistor M1a having a drain D1a electrically connected to a first node nda of the differential detector 102; and a second (high-voltage) transistor M1b having a drain D1b electrically connected to a second node ndb of the differential detector 102. The gate G1a of the first transistor M1a is electrically connected to ground or a fixed DC voltage vb. The gate G1b of the second transistor M1b is also electrically connected to ground or a fixed DC voltage vb. The fixed DC voltage vb can be the same or different for the first transistor M1a and the second transistor M1b.

[0023] The level shifter 100 also includes circuitry 104 that, based on the digital signal pwm_i input to the level shifter 100, simultaneously applies the same voltage vdd_lv to the source S1a of the first transistor M1a and the source S1b of the second transistor M1b. A differential detector 102 converts the digital input signal pwm_i into different voltage levels pwm_o based on the differential current between the first transistor M1a and the second transistor M1b. The first transistor M1a and the second transistor M1b have short pull-down current pulses. The differential detector 102 detects this difference and generates a latched pulse that remains valid until the next cycle. This allows for rapid turn-off of the first transistor M1a (or the second transistor M1b), reducing power loss and relaxing reliability requirements for these transistors.

[0024] exist Figure 1AIn circuit 104, a common capacitor c1 and a common switching network s1-s3 are included. The capacitor c1 and the switching network s1-s3 are "shared" because the same capacitor c1 and the same switching network are used to apply the voltage vdd_lv to the source S1a of the first transistor M1a and the source S1b of the second transistor M1b. Based on the digital signal pwm_i input to the level shifter 100, Figure 1A The shared capacitor / switch network circuit configuration shown allows the same voltage vdd_lv to be applied simultaneously to the source S1a of the first transistor M1a and the source S1b of the second transistor M1b. Therefore, separate capacitors and separate switch networks are not required to adequately bias the sources S1a of the first transistor M1a and the source S1b of the second transistor M1b. Furthermore, switching devices s4a, s5a, s4b, and s5b determine which of the high-voltage transistors M1a and M1b will maintain Vgs equal to 0V, and which of the high-voltage transistors M1a and M1b will maintain a high Vgs to transmit a signal.

[0025] In response to a transition in the digital signal pwm_i input to the level shifter 100, the common switching network s1-s3 connects a common capacitor c1 to the sources of the first transistor and the second transistor, such that a negative voltage is simultaneously applied to the sources S1a of the first transistor M1a and S1b of the second transistor M1b. Simultaneously, the common switching network s1-s3 selects one of the gates G1a and G1b of the first transistor M1a and the second transistor M1b to be short-circuited to the common source (node ​​ns), while keeping the other gate G1b and G1a grounded, such that one of the high-voltage transistors M1a and M1b has Vgs = 0V, and the other high-voltage transistor M1b and M1a has Vgs = 3V. After a transition in the digital input signal pwm_i, the common switching network s1-s3 pre-charges the common capacitor c1 for the next transition in the digital input signal pwm_i.

[0026] exist Figure 1A In the common switching network s1-s3, there are: a first switching device s1, electrically connected between a first DC power supply voltage or local ground reference vdd_lv and a first terminal 106 of a common capacitor c1; a second switching device s2, electrically connected between the first terminal 106 of the common capacitor c1 and a ground or bootstrap node HB; and a third switching device s3, electrically connected between the second terminal 108 of the common capacitor c1 and the ground or bootstrap node HB. The second terminal 108 of the common capacitor c1 is electrically connected to the source S1a of the first transistor M1a and the source S1b of the second transistor M1a.

[0027] The second switching device s2 turns on in response to a transition in the digital signal pwm_i input to the level shifter 100. When the second switching device s2 is on, the first switching device s1 and the third switching device s3 are both off. In this (first) state, the voltage across the common capacitor c1 is simultaneously applied to the source S1a of the first transistor M1a and the source S1b of the second transistor M1b. After a predetermined time from the transition of the digital input signal pwm_i, the second switching device s2 turns off. When the second switching device s2 is off, the first switching device s1 and the third switching device s3 are both on. In this (second) state, the common capacitor c1 is pre-charged to vdd_lv for the next transition in the digital input signal pwm_i.

[0028] exist Figure 1A In this context, level shifter 100 is an up-level shifter, meaning that level shifter 100 converts the digital signal pwm_i input to level shifter 100 into a higher voltage level. In the case of an up-level shifter, differential detector 102 is coupled between bootstrap node HB and first transistor M1a and second transistor M1b. First transistor M1a and second transistor M1b are NMOS (n-channel metal-oxide-semiconductor) devices coupled between differential detector 102 and ground, and differential detector 102 converts the digital input signal pwm_i into a higher voltage level based on the differential current between first transistor M1a and second transistor M1b.

[0029] Figure 1A The level shifter 100 is differential, where the operation of the left and right sides is complementary. Switches s1, s2, and s3 of the shared switch network s1-s3 are used to control node ns, which controls the current of the first transistor M1a and the second transistor M1b. Therefore, the same switch network s1-s3 controls the current on both sides of the level shifter 100.

[0030] In the non-switching state, the third switching device s3 is turned on, ensuring that node ns is connected to GND, and transistors M1a and M1b are turned off. During this state, the first switching device s1 is also turned on, charging the common capacitor c1 with a voltage difference of vdd_lv relative to GND. The second switching device s2 remains off in order to charge the common capacitor c1. Since transistors M1a and M1b are both off in this state, the differential detector 102 is latched to the last state level.

[0031] To lock the differential detector 102 to the first position, the left side of the level shifter 100 is used. To lock the differential detector 102 to the second position, the right side of the level shifter 100 is used. Since the same voltage is transmitted via... Figure 1AThe shared capacitor c1 and the shared switching network s1-s3 are simultaneously applied to the source S1a of the first transistor M1a and the source S1b of the second transistor M1b. Therefore, the level shifter 100 also includes a first switching network 110 and a second switching network 112. The first switching network 110 controls the potential at the gate G1a of the first transistor M1a, and the second switching network 112 controls the potential at the gate G1b of the second transistor M1b. The separate gate potential switching networks 110 and 112 enable the differential detector 102 to be latched to either position.

[0032] The first gate potential switching network 110 includes a first switching device s4a, which is electrically connected at node nga between ground and the gate G1a of the first transistor M1a. The first gate potential switching network 110 also includes a second switching device s5a, which is electrically connected between the gate G1a and source S1a of the first transistor M1a. Similarly, the second gate potential switching network 112 includes a third switching device s4b and a fourth switching device s5b. The third switching device s4b is electrically connected at node ngb between ground and the gate G1b of the second transistor M1b, and the fourth switching device s5b is electrically connected between the gate G1b and the source S1b of the second transistor M1b.

[0033] The first gate potential switching network 110 can be used to connect the gate G1a of the first transistor M1a to ground or near ground potential via closed-circuit switch s4a and open-circuit switch s5a, such that a voltage difference exists between the gate-source voltage (VGS) and drain-source voltage (VDS) of the first transistor M1a, which introduces current into the first (left) node nda of the differential detector 102. The second gate potential switching network 112 can be used to disconnect the gate G1b of the second transistor M1b from ground via open-circuit switch s4b and closed-circuit switch s5b, such that a small or no voltage difference exists between the gate-source voltage and drain-source voltage of the second transistor M1b, and therefore no current is introduced into the second (right) node ndb of the differential detector 102. Figure 1B The diagram illustrates the on / off states of switching devices s1, s2, s3 in the shared switching network s1-s3 and switching devices s4a, s5a, s4b, s5b in the gate potential switching network 110, 112 during the operation of the level shifter 100, as well as the Vgs of the first high-voltage transistor M1a and the second high-voltage transistor M1b.

[0034] Differential detector 102 detects current flowing on the left (from transistor M1a) and no current flowing on the right (from transistor M1b), and in response, switches the output pwm_o of level shifter 100 from low to high (or from high to low). The current flowing in the first transistor M1a is provided by a common capacitor c1, which may, for example, only conduct for a few nanoseconds (the conduction time needs to be slightly longer than the propagation delay of level shifter 100). After a predetermined time, the first gate potential switching network 110 disconnects the gate G1a of the first transistor M1a from ground via open-circuit switching devices s4a and s5a. Since there is no current difference between the first transistor M1a and the second transistor M1b in this state, the output of differential detector 102 is latched.

[0035] To latch the differential detector 102 to the opposite position, a second gate potential switching network 112 can be used to connect the gate G1b of the second transistor M1b to ground or near ground potential via closed-circuit switch s4b and open-circuit switch s5b, such that a voltage difference exists between the gate-source voltage and the drain-source voltage of the second transistor M1b, which introduces current into the second (right) node ndb of the differential detector 102. A first gate potential switching network 110 can be used to disconnect the gate G1a of the first transistor M1a from ground via open-circuit switch s4a and closed-circuit switch s5a, such that a small or no voltage difference exists between the gate-source voltage and the drain-source voltage of the first transistor M1a, and therefore no current is introduced into the first (left) node nda of the differential detector 102.

[0036] Differential detector 102 detects current flowing in the right side (from transistor M1b) and no current flowing in the left side (from transistor M1a), and in response, switches the output pwm_o of level shifter 100 from high to low (or from low to high). The current flowing in the second transistor M1b is provided by a common capacitor c1, which, as explained above, can be turned on for only a few nanoseconds (the on-time needs to be slightly longer than the propagation delay of level shifter 100). After a predetermined time, the second gate potential switching network 112 disconnects the gate G1b of the second transistor M1b from ground via open-circuit switching devices s4b and s5b. Since there is no current difference between the second transistor M1b and the first transistor M1a in this state, the output of differential detector 102 is latched again. The size of the common capacitor c1 should be designed to ensure a small discharge during the on-time of the corresponding high-voltage transistors M1a and M1b.

[0037] Figure 2 A circuit diagram of a level shifter 100 according to another embodiment is shown. Figure 2 The level shifter 100 in the middle is similar to Figure 1A The level shifter 100 in the middle. Figure 2 In this embodiment, the level shifter 100 further includes: a first additional switching device M2a, electrically connected between the source S1a of the first transistor M1a and the common capacitor c1; and a second additional switching device M2b, electrically connected between the source S1b of the second transistor M1b and the common capacitor c1. In this embodiment, the additional switching devices M2a and M2b are NMOS devices and may have a lower rated voltage than the first (main) transistor M1a and the second (main) transistor M1b. Furthermore, the second switching device s5a of the first gate potential switching network 110 and the second switching device s5b of the second gate potential switching network 112 are implemented as follows: Figure 2 The circuit consists of a pair of cross-coupled NMOS devices M3a and M3b. The drain D2a of the first additional switching device M2a is electrically connected to the source S1a of the first transistor M1a. The source S2a of the first additional switching device M2a is electrically connected to the common node ns of circuit 104, and the gate G2a of the first additional switching device M2a is electrically connected to node nga of the first gate potential switching network 110. The drain D2b of the second additional switching device M2b is electrically connected to the source S1b of the second transistor M1b. The source S2b of the second additional switching device M2b is electrically connected to the common node ns of circuit 104, and the gate G2b of the second additional switching device M2b is electrically connected to node ngb of the second gate potential switching network 112.

[0038] Figure 3 A diode-based embodiment of a level shifter 100 is illustrated. Figure 3 In the circuit 104 of the level shifter 100 with a shared capacitor c1, a shared diode d1 is included, and the shared switching network s1-s3 is omitted. The anode of the shared diode d1 is electrically connected to the source S2a of the first additional switching device M2a and the source S2b of the second additional switching device M2b. The cathode of the shared diode d1 is electrically connected to ground. The shared capacitor c1 has a first terminal 106 to which a negative pulse signal 'npulse' derived from the digital input signal pwm_i by the pulse generator 114 is applied. The second terminal 108 of the shared capacitor c1 is electrically connected to the source S2a of the first additional switching device M2a and the source S2b of the second additional switching device M2b, as well as the anode of the shared diode d1.

[0039] Figure 4 A circuit diagram of a level shifter 100 according to another embodiment is shown. Figure 4 The illustrated embodiments are similar to Figure 1A and Figure 2The example shown. In Figure 4 In this configuration, level shifter 100 is a down-level shifter, meaning that level shifter 100 converts the digital signal pwm_i input to level shifter 100 into a lower voltage level. In the down-level shifter configuration, differential detector 102 is coupled between ground and the first transistor M1a and the second transistor M1b. The first transistor M1a and the second transistor M1b are PMOS (p-channel metal-oxide-semiconductor) devices coupled between differential detector 102 and bootstrap node HB, and the additional switching devices M2a and M2b of gate potential switching networks 110 and 112 are also PMOS devices. The first switching device s1 of the common switching network s1-s3 is electrically connected between the first local ground reference vss_local and the first terminal 106 of the common capacitor c1. The second switching device s2 of the common switching network s1-s3 is electrically connected between the first terminal 106 of the common capacitor c1 and the bootstrap node HB. The third switching device S3 of the shared network S1-S3 is electrically connected between the second terminal 108 of the shared capacitor C1 and the bootstrap node HB. The differential detector 102 converts the digital input signal pwm_i into a lower voltage level based on the differential current between the first transistor M1a and the second transistor M1b.

[0040] Figure 5 An embodiment of the shared switch network s1-s3 for an up-level shifter embodiment is illustrated. Figure 5 In the common switching network s1-s3, the first switching device s1 includes a first PMOS transistor M12, which has: a positive pulse gate input G12, which is electrically connected to the first terminal 106 of the common capacitor c1 via an inverter INV2; a drain D12, which is electrically connected to the DC power supply voltage vdd_lv; and a source S12. Figure 5 The first switching device s1 further includes a first inverter 200 formed by a second PMOS transistor M14 and a first NMOS transistor M15. The first inverter 200 has a positive pulse input via inverter INV3, which is applied to the gate G14 of the second PMOS transistor M14 and the gate G15 of the first NMOS transistor M15. The drain D14 of the second PMOS transistor M14 is electrically coupled to the source S12 of the first PMOS transistor M12. The source S15 of the first NMOS transistor M15 is grounded.

[0041] Figure 5 The second switching device s2 of the shared switching network s1-s3 includes: a second NMOS transistor M10 having a grounded gate input G10; a source S10 electrically connected to the source S1 of the first transistor M1a and the second terminal 108 of the shared capacitor c1; and a drain D10. Figure 5The second switching device s2 also includes a third PMOS transistor M13, which has: a grounded gate input G13; a source S13 electrically connected to the output of the first inverter 200; and a drain D13 electrically connected to the drain D10 of the second NMOS transistor M10.

[0042] Figure 5 The third switching device s3 of the shared switching network s1-s3 includes: a third NMOS transistor M11 having: a gate G11 electrically connected to the drain D13 of the third PMOS transistor P13 and the drain D10 of the second NMOS transistor M10; a source S11 electrically connected to the source S1 of the first transistor M1; and a drain D11 electrically connected to ground.

[0043] Figure 6 The diagram illustrates the relationship between... Figure 5 Various waveforms associated with the operation of the implementation of the level shifter shown are illustrated. Pulse generator 114 generates a negative pulse output npulse based on the digital signal pwm_i input to level shifter 100. In a steady state, the negative pulse output of pulse generator 114 is fixed at logic 1 level, and node n11 is at the DC supply voltage vdd_lv to charge the common capacitor c1. The third NMOS transistor M11 of the third switching device s3 provides ground to the common node ns. The gate G11 of the third NMOS transistor M11 is coupled to node n13, which is at the DC supply voltage vdd_lv passed from node n12 via the third PMOS transistor M13 of the second switching device s2. The potential of node n12 is defined by the potentials of nodes n10 and n11 sensed by the inverter INV2 controlling node n14.

[0044] When a negative edge appears at the output of pulse generator 114, node n10 moves upward, causing node n12 to immediately move downward, and thus also moving node n13 downward to near the threshold voltage Vt above ground (until transistor M13 allows it). This causes the third NMOS transistor M11 of the third switching device s3 to be almost turned off. At this time, node n13 becomes high ohms, while the common node nS becomes undriven and is only defined by the charging state of the common capacitor c1 relative to node n11. Turning off transistor M11 before the common node ns moves prevents the common capacitor c1 from being unnecessarily discharged by transistor M11 during the movement of node ns below ground potential.

[0045] Due to the junction current on the first transistor M1a, the upward movement of node n10 also causes node n11 to slowly move downward. The shared capacitor c1 forces the shared node ns to follow the movement of node n11, but node ns moves downward from ground potential to a negative value. Once node ns reaches a threshold voltage Vt below ground, the second NMOS transistor M10 of the second switching device s2 begins to conduct and connects nodes ns1 and n13 together, forcing the third NMOS transistor M11 of the third switching device s3 to remain off throughout the transition.

[0046] In this state, the shared capacitor c1 transfers charge from node n11 to the source S1a of the first transistor M1a, which is held at ground potential by the inverter INV1. The charge on the shared capacitor c1 decays, causing the shared node ns to slowly move upwards towards ground potential. The charge transferred by the shared capacitor c1 is sufficient to be detected in the bootstrap node HB domain. Sufficient time is provided to the bootstrap node HB domain for reliable pulse detection, while simultaneously minimizing the pulse width as much as possible to reduce power consumption.

[0047] When the digital signal pwm_i input to level shifter 100 begins its rising edge, the pulse output npulse of pulse generator 114 terminates the negative pulse. Then node n10 moves down, causing node n11 to begin moving up. Node ns follows node n11 upwards, while the third NMOS transistor M11 of the third switching device s3 remains off (transistor M10 keeps node n13 connected to node ns1). When node n11 moves high enough, inverter INV2 detects this condition and moves node n14 down, causing node n12 to rise. Once the voltage of node n12 exceeds the threshold voltage Vt of the third PMOS transistor M13 of the second switching device s2, node n13 begins to follow node n12. This enables transistor M11, providing a path for the common capacitor c1 to recharge via inverter INV1 and transistor M11. The process returns to its initial position and is then ready to repeat.

[0048] Figure 7 The diagram illustrates the relationship between... Figure 5 The same circuit, but implemented as a down-level shifter. Figure 7In this circuit, pulse generator 114 generates a positive pulse output 'ppulse' based on the digital signal pwm_i input to level shifter 100. Similarly, the first switching device s1 of the shared switching network s1-s3 includes a first NMOS transistor M21 having: a negative pulse gate input G21 electrically connected to a first terminal 106 of a shared capacitor c1 via inverter INV21; a source S21 electrically connected to a first local ground reference vssf; and a drain D21. The first switching device s1 also includes a first inverter 500 formed by a second NMOS transistor M25 and a first PMOS transistor M26. The first inverter 500 has a negative pulse input via inverter INV23, which is applied to the gate G25 of the second NMOS transistor M25 and the gate G25 of the first PMOS transistor M26. The source S25 of the second NMOS transistor M25 is electrically coupled to the drain D21 of the first NMOS transistor M21. The drain D26 of the first PMOS transistor M26 is electrically connected to the bootstrap node HB.

[0049] Figure 5 The second switching device s2 of the shared switching network s1-s3 includes a second PMOS transistor M24, which has: a gate G24 electrically connected to the bootstrap node HB; a source S24 electrically connected to the second terminal 108 of the shared capacitor c1; and a drain D24. Figure 5 The second switching device s2 also includes a third NMOS transistor M22, which has: a gate G22 electrically connected to the bootstrap node HB; a source S22 electrically connected to the output of the first inverter 500; and a drain D22 electrically connected to the drain D24 of the second PMOS transistor M24.

[0050] Figure 5 The third switching device s3 of the shared switching network s1-s3 includes a third PMOS transistor M23, which has: a gate G23 electrically connected to the drain D22 of the third NMOS transistor M22 and the drain D24 of the second PMOS transistor M24; a source S23 electrically connected to the second terminal 108 of the shared capacitor c1; and a drain D23 electrically connected to the bootstrap node HB.

[0051] Figure 8 An embodiment of the first switching devices s4a, 24b included in the gate potential switching networks 110, 112 of the level shifter 100 is illustrated. Figure 8In each gate potential switching network 110, 112, the first switching devices s4a, 24b include a first NMOS transistor M8, which has a body diode BD8, a grounded gate G8, a drain D8 electrically connected to the corresponding gate node nga / ngb, and a source S8. The two first switching devices s4a, 24b also include a second NMOS transistor M7, which has: a body diode BD7; a gate G7 electrically connected to the source S8 of the first NMOS transistor M8 at node n1; a drain D8 electrically connected to the corresponding gate node nga / ngb; and a grounded source S7. The two first switching devices s4a, 24b also include a first PMOS transistor M6, which has: a body diode M6; a grounded gate G6; a drain D6 electrically connected to the control input ctrl_i; and a source S6 electrically connected to the source S8 of the first NMOS transistor M8 and the gate G7 of the second NMOS transistor M7 at node n1. The control input ctrl_i determines whether the first switching devices s4a and 24b are turned on or off. The control input ctrl_i for the first switching devices s4a and 24b is complementary, ensuring that either the left or right side of the level shifter 100 is always active, as explained earlier in conjunction with the latching function of the differential detector 102.

[0052] Figure 9 An embodiment of a power converter 300 (e.g., a half-bridge converter, a full-bridge converter, etc.) is illustrated, which includes the level shifter 100 described herein. The power converter 300 also includes a high-side power switching device MPHS and a (floating) gate driver 302 for driving the gate G_MPHS of the high-side power switching device MPHS. The level shifter 100 converts the digital signal HI input to the level shifter 100 into the voltage domain dr_hs of the high-side gate driver 302.

[0053] As explained herein, the level shifter 100 includes: a differential detector 102; a first transistor M1a having a gate G1a, a source S1a, and a drain D1a electrically connected to a first node nda of the differential detector 102; a second transistor M1b having a gate G1b, a source S1b, and a drain D1b electrically connected to a second node ndb of the differential detector 102; and a circuit 104 configured to simultaneously apply the same voltage to the source S1a of the first transistor M1a and the source S1b of the second transistor M1b based on a digital signal input pwm_i to the level shifter 100. The circuit 104 that simultaneously applies the same voltage to the source S1a of the first transistor M1a and the source S1b of the second transistor M1b of the level shifter 100 includes, for example: a common capacitor c1 having a first terminal 106 and a second terminal 10; a first switching device s1 electrically connected between a first DC power supply voltage vdd_lv or a local ground reference and the first terminal 106 of the common capacitor c1; a second switching device s2 electrically connected between the first terminal 106 of the common capacitor c1 and ground (in the case of an upper level shifter) or a bootstrap node HB (in the case of a lower level shifter); and a third switching device s3 electrically connected between the second terminal 108 of the common capacitor c1 and ground (in the case of an upper level shifter) or a bootstrap node HB (in the case of a lower level shifter). The second terminal 108 of the common capacitor c1 is electrically connected to the source S1a of the first transistor M1a and the source S1b of the second transistor M1b of the level shifter 100. The differential detector 102 converts the digital signal pwm_i to the voltage domain of the high-side gate driver 302 based on the differential current between the first transistor M1a and the second transistor M1b of the level shifter 100.

[0054] exist Figure 9 In this embodiment, power converter 300 has a buck converter topology. However, power converter 300 can have different types of power converter topologies (such as boost, buck-boost, etc.). In the case of a buck converter, power converter 300 also includes a low-side power switch device MPLS electrically connected to a high-side power switch device MPHS in a half-bridge configuration. More specifically, the drain D_MPLS of the low-side power switch device MPLS is electrically connected to the source S_MPHS of the high-side power switch device MPHS at the switching node SW, wherein the source S_MPLS of the low-side power switch device MPLS is electrically connected to a reference potential VSS (such as ground), and the drain S_MPHS of the high-side power switch device MPHS is electrically connected to a voltage source VIN. A gate driver 304 is provided for driving the gate G_MPLS of the low-side power switch device MPLS. In one embodiment, drivers 302 and 304 are GaN (gallium nitride) drivers.

[0055] Inductor L1 is electrically connected to the switching node SW between the low-side power switching device MPLS and the high-side power switching device MPHS. Bootstrap capacitor Cboot is electrically connected between the switching node SW and the bootstrap node HB, which provides the power supply voltage to the gate driver 302 for the high-side power switching device MPHS. The load powered by the power converter 300 is... Figure 9 The resistor Rload is illustrated in the diagram, which has a capacitor Cout that stabilizes the voltage Vout applied to the load Rload. The switching device "bootsw" recharges the bootstrap capacitor Cboot via a voltage source VCC for the high-side gate driver 302.

[0056] In the case of the up-level shifter, the differential detector 102 is coupled between the bootstrap node HB and the first transistor M1a and the second transistor M1b of the up-level shifter 100. The first transistor M1a and the second transistor M1b of the up-level shifter 100 are coupled between the differential detector 102 and ground, and the differential detector 102 converts the digital input signal HI into a higher voltage level based on the differential current between the first transistor M1a and the second transistor M1b of the up-level shifter 100.

[0057] In the case of the down-level shifter, the differential detector 102 is coupled between ground and the first transistor M1a and the second transistor M1b of the down-level shifter 100. The first transistor M1a and the second transistor M1b of the down-level shifter 100 are coupled between the differential detector 102 and the bootstrap node HB. The differential detector 102 converts the digital input signal HI to a lower voltage level based on the differential current between the first transistor M1a and the second transistor M1b of the down-level shifter 100.

[0058] like Figure 1A As shown, circuit 104, which simultaneously applies the same voltage to the source S1a of the first transistor M1a and the source S1b of the second transistor M1b of the level shifter 100, may include a common (shared) capacitor c1 and a common (shared) switching network s1-s3. In response to a first transition in the digital input signal HI for the high-side gate driver 302, the first gate potential switching network 110 of the level shifter activates the left-hand side of the level shifter 100, which includes the first transistor M1a. Since the common switching network s1-s3 and the common capacitor c1 simultaneously apply the same voltage to the source S1a of the first transistor M1a and the source S1b of the second transistor M1b, a negative voltage is applied to the source S1a of the first transistor M1a. After the first transition in the digital input signal HI for the high-side gate driver 302, the common switching network s1-s3 precharges the common capacitor c1 for the next (second) transition in the digital input signal HI.

[0059] In response to a second transition in the digital input signal HI of the high-side gate driver 302, which is opposite to the first transition, the second gate potential switching network 112 of the level shifter activates the right-hand side of the level shifter 100, which includes the second transistor M1b. As described above, the common switching networks s1-s3 and the common capacitor c1 apply the same voltage simultaneously to the source S1a of the first transistor M1a and the source S1b of the second transistor M1b. Therefore, in response to the second transition in the digital input signal HI for the high-side gate driver 302, a negative voltage is applied to the source S1b of the second transistor M1b. After the second transition in the digital input signal HI for the high-side gate driver 302, the common switching networks s1-s3 precharge the common capacitor c1 in the next (first) transition in the digital input signal HI. This allows the differential detector 102 to transition the digital input signal HI for the high-side gate driver 302 to a different voltage level (pwm_o) based on the differential current between the first transistor M1a and the second transistor M1b of the level shifter 100. For down-level shifting, level shifter 100 can be used for both high-side control and level shifting from the VIN domain to the low side. That is, level shifter 100 can be connected to the input of the low-side gate driver 304.

[0060] Although this disclosure is not limited thereto, the following numbered examples illustrate one or more aspects of this disclosure.

[0061] Example 1. A level shifter comprising: a differential detector; a first transistor having a gate, a source, and a drain electrically connected to a first node of the differential detector; a second transistor having a gate, a source, and a drain electrically connected to a second node of the differential detector; and circuitry configured to simultaneously apply the same voltage to the sources of the first transistor and the second transistor based on a digital signal input to the level shifter, wherein the differential detector is configured to convert the digital signal into different voltage levels based on a differential current between the first transistor and the second transistor.

[0062] Example 2. A level shifter according to Example 1, wherein the circuit includes a common capacitor and a common switching network, wherein in response to a transition in the digital signal, the common switching network is configured to connect the common capacitor to the source of a first transistor and the source of a second transistor such that a negative voltage is simultaneously applied to the source of the first transistor and the source of the second transistor, wherein after a transition in the digital signal, the common switching network is configured to precharge the common capacitor for the next transition in the digital signal.

[0063] Example 3. A level shifter according to Example 2, wherein the common switching network includes: a first switching device electrically connected between a first DC power supply voltage or local ground reference and a first terminal of a common capacitor; a second switching device electrically connected between the first terminal of the common capacitor and a ground or bootstrap node; and a third switching device electrically connected between the second terminal of the common capacitor and the ground or bootstrap node, wherein the second terminal of the common capacitor is electrically connected to the source of a first transistor and the source of a second transistor.

[0064] Example 4. A level shifter according to Example 3, wherein a second switching device is configured to turn on in response to a transition in a digital signal, and both a first and a third switching device are configured to turn off when the second switching device is turned on, wherein the second switching device is configured to turn off after a predetermined time from the transition in the digital signal, and both the first and the third switching devices are configured to turn on when the second switching device is turned off.

[0065] Example 5. A level shifter according to any of Examples 1 to 4, wherein a differential detector is coupled between a bootstrap node and a first transistor and a second transistor, wherein the first transistor and the second transistor are coupled between the differential detector and ground, and wherein the differential detector is configured to convert a digital signal to a higher voltage level based on the differential current between the first transistor and the second transistor.

[0066] Example 6. A level shifter according to any of Examples 1 to 4, wherein a differential detector is coupled between ground and a first transistor and a second transistor, wherein the first transistor and the second transistor are coupled between the differential detector and a bootstrap node, and wherein the differential detector is configured to convert a digital signal to a lower voltage level based on the differential current between the first transistor and the second transistor.

[0067] Example 7. A level shifter according to any one of Examples 1 to 6, further comprising: a first switching network configured to control the potential at the gate of a first transistor; and a second switching network configured to control the potential at the gate of a second transistor.

[0068] Example 8. A level shifter according to Example 7, wherein a first switching network includes a first switching device electrically connected between ground and the gate of a first transistor and a second switching device electrically connected between the gate and source of the first transistor, and wherein a second switching network includes a third switching device electrically connected between ground and the gate of a second transistor and a fourth switching device electrically connected between the gate and source of the second transistor.

[0069] Example 9. A level shifter according to any one of Examples 1 to 8, further comprising: a first switching device electrically connected between the source of a first transistor and a common capacitor of the circuit; a second switching device electrically connected between the source of a second transistor and the common capacitor; a first switching network configured to control the potential at the gate of the first switching device; and a second switching network configured to control the potential at the gate of the second switching device.

[0070] Example 10. A level shifter according to Example 9, wherein a common diode of the circuit has an anode and a cathode, the anode being electrically connected to the source of a first switching device and the source of a second switching device, the cathode being electrically connected to ground, wherein a common capacitor has a first terminal and a second terminal, a pulse signal derived from a digital signal being applied to the first terminal, and the second terminal being electrically connected to the source of the first switching device, the source of the second switching device, and the anode of the common diode.

[0071] Example 11. A level shifter comprising: a differential detector; a first transistor having a gate, a source, and a drain electrically connected to a first node of the differential detector; a second transistor having a gate, a source, and a drain electrically connected to a second node of the differential detector; a common capacitor having a first terminal and a second terminal; a first switching device electrically connected between a first DC power supply voltage or a local ground standard and the first terminal of the common capacitor; a second switching device electrically connected between the first terminal of the common capacitor and a ground or bootstrap node; and a third switching device electrically connected between the second terminal of the common capacitor and the ground or bootstrap node, wherein the second terminal of the common capacitor is electrically connected to the source of the first transistor and the source of the second transistor.

[0072] Example 12. A level shifter according to Example 11, wherein the first switching device comprises: a first PMOS transistor having a positive pulse gate input electrically connected to a first terminal of a common capacitor, a drain electrically connected to a first DC power supply voltage, and a source; and a first inverter formed by a second PMOS transistor and a first NMOS transistor, the first inverter having a positive pulse input, the drain of the second PMOS transistor being electrically coupled to the source of the first PMOS transistor, and the source of the first NMOS transistor being grounded, wherein the second switching device comprises: a second NMOS transistor having a grounded gate input, a source electrically connected to the source of the first transistor and a second terminal of the common capacitor, and a drain; and a third PMOS transistor having a grounded gate input, a source electrically connected to the output of the first inverter, and a drain electrically connected to the drain of the second NMOS transistor, wherein the third switching device comprises: a third NMOS transistor having a gate electrically connected to the drain of the third PMOS transistor and the drain of the second NMOS transistor, a source electrically connected to the source of the first transistor, and a drain electrically connected to ground.

[0073] Example 13. According to the level shifter of Example 11, the first switching device includes: a first NMOS transistor having a negative pulse gate input electrically connected to a first terminal of a common capacitor, a source electrically connected to a local ground reference, and a drain; and a first inverter formed by a second NMOS transistor and a first PMOS transistor, the first inverter having a negative pulse input, the source of the second NMOS transistor being electrically coupled to the drain of the first NMOS transistor, and the drain of the first PMOS transistor being electrically connected to a bootstrap node, wherein the second switching device includes: a second PMOS transistor having a gate electrically connected to the bootstrap node, a source electrically connected to a second terminal of the common capacitor, and a drain; and a third NMOS transistor having a gate electrically connected to the bootstrap node, a source electrically connected to the output of the first inverter, and a drain electrically connected to the drain of the second PMOS transistor, wherein the third switching device includes: a third PMOS transistor having a gate electrically connected to the drain of the third NMOS transistor and the drain of the second PMOS transistor, a source electrically connected to the second terminal of the common capacitor, and a drain electrically connected to the bootstrap node.

[0074] Example 14. A level shifter according to any one of Examples 11 to 13, further comprising: a first switching network configured to control the potential at the gate of a first transistor; and a second switching network configured to control the potential at the gate of a second transistor.

[0075] Example 15. A power converter includes: a high-side power switching device; a gate driver configured to drive the gate of the high-side power switching device; and a level shifter, wherein the level shifter includes: a differential detector; a first transistor having a gate, a source, and a drain electrically connected to a first node of the differential detector; a second transistor having a gate, a source, and a drain electrically connected to a second node of the differential detector; and circuitry configured to simultaneously apply the same voltage to the source of the first transistor and the source of the second transistor based on a digital signal input to the level shifter, wherein the differential detector is configured to shift the digital signal to the voltage domain of the gate driver based on a differential current between the first transistor and the second transistor.

[0076] Example 16. The power converter according to Example 15 further includes: a low-side power switching device electrically connected to a high-side power switching device in a half-bridge configuration; an inductor electrically connected to a switching node between the low-side power switching device and the high-side power switching device; and a capacitor electrically connected between the switching node and a bootstrap node, the bootstrap node providing a power supply voltage to a gate driver for use with the high-side power switching device.

[0077] Example 17. A power converter according to Example 16, wherein a differential detector is coupled between a bootstrap node and a first and second transistor of a level shifter, wherein the first and second transistors of the level shifter are coupled between the differential detector and ground, and wherein the differential detector is configured to convert a digital signal to a higher voltage level based on the differential current between the first and second transistors of the level shifter.

[0078] Example 18. A power converter according to Example 16, wherein a differential detector is coupled between ground and a first transistor and a second transistor of a level shifter, wherein the first transistor and the second transistor of the level shifter are coupled between the differential detector and a bootstrap node, and wherein the differential detector is configured to convert a digital signal to a lower voltage level based on the differential current between the first transistor and the second transistor of the level shifter.

[0079] Example 19. A power converter according to any one of Examples 15 to 18, wherein the circuitry of the level shifter includes a common capacitor and a common switching network, wherein in response to a transition in the digital signal, the common switching network is configured to connect the common capacitor to the source of a first transistor and the source of a second transistor such that a negative voltage is simultaneously applied to the source of the first transistor and the source of the second transistor, wherein after a transition in the digital signal, the common switching network is configured to precharge the common capacitor for the next transition in the digital signal.

[0080] Example 20. A power converter according to Example 19, wherein the common switching network of the level shifter includes: a first switching device electrically connected between a first DC power supply voltage or local ground reference and a first terminal of a common capacitor; a second switching device electrically connected between the first terminal of the common capacitor and a ground or bootstrap node; and a third switching device electrically connected between a second terminal of the common capacitor and a ground or bootstrap node, wherein the second terminal of the common capacitor is electrically connected to the source of a first transistor and the source of a second transistor.

[0081] Terms such as "first" and "second" are used to describe various elements, regions, sections, etc., and are not intended to be limiting. Throughout the specification, the same term refers to the same element.

[0082] As used herein, the terms “having,” “containing,” “including,” “comprising,” etc., are open-ended terms that indicate the presence of the stated element or feature but do not exclude additional elements or features. The articles “a,” “an,” and “the” are intended to include both plural and singular forms unless the context clearly indicates otherwise.

[0083] The expression "and / or" should be interpreted to include all possible combinations and separations unless otherwise expressly stated. For example, the expression "A and / or B" should be interpreted to mean only A, only B, or both A and B. The expression "at least one of" should be interpreted in the same way as "and / or" unless otherwise expressly stated. For example, the expression "at least one of A and B" should be interpreted to mean only A, only B, or both A and B.

[0084] It should be understood that the features of the various embodiments described herein can be combined with each other unless otherwise specifically indicated.

[0085] Although specific embodiments are illustrated and described herein, those skilled in the art will understand that various substitutions and / or equivalent implementations can be made to the specific embodiments shown and described without departing from the scope of the invention. This application is intended to cover any modifications or variations of the specific embodiments discussed herein. Therefore, the invention is intended to be defined only by the claims and their equivalents.

Claims

1. A level shifter, comprising: Differential detector; The first transistor has a gate, a source, and a drain that is electrically connected to a first node of the differential detector; The second transistor has a gate, a source, and a drain that is electrically connected to a second node of the differential detector; as well as The circuit is configured to simultaneously apply the same voltage to the sources of the first transistor and the second transistor based on the digital signal input to the level shifter. The differential detector is configured to convert the digital signal into different voltage levels based on the differential current between the first transistor and the second transistor.

2. The level shifter according to claim 1, The circuit described includes a common capacitor and a common switching network. In response to a transition in the digital signal, the common switching network is configured to connect the common capacitor to the source of the first transistor and the source of the second transistor, such that a negative voltage is simultaneously applied to the source of both the first transistor and the source of the second transistor. Following the transition in the digital signal, the shared switching network is configured to precharge the shared capacitor for the next transition in the digital signal.

3. The level shifter according to claim 2, The shared switch network includes: A first switching device is electrically connected between a first DC power supply voltage or a local ground reference and a first terminal of the common capacitor; A second switching device is electrically connected between the first terminal of the common capacitor and the ground or bootstrap node; as well as A third switching device is electrically connected between the second terminal of the common capacitor and ground or the bootstrap node; The second terminal of the common capacitor is electrically connected to the source of the first transistor and the source of the second transistor.

4. The level shifter according to claim 3, in, The second switching device is configured to turn on in response to the transition in the digital signal, and both the first and third switching devices are configured to turn off when the second switching device is turned on. The second switching device is configured to turn off after a predetermined time following the transition in the digital signal, and both the first and third switching devices are configured to turn on when the second switching device is turned off.

5. The level shifter of claim 1, wherein the differential detector is coupled between the bootstrap node and the first transistor and the second transistor, wherein the first transistor and the second transistor are coupled between the differential detector and ground, and wherein the differential detector is configured to convert the digital signal to a higher voltage level based on the differential current between the first transistor and the second transistor.

6. The level shifter of claim 1, wherein the differential detector is coupled between ground and the first transistor and the second transistor, wherein the first transistor and the second transistor are coupled between the differential detector and the bootstrap node, and wherein the differential detector is configured to convert the digital signal to a lower voltage level based on the differential current between the first transistor and the second transistor.

7. The level shifter according to claim 1, further comprising: A first switching network is configured to control the potential at the gate of the first transistor; as well as A second switching network is configured to control the potential at the gate of the second transistor.

8. The level shifter according to claim 7, in, The first switching network includes a first switching device and a second switching device. The first switching device is electrically connected between ground and the gate of the first transistor, and the second switching device is electrically connected between the gate and source of the first transistor. The second switching network includes a third switching device and a fourth switching device. The third switching device is electrically connected between ground and the gate of the second transistor, and the fourth switching device is electrically connected between the gate and the source of the second transistor.

9. The level shifter according to claim 1, further comprising: A first switching device is electrically connected between the source of the first transistor and a common capacitor of the circuit; A second switching device is electrically connected between the source of the second transistor and the common capacitor; A first switching network is configured to control the potential at the gate of the first switching device; as well as The second switching network is configured to control the potential at the gate of the second switching device.

10. The level shifter according to claim 9, in, The common diode in the circuit has an anode and a cathode, the anode being electrically connected to the source of the first switching device and the source of the second switching device, and the cathode being electrically connected to ground. The common capacitor has a first terminal and a second terminal. A pulse signal derived from the digital signal is applied to the first terminal, and the second terminal is electrically connected to the source of the first switching device, the source of the second switching device, and the anode of the common diode.

11. A level shifter, comprising: Differential detector; The first transistor has a gate, a source, and a drain that is electrically connected to a first node of the differential detector; The second transistor has a gate, a source, and a drain that is electrically connected to a second node of the differential detector; A common capacitor has a first terminal and a second terminal; A first switching device is electrically connected between a first DC power supply voltage or a local ground reference and the first terminal of the common capacitor; A second switching device is electrically connected between the first terminal of the common capacitor and the ground or bootstrap node; as well as A third switching device is electrically connected between the second terminal of the common capacitor and ground or the bootstrap node. The second terminal of the common capacitor is electrically connected to the source of the first transistor and the source of the second transistor.

12. The level shifter according to claim 11, The first switching device includes: The first PMOS transistor has a positive pulse gate input electrically connected to the first terminal of the common capacitor, a drain electrically connected to the first DC power supply voltage, and a source. as well as A first inverter is formed by a second PMOS transistor and a first NMOS transistor. The first inverter has a positive pulse input. The drain of the second PMOS transistor is electrically coupled to the source of the first PMOS transistor, and the source of the first NMOS transistor is grounded. The second switching device includes: The second NMOS transistor has a grounded gate input, a source electrically connected to the second terminal of the first transistor and the common capacitor, and a drain; and The third PMOS transistor has a grounded gate input, a source electrically connected to the output of the first inverter, and a drain electrically connected to the drain of the second NMOS transistor. The third switching device includes: The third NMOS transistor has a gate electrically connected to the drain of the third PMOS transistor and the drain of the second NMOS transistor, a source electrically connected to the source of the first transistor, and a drain electrically connected to ground.

13. The level shifter according to claim 11, The first switching device includes: A first NMOS transistor has a negative pulse gate input electrically connected to the first terminal of the common capacitor, a source electrically connected to a local ground reference, and a drain. as well as A first inverter, formed by a second NMOS transistor and a first PMOS transistor, has a negative pulse input. The source of the second NMOS transistor is electrically coupled to the drain of the first NMOS transistor, and the drain of the first PMOS transistor is electrically connected to a bootstrap node. The second switching device includes: The second PMOS transistor has a gate electrically connected to the bootstrap node, a source electrically connected to the second terminal of the common capacitor, and a drain; and The third NMOS transistor has a gate electrically connected to the bootstrap node, a source electrically connected to the output of the first inverter, and a drain electrically connected to the drain of the second PMOS transistor. The third switching device includes: The third PMOS transistor has a gate electrically connected to the drain of the third NMOS transistor and the drain of the second PMOS transistor, a source electrically connected to the second terminal of the common capacitor, and a drain electrically connected to the bootstrap node.

14. The level shifter according to claim 11, further comprising: A first switching network is configured to control the potential at the gate of the first transistor; as well as A second switching network is configured to control the potential at the gate of the second transistor.

15. A power converter, comprising: High-side power switching devices; A gate driver is configured to drive the gate of the high-side power switching device; as well as Level shifter, The level shifter mentioned above includes: Differential detector; The first transistor has a gate, a source, and a drain that is electrically connected to a first node of the differential detector; The second transistor has a gate, a source, and a drain electrically connected to a second node of the differential detector; and The circuit is configured to simultaneously apply the same voltage to the sources of the first transistor and the second transistor based on the digital signal input to the level shifter. The differential detector is configured to convert the digital signal to the voltage domain of the gate driver based on the differential current between the first transistor and the second transistor.

16. The power converter of claim 15, further comprising: The low-side power switching device is electrically connected to the high-side power switching device in a half-bridge configuration; An inductor is electrically connected to a switching node between the low-side power switching device and the high-side power switching device; as well as A capacitor is electrically connected between the switching node and the bootstrap node, the bootstrap node providing a power supply voltage to the gate driver for use with the high-side power switching device.

17. The power converter of claim 16, wherein the differential detector is coupled between the bootstrap node and the first and second transistors of the level shifter, wherein the first and second transistors of the level shifter are coupled between the differential detector and ground, and wherein the differential detector is configured to convert the digital signal to a higher voltage level based on the differential current between the first and second transistors of the level shifter.

18. The power converter of claim 16, wherein the differential detector is coupled between ground and the first transistor and the second transistor of the level shifter, wherein the first transistor and the second transistor of the level shifter are coupled between the differential detector and the bootstrap node, and wherein the differential detector is configured to convert the digital signal to a lower voltage level based on the differential current between the first transistor and the second transistor of the level shifter.

19. The power converter according to claim 15, The circuit of the level shifter includes a common capacitor and a common switching network. In response to a transition in the digital signal, the common switching network is configured to connect the common capacitor to the source of the first transistor and the source of the second transistor, such that a negative voltage is simultaneously applied to the source of both the first transistor and the source of the second transistor. in, Following the transition in the digital signal, the shared switching network is configured to precharge the shared capacitor for the next transition in the digital signal.

20. The power converter according to claim 19, The common switching network of the level shifter includes: A first switching device is electrically connected between a first DC power supply voltage or a local ground reference and a first terminal of the common capacitor; A second switching device is electrically connected between the first terminal of the common capacitor and the ground or bootstrap node; as well as A third switching device is electrically connected between the second terminal of the common capacitor and ground or the bootstrap node; The second terminal of the common capacitor is electrically connected to the source of the first transistor and the source of the second transistor.

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