Offset calibration method and system for SAR ADC with multi-comparator structure

Abstract

The invention provides an offset calibration method and system for a multi-comparator structure SAR ADC, and the method comprises the steps: sequentially carrying out the following calibration steps on each comparator according to a sequence from the highest comparator to the lowest comparator: obtaining the statistical information of a digital code outputted by the current comparator in the quantization process of the multi-comparator structure SAR ADC; judging the polarity of the offset voltage corresponding to the current comparator according to the statistical information of the digital code output by the current comparator; and adjusting the offset voltage of the current comparator according to the polarity of the offset voltage corresponding to the current comparator. According to the method, the defects that the quantization time is occupied and the conversion speed is limited in a traditional method are overcome, meanwhile, calibration is conducted in sequence from the highest comparator to the lowest comparator, it is ensured that high-order imbalance is corrected preferentially, interference of the high-order imbalance to low-order calibration is prevented, and therefore the accuracy of overall calibration of the SAR ADC of the multi-comparator structure is improved.

Description

Technical Field

[0001] This invention relates to the field of offset calibration technology for multi-comparator SAR ADCs, and specifically to an offset calibration method and system for multi-comparator SAR ADCs. Background Technology

[0002] Analog-to-digital converters (ADCs), as key devices connecting analog and digital signals, are widely used in communication, radar, medical electronics, and high-speed data acquisition systems. Successive approximation ADCs (SAR ADCs) have become one of the mainstream architectures for medium-to-high-speed, high-precision ADCs due to their simple structure, low power consumption, and ease of integration with advanced processes. To improve the conversion speed of SAR ADCs, researchers have proposed a multi-comparator structure SAR ADC, where each bit of quantization is generated in parallel by independent comparators. This structure significantly reduces the timing delays caused by comparator resets and logic feedback in traditional SAR ADCs, thereby greatly improving the conversion rate, especially suitable for high-speed, time-interleaved, and multi-channel applications.

[0003] However, due to process variations in integrated circuit manufacturing, offset voltage differences inevitably exist between comparators. These differences cause nonlinear distortion in the ADC during quantization, severely reducing the system's signal-to-noise ratio and effective bit depth, thus limiting the practical application of this structure in high-precision applications. To calibrate the comparator offset voltage, existing technologies typically employ a calibration phase inserted outside the quantization cycle. For example, after ADC conversion, the comparator input is shorted to the common-mode voltage, and then a comparison is performed to detect the offset polarity. The offset voltage is then adjusted analogally or digitally. While this method can improve the offset problem to some extent, its drawbacks are significant: calibration must be performed independently outside of normal quantization, encroaching on the ADC's effective sampling and conversion time, limiting the overall system throughput. Furthermore, the calibration phase requires additional control timing and switching circuitry, increasing system design complexity and potentially introducing additional noise and interference.

[0004] Therefore, there is currently a lack in the field of multi-comparator offset voltage calibration scheme that can achieve high efficiency, real-time, and low complexity without affecting the normal conversion speed of the ADC, so as to give full play to the comprehensive advantages of multi-comparator structure SAR ADC in terms of speed and accuracy.

[0005] Therefore, the existing technology still needs further development. Summary of the Invention

[0006] The purpose of this invention is to overcome the above-mentioned technical deficiencies and provide an offset calibration method and system for multi-comparator structure SAR ADCs to solve the problems existing in the prior art.

[0007] To achieve the above-mentioned technical objectives, according to a first aspect of the present invention, the present invention provides an offset calibration method for a multi-comparator SAR ADC, wherein the following calibration steps are performed sequentially on each comparator from the most significant bit comparator to the least significant bit comparator: S100. During the quantization process of the multi-comparator structure SAR ADC, obtain the statistical information of the digital code output by the current comparator. S200. Based on the statistical information of the digital code output by the current comparator, determine the polarity of the offset voltage corresponding to the current comparator. S300. Adjust the offset voltage of the current comparator according to the polarity of the offset voltage corresponding to the current comparator.

[0008] Specifically, the method for obtaining statistical information of the digital code output by the current comparator includes: The probability of the digital code output by each comparator as the first logic value is obtained by counting the digital codes output during multiple quantization cycles.

[0009] Specifically, the method for determining the polarity of the offset voltage corresponding to the current comparator based on the statistical information of the digital code output by the current comparator includes: Determine whether the probability of the current comparator output digital code being the first logic value is within a preset neighborhood of the first preset threshold, and determine whether the offset voltage of the current comparator needs to be adjusted based on the determination result; If it is necessary to adjust the offset voltage of the current comparator, it is determined whether the probability of the digital code output by the current comparator being the first logic value is greater than the first preset threshold, and the polarity of the offset voltage corresponding to the current comparator is determined based on the determination result.

[0010] Specifically, the method for determining whether the offset voltage corresponding to the current comparator needs to be adjusted based on the judgment result includes: If the probability of the digital code output by the current comparator being the first logic value is within a preset neighborhood of the first preset threshold, then there is no need to adjust the offset voltage corresponding to the current comparator. If the probability of the digital code output by the current comparator being the first logic value is not within the preset neighborhood of the first preset threshold, then the offset voltage corresponding to the current comparator needs to be adjusted.

[0011] Specifically, determining whether the probability of the current comparator output digital code being the first logic value is greater than a first preset threshold, and determining the polarity of the offset voltage corresponding to the current comparator based on the determination result, includes: If the probability of the digital code output by the current comparator being the first logic value is greater than the first preset threshold, then the polarity of the offset voltage corresponding to the current comparator is determined to be negative. If the probability of the digital code output by the current comparator being the first logic value is less than the first preset threshold, then the polarity of the offset voltage corresponding to the current comparator is determined to be positive.

[0012] Specifically, the first preset threshold is 0.5.

[0013] Specifically, the method for adjusting the offset voltage of the current comparator according to the polarity of the offset voltage corresponding to the current comparator includes: If the polarity of the offset voltage corresponding to the current comparator is positive, the offset voltage of the current comparator is reduced by a preset adjustment step. Then, the probability of the digital code output by the current comparator being the first logic value is obtained again, and the polarity of the offset voltage corresponding to the current comparator is determined based on the probability of occurrence. The offset voltage of the current comparator is then adjusted again until the probability of occurrence is within a preset neighborhood of the first preset threshold.

[0014] Specifically, the method for adjusting the offset voltage of the current comparator according to the polarity of the offset voltage corresponding to the current comparator further includes: If the polarity of the offset voltage corresponding to the current comparator is negative, the offset voltage of the current comparator is increased by a preset adjustment step. Then, the probability of the digital code output by the current comparator being the first logic value is obtained again, and the polarity of the offset voltage corresponding to the current comparator is determined based on the probability of occurrence. The offset voltage of the current comparator is then adjusted again until the probability of occurrence is within a preset neighborhood of the first preset threshold.

[0015] According to a second aspect of the present invention, an offset calibration system for a multi-comparator SAR ADC is provided, comprising: Acquisition module: used to acquire statistical information of the digital code output by each comparator in the order from the most significant bit comparator to the least significant bit comparator during the quantization process of a multi-comparator structure SAR ADC; Calibration module: used to determine the polarity of the offset voltage corresponding to the current comparator based on the statistical information of the digital code output by the current comparator; and used to adjust the offset voltage of the current comparator based on the polarity of the offset voltage corresponding to the current comparator.

[0016] Specifically, the calibration module includes a digital processing unit, which is used to perform statistical analysis on the digital code output by the current comparator through an accumulation and summation operation, and to determine the polarity of the current comparator's offset voltage through a comparison operation.

[0017] Beneficial effects: This invention provides an offset calibration method and system for multi-comparator SAR ADCs. Without interrupting the normal quantization process of the SAR ADC, it utilizes statistical information from the output digital code of each comparator to determine the polarity of its offset voltage in real time, and performs directional adjustment based on the polarity of the offset voltage. Since the statistical information required for calibration can be directly extracted from the normal quantization results, no additional dedicated calibration cycle is needed, avoiding the shortcomings of traditional methods that encroach on quantization time and limit conversion speed. Furthermore, by calibrating sequentially from the most significant bit comparator to the least significant bit comparator, it ensures that high-bit offsets are corrected first, preventing them from interfering with low-bit calibration, thereby improving the overall calibration accuracy and further enhancing the linearity and effective number of bits of the SAR ADC while maintaining its high-speed conversion advantage. It also supports real-time, adaptive background calibration during system operation, greatly enhancing the stability and practicality of the SAR ADC in dynamic environments. Attached Figure Description

[0018] Figure 1 This is a flowchart of an offset calibration method for a multi-comparator structure SAR ADC provided in a specific embodiment of the present invention; Figure 2 This is a schematic diagram of the system composition of the offset calibration system for a multi-comparator structure SAR ADC provided in a specific embodiment of the present invention. Figure 3 This is a schematic diagram of the main circuit of the multi-comparator structure SAR ADC provided in a specific embodiment of the present invention; Figure 4 This is a probability distribution diagram of the output code of the most significant bit comparator of the SAR ADC under different offset voltages provided in a specific embodiment of the present invention; Figure 5 This is a flowchart of the multi-comparator offset voltage calibration algorithm provided in a specific embodiment of the present invention; Figure 6 This is a circuit structure diagram of the SAR ADC provided in a specific embodiment of the present invention; Figure 7 This is a convergence diagram of the offset voltage calibration of each comparator provided in a specific embodiment of the present invention; Figure 8 This is a SAR ADC spectrum diagram before and after comparator offset voltage calibration provided in a specific embodiment of the present invention. Detailed Implementation

[0019] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Based on the embodiments in this application, other similar embodiments obtained by those skilled in the art without creative effort should all fall within the scope of protection of this application. Furthermore, directional terms mentioned in the following embodiments, such as "up," "down," "left," and "right," are only for reference to the directions in the accompanying drawings; therefore, the directional terms used are for illustrative purposes and not for limiting the invention.

[0020] The present invention will be further described below with reference to the accompanying drawings and preferred embodiments.

[0021] Example 1 Please see Figure 1 This embodiment provides an offset calibration method for a multi-comparator SAR ADC. The following calibration steps are performed on each comparator sequentially, from the most significant bit comparator to the least significant bit comparator: During the quantization process of the multi-comparator SAR ADC, statistical information of the digital code output by the current comparator is obtained; based on the statistical information of the digital code output by the current comparator, the polarity of the offset voltage corresponding to the current comparator is determined; and based on the polarity of the offset voltage corresponding to the current comparator, the offset voltage of the current comparator is adjusted.

[0022] Understandably, by statistically analyzing the probability distribution of each comparator's output code sequentially from the most significant bit comparator to the least significant bit comparator during the normal quantization process of a multi-comparator SAR ADC, the offset voltage polarity of each comparator can be determined in real time and accurately without interrupting signal conversion, and directional adjustments can be made accordingly. This scheme not only effectively eliminates the nonlinear error introduced by comparator offset mismatch, significantly improving the ADC's conversion accuracy and effective bit depth, but also maintains the ADC's original high-speed conversion characteristics because it eliminates the need for an independent calibration cycle. Furthermore, the closed-loop calibration mechanism based on digital statistics possesses good stability and adaptability, supporting real-time background calibration during operation, significantly enhancing the chip's reliability and practicality in complex application environments.

[0023] It should be further explained that the calibration algorithm circuit for the comparator offset voltage of the multi-comparator structure SAR ADC proposed in this embodiment mainly includes two parts: the main circuit module of the multi-comparator structure SAR ADC and the polarity detection module of the multi-comparator offset voltage. The main circuit module of the multi-comparator structure SAR ADC is as follows: Figure 3 As shown, its structure is an n-bit multi-comparator SAR ADC, whose main function is to convert continuous analog input signals into discrete digital signals.

[0024] Furthermore, in Figure 3 In the process, the sampling switch samples the differential input signals Vip and Vin, and transmits the sampled signals to the n-bit comparator array and DAC array for quantization. Specifically, the n-bit comparator array is responsible for comparing the sampled signals one by one. After sampling, the nth comparator is enabled and compares the input signals Vip-Vin. The comparison result is output to the SAR logic module, which outputs the quantization result dou[n]. dou[n] is fed back to the DAC array to control the DAC array to switch, increasing or decreasing the voltage at the comparator input. At the same time, the SAR logic also generates a control signal clk_en[n-1] to enable the (n-1)th comparator. The (n-1)th comparator compares the increased or decreased signal, and the comparison result is output to the SAR logic to generate the quantization result dou[n-1]. This process continues until the last comparator completes the comparison, and the SAR logic generates the quantization result dou[1]. Thus, the entire SAR ADC completes one quantization, and dou[n:1] is the output result of this quantization.

[0025] It should be noted that Vos[n:1] represents the offset voltage of each of the n-bit comparators. Due to process variations, the offset voltage of each comparator may be different, which can lead to serious nonlinearity problems in the SAR ADC during quantization.

[0026] See Figure 1 In this embodiment, the offset calibration method for a multi-comparator SAR ADC performs the following calibration steps sequentially on each comparator, from the most significant bit to the least significant bit: S100. During the quantization process of the multi-comparator structure SAR ADC, obtain the statistical information of the digital code output by the current comparator. Furthermore, the method for obtaining statistical information about the digital code output by the current comparator includes: The probability of the digital code output by each comparator as the first logic value is obtained by counting the digital codes output during multiple quantization cycles.

[0027] It should be noted that, in specific implementation, obtaining the statistical information of the digital code output by the current comparator is achieved through a probability statistical mechanism based on counting. The aforementioned first logic value refers to a predefined logic state, such as logic "1". In differential signal or inverting logic design, it can also be equivalently defined as logic "0". Multiple quantization cycles refer to multiple complete cycles of normal analog-to-digital conversion performed continuously by the SAR ADC. The number of cycles can be configured according to the requirements of calibration accuracy and speed. For example, the number of cycles N can be set through a programmable register (e.g., N=1024, 4096, etc.). In the actual circuit, the counting function can be implemented through a digital accumulator connected to each comparator output: at the end of each quantization cycle, if the digital code output by the comparator is equal to the first logic value, the accumulator is incremented by 1; otherwise, it remains unchanged. After accumulating a preset N quantization cycles, the final count value M of the accumulator is divided by the total number of cycles N, which gives the probability P of the digital code being the first logic value. M / N, the probability P, truly reflects the output code distribution deviation caused by the comparator's own offset voltage under the condition that the statistical characteristics of the input signal are known (such as the mean is zero), thus providing a reliable and quantitative basis for subsequent polarity determination.

[0028] S200. Based on the statistical information of the digital code output by the current comparator, determine the polarity of the offset voltage corresponding to the current comparator. In this embodiment, the method for determining the polarity of the offset voltage corresponding to the current comparator based on the statistical information of the digital code output by the current comparator includes: Determine whether the probability of the current comparator outputting the digital code being the first logic value is within a preset neighborhood of a first preset threshold. Based on the determination result, determine whether the offset voltage of the current comparator needs to be adjusted. If the probability of the current comparator outputting the digital code being the first logic value is within a preset neighborhood of a first preset threshold, then the offset voltage of the current comparator does not need to be adjusted. If the probability of the current comparator outputting the digital code being the first logic value is not within a preset neighborhood of a first preset threshold, then the offset voltage of the current comparator needs to be adjusted.

[0029] Preferably, in this embodiment, the first preset threshold is 0.5.

[0030] It should be noted that the core of the method for determining the polarity of the offset voltage corresponding to the current comparator lies in establishing a decision-making mechanism based on probability comparison. When the statistical mean of the input signal is zero and the comparator is ideally offset-free, its output digital code is 1, meaning the probability of the first logic value occurring should theoretically be 50%, or 0.5. Therefore, setting the first preset threshold to 0.5 is a theoretical benchmark value directly corresponding to this ideal statistical characteristic. The aforementioned preset neighborhood range refers to a tolerance interval set around the first preset threshold of 0.5, for example, 0.5 ± Δ, where Δ is a small value, such as 0.01, 0.02, etc. The reason for setting this preset neighborhood range is that, on the one hand, in actual circuits, due to factors such as noise and limited statistical samples, even if the offset voltage has been calibrated to near zero, its statistical probability may not be absolutely accurate and stable at 0.5. Allowing a small tolerance can prevent the system from endlessly oscillating and adjusting near the equilibrium point. On the other hand, the size of the preset neighborhood range can be flexibly configured according to the system's requirements for calibration accuracy and convergence speed, achieving a trade-off between accuracy and efficiency.

[0031] In practical implementation, the judgment process can be implemented by a digital comparison logic circuit. This circuit receives the current occurrence probability value P from the probability statistics module and compares it with the preset lower threshold (0.5-Δ) and upper threshold (0.5+Δ). If P falls within the range of [0.5-Δ, 0.5+Δ], it is determined that the comparator offset voltage is within an acceptable small range and no further adjustment is needed. The calibration process can be terminated or enter a maintenance state for this bit. If P falls outside the range of [0.5-Δ, 0.5+Δ], it is determined that there is a significant offset, and the calibration adjustment process needs to be initiated. The polarity (positive or negative) of the offset voltage is further determined based on whether P is greater than the upper threshold or less than the lower threshold. This design ensures the stability and robustness of the calibration process, enabling the system to efficiently and reliably identify comparators that truly need calibration and avoid unnecessary intervention in calibrated circuits.

[0032] Furthermore, if it is necessary to adjust the offset voltage of the current comparator, it is determined whether the probability of the digital code output by the current comparator being the first logic value is greater than a first preset threshold. Based on the determination result, the polarity of the offset voltage corresponding to the current comparator is determined. If the probability of the digital code output by the current comparator being the first logic value is greater than the first preset threshold, the polarity of the offset voltage corresponding to the current comparator is determined to be negative; if the probability of the digital code output by the current comparator being the first logic value is less than the first preset threshold, the polarity of the offset voltage corresponding to the current comparator is determined to be positive.

[0033] In one specific embodiment, taking the nth bit comparator as an example, see [link to example]. Figure 3If the mean of the input signal Vip-Vin is 0 over a period of time, and the offset voltage Vos[n] = 0, then the probabilities of the nth comparator's comparison result being 0 or 1 are respectively: P(dout[n]=0)=0.5, P(dout[n]=1)=0.5; When the offset voltage Vos[n] > 0, the probabilities of the nth comparator being 0 or 1 are respectively: P(dout[n]=0)>0.5, P(dout[n]=1)<0.5; When the offset voltage Vos[n] < 0, the probabilities of the nth comparator being 0 or 1 are as follows: P(dout[n]=0)<0.5, P(dout[n]=1)>0.5; The probability of the digital code dou[n] being 1 under different polarities and magnitudes of offset voltage was statistically analyzed using a MATLAB model. The results are as follows: Figure 4 As shown, Figure 4 The horizontal axis represents different offset voltages, which are expressed in units of the ADC's Least Significant Bit (LSB), ranging from -5 LSB to +5 LSB. Figure 4 The vertical axis represents the probability of the highest-order digit, dou[n], being 1. This section summarizes the results of 16384 quantizations. Figure 4 The results show that the actual situation conforms to the above theoretical analysis.

[0034] Based on the above analysis, the polarity of the comparator offset voltage can be determined by whether the probability of the output code being 0 or 1 is greater than or less than 50%. After obtaining the polarity of the offset voltage, the comparator is controlled by a register in the analog circuit to adjust the magnitude of its own offset voltage until the probability of detecting a digital code of 0 or 1 stabilizes at around 50%. That is, the probability of the current comparator outputting a digital code that is the first logic value stabilizes within the preset neighborhood of the first preset threshold. At this point, the comparator has completed the calibration of the offset voltage.

[0035] It is understandable that, since the comparison result of the (n-1)th comparator is affected by the comparison result of the nth comparator, the offset voltage of the (n-1)th comparator needs to be calibrated after the offset voltage of the nth comparator is calibrated, and so on, until the offset voltages of all comparators are calibrated. During calibration, a bit-by-bit sequence is adopted from the most significant bit comparator to the least significant bit comparator. This is determined by the working principle and signal path of the multi-comparator SAR ADC itself, and is crucial to ensuring the correctness and effectiveness of the calibration. The quantization process of the SAR ADC is a successive approximation decision sequence. Specifically, the output result of the most significant bit comparator is immediately fed back to the internal digital-to-analog converter (DAC) array. Based on this result, the DAC array increases or decreases the residual voltage input to subsequent comparators accordingly. This means that when the (n-1)th bit comparator performs its own comparison, the input voltage it faces is no longer the original sampled voltage, but the voltage modified by the decision result of the nth bit comparator. Therefore, the output code statistical characteristics of the (n-1)th bit comparator are simultaneously affected by its own offset voltage and the offset voltage of the nth bit comparator.

[0036] Furthermore, if the offset of the nth comparator is not calibrated, its error will systematically distort the input voltage environment of all subsequent lower-order comparators through the DAC feedback mechanism. In this case, if the (n-1)th comparator is calibrated directly, the output probability distribution statistically obtained by the calibration algorithm will reflect the mixed result of its own offset and the coupling effect of higher-order offset, rather than its true offset characteristics. The calibration adjustment based on this mixed signal will be erroneous and ineffective, and may even introduce new nonlinearities. Therefore, this embodiment first calibrates the highest-order comparator. At this time, its subsequent comparators have not yet been enabled or started calibration, and its output statistics are only affected by its own offset and the statistical characteristics of the input signal. Calibration can make its offset approach zero, thereby eliminating its systematic interference source to the subsequent signal chain. Then, the second-highest-order comparator is calibrated. After the highest-order comparator is calibrated, its offset is eliminated, and the DAC feedback operation is based on correct decisions. At this time, the input voltage environment of the second-highest-order comparator is no longer polluted by higher-order offset, and its output statistical probability can truly and independently reflect its own offset voltage, thereby allowing for accurate calibration. In this manner, each comparator is calibrated under the input condition that all its higher-order comparators have been calibrated. This ensures that each calibration operation is for the comparator's own independent offset parameter, ultimately resulting in the systematic elimination of the offset voltage of all comparators.

[0037] S300. Adjust the offset voltage of the current comparator according to the polarity of the offset voltage corresponding to the current comparator.

[0038] In this embodiment, the method for adjusting the offset voltage of the current comparator according to the polarity of the offset voltage corresponding to the current comparator specifically includes: If the polarity of the offset voltage corresponding to the current comparator is positive, the offset voltage of the current comparator is reduced by a preset adjustment step. Then, the probability of the digital code output by the current comparator being the first logic value is obtained again, and the polarity of the offset voltage corresponding to the current comparator is determined based on the probability of occurrence. The offset voltage of the current comparator is then adjusted again until the probability of occurrence is within a preset neighborhood of a first preset threshold. If the polarity of the offset voltage corresponding to the current comparator is negative, the offset voltage of the current comparator is increased by a preset adjustment step. Then, the probability of the digital code output by the current comparator being the first logic value is obtained again, and the polarity of the offset voltage corresponding to the current comparator is determined based on the probability of occurrence. The offset voltage of the current comparator is then adjusted again until the probability of occurrence is within a preset neighborhood of a first preset threshold.

[0039] It should be noted that in this embodiment, the offset voltage calibration is not completed in one step, but rather is a gradual approximation process based on probabilistic feedback to ensure the accuracy and stability of the adjustment. Specifically, the preset adjustment step refers to the minimum voltage change each time the offset voltage is adjusted, usually measured in units of the ADC's LSB or its fraction. The selection of this step value requires a trade-off between calibration speed and final accuracy. Too large a step may cause oscillations around the equilibrium point, making precise convergence difficult; too small a step will make the calibration process too slow. In actual circuits, this step value can be configured through a digital register and can be designed to be variable, for example, initially using a larger step for rapid approximation and later switching to a smaller step for fine adjustment.

[0040] Furthermore, adjustable offset calibration elements can typically be integrated within the comparator. For example, a binary weighted capacitor array controlled by switches can be connected to the comparator input, or a current source controlled by digital codes can be used. When the offset voltage needs to be increased or decreased, corresponding digital control codes are generated to control the switching state of the calibration elements, thereby changing the comparator's equivalent input offset voltage in discrete steps. After one voltage adjustment is completed, the next adjustment is not performed immediately. Instead, the system re-enters the statistical information acquisition stage, sampling and statistically analyzing the digital code output in the new state of the comparator N times to calculate the new probability P'. This process is repeated, forming a closed loop, until the newly calculated probability P' falls within a preset neighborhood centered at 0.5 and bounded by ±Δ. At this point, the offset voltage is considered to have been calibrated to an acceptable error range, and the iterative calibration cycle for that comparator terminates. The calibration process then continues for the next comparator. The entire calibration process requires no external intervention, achieving fully automated background calibration.

[0041] In one specific embodiment, see Figure 5 The calibration procedure for adjusting the comparator offset voltage described above is as follows: After calibration begins, the offset voltage of the nth comparator is calibrated first. The probability of the highest bit code dou[n] being 1 is calculated and denoted as Pn. It is then determined whether Pn is within the preset neighborhood of 0.5. If Pn exceeds the preset neighborhood of 0.5, it indicates that the current comparator has a serious nonlinearity problem during quantization. Then, the relationship between Pn and the first preset value 0.5 is determined. If Pn > 0.5, it means Vos[n] < 0, and the offset voltage of the nth comparator is negative, so its offset voltage needs to be increased. If Pn < 0.5, it means Vos[n] > 0, and the offset voltage of the nth comparator is positive, so its offset voltage needs to be decreased. Finally, it is determined whether Pn converges to around 0.5, that is, converges within the preset neighborhood of 0.5. If it converges, the calibration of the highest bit comparator offset voltage ends. If it does not converge, the above process is repeated until Pn converges within the preset neighborhood of 0.5. After the offset voltage of the nth comparator is calibrated, the offset voltage of the (n-1)th comparator is calibrated, and so on, until the offset voltage of the first comparator is calibrated. At this point, the offset voltage calibration of the entire comparator is complete.

[0042] It should be noted that the above-described process for detecting the polarity of the comparator offset voltage can be implemented in digital circuits through summation and comparison. The number of summations can be controlled by setting registers, balancing the overhead of the digital circuits with the accuracy of the calibration. Furthermore, this detection process does not require additional quantization time from the SAR ADC and places no additional design requirements on the SAR ADC timing logic, reducing the complexity of the analog circuits. Simultaneously, this detection process does not affect the normal quantization process of the ADC. Therefore, this comparator offset voltage detection algorithm can be performed in the foreground or in real-time in the background, greatly expanding its application scenarios.

[0043] See Figures 6 to 8 The working principle of this invention will be illustrated below with specific examples: The multi-comparator structure-based SAR ADC comparator offset voltage calibration method proposed in this embodiment is applied to a high-speed, medium-precision multi-channel time-interleaved SAR ADC chip. The sampling rate of a single-channel SAR ADC in this chip is 1 GSPS, and the quantization bit depth is 8 bits. The specific circuit structure of this ADC chip is as follows: Figure 6As shown, the circuit includes a multi-channel SARADC circuit, a multi-phase clock circuit, and a comparator offset voltage polarity detection module. Each channel of the SAR ADC sequentially quantizes the sampled input signal, and the quantization result is output to the digital circuit for processing. The comparator offset voltage polarity detection module sums and statistically analyzes each bit of the quantization result of each single-channel SAR ADC. By determining the probability distribution of 0 and 1 in each bit of the quantization result, the polarity of the comparator offset voltage for each bit is obtained. Based on the obtained offset voltage polarity, it is fed back to the SAR ADC circuit of each channel. Figure 6 The signal voscali[8:1] in the analog circuit is used to adjust the comparator offset voltage; A multi-phase clock circuit takes a high-frequency clock as input and outputs various phase clocks required for the operation of a multi-channel ADC. A MATLAB model is used for modeling, and the proposed comparator offset voltage calibration method is implemented. Taking the comparator offset voltage calibration result of a single-channel SAR ADC as an example, ... Figure 7 As shown, following the calibration sequence from the most significant bit comparator to the least significant bit comparator, the offset voltage of each comparator eventually converges to near 0, indicating that the multi-comparator offset voltage calibration method proposed in this embodiment can accurately determine the polarity of the comparator offset voltage and complete the calibration of the multi-comparator offset voltage. Based on the above MATLAB model, a sinusoidal signal at a certain frequency is input to the SAR ADC. FFT analysis is performed on the SAR ADC quantization results before and after comparator offset voltage calibration. The results are as follows: Figure 8 As shown, Figure 8 The left image shows the nonlinear effect of comparator offset voltage on the SAR ADC before calibration, while the right image shows the nonlinear effect of comparator offset voltage on the SAR ADC after calibration. It can be seen that the effective bit depth of the SAR ADC before calibration is only 6.26 bits due to the nonlinear effect caused by the comparator offset voltage, while the effective bit depth of the ENOB after calibration reaches 7.93 bits. This further illustrates that the multi-comparator structure SAR ADC offset voltage calibration method proposed in this embodiment can eliminate the nonlinearity of the SAR ADC caused by the multi-comparator offset voltage, thereby improving the performance of the SAR ADC.

[0044] It should be noted that this embodiment provides an offset calibration method for a multi-comparator SAR ADC. During the normal quantization process of the multi-comparator SAR ADC, the probability distribution of the output code of each comparator is statistically analyzed sequentially from the most significant bit comparator to the least significant bit comparator. Without interrupting the signal conversion, the method achieves real-time and accurate judgment and directional adjustment of the polarity of the offset voltage of each comparator, effectively eliminating the nonlinear error introduced by comparator mismatch, significantly improving the conversion accuracy and effective number of bits of the ADC. Furthermore, since no independent calibration cycle is required, the original high-speed conversion characteristics of the ADC are fully maintained. At the same time, the closed-loop calibration mechanism based on digital statistics has good stability and adaptability, supporting real-time background calibration during system operation, which significantly enhances the reliability and practicality of the chip in dynamic application environments.

[0045] Example 2 Please see Figure 2 This embodiment provides an offset calibration system for a multi-comparator SAR ADC, the system comprising: Acquisition module 100: used to acquire statistical information of the digital code output by each comparator in the order from the most significant bit comparator to the least significant bit comparator during the quantization process of a multi-comparator structure SAR ADC; Calibration module 200: used to determine the polarity of the offset voltage corresponding to the current comparator based on the statistical information of the digital code output by the current comparator; and used to adjust the offset voltage of the current comparator based on the polarity of the offset voltage corresponding to the current comparator.

[0046] In some preferred embodiments, the calibration module 200 includes a digital processing unit, which is used to perform statistical analysis on the digital code output by the current comparator through an accumulation and summation operation, and to determine the polarity of the current comparator's offset voltage through a comparison operation.

[0047] It should be further explained that, in this embodiment, the digital processing unit is used to implement statistical analysis and polarity determination of the offset voltage in the form of digital circuits. The digital processing unit mainly includes two functional parts, which are coordinated and controlled by an internal logic state machine: (1) Accumulation and summation operation unit: For the comparator currently being calibrated, the digital code stream output by it is received. At the end of each SAR ADC quantization cycle, the output code of the current comparator is latched and input into the accumulation and summation operation unit. If the output code is equal to the first logic value, such as "1", the accumulator count value is incremented by 1; otherwise, the count value remains unchanged. The accumulation process is controlled by a preset counter for N quantization cycles. After that, the count value M stored in the accumulator is the total number of times the first logic value appears in N cycles.

[0048] (2) Comparison operation unit: used to receive the cumulative result M (or the probability value P calculated by dividing M by N) from the accumulation and summation operation unit. It contains a digital comparison logic circuit, which compares M or P with a set of pre-stored digital thresholds. First, it determines whether the statistical result has met the calibration convergence condition. For example, it compares P with the upper and lower tolerance boundaries (0.5±Δ) of the first preset threshold 0.5. If it does not converge, it further compares P with the center value 0.5. If P>0.5, the decision unit outputs a logic signal indicating that the offset voltage is negative; if P<0.5, it outputs a logic signal indicating that the offset voltage is positive. These comparison operations are all completed by digital circuits, which are fast and have controllable accuracy.

[0049] The aforementioned digital processing unit only needs to obtain the comparator output data from the SAR logic and send the control signal for adjusting the direction to the analog comparator calibration circuit. The interface is clear and easy to integrate. This all-digital implementation ensures the stability and repeatability of the calibration process, while avoiding the introduction of any analog test signals or complex timing switching, thus achieving the design goal of uninterrupted quantization during the calibration process.

[0050] It should be noted that the above calibration module is configured to independently perform statistical analysis on the digital codes output by each comparator in the main circuit of the multi-comparator SAR ADC.

[0051] In a preferred embodiment, the offset calibration system for the multi-comparator SAR ADC in this embodiment is a time-interleaved ADC system, which includes multiple SAR ADC main circuit channels.

[0052] It should be noted that, in this preferred embodiment, the offset calibration system for the multi-comparator SAR ADC is specifically implemented as a time-interleaved analog-to-digital converter system. Its purpose is to significantly improve the overall sampling rate through parallel processing. Its core consists of multiple parallel SAR ADC channels, each of which is an independent multi-comparator SAR ADC main circuit, as described in Embodiment 1 above, including its own sampling switch, comparator array, DAC array, and SAR logic. These channels work in an interleaved manner, with a multi-phase clock circuit generating a set of clock signals with a fixed phase difference to drive the sampling and quantization timing of each channel. In this way, each channel takes turns sampling and converting the input analog signal, and finally the digital outputs of each channel are combined and synchronized in the digital domain, thereby achieving an effective sampling rate of M times based on the conversion rate of a single ADC core.

[0053] Furthermore, in the time interleaving system of this embodiment, the acquisition module and calibration module in the offset calibration system need to serve all channels. A specific implementation method for this can be: (1) Centralized processing: A shared digital calibration engine is connected to the digital output of each channel in sequence or time-division multiplexing via a multiplexer. It reads and processes the output code of each comparator in each channel. The calibration engine maintains an independent statistical counter and state machine for each comparator of each channel. (2) Distributed processing: Each ADC channel is equipped with a local digital processing unit, such as an accumulator, which is responsible for performing preliminary statistics on the comparator output of the channel. A central calibration control unit polls the statistical results of each local unit, performs the final probability calculation, polarity judgment and generates calibration control signals.

[0054] It is understandable that, regardless of which processing method is adopted, the core of the calibration module is to independently perform statistical analysis on each SAR ADC channel in the system and the digital code output by each bit of the comparator in each channel. The calibration module maintains an independent calibration state and adjustment parameters for each comparator. After determining the polarity of the offset voltage of each comparator based on the statistical results, the calibration module generates a corresponding digital control signal, such as the voscali[8:1] signal mentioned in Example 1. This control signal is fed back to the analog circuit part of the target channel. Usually, the offset voltage of the corresponding comparator is adjusted by controlling adjustable calibration elements, such as a calibration capacitor array or current source connected in parallel with the comparator input tube.

[0055] By adopting the above technical solution, the technical problems of inter-channel mismatch and intra-channel comparator mismatch caused by process deviation in multi-channel systems are solved. Moreover, the calibration process can be carried out in parallel with the normal operation of channel sampling without reducing the overall sampling rate of the system. The calibration of all channels can be performed in real time in the background, ensuring that the entire time-interleaved ADC system maintains an ultra-high sampling rate while obtaining high linearity dynamic performance.

[0056] It should be noted that this embodiment provides an offset calibration system for a multi-comparator SAR ADC, including an acquisition module 100 and a calibration module 200. Without interrupting the normal quantization timing of the ADC, it achieves independent, real-time detection and offset mismatch calibration of the offset voltage of each comparator. Employing fully digital circuitry for probability statistics and polarity determination, it effectively eliminates nonlinear errors caused by comparator mismatch, significantly improving conversion accuracy and the system's effective bit depth, while fully maintaining the original high-speed conversion characteristics of the ADC without requiring additional quantization time. Furthermore, the system has excellent scalability, adaptable to multi-channel time-interleaved ADC architectures, and allows for independent and parallel background calibration of each channel and comparator. This maintains the system's ultra-high sampling rate while ensuring overall dynamic performance and stability, greatly enhancing the reliability of data acquisition in complex application environments.

[0057] In a preferred embodiment, this application also provides an electronic device, the electronic device comprising: The computer device includes a memory and a processor, wherein the memory stores computer-readable instructions that, when executed by the processor, implement the offset calibration system for a multi-comparator SAR ADC. The computer device can be broadly categorized as a server, terminal, or any other electronic device with the necessary computing and / or processing capabilities. In one embodiment, the computer device may include a processor, memory, network interface, communication interface, etc., connected via a system bus. The processor of the computer device can be used to provide the necessary computing, processing, and / or control capabilities. The memory of the computer device may include a non-volatile storage medium and internal memory. The non-volatile storage medium may store an operating system, computer programs, etc. The internal memory can provide an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The network interface and communication interface of the computer device can be used to connect and communicate with external devices via a network. When the computer program is executed by the processor, it performs the steps of the method of the present invention.

[0058] This invention can be implemented as a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, causes the steps of the methods of embodiments of the invention to be performed. In one embodiment, the computer program is distributed across multiple network-coupled computer devices or processors, such that the computer program is stored, accessed, and executed in a distributed manner by one or more computer devices or processors. A single method step / operation, or two or more method steps / operations, may be executed by a single computer device or processor or by two or more computer devices or processors. One or more method steps / operations may be executed by one or more computer devices or processors, and one or more other method steps / operations may be executed by one or more other computer devices or processors. One or more computer devices or processors may execute a single method step / operation, or execute two or more method steps / operations.

[0059] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0060] The technical features described above can be combined arbitrarily. Although not all possible combinations of these technical features are described, any combination of these technical features should be considered to be covered by this specification, provided that such combination does not contain contradictions.

[0061] The specific embodiments of the present invention described above do not constitute a limitation on the scope of protection of the present invention. Any other corresponding changes and modifications made in accordance with the technical concept of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. An offset calibration method for a multi-comparator SAR ADC, characterized in that, Perform the following calibration steps on each comparator in sequence, from the most significant bit comparator to the least significant bit comparator: S100. During the quantization process of the multi-comparator structure SAR ADC, obtain the statistical information of the digital code output by the current comparator. S200. Based on the statistical information of the digital code output by the current comparator, determine the polarity of the offset voltage corresponding to the current comparator. S300. Adjust the offset voltage of the current comparator according to the polarity of the offset voltage corresponding to the current comparator.

2. The offset calibration method for a multi-comparator SAR ADC according to claim 1, characterized in that, The method for obtaining statistical information of the digital code output by the current comparator includes: The probability of the digital code output by each comparator as the first logic value is obtained by counting the digital codes output during multiple quantization cycles.

3. The offset calibration method for a multi-comparator SAR ADC according to claim 2, characterized in that, The method for determining the polarity of the offset voltage corresponding to the current comparator based on the statistical information of the digital code output by the current comparator includes: Determine whether the probability of the current comparator output digital code being the first logic value is within a preset neighborhood of the first preset threshold, and determine whether the offset voltage of the current comparator needs to be adjusted based on the determination result; If it is necessary to adjust the offset voltage of the current comparator, it is determined whether the probability of the digital code output by the current comparator being the first logic value is greater than the first preset threshold, and the polarity of the offset voltage corresponding to the current comparator is determined based on the determination result.

4. The offset calibration method for a multi-comparator SAR ADC according to claim 3, characterized in that, The method for determining whether the offset voltage of the current comparator needs to be adjusted based on the judgment result includes: If the probability of the digital code output by the current comparator being the first logic value is within a preset neighborhood of the first preset threshold, then there is no need to adjust the offset voltage corresponding to the current comparator. If the probability of the digital code output by the current comparator being the first logic value is not within the preset neighborhood of the first preset threshold, then the offset voltage corresponding to the current comparator needs to be adjusted.

5. The offset calibration method for a multi-comparator SAR ADC according to claim 3, characterized in that, The step of determining whether the probability of the digital code output by the current comparator being the first logic value is greater than a first preset threshold, and determining the polarity of the offset voltage corresponding to the current comparator based on the determination result, includes: If the probability of the digital code output by the current comparator being the first logic value is greater than the first preset threshold, then the polarity of the offset voltage corresponding to the current comparator is determined to be negative. If the probability of the digital code output by the current comparator being the first logic value is less than the first preset threshold, then the polarity of the offset voltage corresponding to the current comparator is determined to be positive.

6. The offset calibration method for a multi-comparator SAR ADC according to claim 3, characterized in that, The first preset threshold is 0.

5.

7. The offset calibration method for a multi-comparator SAR ADC according to claim 5, characterized in that, The method for adjusting the offset voltage of the current comparator according to the polarity of the offset voltage corresponding to the current comparator includes: If the polarity of the offset voltage corresponding to the current comparator is positive, the offset voltage of the current comparator is reduced by a preset adjustment step. Then, the probability of the digital code output by the current comparator being the first logic value is obtained again, and the polarity of the offset voltage corresponding to the current comparator is determined based on the probability of occurrence. The offset voltage of the current comparator is then adjusted again until the probability of occurrence is within a preset neighborhood of the first preset threshold.

8. The offset calibration method for a multi-comparator SAR ADC according to claim 7, characterized in that, The method for adjusting the offset voltage of the current comparator according to the polarity of the offset voltage corresponding to the current comparator further includes: If the polarity of the offset voltage corresponding to the current comparator is negative, the offset voltage of the current comparator is increased by a preset adjustment step. Then, the probability of the digital code output by the current comparator being the first logic value is obtained again, and the polarity of the offset voltage corresponding to the current comparator is determined based on the probability of occurrence. The offset voltage of the current comparator is then adjusted again until the probability of occurrence is within a preset neighborhood of the first preset threshold.

9. An offset calibration system for a multi-comparator SAR ADC, characterized in that, include: Acquisition module: used to acquire statistical information of the digital code output by each comparator in the order from the most significant bit comparator to the least significant bit comparator during the quantization process of a multi-comparator structure SAR ADC; Calibration module: used to determine the polarity of the offset voltage corresponding to the current comparator based on the statistical information of the digital code output by the current comparator; And for adjusting the offset voltage of the current comparator according to the polarity of the offset voltage corresponding to the current comparator.

10. The offset calibration system for a multi-comparator SAR ADC according to claim 9, characterized in that, The calibration module includes a digital processing unit, which is used to perform statistical analysis on the digital code output by the current comparator through an accumulation and summation operation, and to determine the polarity of the current comparator's offset voltage through a comparison operation.

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