Existing all-system intercommunication system based on covered wire remote transmission and application method

Abstract

The invention discloses an existing all-standard intercommunication system based on covered wire remote transmission and an application method, the system comprises an FPGA and analog front-end units matched with the FPGA, each analog front-end unit is provided with an independent covered wire, a power supply unit is composed of a DC / DC power supply chip and provides needed power supply voltage for the FPGA and the analog front-end units, a debugging module is also connected between the FPGA and the TDM; the SOC subsystem is configured to adopt an embedded kernel, and the embedded kernel is provided with a UART (Universal Asynchronous Receiver / Transmitter) serial port. The invention supports the covered wire remote transmission function of two paths of general TDM interfaces and supports the transmission capability of synchronous data.

Description

Technical Field

[0001] This invention relates to the field of communication technology. More specifically, this invention relates to an interoperability system and application method based on existing full-standard multi-line long-distance transmission. Background Technology

[0002] There are currently five types of multi-line remote transmission standards, which cannot establish links or interoperate with each other. Different transmission standards are used in different scenarios, and there are many related devices for multi-line remote transmission. The various multi-line remote transmission modules are not interchangeable or compatible. Currently, there is no technology that can establish links with all transmission standards and enable interoperability.

[0003] To adapt to more flexible and varied application scenarios, the multiplexed remote transmission module needs to establish links and interoperate with equipment of different transmission standards, be compatible with all transmission standards, and achieve interchangeability and universality between different devices. This invention proposes an effective solution to this problem. Summary of the Invention

[0004] One object of the present invention is to solve at least the above-mentioned problems and / or defects, and to provide at least the advantages described below.

[0005] To achieve these objectives and other advantages of the present invention, an interoperability system based on a multi-line long-distance transmission of existing full-standard systems is provided, comprising: an FPGA and analog front-end unit A and analog front-end unit B that cooperate with it, wherein each analog front-end unit is provided with an independent multi-line, and a power supply unit composed of DC / DC power chips provides the required power voltage to the FPGA and the analog front-end units respectively, wherein the FPGA is configured to include: Two sets of DFEs for processing the sampled signals are connected to the corresponding analog front-end units; The data processing unit is equipped with a framing and deframing unit, a digital front-end unit, and an interface unit. It connects to the TDM through the interface unit and to the user's network equipment through the TDM. A SOC subsystem that connects to the data processing unit to complete link establishment and status management; One of the analog front-end units is configured to include: Interface protection unit A is connected to the communication interface between the duplicated line A and BFX-A; And the interface protection unit B, which is connected to the BFX-B via communication between the multiplexed line B; A debugging module is also connected between the FPGA and the user's network equipment. The SOC subsystem is configured to use an embedded kernel, and the embedded kernel has a UART serial port.

[0006] Preferably, the analog front-end unit is configured to further include: Digital-to-analog converter (DAC) connected to DFE; The ADC is connected to the output of the DAC, and the ADC is also connected to the DFE. A hybrid circuit connected to interface protection unit A or interface protection unit B, and the hybrid circuit is connected to the ADC and DAC.

[0007] Preferably, the DC / DC power supply chip is configured as follows: The XC8222AIA connects to the built-in conversion module and FPGA; The SM4644EIPY has three channels connected to the FPGA and one channel connected to the analog front-end unit. One of the SM4644EIPY's connections to the analog front-end unit is split into two parts: one part is sent to the XC1965DHA and then output to the analog front-end unit; the other part is sequentially split into the XC1965DHA and XC5121DSA and finally output to the analog front-end unit.

[0008] Preferably, the FPGA is configured to further include: The configuration management unit is interconnected with the SOC subsystem via a UART interface; A status indication unit, which is interconnected with the SOC subsystem via indication I / O; The operation and maintenance unit is interconnected with the I2C / ETH and SOC subsystems; The data processing unit is interconnected with the SOC subsystem via the TDM interface unit.

[0009] Preferably, the process of completing BFX-A and BFX-B communication through an existing full-standard interoperability system based on multiplexed long-distance transmission is configured to include: Step 1: The FPGA receives the service data sent by BFX-A through the analog front-end unit A, and frames, encodes and modulates the received signal before sending it to the network device at the user end. Step two: The network equipment at the user end then performs digital-to-analog conversion, shaping and filtering, and signal amplification on the received signal through the FPGA, and then sends it to BFX-B through the analog front-end unit B; Step 3: Before BFX-A and BFX-B transmit and receive service data, the SOC subsystem of the existing full-standard interconnection system based on the multiplexed remote transmission manages the configuration parameters and the functional modules corresponding to the digital front-end multiplexing algorithm to switch the communication channels under SDSL and SHDSL technologies, and completes data communication or handshake link establishment through steps 1 to 2.

[0010] Preferably, the digital front-end unit of the FPGA is configured to include: The Encoder module contains an initialization symbol encoding mode for operations such as channel estimation and equalization of the line, a synchronization symbol encoding mode mainly used for periodic synchronization of the line, and a data symbol encoding mode for encoding bit stream data into data for transmission channels. The Decoder module includes an initialization symbol decoding mode for operations such as channel estimation and equalization of the line, and a data symbol decoding mode for decoding bit stream data into service data.

[0011] The present invention has at least the following beneficial effects: This invention supports the remote transmission function of two general-purpose TDM (Time Division Multiplexing) interfaces and the ability to transmit synchronous data; each remote transmission interface supports five standards and the rates supported by each standard; it has the ability to detect link faults; the management interface supports the transmission of standard control, configuration of rate control, master-slave control and other parameters and reporting of link status via serial port; and it has the ability to upgrade the service interface online without opening the box.

[0012] Other advantages, objectives and features of the present invention will become apparent in part from the following description, and in part from those skilled in the art through study and practice of the invention. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the principle of the existing full-system interconnection system based on the multiplexed long-distance transmission of the present invention. Figure 2 This is a block diagram of the analog front-end unit of the present invention.

[0014] Figure 3 This is a schematic diagram of the power supply principle of the power supply unit of the present invention.

[0015] Figure 4 This is a diagram of the FPGA software composition of the present invention; Figure 5 This is a functional block diagram of the data processing unit of the present invention; Figure 6 This is a schematic diagram of the hybrid circuit of the present invention; Figure 7 This is the constellation diagram of the present invention; Figure 8 This is the 8QAM constellation diagram of the present invention; Figure 9 This is the 32QAM constellation diagram of the present invention; Figure descriptions: 1. FPGA, 11. Configuration management unit, 12. Status indication unit, 13. Operation and maintenance unit, 2. Analog front-end unit, 21. DAC, 22. ADC, 23. Hybrid circuit, 3. Power supply unit, 4. DFE, 5. Data processing unit, 51. Framing and deframing unit, 52. Digital front-end unit, 53. Interface unit, 6. Debugging module. Detailed Implementation

[0016] The present invention will now be described in further detail with reference to the accompanying drawings, so that those skilled in the art can implement it based on the description. It should be understood that terms such as "having," "comprising," and "including" as used herein do not exclude the presence or addition of one or more other elements or combinations thereof. It should be noted that in the description of the present invention, the orientation or positional relationship indicated by terms is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present invention and simplifying the description; it does not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. In the description of the present invention, unless otherwise expressly specified and limited, terms such as "installed," "provided with," "sleeved / connected," and "connected," etc., should be interpreted broadly. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two elements. Those skilled in the art can understand the specific meaning of the above terms in the present invention based on the specific circumstances. Furthermore, in this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Moreover, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0017] Figure 1-9 This invention illustrates an interoperability system for existing full-standard remote transmission based on a multi-line, comprising: an FPGA 1 and analog front-end units A2 and B2 that cooperate with it, wherein each analog front-end unit 2 is provided with an independent multi-line; a power supply unit 3 is composed of DC / DC power chips, which provide the required power voltages to the FPGA 1 and the analog front-end units 2 respectively; the FPGA 1 is configured to include: Two sets of DFE4 for processing the sampled signals are connected to the corresponding analog front-end unit 2; The data processing unit 5 is equipped with a framing and deframing unit 51, a digital front-end unit 52, and an interface unit 53. It is connected to the TDM through the interface unit 53 and to the network equipment of the user terminal through the TDM. It connects to the data processing unit 5 to complete the link establishment and status management of the SOC subsystem; One of the analog front-end units 2 is configured to include: Interface protection unit A is connected to the communication interface between the duplicated line A and BFX-A; And the interface protection unit B, which is connected to the BFX-B via communication between the multiplexed line B; Among them, a debugging module 6 is also connected between FPGA1 and the network equipment at the user end; The SOC subsystem is configured to use an embedded kernel, and the embedded kernel has a UART serial port.

[0018] Working principle: Step 1: FPGA1 receives service data sent from BFX-A on the multiplexed line A through analog front-end unit A2, and the data processing unit 5 frames, encodes and modulates the received signal before sending it to the network device at the user end through interface unit 53. Step 2: The network device at the user end then performs digital-to-analog conversion, shaping and filtering, and signal amplification on the signal received from FPGA1 through the data processing unit 5 of FPGA1, and then sends it to BFX-B through the complex line B of the analog front-end unit B2. Step 3: Before BFX-A and BFX-B transmit and receive service data, the SOC subsystem of the existing full-standard interconnection system based on the multiplexed remote transmission manages the configuration parameters and the functional modules corresponding to the digital front-end multiplexing algorithm to switch the communication channel, and completes data communication or handshake link establishment through steps 1 to 2.

[0019] Among them, ① the multi-line software runs on the FPGA1 chip (FPGA is a programmable unit used to implement modulation and demodulation algorithms, framing and deframing, interface, system control and other functions of the interoperability system), using the VHD hardware description language, referring to "GJB 9432-2018 General Requirements for Software Development of Military Programmable Logic Devices", mainly to implement framing mapping, encoding and decoding, modulation and demodulation, line equalization and echo cancellation of SDSL and SHDSL technologies. The data processing unit 5 of each standard is different, and according to the standard configuration, it needs to handle different framing mapping, encoding and decoding, modulation and demodulation and other functions to achieve interoperability of links and services of all standards.

[0020] The UART serial port of the embedded kernel of the SOC subsystem serves as the configuration and management channel. The framing and deframing unit 51 performs mapping, encapsulation, positioning, multiplexing, and demultiplexing; in quasi-synchronous mode, it also performs bit stuffing / removal operations. The digital front-end unit 52 uses a constellation module to decode and encode data. The debugging module 6 is used for log generation and recording on FPGA1.

[0021] ②FPGA1 provides an interface unit 53 adapted to the network equipment of the user end. It can provide multiple TDM interfaces for synchronous data transmission, or a Serdes interface for asynchronous data packet transmission, which can be flexibly configured as needed.

[0022] ③ The power supply unit 3 consists of DC / DC power supply chips, which provide the required power supply voltages for FPGA1 and analog front-end unit 2, respectively.

[0023] ④ Interface protection unit A and interface protection unit B separate the data between BFX-A or BFX-B and the simulated front-end unit 2, preventing the current task from accessing other data without authorization. Simultaneously, they prevent abnormal access.

[0024] This invention supports the remote transmission function of two general-purpose TDM (Time Division Multiplexing) interfaces and the ability to transmit synchronous data; each remote transmission interface supports five standards and the rates supported by each standard; it has the ability to detect link faults; the management interface supports the transmission of standard control, configuration of rate control, master-slave control and other parameters and reporting of link status via serial port; and it has the ability to upgrade the service interface online without opening the box.

[0025] In the above scheme, the analog front-end unit 2 is configured to further include: The digital-to-analog converter DAC21 is connected to the DFE4; ADC22 is connected to the output of DAC21, and ADC22 is also connected to DFE4; Hybrid circuit 23 is connected to interface protection unit A or interface protection unit B, and hybrid circuit 23 is connected to ADC22 and DAC21.

[0026] Working principle: This invention includes two independent analog front-end units 21 and 22. Each AFE performs analog signal processing for one line of analog signal being transmitted over a complex line. Taking any one of them as an example: Transmitter section: DAC21 converts the data stream output from DFE4 into an analog signal suitable for transmission on the repeater line.

[0027] Receiver section: The ADC22 extracts the analog signal sent by the other end from the line and converts it into a digital signal that the DFE4 can process.

[0028] Hybrid circuit 23 provides low-pass filtering, transmit signal amplification, and two-wire / four-wire signal conversion for analog signals. Hybrid circuit 23 mainly consists of several basic analog circuits such as resistors, capacitors, inductors, and transformers. Its specific operation is illustrated below. Figure 6 The low-pass filter circuit (composed of three sets of parallel capacitors C9, C8, C10 and four sets of inductors L5, L6, L7, L8) processes the signal from the DAC and then transmits it to the transmitting signal amplification circuit (composed of multiple resistors R9, R10, R11, R2, R1 and two sets of diodes connected in parallel with the low-pass filter circuit, with R9 and R1 connected in parallel with the same diode, R10 and R2 connected in parallel with the same diode, and capacitor C7 connected in series between R11 and R2). The signal is then transmitted to the transmitting circuit. The signal amplification circuit transmits the signal to the two-wire / four-wire signal conversion circuit (composed of R6 and R7, and multiple parallel circuits are sent to the receiving operational amplifier circuit (connected in parallel with the transmitting signal amplification circuit and with multiple built-in resistors R8, R13, R4 and R6 in parallel, while R12, R5, R3 and R7 are connected in parallel, and the two sets of parallel circuits are connected in series through two sets of diodes), and then the receiving operational amplifier circuit transmits the signal to the ADC, or it is directly processed by the low-pass filter circuit and the transmitting signal amplification circuit and then sent to the interface protection unit.

[0029] Among them, the high-frequency clock of the data processing unit 5 module inside FPGA1 is also used to generate the sampling clock for ADC22 / DAC21.

[0030] In the above scheme, the DC / DC power supply chip is configured as follows: The XC8222AIA connects to the built-in conversion module and FPGA1. The SM4644EIPY has three channels connected to FPGA1 and one channel connected to analog front-end unit 2. One of the SM4644EIPY connected to analog front-end unit 2 is split into XC1965DHA and then output to analog front-end unit 2. The other part is split into XC1965DHA and XC5121DSA in sequence and finally output to analog front-end unit 2.

[0031] Working principle: The DC / DC unit adopts a mature and stable circuit design. The rear plug-in board is powered by a +12V power supply, which converts the voltage to power other circuits on the board. Specifically: The SM4644EIPY is a four-channel DC / DC step-down miniature module regulator capable of outputting 4A of current per output. The SM4644EIPY operates within an input voltage range of 4V to 14V and supports an output voltage range of 0.6V to 5.5V. Its operating temperature range is -55℃ to +125℃, meeting the requirements of FPGA1 and analog front-end unit 2.

[0032] The XC1965DHA is an ultra-low voltage linear regulator chip capable of outputting 3A, featuring stability, extremely low quiescent current, and low noise. Its operating temperature range is -40℃ to +125℃, meeting the requirements of Analog Front-End Unit 2.

[0033] The XC5121DSA is an ultra-low voltage linear regulator chip capable of outputting 1A, featuring stability and low noise. Its operating temperature range is -40℃ to +125℃, meeting the requirements of Analog Front-End Unit 2.

[0034] The XC8222AIA is a high-efficiency synchronous rectification buck power supply chip with an input voltage range of 4.5V to 36V and an output current of 3A. It features adjustable frequency, peak current protection, short-circuit protection, and thermal protection. The operating temperature range is -40℃ to +125℃, meeting the requirements of the built-in conversion module and FPGA1.

[0035] In the above scheme, FPGA1 is configured to further include: Configuration management unit 11, which is interconnected with the SOC subsystem via a UART interface; Status indication unit 12, which is interconnected with the SOC subsystem via indication I / O; Operation and maintenance unit 13, which is interconnected with the I2C / ETH and SOC subsystems; The data processing unit 5 is interconnected with the SOC subsystem via the TDM interface unit 53.

[0036] Working principle: The software used for duplicating the lines works in conjunction with the hardware to perform functions such as control and management of the duplicated modules, and processing of business data. Specifically: The configuration management unit 11 is mainly responsible for receiving configuration frames from the front board through the serial interface, parsing the frame information, extracting configuration information, and setting parameters such as module transmission mode, rate, master-slave configuration, etc.

[0037] The status indicator unit 12 mainly indicates the running status of the replicated link and detects the fault status information of the replicated link. When the replicated link has not established a link, the link indicator light flashes slowly. When the replicated link starts training, the link indicator light flashes quickly. When the replicated link data is synchronized, the link indicator light stays on.

[0038] The operation and maintenance unit 13 mainly implements online upgrade functions, while the data processing unit 5 implements digital signal processing functions.

[0039] In the above scheme, the digital front-end unit 52 of FPGA1 is configured to include: The Encoder module contains an initialization symbol encoding mode for operations such as channel estimation and equalization of the line, a synchronization symbol encoding mode mainly used for periodic synchronization of the line, and a data symbol encoding mode for encoding bit stream data into data for transmission channels. The Decoder module includes an initialization symbol decoding mode for operations such as channel estimation and equalization of the line, and a data symbol decoding mode for decoding bit stream data into service data.

[0040] Working principle: The digital front-end unit 52 module differs in the constellation mapping order and the data content it carries. The Encoder module is responsible for generating the encoding of symbols in these three modes: 1. Initialization Symbol Encoding Mode: Initialization symbols are mainly used for channel estimation, equalization and other operations of the line. It is a fixed 4QAM mapping method and known training symbols.

[0041] 2. Synchronization symbol encoding: Synchronization symbols are mainly used for the periodic synchronization of the line. They are fixed 4QAM mapping methods and known training symbols.

[0042] 3. Data symbol encoding: The module receives bit stream data from the upstream module and encodes it into data symbols for sending channel data, supporting 4QAM~128QAM constellation mapping.

[0043] Constellation points are represented by (X, Y), where X and Y must be located at odd integer positions such as ±1, ±3, ±5, etc. A constellation diagram is shown below. Figure 7 : Even-numbered point mapping: V=(vb-1vb-2…v1v0) X=(vb-1…v1),Y=(vb-2…v0) Using 4QAM as a sub-block, it is expanded in the four quadrants according to the rules of 4n+1, 4n+3, 4n, and 4n+2 to obtain a higher-order constellation diagram.

[0044] Odd point mapping: a)b=1 b)b=3 8QAM constellation chart as shown Figure 8 : c)b>3 X=(vb-1…v1),Y=(vb-2…v0) 32QAM constellation chart as shown Figure 9 ; Digital Front-End Unit Module 52: The difference lies in the constellation mapping order and the data content it carries. The Decoder module is responsible for decoding and generating symbols in these three modes. 1. Initialization Symbol Decoding Mode: The initialization symbol is mainly used for channel estimation, equalization and other operations of the line. It is a fixed 4QAM mapping method and a known training symbol. The decoding module mainly parses the SOC message in the initialization symbol.

[0045] 2. Data symbol decoding: The module receives bit stream data from the decoding module and decodes it into business data, supporting 4QAM~128QAM constellation mapping.

[0046] Although embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and embodiments. They can be applied to various fields suitable for the present invention. For those skilled in the art, other modifications can be easily made. Therefore, without departing from the general concept defined by the claims and their equivalents, the present invention is not limited to the specific details and illustrations shown and described herein.

Claims

1. An interoperability system based on existing full-standard multi-line long-distance transmission, comprising: The FPGA and its corresponding analog front-end units A and B, with each analog front-end unit having an independent power supply line, are configured to provide the required power voltages to the FPGA and the analog front-end units. The FPGA is configured to include: Two sets of DFEs for processing the sampled signals are connected to the corresponding analog front-end units; The data processing unit is equipped with a framing and deframing unit, a digital front-end unit, and an interface unit. It connects to the TDM through the interface unit and to the user's network equipment through the TDM. A SOC subsystem that connects to the data processing unit to complete link establishment and status management; One of the analog front-end units is configured to include: Interface protection unit A is connected to the communication interface between the duplicated line A and BFX-A; And the interface protection unit B, which is connected to the BFX-B via communication between the multiplexed line B; A debugging module is also connected between the FPGA and the user's network equipment. The SOC subsystem is configured to use an embedded kernel, and the embedded kernel has a UART serial port.

2. The interoperability system based on existing full-standard multi-line long-distance transmission as described in claim 1, characterized in that, One of the analog front-end units is configured to further include: Digital-to-analog converter (DAC) connected to DFE; The ADC is connected to the output of the DAC, and the ADC is also connected to the DFE. A hybrid circuit connected to interface protection unit A or interface protection unit B, and the hybrid circuit is connected to the ADC and DAC.

3. The interoperability system based on existing full-standard multi-line long-distance transmission as described in claim 1, characterized in that, The DC / DC power supply chip is configured as follows: The XC8222AIA connects to the built-in conversion module and FPGA; The SM4644EIPY has three channels connected to the FPGA and one channel connected to the analog front-end unit. One of the SM4644EIPY's connections to the analog front-end unit is split into two parts: one part is sent to the XC1965DHA and then output to the analog front-end unit; the other part is sequentially split into the XC1965DHA and XC5121DSA and finally output to the analog front-end unit.

4. The interoperability system based on existing full-standard multi-line long-distance transmission as described in claim 1, characterized in that, The FPGA is configured to further include: The configuration management unit is interconnected with the SOC subsystem via a UART interface; A status indication unit, which is interconnected with the SOC subsystem via indication I / O; The operation and maintenance unit is interconnected with the I2C / ETH and SOC subsystems; The data processing unit is interconnected with the SOC subsystem via the TDM interface unit.

5. A method for implementing an interoperability system based on existing full-standard multi-line long-distance transmission as described in claim 1, characterized in that, The process for completing BFX-A and BFX-B communication using an existing full-standard interoperability system based on dual-line long-distance transmission is configured to include: Step 1: The FPGA receives the service data sent by BFX-A through the analog front-end unit A, and frames, encodes and modulates the received signal before sending it to the network device at the user end. Step two: The network equipment at the user end then performs digital-to-analog conversion, shaping and filtering, and signal amplification on the received signal through the FPGA, and then sends it to BFX-B through the analog front-end unit B; Step 3: Before BFX-A and BFX-B transmit and receive service data, the SOC subsystem of the existing full-standard interconnection system based on the multiplexed remote transmission manages the configuration parameters and the functional modules corresponding to the digital front-end multiplexing algorithm to switch the communication channels under SDSL and SHDSL technologies, and completes data communication or handshake link establishment through steps 1 to 2.

6. The implementation method of the existing full-standard interoperability system based on multiplexed long-distance transmission as described in claim 5, characterized in that, The FPGA's digital front-end unit is configured to include: The Encoder module contains an initialization symbol encoding mode for operations such as channel estimation and equalization of the line, a synchronization symbol encoding mode mainly used for periodic synchronization of the line, and a data symbol encoding mode for encoding bit stream data into data for transmission channels. The Decoder module includes an initialization symbol decoding mode for operations such as channel estimation and equalization of the line, and a data symbol decoding mode for decoding bit stream data into service data.

Images