Parallel multi-network-port full-bandwidth testing method based on FPGA and CPU collaborative architecture

Abstract

The invention discloses a parallel multi-network-port full-bandwidth testing method based on an FPGA (Field Programmable Gate Array) and CPU (Central Processing Unit) collaborative architecture, which belongs to the field of network data communication and comprises the following steps of: configuring at least two paths of Ethernet hardware circuits which are externally connected to the FPGA, have the same structure and are mutually independent; for a CPU configured to be multi-core, each CPU core is configured with a physical network port linked with the FPGA, and each physical network port is externally connected with an Ethernet hardware circuit through the FPGA; and each CPU core continuously monitors the state flag of the receiving buffer area of the corresponding physical network port in a polling or interruption mode, verifies the data received by the single physical network port and generates a test report. According to the method, bandwidth performance verification and high-concurrency data flow processing capability evaluation of the multi-network-port equipment under the full-load working condition can be comprehensively covered, and fault tolerance and robustness tests on protocol layer abnormal scenes such as MAC address conflicts, IP address duplication and abnormal frame injection are supported.

Description

Technical Field

[0001] This invention relates to the field of network data communication, and specifically to a parallel multi-port full bandwidth testing method based on an FPGA and CPU collaborative architecture. Background Technology

[0002] With the application of artificial intelligence and big data technologies, higher requirements are being placed on network data transmission in fields such as communication infrastructure, industrial applications, military defense, and aerospace. In complex electronic equipment systems, there are a large number of Ethernet data interfaces, and the system network interfaces often operate at full load and full bandwidth in practical applications. Real-world application scenarios place higher demands on the reliability, stability, and security of devices with multiple network interfaces.

[0003] Current technologies typically extend network ports using switches (e.g., patent publication number: CN117435410A) or implement multi-port functionality through time-division multiplexing of a single network protocol stack (e.g., patent publication number: CN117221156A). This approach cannot perform simultaneous testing of multiple network interfaces in a system device; it can only perform time-division multiplexing testing of network interfaces through interface switching; or it can use an FPGA to connect multiple PHYs, ultimately squeezing data onto a single RGMII in a pseudo-parallel state (e.g., patent publication number: CN119966925A). Therefore, it is impossible to perform full-bandwidth testing of the system, multi-interface data concurrency testing, or stress testing of the system's IP addresses, MAC addresses, and other protocol layers. Summary of the Invention

[0004] The purpose of this invention is to simplify the complexity and reduce the cost of the test system by implementing multiple independent network port functions through embedded systems using the existing physical architecture of FPGA and CPU. This solves the problems that the test system cannot perform full bandwidth stress testing, multi-interface data concurrency testing, IP address and MAC address protocol layer stress testing, and fault tolerance testing on multi-network port devices.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] A parallel multi-port full bandwidth testing method based on an FPGA and CPU collaborative architecture includes:

[0007] In the FPGA-side logic architecture, an independent AXI-DMAI IP core is instantiated for each network port controller under test, and a unique AXI bus address space is allocated to each AXI-DMA IP core. Through the PCIe-AXI translation bridge, the unique AXI bus address space is mapped to an independent register window and data path that can be addressed by the CPU. This allows the CPU to transmit register configuration instructions and data read / write operations for any network port controller through the dedicated address space of that network port, thereby achieving physical address isolation of each network port at the FPGA logic level.

[0008] In the CPU operating environment, each network port under test is allocated independent transmit and receive buffers in DDR memory. The driver maps the physical address of the DDR buffer corresponding to each network port to an independent virtual memory space in user mode or kernel mode, and provides independent read and write interfaces bound to each virtual memory space for the upper-layer Ethernet protocol stack. This ensures that the data encapsulation and parsing operations of each network port are only executed in their respective allocated memory areas, thereby achieving logical data isolation of each network port at the CPU memory level.

[0009] Based on the independent address space on the FPGA side and the independent memory resource pool on the CPU side, the CPU monitors the status flags of the dedicated receive buffer of each network port through polling or interrupt mechanisms. When data transmission and reception are triggered, the CPU drives each network port controller to perform high-speed transmission and reception and verification of data packets in parallel on their respective independent data channels via the PCIe-AXI conversion bridge and the corresponding independent AXI bus address space. By maintaining the saturated load state of all independent data channels, parallel full-bandwidth stress testing in a multi-network port environment is achieved.

[0010] In the above technical solution, the CPU is connected to the FPGA via a PCIe interface. Within the FPGA,

[0011] Data received and sent from the PCIe interface is buffered using a FIFO.

[0012] Address mapping is performed through the PCIe-AXI protocol translation layer;

[0013] The FIFO is read and written by the AXI interface controller at the corresponding address, realizing the mutual conversion between PCIe signals and AXI signals.

[0014] In the above technical solution, data streams from different AXI interface controllers at the same time are accessed in parallel to the PCIe controller via the PCIe-AXI protocol conversion layer.

[0015] In the above technical solution, an AXI-DMAIP core is integrated into the FPGA-side logic. Without the CPU's involvement, the FPGA establishes a bidirectional data path between the FPGA and the CPU via the PCIe bus for high-speed batch data transfer between the FPGA's internal data and the CPU's main memory.

[0016] In the above technical solution, when the CPU needs to send large blocks of data to the FPGA:

[0017] Transfer parameters are written to the AXI-DMA control register in the FPGA via the PCIe configuration space or MMIO register.

[0018] AXI-DMA initiates PCIe memory read requests as the bus master, reads data from the CPU DDR, transmits it to the AXI bus via the PCIe-AXI conversion bridge, and delivers it to the FPGA user logic.

[0019] In the above technical solution, after the FPGA completes data processing, AXI-DMA reads the result data from the internal FIFO or BRAM and writes the data to the pre-allocated result buffer in the CPU DDR in the form of PCIe memory write transactions.

[0020] In the above technical solution, the CPU includes:

[0021] The PCIe driver module is used to complete the low-level initialization, link establishment and memory mapping configuration of the PCIe controller;

[0022] The CPU configures an independent DDR transmit buffer and receive buffer for each physical network port.

[0023] Ethernet protocol stack, using the IP protocol at the network layer and the UDP protocol at the transport layer to perform protocol layer stress tests;

[0024] Network port stress testing sequencing is used to achieve parallel and automated protocol layer stress testing of each network port.

[0025] In the above technical solution, the PCIe driver module includes:

[0026] Initialize, enable the clock and power domains of the PCIe root port controller, release the reset signal, configure it to Root Port operating mode, set the link rate, maximum payload size and maximum read request size, and enable the internal address translation unit.

[0027] Once the link is established, the driver polls the flag bits in the PCIe controller status register, waiting for the FPGA to power on and successfully complete the negotiation between the physical layer and the data link layer.

[0028] In memory mapping configuration, the driver utilizes the configuration transaction capabilities of the internal address translation unit to set up a dedicated address translation region, configure its address, and write it to the target address register.

[0029] In the above technical solution, the PCIe driver maps the DDR buffer address corresponding to each physical network port to the CPU-accessible memory space, so as to provide an independent read and write interface for the Ethernet protocol stack.

[0030] In the above technical solution, each CPU core independently runs a lightweight TCP / IP protocol stack instance and a corresponding test task thread. The test includes:

[0031] When valid data is detected, the local lwIP protocol stack is invoked to parse the received frame and extract the test payload data.

[0032] The integrity of the data is verified according to the preset verification rules, and the number of correct frames and the number of incorrect frames are counted respectively.

[0033] Once a single network port has received a specified number of test data packets, the CPU core automatically generates a test report containing metrics such as throughput, packet loss rate, and verification results, and then ends the current test task.

[0034] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0035] This invention effectively solves the technical bottlenecks in the prior art by adopting an embedded hardware architecture that coordinates FPGA and CPU, combined with a high-speed PCIe interconnect bus and multiple independent Ethernet physical interfaces. This allows for the implementation of full-bandwidth concurrent testing, synchronous stress loading of multiple interfaces, and fault tolerance verification of protocol layer functions (including IP address, MAC address, etc.) for multi-port devices.

[0036] This invention utilizes an FPGA to implement multiple completely independent network port hardware controllers. Each controller connects to a dedicated PHY chip via an RGMII / SGMII interface, thereby achieving electrical and logical isolation between the network ports at the physical and data link layers. Simultaneously, through a PCIe-AXI conversion bridge and an AXI-DMA mechanism, a high-throughput, low-CPU-overhead data path is constructed, enabling the CPU to run multiple lightweight protocol stack instances (such as lwIP) in parallel, and to perform independent IP layer and UDP / TCP layer configuration and stress testing on each network port.

[0037] Compared to traditional testing solutions that rely on external switches for expansion or single-protocol stack time-division multiplexing, this invention eliminates the need for complex external networking. It enables simultaneous full-bandwidth transmission and reception, independent protocol parameter configuration, and automated concurrent testing of dozens or even hundreds of network ports on a single embedded board, significantly improving the integration, scalability, and cost-effectiveness of the testing system. Furthermore, by allocating independent DDR transmit / receive buffers and AXI address spaces to each network port, data path coupling is avoided, ensuring the determinism and timing controllability of multi-channel testing.

[0038] This invention not only comprehensively covers the bandwidth performance verification and high-concurrency data stream processing capability evaluation of multi-port devices under full load conditions, but also supports fault tolerance and robustness testing for protocol layer anomalies such as MAC address conflicts, IP address duplication, and abnormal frame injection. It provides an efficient, flexible, and scalable testing platform for the research and development and verification of highly reliable multi-port devices in fields such as communication infrastructure, industrial control, and aerospace. Attached Figure Description

[0039] To more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be considered as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In the drawings:

[0040] Figure 1 This is a hardware connection diagram for this embodiment;

[0041] Figure 2 This is a block diagram of the FPGA software in this embodiment;

[0042] Figure 3 This is a block diagram of the CPU software in this embodiment;

[0043] Figure 4 This is a schematic diagram of the PCIe-AXI conversion bridge in this embodiment;

[0044] Figure 5 This is a schematic diagram of the network port hardware controller structure;

[0045] Figure 6 This is a schematic diagram of the PCEI driver module;

[0046] Figure 7 This is a flowchart for testing multi-port software. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0048] This embodiment is based on a physical architecture of CPU and FPGA. The following is an explanation of the technical terms involved:

[0049] CPU (Central Processing Unit) is the core of a computer system for computation and control, and is the final execution unit for information processing and program execution. FPGA (Field-Programmable Gate Array) is a field-programmable gate array that allows for the modification of its internal logic structure through programming, thereby implementing complex sequential and combinational logic functions. PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard, primarily used to connect various internal hardware components of a computer. FIFO (First in, First out) is a data storage and processing principle, meaning that the first data to enter is processed or output first. PCIe-AXI is a protocol conversion. AXI (Advanced eXtensible Interface) is a bus protocol. BRAM stands for Block Random Access Memory, used to store large amounts of data within an FPGA. MMIO (Memory Mapped I / O) is part of the PCI specification, referring to mapping the internal memory and registers of I / O devices to a unified memory address space. Root A port is a key logic interface located inside the CPU or chipset; DDR (Double Data Rate Synchronous Dynamic Random Access Memory) is a type of computer memory; the AXI-DMA IP core is an important component in an FPGA, providing high-bandwidth direct memory access between the memory and the target peripheral of the AXI4-Stream interface; AXI-DMA enables the sending of large amounts of continuous data to DDR memory. Example 1

[0050] This implementation example Figure 1As shown, the architecture includes an FPGA and CPU working together, with the FPGA and CPU connected via a PCIe interface. The FPGA connects to multiple PHY chips via RGMII or SGMII interfaces, with each PHY chip corresponding to one RGMII or SGMII interface. A matching Ethernet interface circuit and a corresponding test cable together constitute one network port hardware circuit, which connects to the device under test (DUT) via the test cable for performing network function and performance tests. In this embodiment, the network port hardware circuits are identical in structure and independent of each other.

[0051] In this embodiment, regarding bandwidth capability, the unidirectional line rate of a single PCIe 6.0 channel is 64Gbps, and it supports a maximum configuration of x16 channels. Therefore, the theoretical peak bandwidth of the PCIe interface between the CPU and the FPGA can reach 1024Gbps. The maximum data rate supported by each RGMII or SGMII interface is 1.25Gbps. Theoretically, this architecture can support concurrent full-bandwidth testing of hundreds of Gigabit Ethernet interfaces; the specific number can be flexibly adjusted according to FPGA resources and PCIe channel configuration.

[0052] In this embodiment, during hardware design, the PCIe interface bandwidth between the CPU and the FPGA should be greater than the total bandwidth requirement of all network port hardware circuits. If the PCIe bandwidth significantly exceeds this total, it will lead to interface resource redundancy and increase system power consumption and cost. Therefore, it is necessary to reasonably select the PCIe version (such as Gen2, Gen3, Gen4, etc.) and the number of channels (x1, x4, x8, x16, etc.) according to the actual number of network ports configured, so as to optimize cost and power consumption while meeting performance requirements.

[0053] The software portion of this embodiment includes two parts: FPGA-side logic and CPU-side program, specifically:

[0054] like Figure 2 As shown, the FPGA-side logic includes a PCIe-AXI conversion bridge, an AXI-DMA module, and multiple network port hardware controllers; for example... Figure 3 As shown, the CPU-side program includes a PCIe driver, transmit / receive data buffers, an Ethernet protocol stack, and a network port stress test program, with the following structure: Figure 3 As shown, each network interface runs an independent lwIP protocol stack instance on the CPU side, with its own network interface descriptor, ARP table, IP address and MAC address configuration space, and there is no sharing between them.

[0055] Through the collaborative work of FPGA-side logic and CPU-side program, the system can achieve parallel full-bandwidth data transmission and reception across multiple network ports, and supports independent configuration and stress testing of network layer and link layer parameters such as IP address and MAC address.

[0056] In this embodiment, as Figure 4 As shown, the PCIe-AXI conversion bridge in the FPGA side logic consists of a PCIe interface controller, an AXI interface controller, and a PCIe-AXI protocol conversion layer.

[0057] In this embodiment, as Figure 5 As shown, in the FPGA program, the data received and transmitted by the PCIe interface is buffered through FIFOs. After address mapping via the PCIe-AXI protocol conversion layer, the AXI interface controller can perform read and write operations on these FIFOs, thereby realizing the mutual conversion between PCIe and AXI signals. Multiple AXI data streams are connected to the PCIe controller in parallel through the PCIe-AXI protocol conversion layer, enabling the system to support multiple network port devices to simultaneously perform full-bandwidth stress tests.

[0058] The FPGA-side logic integrates an AXI-DMA IP core to enable high-speed bulk data transfer between the FPGA's internal data and the CPU's main memory (DDR) without CPU intervention, establishing a bidirectional data path via the PCIe bus. AXI-DMA is a key module for achieving high-throughput, low-CPU-overhead data transfer.

[0059] When the CPU needs to send large blocks of data to the FPGA, it writes transmission parameters, including the data length, the physical address of the DDR buffer, and the start command, to the AXI-DMA control register in the FPGA via the PCIe configuration space or MMIO register. Subsequently, the AXI-DMA, acting as the bus master, initiates a PCIe memory read request, directly reading data from the CPU's DDR memory, transmitting it to the AXI bus via the PCIe-AXI converter bridge, and finally delivering it to the FPGA user logic. This process bypasses the CPU data path, effectively reducing processor load and improving transmission efficiency.

[0060] After the FPGA completes data processing, AXI-DMA can read the result data from the internal FIFO or BRAM and write the data directly to the pre-allocated result buffer in the CPUDDR in the form of a PCIe memory write transaction. This write operation is also completed autonomously by AXI-DMA without CPU intervention.

[0061] The network port hardware controller in the FPGA side logic consists of an AXI Ethernet MAC controller and an SGMII / RGMII interface controller.

[0062] In the transmitting direction, the network port hardware controller receives Ethernet data packets from the upper layer through the AXI interface; the AXI Ethernet MAC controller encapsulates the data packets into Ethernet frames conforming to the IEEE 802.3 standard, and then passes them to the SGMII or RGMII interface controller to convert them into a serial bit stream, which is then output to the external PHY chip.

[0063] In the receiving direction, the SGMII or RGMII interface controller receives the serial bit stream from the external PHY chip, recovers it into Ethernet frames, and sends them to the AXI Ethernet MAC controller. The MAC controller parses the frame structure, extracts the payload, and transmits the data frames to the upper-layer logic through the AXI interface.

[0064] The network port controller adopts a modular design, with each network port corresponding to an independent instance. It can realize bidirectional conversion between raw bit streams and Ethernet frames and support multiple network ports to perform full bandwidth functional tests at the same time.

[0065] Each network port hardware controller establishes a communication connection with the PCIe-AXI bridge by being assigned an independent AXI interface address. Each network port hardware controller corresponds to a unique AXI base address, and the CPU accesses the corresponding network port controller registers and data channels via the PCIe-AXI bridge using this address. This address isolation mechanism supports simultaneous data transmission and reception across multiple network ports, enabling concurrent testing of multiple interfaces.

[0066] In this embodiment, as Figure 6 As shown, the PCIe driver module on the CPU side is responsible for completing the underlying initialization of the PCIe controller, link establishment and memory mapping configuration, providing basic support for efficient communication with the FPGA endpoint device (EP) in the future.

[0067] During the initialization phase, the driver first enables the clock and power domains of the PCIe root complex (RC) controller, releases the reset signal, and configures it to the root port operating mode. Then, it sets the link rate (such as Gen2 or Gen3), the maximum payload size, and the maximum read request size, and enables the internal address translation unit (iATU) to prepare for subsequent address mapping.

[0068] During link training, the driver polls the "Link Up" flag in the PCIe controller status register, waiting for the FPGA EP device to power on and successfully complete the negotiation between the physical layer and the data link layer, ensuring a stable link establishment.

[0069] Regarding memory mapping configuration, the driver utilizes iATU's configuration transaction capabilities to set up a dedicated Outbound iATU region, configure its target type to CFG0 mode, and configure the address format according to the standard PCIe configuration:

[0070] ConfigAddr=(Bus≪20)∣(Device≪15)∣(Function≪12)∣(Register Offset&0xFFC)

[0071] Write this address to the iATU's target address register. Afterward, ordinary memory read / write operations by the CPU to the local preset window (e.g., 0x80000000) will be automatically converted by the hardware into the corresponding Type 0 / Type 1 configuration transactions, transparently accessing the configuration space or BAR mapping area under the specified BDF (Bus / Device / Function) of the FPGA EP device, thereby achieving low-latency, high-efficiency access to FPGA registers or data buffers.

[0072] The CPU software allocates independent DDR transmit and receive buffers for each network port. Data transmission and reception operations for each network port are completed within their respective buffers, isolated from each other to avoid mutual interference. Due to the physical separation of data channels, the CPU does not need to merge or split data from multiple network ports, reducing processing overhead.

[0073] The PCIe driver maps the DDR buffer address corresponding to each network port to the CPU-accessible memory space, providing an independent read / write interface for the network protocol stack. Through this mechanism, multiple network ports can simultaneously send and receive data, enabling concurrent testing.

[0074] In this embodiment, the CPU software uses the lightweight TCP / IP protocol stack lwIP to adapt to the resource-constrained operating environment of embedded systems. This protocol stack includes a network layer, a transport layer, and an application layer. In this multi-port test system, the IP protocol at the network layer and the UDP protocol at the transport layer are mainly enabled for performing protocol layer stress tests.

[0075] The CPU software further includes a network interface stress testing program deployed on a multi-core processor, used to achieve parallel and automated protocol layer stress testing of each network interface. Specifically, the system binds multiple physical network interfaces to different CPU cores, with each core independently running a lightweight TCP / IP protocol stack instance (such as lwIP) and a corresponding test task thread, thereby achieving complete logical and resource isolation of the data processing paths for each network interface. Figure 7 As shown.

[0076] During testing, each CPU core continuously monitors the receive buffer status flags of its corresponding network port via polling or interrupts. When valid data is detected, the local LWIP protocol stack is invoked to parse the received frame and extract the test payload data. Subsequently, the data integrity is verified according to preset verification rules, and the number of correct frames and incorrect frames are counted respectively. When a single network port has received a specified number of test data packets, the core automatically generates a test report containing metrics such as throughput, packet loss rate, and verification results, and then ends the current round of testing.

[0077] This embodiment enables the system to simultaneously execute complex stress test scenarios such as full bandwidth transmission and reception of multiple network ports, IP address / MAC address configuration changes, abnormal frame injection, and protocol fault tolerance on a single-board embedded platform, significantly improving test efficiency and coverage, while avoiding data competition and resource contention issues between multiple channels.

[0078] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A parallel multi-port full bandwidth testing method based on an FPGA and CPU collaborative architecture, characterized in that... include: In the FPGA-side logic architecture, an independent AXI-DMAI IP core is instantiated for each network port controller under test, and a unique AXI bus address space is allocated to each AXI-DMA IP core. Through the PCIe-AXI translation bridge, the unique AXI bus address space is mapped to an independent register window and data path that can be addressed by the CPU. This allows the CPU to transmit register configuration instructions and data read / write operations for any network port controller through the dedicated address space of that network port, thereby achieving physical address isolation of each network port at the FPGA logic level. In the CPU operating environment, each network port under test is allocated independent transmit and receive buffers in DDR memory. The driver maps the physical address of the DDR buffer corresponding to each network port to an independent virtual memory space in user mode or kernel mode, and provides independent read and write interfaces bound to each virtual memory space for the upper-layer Ethernet protocol stack. This ensures that the data encapsulation and parsing operations of each network port are only executed in their respective allocated memory areas, thereby achieving logical data isolation of each network port at the CPU memory level. Based on the independent address space on the FPGA side and the independent memory resource pool on the CPU side, the CPU monitors the status flags of the dedicated receive buffer of each network port through polling or interrupt mechanisms. When data transmission and reception are triggered, the CPU drives each network port controller to perform high-speed transmission and reception and verification of data packets in parallel on their respective independent data channels via the PCIe-AXI conversion bridge and the corresponding independent AXI bus address space. By maintaining the saturated load state of all independent data channels, parallel full-bandwidth stress testing in a multi-network port environment is achieved.

2. The parallel multi-port full bandwidth testing method based on FPGA and CPU collaborative architecture according to claim 1, characterized in that... The CPU is connected to the FPGA via a PCIe interface. Within the FPGA... Data received and sent from the PCIe interface is buffered using a FIFO. Address mapping is performed through the PCIe-AXI protocol translation layer; The FIFO is read and written by the AXI interface controller at the corresponding address, realizing the mutual conversion between PCIe signals and AXI signals.

3. The parallel multi-port full bandwidth testing method based on FPGA and CPU collaborative architecture according to claim 2, characterized in that: Data streams from different AXI interface controllers at the same time are accessed in parallel to the PCIe controller via the PCIe-AXI protocol conversion layer.

4. A parallel multi-port full bandwidth testing method based on an FPGA and CPU collaborative architecture as described in claim 2 or 3, characterized in that... An AXI-DMAIP core is integrated into the FPGA-side logic. Without the CPU's involvement, the FPGA establishes a bidirectional data path between the FPGA and the CPU via the PCIe bus, enabling high-speed batch data transfer between the FPGA's internal data and the CPU's main memory.

5. The parallel multi-port full bandwidth testing method based on FPGA and CPU collaborative architecture according to claim 4, characterized in that... When the CPU needs to send large blocks of data to the FPGA: Transfer parameters are written to the AXI-DMA control register in the FPGA via the PCIe configuration space or MMIO register. AXI-DMA initiates PCIe memory read requests as the bus master, reads data from the CPU DDR, transmits it to the AXI bus via the PCIe-AXI conversion bridge, and delivers it to the FPGA user logic.

6. The parallel multi-port full bandwidth testing method based on FPGA and CPU collaborative architecture according to claim 4, characterized in that... After the FPGA completes data processing, AXI-DMA reads the result data from the internal FIFO or BRAM and writes the data to the pre-allocated result buffer in the CPU DDR in the form of a PCIe memory write transaction.

7. The parallel multi-port full bandwidth testing method based on FPGA and CPU collaborative architecture according to claim 1, characterized in that... The CPU includes: The PCIe driver module is used to complete the low-level initialization, link establishment and memory mapping configuration of the PCIe controller; The CPU configures an independent DDR transmit buffer and receive buffer for each physical network port. Ethernet protocol stack, using the IP protocol at the network layer and the UDP protocol at the transport layer to perform protocol layer stress tests; Network port stress testing sequencing is used to achieve parallel and automated protocol layer stress testing of each network port.

8. The parallel multi-port full bandwidth testing method based on FPGA and CPU collaborative architecture according to claim 7, characterized in that... The PCIe driver module includes: Initialize, enable the clock and power domains of the PCIe root port controller, release the reset signal, configure it to RootPort operating mode, set the link rate, maximum payload size and maximum read request size, and enable the internal address translation unit. Once the link is established, the driver polls the flag bits in the PCIe controller status register, waiting for the FPGA to power on and successfully complete the negotiation between the physical layer and the data link layer. In memory mapping configuration, the driver utilizes the configuration transaction capabilities of the internal address translation unit to set up a dedicated address translation region, configure its address, and write it to the target address register.

9. The parallel multi-port full bandwidth testing method based on FPGA and CPU collaborative architecture according to claim 8, characterized in that: The PCIe driver maps the DDR buffer address corresponding to each physical network port to the CPU-accessible memory space, providing an independent read / write interface for the Ethernet protocol stack.

10. A parallel multi-port full bandwidth testing method based on an FPGA and CPU collaborative architecture as described in any one of claims 1 to 7-9, characterized in that... Within the CPU, each CPU core independently runs a lightweight TCP / IP protocol stack instance and a corresponding test task thread. The tests include: When valid data is detected, the local lwIP protocol stack is invoked to parse the received frame and extract the test payload data. The integrity of the data is verified according to the preset verification rules, and the number of correct frames and the number of incorrect frames are counted respectively. Once a single network port has received a specified number of test data packets, the CPU core automatically generates a test report containing metrics such as throughput, packet loss rate, and verification results, and then ends the current test task.

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