High-speed interconnection switching chip system based on Chiplet

Abstract

The invention discloses a Chiplet-based high-speed interconnection exchange chip system, belongs to the technical field of high-performance computing and high-speed interconnection, and solves the problems of difficulty in port expansion, high power consumption and insufficient flexibility in the existing scheme. The system comprises a plurality of interfaces (Chiplets), at least one exchange interconnection (Chiplet) and a high-speed interconnection channel between the Chiplets. The interface Chiplet completes conversion between an external protocol and the AXI-Stream and carries routing information, the exchange interconnection Chiplet achieves all-to-all data exchange through deterministic routing, hierarchical arbitration and multi-stage flow control, and multi-protocol adaptation and Chiplet cascade extension are supported. The circuit is adaptive to 2.5 D / 3D advanced packaging, the number of ports can be linearly expanded, the complexity of a single chip is reduced, and the circuit is suitable for high-speed interconnection between a GPU and an AI accelerator.

Description

Technical Field

[0001] This invention relates to the field of high-performance computing and high-speed interconnect technology, specifically to a high-speed interconnect switching chip system based on the Chiplet architecture, which is particularly suitable for high-bandwidth, low-latency, many-to-many high-speed interconnect and data exchange scenarios between computing chips such as GPUs and AI accelerators. Background Technology

[0002] With the rapid development of applications such as artificial intelligence, large model training, and high-performance computing (HPC), the interconnection requirements between multiple GPUs, AI accelerators, and storage resources in distributed computing systems exhibit characteristics of high bandwidth, low latency, and many-to-many relationships. Existing GPU interconnection and switching solutions have significant shortcomings, mainly falling into three categories: (1) Traditional switching chips based on PCIe or CXL adopt a single large-scale SoC architecture, integrating the high-speed physical layer, protocol processing logic and switching matrix into the same chip. As the number of ports and bandwidth increases, the chip area increases sharply, the power consumption remains high, and the chip yield decreases significantly, greatly increasing the production cost. (2) Dedicated GPU interconnect solutions, such as point-to-point or fixed topology, are only applicable to GPU architectures of specific manufacturers, have poor flexibility, cannot support interconnection of GPUs or heterogeneous accelerators from multiple manufacturers, and have low adaptability. (3) While the chiplet interconnection scheme based on advanced packaging can reduce the complexity of single-chip design, the functional responsibilities between different chips are unclear, the protocol processing logic and the switching logic are highly coupled, and it is difficult to achieve a true scale expansion of the number of ports and adapt to the needs of multi-protocol interconnection.

[0003] Therefore, there is an urgent need in the field for a new high-speed interconnect switching chip system that is oriented towards GPU / AI accelerator interconnection, supports chiplet modular design, protocol decoupling, linear scalability, and adaptable to advanced packaging processes, in order to solve the above-mentioned problems of the prior art. Summary of the Invention

[0004] The purpose of this invention is to provide a high-speed interconnect switching chip system based on Chiplet, which realizes high-bandwidth, low-latency all-to-all interconnect between GPUs and AI accelerators, solves the problems of difficult port expansion, high power consumption, insufficient flexibility and high protocol coupling in existing solutions, and adapts to 2.5D / 3D advanced packaging technology, reduces the complexity of single-chip design and extends the architecture life cycle.

[0005] To solve the above-mentioned technical problems, the present invention is achieved through the following technical solution: To achieve the aforementioned objectives, this invention provides a high-speed interconnect switching chip system based on Chiplet. The core of this system is a modular Chiplet design and protocol decoupling architecture. Specifically, it comprises three parts: multiple interface Chiplet (IODie), at least one switching interconnect Chiplet (Logic Die), and high-speed interconnect channels between Chiplet. The system supports flexible scalability. The specific technical solution is as follows: Interface Chiplet: Each interface chiplet integrates a high-speed interface module, a protocol processing and conversion module, and an inter-chiplet interconnection interface module, independently realizing communication with external computing chips, protocol conversion, and data interaction with the switching interconnection chiplet; High-speed interface module: Supports mainstream high-speed interconnect protocols such as PCIe, CXL, NVLink, UALink, and SUE, as well as custom protocols. Configure interface chiplets of different protocols according to actual needs to realize interconnection of multi-protocol and heterogeneous GPU / AI accelerators. Protocol processing and conversion module: Converts the transmission units of external high-speed interconnection protocols into internal unified AXI-Stream streams, and writes service information such as routing identifiers, virtual channel identifiers, and priority identifiers into the user-side band signals of the AXI-Stream streams, providing a basis for subsequent data forwarding and quality of service assurance; Chiplet Interconnect Interface Module: Adapts to the physical layer of the high-speed inter-chip interconnect channel to enable high-speed transmission and reception of the converted AXI-Stream.

[0006] Chiplet: The Chiplet is the logical core of the system, integrating a multi-port switching interconnect module, a port abstraction and mapping module, a routing, arbitration and flow control module. It independently realizes data switching and forwarding, flow control and quality of service assurance, and is decoupled from external protocols, so it can be reused for a long time. Multi-port switching interconnect module: Provides an all-to-all interconnect path between multiple interface Chiplets, ensuring bidirectional data transmission between any two interface Chiplets; Port abstraction and mapping module: Maps the physical ports of different interface chiplets to logical ports in a unified manner, shielding the differences between physical ports and simplifying routing and forwarding logic; The routing, arbitration, and flow control modules are the core functional modules, specifically including: Routing mechanism: It adopts deterministic single-hop routing based on destination port identifier, maintains an internal port routing mapping table, and accurately forwards the data stream to the corresponding output port according to the destination port identifier with field on the AXI-Stream flow side, with no loops and low latency; it also supports equal cost multipath routing (ECMP) and fault avoidance routing, and the routing policy can be dynamically updated through configuration registers or control plane; Arbitration Mechanism: The output port serves as the arbitration center, with an arbitration granularity of one AXI-Stream data packet (TLAST signal identifies the boundary) or a fixed number of consecutive data beats. A hierarchical arbitration strategy is adopted, first performing virtual channel priority arbitration, with higher priority data scheduled first. Within the same virtual channel, round-robin or weighted round-robin is used to achieve fair arbitration. Backpressure-aware arbitration is also supported, suspending scheduling when the target port experiences backpressure, balancing bandwidth utilization and scheduling fairness. Flow control mechanism: Based on the valid / ready backpressure mechanism of AXI-Stream combined with a multi-level buffer structure, a buffer queue is set up at each input and output port to absorb instantaneous traffic fluctuations; the buffer queue depth of each virtual channel is configured to 8~64 data packets, the high water level threshold is 70%~80% of the queue depth, and the low water level threshold is 30%~40%. When the high water level is reached, the ready signal is pulled down to apply backpressure upstream, and reception is resumed when the water level is lowered, effectively preventing congestion from spreading. Quality of Service Assurance: AXI-Stream uses virtual channel identifiers and priority identifiers with fields on the stream side. Combined with priority scheduling, bandwidth reservation, traffic shaping, and starvation prevention mechanisms, it ensures the low latency requirements of critical services while preventing low-priority services from being blocked for extended periods.

[0007] High-speed interconnect channel between Chiplet: As the transmission medium between interface Chiplet and switching interconnect Chiplet, it supports parallel interconnect, serial interconnect or die-to-die standard interfaces such as UCIe and HIPI, and can also adopt custom die-to-die interfaces; it can be deployed on silicon interposers, silicon bridges or advanced packaging substrates, and is compatible with 2.5D / 3D advanced packaging processes, shortening interconnect distance and improving signal integrity and system energy efficiency.

[0008] Scalable architecture: The number of interface Chiplet increases linearly according to the actual needs of the system's switching ports, directly matching the port expansion requirements; multiple switching interconnect Chiplet can be cascaded or hierarchically connected to form 16-port, 32-port, or even larger-scale GPU / AI accelerator interconnect switching networks, meeting the large-scale interconnection needs of distributed computing systems.

[0009] The present invention has the following advantages over the prior art: (1) Significantly improved port expansion capability: The chiplet modular design allows the number of interface chiplets to increase linearly, and the switching interconnection chiplets support cascading and hierarchical arrangement, enabling the system to expand the number of ports without bottlenecks and solving the problem of port expansion difficulties in existing solutions; (2) Reduced single-chip complexity and power consumption: The protocol processing logic and the switching logic are decoupled and implemented independently by the interface chiplet and the switching interconnect chiplet, respectively, which greatly reduces the design scale of a single chiplet, reduces chip power consumption and production cost, and improves chip yield; (3) Support for multiple protocols and heterogeneous interconnection: Different interface Chiplet can be configured with different high-speed interconnection protocols, compatible with mainstream protocols such as PCIe, CXL, NVLink and custom protocols, to realize interconnection of GPUs from multiple manufacturers and heterogeneous AI accelerators, greatly improving flexibility and adaptability; (4) Adaptation to advanced packaging technology: The high-speed interconnect channel between chips can be deployed on silicon interposers, silicon bridges or advanced packaging substrates, adapting to 2.5D / 3D advanced packaging processes, shortening the interconnection distance between chips, improving signal integrity, reducing transmission loss and improving the overall energy efficiency of the system; (5) Extended architecture lifecycle: The switching interconnect chiplet is designed independently of the external high-speed interconnect protocol, decoupled from the protocol, and adapted to the interface chiplet of different protocols. When the external protocol is upgraded, there is no need to redesign the switching interconnect chiplet, which enables long-term reuse and extends the system architecture lifecycle. (6) Stable and controllable data exchange performance: Through deterministic single-hop routing, hierarchical arbitration, multi-level flow control and multi-dimensional quality of service assurance mechanisms, low-latency and loop-free data exchange is achieved, effectively preventing congestion spread and ensuring the stability and predictability of data exchange performance in multi-service concurrent scenarios.

[0010] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of the GPU interconnect switching chip structure based on Chiplet in Embodiment 1 of the present invention; Figure 2This is a schematic diagram of a multi-level GPU interconnect switching chip structure based on Chiplet, according to Embodiment 2 of the present invention. Detailed Implementation

[0013] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0014] In this scheme: the number of interface Chiplet1 is N (N≥1, which can be increased linearly). Each interface Chiplet integrates a high-speed interface module, a protocol processing and conversion module, and an inter-Chiplet interconnection interface module, which are connected to the GPU / AI accelerator respectively; the number of switching interconnection Chiplet is M (M≥1, through cascading and layering), which integrates a multi-port switching interconnection module, a port abstraction and mapping module, and a routing, arbitration, and flow control module; the interface Chiplet and the switching interconnection Chiplet are connected through a high-speed inter-Chiplet interconnection channel deployed on the silicon interposer layer to achieve high-speed data transmission.

[0015] Example 1: 8-Port GPU High-Speed ​​Interconnect Switching Chip System like Figure 1 As shown, this embodiment is an 8-port GPU high-speed interconnect switching chip system: Module connection relationship: The Chiplet interconnection interface module and the port abstraction and mapping module of the Chiplet interconnection module are directly connected through the high-speed Chiplet interconnection channel; Signal flow: GPU / AI accelerator → high-speed interface module → protocol processing and conversion module → chiplet interconnection interface module → chiplet high-speed interconnection channel → port abstraction and mapping module → routing, arbitration and flow control module → multi-port switching interconnection module → return to the target GPU / AI accelerator via the original path. This solution is compatible with advanced 2.5D silicon interposer packaging technology. The specific configuration and implementation are as follows: Hardware configuration: It is equipped with 8 interface chiplets and 1 switching interconnect chiplet. All interface chiplets and switching interconnect chiplets are connected through high-speed interconnect channels between chiplets, and the interconnect channels are deployed on a 2.5D silicon interposer. Interface Chiplet Configuration: Each interface chip's high-speed interface module is configured with the NVLink protocol and connects to a GPU chip. The protocol processing and conversion module converts the NVLink protocol's transmission unit into an AXI-Stream and writes the port identifier, virtual channel identifier, and priority identifier corresponding to the destination GPU into the sideband field. The specific definition and writing rules of AXI-Stream sideband signals are as follows: Based on the standard AXI-Stream, 32-bit sideband signals are extended and the fields are split: bits 0-7 are the destination port identifier, bits 8-11 are the virtual channel identifier, bits 12-15 are the priority identifier, and bits 16-31 are reserved fields. The encoding rules for each field are as follows: the destination port identifier uses 8-bit binary encoding, supporting 0-255 port addresses; the priority identifier uses 4-bit encoding, with 0 representing the highest priority and 15 representing the lowest priority. The AXI-Stream adopts the AXI-Stream 3.0 standard, with a data bit width of 256 bits, a clock frequency of 1 GHz, a sideband signal extension of 32 bits (the field division is consistent with the invention content), and a data transmission rate of 256 Gbps (256 bits × 1 GHz), matching the bandwidth requirements of the high-speed interconnect channel between Chiplet. Chiplet high-speed interconnect channel configuration: adopts UCIe standard Die-to-Die interface, based on Samsung 8nm process technology, single channel data transmission speed is 16Gbps, a total of 64 transmission channels are configured to meet the high bandwidth transmission requirements between 8 interface Chiplet and switch interconnect Chiplet; Write timing: While the external protocol data is being converted into AXI-Stream data, the sideband field is written in the same clock cycle. After the write is completed, the TVALID signal is set high and transmitted synchronously with the data. The working mechanism of the Chiplet switching interconnection: The port abstraction and mapping module of the Chiplet switching interconnection maps 8 interface Chiplets to 8 logical ports. The routing module forwards data to the corresponding interface Chiplet through deterministic single-hop routing based on the destination port identifier of the AXI-Stream. The arbitration module adopts a hierarchical strategy of "priority arbitration + weighted round-robin arbitration" to ensure the priority scheduling of high-priority GPU computing data. The buffer queue depth of the flow control module is configured to 32 data packets, with a high watermark threshold of 75% and a low watermark threshold of 35%, effectively absorbing instantaneous traffic fluctuations. The arbitration execution sequence of the hierarchical arbitration strategy is as follows: A three-level decision is adopted in a single clock cycle. The rising edge of the clock first detects the backpressure signal of the output port (if the backpressure signal is high, all scheduling requests for input ports are directly suspended; if the backpressure signal is low, the next level of decision is entered) → the virtual channel priority identifier of all input ports is extracted, and the input port with the highest priority is selected → if there are multiple input ports with the highest priority, they enter into fair arbitration at the same level. The priority determination rule of the hierarchical arbitration strategy adopts a weighted round-robin configuration: the weights are encoded in 4-bit binary, ranging from 1 to 15. A weight value is assigned to each input port through a configuration register, and the arbitrator allocates transmission time slices according to the weight value (e.g., if port A has a weight of 4 and port B has a weight of 2, then port A transmits 4 data cycles, and port B transmits 2 data cycles). The backpressure sensing judgment standard is as follows: when the buffer queue of the output port reaches the high-water level threshold, the backpressure signal is set high, and the arbitrator suspends all scheduling requests for that output port; when the buffer queue is below the low-water level threshold, the backpressure signal is set low, and scheduling resumes. The buffer queue management and signal interaction logic of the flow control mechanism: Hardware implementation structure of the buffer queue: FIFO / circular buffer is used, with read / write pointer control logic for each queue; High / low water level threshold detection logic: A counter is used to count the number of data packets in the queue, and the timing of comparison with the threshold is determined; Ready signal pull-down / recovery timing: After detecting that the queue has reached the high water level, in which clock cycle is the ready signal pulled low, and its interaction with the valid signal from the upstream module; Independent management method of the buffer queue under multiple virtual channels: Each virtual channel corresponds to an independent FIFO, or a shared FIFO is used with divided areas; System Functionality: Computational data sent by any GPU undergoes protocol conversion via the corresponding interface Chiplet, then is transmitted to the switching interconnect Chiplet through the high-speed interconnect channel between Chiplets. The switching interconnect Chiplet then forwards the data to the interface Chiplet corresponding to the target GPU, and finally converts it into NVLink protocol data for transmission to the target GPU. This achieves all-to-all high-speed interconnection between 8 GPUs, with a unidirectional transmission bandwidth of up to 1024Gbps (64 channels × 16Gbps) and an end-to-end latency of less than 1μs. Physical layer parameters and adaptation rules for high-speed interconnect channels between Chiplet: Parallel interconnect: 32 / 64 / 128-bit bit width selectable, clock frequency supports 1GHz / 2GHz, using source synchronous clock method; Serial interconnect: 64b / 66b encoding, differential pair quantity is 1 / 2 / 4 pairs, physical layer rate supports 10Gbps / 16Gbps / 32Gbps. UCIe / HIPI adaptation logic: Adopting the UCIe 1.0 standard, the PHY layer of the interconnection interface module between the physical layer and the Chiplet is connected. The link training follows the UCIe standard process. After clock synchronization and link balancing are completed, a data transmission channel is established. Packaging wiring parameters: Under silicon interposer wiring impedance is 50Ω±10%, line width is 2μm, and line spacing is 4μm; Under silicon bridge wiring impedance is 45Ω±10%, line width is 3μm, and line spacing is 6μm. Channel allocation rules: A static equal distribution + dynamic adjustment method is adopted. The basic method is to allocate 8 channels to each of the 8 interface chiplets. It supports allocating idle channels to interface chiplets with high bandwidth requirements through configuration registers.

[0016] Example 2: Figure 2 As shown, in the 16-port heterogeneous computing chip interconnect switching chip system, two switching interconnect chips are connected through a dedicated cascading interface (integrated into the multi-port switching interconnect module). The cascading interface adopts the UCIe 1.0 standard, supports global routing mapping table synchronization and cross-chip data transmission, and the signal flow is as follows: Interface Chiplet → Switching Interconnect Chiplet 1 → Cascading Interface → Switching Interconnect Chiplet 2 → Target Interface Chiplet. This embodiment, based on Embodiment 1, implements the interconnection of 16-port heterogeneous computing chips (8 GPUs + 8 AI accelerators). The specific expansion and configuration methods are as follows: Hardware expansion: Based on the first embodiment, 8 interface Chiplet and 1 switching interconnect Chiplet are added. The 2 switching interconnect Chiplet are cascaded through the high-speed interconnect channel between Chiplet to form a 16-port interconnect switching network. The 8 newly added interface Chiplet high-speed interface modules are configured with the CXL protocol and are connected to 8 AI accelerators respectively. Protocol adaptation: The 8 interface chiplets corresponding to the GPU maintain the NVLink protocol configuration, and the 8 interface chiplets corresponding to the AI ​​accelerator are configured with the CXL protocol. All interface chiplets convert the external protocol into a unified AXI-Stream, realizing heterogeneous interconnection between NVLink and CXL protocols. Routing and scheduling optimization: Both interconnected chiplets maintain global port routing maps, supporting deterministic single-hop routing across chiplets; the arbitration module configures different virtual channels and priorities for GPU computing data and AI accelerator inference data, reserving 30% bandwidth for real-time AI inference data to ensure the synergy of heterogeneous computing; bandwidth reservation specifically involves allocating dedicated bandwidth counters to specific virtual channels. These counters generate transmission licenses based on the reserved bandwidth percentage (e.g., 30%). Other channels can only use this bandwidth when the counter has a license; otherwise, the bandwidth is reserved solely for the reserved channel; traffic shaping uses a token bucket algorithm for rate limiting. The token bucket has a capacity of 8 data packets. The generation rate is 1 token per clock cycle. Low-priority virtual channels can only send data after acquiring a token; if the rate is exceeded, they wait for token generation. An 8-bit aging counter is configured for each input port. The counter starts counting when the port is not scheduled, and the counting cycle is 1 clock cycle. When the count value reaches 255, the priority of the port is temporarily increased by one level until the port is scheduled, at which point the counter is reset to zero. After data enters the switching interconnect chiplet, it first undergoes traffic shaping (limiting the rate of low-priority channels) → then bandwidth reservation (ensuring bandwidth for critical channels) → then priority scheduling (filtering high-priority data) → finally, starvation prevention is achieved through the aging counter, ensuring scheduling opportunities for low-priority channels. Cross-Chiplet routing employs a global table synchronization mechanism and cross-Chiplet port identification rules. The global table synchronization mechanism involves two interconnected Chiplets synchronizing their routing tables via dedicated synchronization channels (two UCIe channels). When an entry in one Chiplet is updated, the updated data is sent to the other Chiplet via the synchronization channel. After synchronization is complete, an acknowledgment signal is sent to ensure complete consistency between the two entries. The cross-Chiplet port identification rules specify that in the 8-bit encoding of the destination port identifier, bit 7 is the cross-Chiplet identifier (0 for local port, 1 for remote port), and bits 0-6 are the port number. For example, a remote port identifier of 10000001 indicates port 1 of another Chiplet. The routing module forwards data to the cross-Chiplet interconnection channel based on the identifier in bit 7. The routing table uses on-chip dual-port RAM as its storage medium, supporting simultaneous read and write operations to avoid data forwarding interruptions. The table structure is as follows: each entry is 32 bits, where bits 0-7 are the source port identifier, bits 8-15 are the destination port identifier, bits 16-23 are the output port identifier, and bits 24-31 are the routing status identifier (0 for available, 1 for unavailable, used for fault avoidance). Dynamic update methods include: ① Configuration register update: 16 32-bit configuration registers are allocated, register 0 is for write enable, and registers 1-15 are for entry data. Entry writing is completed after the write enable is set high; ② Control plane update: Communication with the external control unit is achieved using the I2C / SPI protocol. During update, the corresponding routing status identifier is first set to unavailable, and then restored to available after the update to avoid data flow forwarding errors. System Functionality: Enables full interconnection between 8 GPUs and 8 AI accelerators, supports bidirectional high-bandwidth data transmission between GPUs, between AI accelerators, and between GPUs and AI accelerators, meets the interconnection requirements of heterogeneous distributed computing systems, and achieves an overall system switching bandwidth of up to 2048Gbps with an end-to-end latency of less than 2μs.

[0017] The embodiments of the present invention are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Those skilled in the art can adjust the protocol type and number of interface Chiplet, the cascading method of interconnected Chiplet, and the interface type and process parameters of high-speed interconnection channels between Chiplet according to actual needs. All modifications, equivalent substitutions, improvements, etc., made within the scope of the technical concept of the present invention should be included within the protection scope of the present invention.

[0018] The preferred embodiments of the present invention disclosed above are merely illustrative of the invention. These preferred embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A high-speed interconnect switching chip system based on Chiplet, characterized in that, include: Multiple interface chiplets communicate with GPUs, AI accelerators or other computing chips, convert the transmission units of external high-speed interconnect protocols into AXI-Stream streams, and carry routing and service information in the user-side band signals of the AXI-Stream streams; At least one switching interconnect chiplet communicates with the interface chiplet to enable all-to-all data exchange between multiple interface chiplets; A high-speed interconnect channel between Chiplets connects the interface Chiplet to the switch interconnect Chiplet, enabling high-speed data transmission between them; The number of interface Chiplet increases linearly according to the switching port requirements, and multiple switching interconnect Chiplet are connected in a cascaded or hierarchical manner to form a large-scale interconnected switching network.

2. The system according to claim 1, characterized in that, The interface Chiplet includes: High-speed interface module, supporting PCIe, CXL, NVLink, UALink, SUE or custom high-speed interconnect protocols; The protocol processing and conversion module completes the bidirectional conversion between external high-speed interconnection protocols and AXI-Stream streams, and writes the routing, virtual channel, and priority identifiers to the sideband fields of the AXI-Stream stream; The Chiplet interconnect interface module is adapted to the high-speed interconnect channel between Chiplets to enable the sending and receiving of converted data.

3. The system according to claim 1, characterized in that, The switching interconnect chiplet includes: The multi-port switching interconnect module provides an all-to-all interconnect path between multi-interface chiplets; The port abstraction and mapping module maps the physical ports of different interface Chiplet to logical ports in a unified manner. The routing, arbitration, and flow control modules enable data path selection, bandwidth allocation, traffic control, and quality of service assurance.

4. The system according to claim 3, characterized in that, The routing, arbitration, and flow control module employs a deterministic single-hop routing mechanism based on the destination port identifier. The switching interconnect chiplet maintains a port routing mapping table internally and forwards the data stream to the corresponding output port according to the destination port identifier. The routing mechanism also supports equal-cost multi-path routing and fault-avoidance routing, and the routing policy can be dynamically updated through configuration registers or the control plane.

5. The system according to claim 3, characterized in that, The arbitration mechanism of the routing, arbitration and flow control module takes the output port as the arbitration center, and the arbitration granularity is one AXI-Stream data packet or a fixed number of continuous data frames; The arbitration mechanism adopts a tiered arbitration strategy, including virtual channel priority arbitration, polling / weighted polling fair arbitration within the same virtual channel, and backpressure sensing arbitration.

6. The system according to claim 3, characterized in that, The flow control mechanism of the routing, arbitration and flow control module is based on the valid / ready backpressure mechanism of AXI-Stream combined with a multi-level buffer structure, with a buffer queue set up for each input and output port. The buffer queue depth for each virtual channel is 8 to 64 data packets. The high watermark threshold is 70% to 80% of the queue depth, and the low watermark threshold is 30% to 40%. When the high watermark is reached, the ready signal is pulled down to apply back pressure, and when the low watermark is reached, data reception is resumed.

7. The system according to claim 3, characterized in that, The routing, arbitration, and flow control modules ensure quality of service through virtual channel identifiers and priority identifiers. The assurance mechanisms include priority scheduling, bandwidth reservation, traffic shaping, and starvation prevention mechanisms.

8. The system according to claim 1, characterized in that, The high-speed interconnect channel between Chiplet is a parallel interconnect, a serial interconnect, or a Die-to-Die standard interface, and the Die-to-Die standard interface includes UCIe, HIPI, or a custom Die-to-Die interface; The high-speed interconnect channels between the chips are deployed on silicon interposers, silicon bridges, or advanced packaging substrates.

9. The system according to claim 1, characterized in that, The system is compatible with 2.5D / 3D advanced packaging technology. When using Samsung's 8nm process, the single-channel data speed of the high-speed interconnect channel between chips is 16Gbps, and the number of channels is 64.

10. The system according to any one of claims 1-9, characterized in that, The switching interconnect chiplet is designed independently of external high-speed interconnect protocols, and its interface chiplets are adapted to and reused for a long time with different protocols.

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