Integrated circuit with transistor

Abstract

The invention provides an integrated circuit with a transistor, which is characterized in that an oxide semiconductor layer such as indium tin oxide (ITO) and a gate dielectric layer are sequentially and fully surrounded on the side wall of at least part of height of an oxide insulating core column, and a gate electrode is enabled to surround part of the gate dielectric layer; therefore, the oxide semiconductor layer in the area surrounded by the grid is used as a conducting channel of the MOS transistor, and the oxide semiconductor layers on the two sides of the grid are used as a source region and a drain region of the MOS transistor, so that the size of the transistor can be further miniaturized, the short-channel effect is improved, the performance of the miniaturized transistor is ensured, and the reliability of the MOS transistor is improved. And the miniaturization and the performance improvement of an integrated circuit with the transistor are facilitated.

Description

[0001] Information related to divisional application

[0002] This application is a divisional application of the parent application with application number CN202211143063.3, application date September 20, 2022, and invention title "Integrated Circuit with Transistor". Technical Field

[0003] This invention relates to the field of integrated circuit manufacturing technology, and in particular to an integrated circuit having transistors. Background Technology

[0004] In the field of semiconductor technology, transistors, especially metal-oxide-semiconductor field-effect transistors (MOSFETs), are key components of integrated circuits (such as logic circuits, memory circuits, and control circuits for memory circuits). For example, they can be used as the most basic electronic components to form memory cells (also a type of integrated circuit) such as DRAM, and as basic electronic elements to form logic circuits (or logic devices, logic chips) and other integrated circuits. A transistor has a gate, source region, drain region, and channel region. The channel region is located between the source and drain regions and is insulated from the gate by a gate dielectric layer. Applying a suitable voltage to the gate allows current to flow through the channel region from one of the source and drain regions to the other.

[0005] However, as circuit integration increases and transistor size decreases, the characteristics of traditional planar MOSFET devices deteriorate due to the enhanced short-channel effect. The gate's control over the transistor weakens, and the off-state leakage current increases, leading to a sharp increase in chip power consumption. While reducing the chip's operating voltage can reduce power consumption, insufficient transistor driving force at low voltages can affect the read / write speed of DRAM chips or the signal processing speed of logic chips.

[0006] Furthermore, traditional memory consists of a transistor and a capacitor, with data stored on the capacitor in the form of electrical charge. The size of the transistor affects the further reduction of memory cell size and the increase of storage density.

[0007] Therefore, how to apply new materials and structures to design transistors and integrated circuits using these transistors has become one of the key issues of concern to those skilled in the art. Summary of the Invention

[0008] The purpose of this invention is to provide an integrated circuit with a transistor that facilitates further miniaturization of the transistor and the integrated circuit having the transistor.

[0009] To achieve the above objectives, the present invention provides an integrated circuit having transistors, comprising a plurality of transistors, wherein at least one of the plurality of transistors comprises:

[0010] Oxide insulating core post;

[0011] An oxide semiconductor layer that completely surrounds the sidewalls of at least a portion of the height of the oxide insulating core;

[0012] A gate dielectric layer that completely surrounds the sidewalls of at least a portion of the height of the oxide semiconductor layer;

[0013] A gate whose sidewalls completely surround a portion of the height of the gate dielectric layer;

[0014] In this transistor, the oxide semiconductor layer in the gate-enclosed region serves as the channel region, the oxide semiconductor layer on one side of the channel region serves as the source region, and the oxide semiconductor layer on the other side of the channel region serves as the drain region.

[0015] Optionally, the oxide semiconductor layer is a single-layer film structure or a composite structure of multiple films stacked sequentially, and the material of the oxide semiconductor layer includes at least one of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, and indium gallium zinc oxide.

[0016] Optionally, the material of the gate dielectric layer includes silicon oxide and / or a high-k dielectric with a dielectric constant k greater than 7, and the material of the gate includes metal and / or doped polysilicon.

[0017] Optionally, the plurality of transistors are distributed in the same layer structure or distributed in a three-dimensional stacked multilayer structure.

[0018] Optionally, the integrated circuit includes a memory circuit, the memory circuit having:

[0019] At least one memory layer having a plurality of memory cells arranged in an array, each memory cell having a transistor, and a data storage structure electrically connected to one of the source and drain regions of the transistor.

[0020] At least one bit line layer having multiple bit lines extending along a first direction and isolated from each other, each bit line being electrically connected to the other of the source and drain regions of the transistors of multiple memory cells arranged along the first direction in the corresponding memory layer.

[0021] At least one word line layer having multiple word lines extending along a second direction and isolated from each other, each word line being electrically connected to the gate of a plurality of memory cells arranged along the second direction in a corresponding memory layer;

[0022] Each memory cell in each memory layer is located at the intersection of the corresponding word line and bit line.

[0023] Optionally, the gates of a plurality of memory cells arranged along the second direction in the corresponding memory layer are connected together to form the corresponding word line.

[0024] Optionally, the multiple memory layers are stacked sequentially along a third direction perpendicular to the first direction and the second direction, and one end of the word line of the multiple memory layers is shortened or lengthened layer by layer to form a stepped word line arrangement end, and one end of the bit line of the multiple memory layers is shortened or lengthened layer by layer to form a stepped bit line arrangement end.

[0025] Optionally, the integrated circuit further includes word line contacts for electrically leading the corresponding word lines to the outside, and bit line contacts for electrically leading the corresponding bit lines to the outside; wherein the word line contacts of each layer of word lines are disposed at the stepped word line arrangement end in a staggered arrangement, and the bit line contacts of each layer of bit lines are disposed at the stepped bit line arrangement end in a staggered arrangement.

[0026] Optionally, the integrated circuit further includes a multilayer metal interconnect structure, the memory circuit being disposed above or below the corresponding multilayer metal interconnect structure, the multilayer metal interconnect structure having multiple layers of metal interconnects and an inter-metal dielectric layer for insulating and isolating metal interconnects between the same layer and different layers, the word lines of the corresponding memory layer being electrically connected to a corresponding portion of the metal interconnects in the multilayer metal interconnect structure through corresponding word line contacts, and the bit lines of the corresponding memory layer being electrically connected to another corresponding portion of the metal interconnects in the multilayer metal interconnect structure through corresponding bit line contacts;

[0027] Alternatively, the integrated circuit further includes a multilayer metal interconnect structure, with the memory circuit disposed inside the corresponding multilayer metal interconnect structure. The multilayer metal interconnect structure has multiple layers of metal interconnects and an inter-metal dielectric layer for insulating and isolating metal interconnects between metal interconnects of the same layer and different layers. The corresponding memory layer is disposed in the corresponding inter-metal dielectric layer. The word lines and bit lines of the memory layer are metal interconnects of different layers in the multilayer metal interconnect structure. The word lines of the same layer are metal interconnects of the same layer in the multilayer metal interconnect structure, and the bit lines of the same layer are metal interconnects of the same layer in the multilayer metal interconnect structure.

[0028] Optionally, the integrated circuit includes a non-memory circuit having at least one transistor device layer, the transistor device layer having at least one of the aforementioned transistors; the transistors in the same or different layers of the non-memory circuit are connected in series or in parallel.

[0029] Optionally, the integrated circuit further includes a substrate layer formed above or below the transistor device layer, wherein at least one first conductive structure is formed in the substrate layer, and the first conductive structure is electrically connected to the source region of at least one transistor in the transistor device layer.

[0030] Compared with the prior art, the technical solution of the present invention has at least the following beneficial effects:

[0031] 1. An oxide semiconductor layer such as indium tin oxide (ITO) and a gate dielectric layer are sequentially and completely surrounded on the sidewalls of at least a portion of the height of the oxide insulating core, such that the gate surrounds the sidewalls of a portion of the gate dielectric layer. Thus, the oxide semiconductor layer in the gate-surrounded region serves as the conductive channel of the MOS transistor, and the oxide semiconductor layers on both sides of the gate serve as the source and drain regions of the MOS transistor. On the one hand, the gate completely surrounds the conductive channel, which can enhance the gate's control over the transistor. On the other hand, a MOS transistor with a vertical channel structure is formed. By controlling the height of the gate and the perimeter of the oxide insulating core, the aspect ratio of the transistor channel can be controlled, which can facilitate further miniaturization of the transistor size, improve the short-channel effect, and ensure the performance of the miniaturized transistor.

[0032] 3. When the oxide semiconductor layer is indium tin oxide (ITO), ITO's wide bandgap (Eg > 3eV) and high carrier mobility (50 cm⁻¹) are utilized. 2 The material properties of / Vs) enable transistors to achieve up to 10 14 The switching current ratio Ion / Ioff is increased, the off-state leakage current of the device is reduced, and the power consumption of the device is reduced.

[0033] 4. Since the transistors of this invention are used in integrated circuits such as memory circuits (e.g., DRAM) or non-memory circuits (e.g., logic circuits or control circuits of memory circuits), not only can the performance of integrated circuits be improved, but it is also beneficial to realize three-dimensional stacking, break through the process bottleneck of existing planar integrated circuit miniaturization, and achieve smaller chip size.

[0034] 5. When applied to memory circuits (or memory chips), it can achieve 4F in a single-level memory cell. 2(F is the minimum lithographic linewidth) While having the smallest area, it also has a longer data retention time. For example, the data retention time of a traditional memory cell is 64ms, while the data retention time of the memory cell of this invention is 300s.

[0035] 6. When an integrated circuit with this transistor is mounted inside a corresponding multilayer metal interconnect structure, the process can be simplified, the device size can be reduced, and the integration level of the device can be improved. In particular, when the integrated circuit with this transistor is a memory circuit, it can help shorten the signal transmission distance between the logic circuit and the memory chip, thereby improving the read and write speed of the memory and the reliability of data storage. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of a transistor structure in an integrated circuit according to an embodiment of the present invention.

[0037] Figure 2 This is a schematic cross-sectional view of a transistor in an integrated circuit according to an embodiment of the present invention along line AA'.

[0038] Figure 3 This is a top view schematic diagram of the memory circuit in an integrated circuit according to an embodiment of the present invention.

[0039] Figure 4 and Figure 5 These are schematic diagrams of the three-dimensional structure of a memory circuit along the word line and along the bit line in an integrated circuit according to an embodiment of the present invention.

[0040] Figure 6 and Figure 7 These are schematic diagrams of the three-dimensional structure of the memory circuit along the word line and bit line, and the three-dimensional structure of the contact structure in an integrated circuit according to an embodiment of the present invention.

[0041] Figure 8 This is a schematic diagram illustrating an example of a three-dimensional structure of a non-memory circuit in an integrated circuit according to an embodiment of the present invention.

[0042] Figure 9 This is a schematic diagram illustrating an example of a three-dimensional structure of a non-memory circuit in an integrated circuit according to another embodiment of the present invention. Detailed Implementation

[0043] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the invention. It should be understood that the invention can be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected" or "coupled" to other elements, it may be directly connected to other elements, or there may be intervening elements. Conversely, when an element is referred to as "directly connected" to other elements, there are no intervening elements. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "one side," and "the other side," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more, and "multi-layer" means two or more layers. When used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to determine the presence of possible features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0044] The technical solution proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0045] Please refer to Figures 1 to 2One embodiment of the present invention provides an integrated circuit having transistors, which is formed on any suitable substrate 100 and includes a plurality of transistors, for example, two or more transistors. At least one of the plurality of transistors includes an oxide insulating core 101, an oxide semiconductor layer 102, a gate dielectric layer 103, and a gate 104.

[0046] The oxide insulating core 101 is vertically disposed on the surface of the substrate, and the oxide semiconductor layer 102, the gate dielectric layer 103, and the gate 104 are sequentially stacked on the sidewalls of the oxide insulating core 101. Specifically, the oxide semiconductor layer 102 completely surrounds part or all of the sidewalls of the oxide insulating core 101, the gate dielectric layer 103 completely surrounds part or all of the sidewalls of the oxide semiconductor layer 102, and the gate 104 completely surrounds part of the sidewalls of the gate dielectric layer 103.

[0047] In other words, the oxide semiconductor layer 102, the gate dielectric layer 103, and the gate 104 are all tubular structures with the oxide insulating core 101 as the central axis. At this time, the two ends (i.e., the top and bottom ends) of the oxide semiconductor layer 102 and the gate dielectric layer 103 can be aligned or not aligned; the two ends (i.e., the top and bottom ends) of the gate dielectric layer 103 and the gate 104 can be aligned or not aligned.

[0048] In this embodiment, the top end of the oxide semiconductor layer 102 is higher than the top end of the gate 104, and the bottom end of the oxide semiconductor layer 102 is lower than the bottom end of the gate 104. Thus, the oxide semiconductor layer 102 in the area surrounded by the gate 104 serves as the channel region (not labeled) of the transistor, the oxide semiconductor layer 102 on one side of the channel region (i.e., below the lower side of the gate 104) serves as the source region 100s of the transistor, and the oxide semiconductor layer 102 on the other side of the channel region (i.e., above the upper side of the gate 104) serves as the drain region 100d of the transistor.

[0049] The integrated circuit of this embodiment forms a transistor with a vertical channel. The gate of the transistor completely surrounds the channel. Therefore, the aspect ratio of the channel depends on the perimeter of the oxide insulating core 101 and the height of the gate 104. By controlling the height of the gate 104 and the perimeter of the oxide insulating core 101, the aspect ratio of the transistor channel can be controlled, which is conducive to further miniaturization of the transistor size, improving gate control capability, improving short-channel effect, ensuring the performance of the miniaturized transistor, and thus facilitating the miniaturization and performance improvement of the integrated circuit.

[0050] It should be noted that, in this embodiment, the substrate 100 may include any one or more of any suitable conductor material, semiconductor material, and insulating material. For example, it may be a conventional semiconductor substrate such as silicon, germanium, gallium arsenide, or silicon-on-insulator, or an insulating substrate such as inorganic glass or plexiglass. The substrate may be a bare substrate without any devices, or it may be a device substrate after certain integrated circuit processing. For example, it may have corresponding logic transistors, resistors, diodes, power sources, capacitors, inductors, sensors, transceivers, receivers, antennas, microprocessors, optoelectronic devices, logic blocks, audio amplifiers, other memory devices, and other electronic components or multilayer metal interconnect structures formed inside it. In this embodiment, the transistors can be electrically connected to various electronic components associated with the substrate through corresponding metal interconnects to perform one or more related functions.

[0051] The cross-sectional shape of the oxide insulating core 101 can be any suitable shape, such as circular, elliptical, or polygonal (e.g., quadrilateral, pentagonal, hexagonal, etc.). The material of the oxide insulating core 101 can be any suitable oxide insulating material that is conducive to the growth and coverage of the oxide semiconductor layer 102, such as silicon oxide, silicon oxynitride, or a high-k dielectric with a dielectric constant k greater than 7, etc.

[0052] The oxide semiconductor layer 102 can be a single-layer film structure or a composite structure of multiple films stacked sequentially. Specifically, the material of the oxide semiconductor layer 102 includes at least one of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide (ITO), nickel oxide, niobium oxide, copper peroxide, and indium gallium zinc oxide. It can be deposited at a relatively low temperature (e.g., not higher than 200°C) to avoid damaging the electronic components already formed in the substrate.

[0053] The gate dielectric layer 103 and the gate 104 can each be a single-layer film structure or a composite structure formed by stacking multiple films. The material of the gate dielectric layer 103 may include silicon dioxide or a high-k dielectric with a dielectric constant k greater than 7. The material of the gate 104 may include a metal (including a single metal or alloy) and / or doped (n-type or p-type) polycrystalline silicon, wherein the metal is, for example, copper, ruthenium, palladium, platinum, cobalt, nickel, hafnium, zirconium, titanium, tantalum, aluminum, tantalum nitride, titanium nitride, tungsten, or an alloy formed of at least two of these. When the gate 104 is a polycrystalline silicon gate, the material of the gate dielectric layer 103 is preferably silicon dioxide; when the gate 104 is a metal gate, the material of the gate dielectric layer 103 is preferably a high-k dielectric.

[0054] The high-k dielectric described above may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Furthermore, the high-k dielectric that can be used in the gate dielectric layer 103 may include, but is not limited to, at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, the gate dielectric layer 103 may be annealed during transistor fabrication to improve the quality of the gate dielectric layer 103.

[0055] As an example, the oxide insulating core 101 is silicon oxide, the oxide semiconductor layer 102 is indium tin oxide (ITO), the gate dielectric layer 103 is hafnium oxide, and the gate 104 is a metal gate. Indium tin oxide (ITO) is a tin-doped wide-bandgap semiconductor with a bandgap of approximately 3.5 eV to 4.3 eV, exhibiting high carrier concentration. When its film thickness is significantly reduced, the carrier concentration can be correspondingly controlled, achieving a transition from metallic to semiconductor characteristics. Furthermore, ITO has a relatively low permittivity, allowing ITO transistors to better overcome short-channel effects and achieve nanoscale transistors with switching current ratios as high as 10^14 (Ion / Ioff). This enables smaller driving unit areas for individual transistors. Ion is the on-state current, and Ioff is the off-state current.

[0056] Furthermore, it should be understood that any suitable interlayer dielectric (ILD) material (not shown) may be provided around the transistor in this embodiment to insulate and isolate the transistor from surrounding devices. Interlayer dielectric (ILD) includes at least one of silicon oxide, silicon nitride, aluminum oxide, silicon oxynitride, etc.

[0057] It should be understood that the integrated circuit with the transistors described above in this embodiment can be any suitable integrated circuit, such as a memory module, device driver, power module, communication modem, processor module, logic module and other special-purpose modules, and can include multi-layer and multi-chip modules, which can ultimately form corresponding products, such as cameras, wireless devices, displays, chipsets, set-top boxes, game consoles, lighting equipment, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0058] Please refer to Figures 3 to 7 In this embodiment, the integrated circuit may include a memory circuit, which may specifically include at least one memory layer, at least one bit line layer, and at least one word line layer.

[0059] Each bit line layer has multiple bit lines BL extending along a first direction and isolated from each other (e.g., parallel to each other). Each word line layer has multiple word lines WL extending along a second direction and isolated from each other (e.g., parallel to each other). Each memory layer has several memory cells arranged in an array. Each memory cell is located at the intersection of a corresponding word line WL and a bit line WL. Each memory cell has a 1T1C structure, including a transistor MOS as described in this invention (i.e., 1T in the 1T1C structure) and a capacitor C (i.e., 1C in the 1T1C structure) electrically connected to one of the source and drain regions of the transistor MOS. Thus, a single-layer memory cell can have 4F 2 (F is the minimum lithographic linewidth) Minimum area.

[0060] Each bit line BL is electrically connected to the other of the source and drain regions of the transistor MOS of the plurality of memory cells arranged along the first direction in the corresponding memory layer. Each word line WL is electrically connected to the gate 104 of the plurality of memory cells arranged along the second direction in the corresponding memory layer. As an example, the gates 104 of the plurality of memory cells arranged along the second direction in the corresponding memory layer are connected as a single unit to form the corresponding word line WL.

[0061] In addition, the lower plate of the capacitor C of each memory cell can be electrically connected to either the source or drain region of the transistor MOS through a corresponding memory node contact CT, wherein the material of the memory node contact CT includes at least one of metal, metal silicide, or doped polysilicon.

[0062] For example, bit line BL is electrically connected to the source region of transistor MOS, and capacitor C is electrically connected to the drain region of transistor MOS.

[0063] Please refer to Figure 6 and Figure 7The memory circuit of this embodiment has multiple memory layers, and these memory layers are stacked sequentially along a third direction perpendicular to the first direction (i.e. the length extension direction of bit line BL) and the second direction (i.e. the length extension direction of word line WL). One end of the word line WL of the multiple memory layers is shortened or lengthened layer by layer along the third direction to form a stepped word line arrangement end, and one end of the bit line BL of the multiple memory layers is shortened or lengthened layer by layer along the third direction to form a stepped bit line arrangement end. Furthermore, the memory also includes word line contacts WVia for electrically leading the corresponding word lines WL to the outside, and bit line contacts BVia for electrically leading the corresponding bit lines BL to the outside. The word line contacts WVia of each layer of word lines WL are all disposed at the stepped word line arrangement end, so that the word line contacts WVia of adjacent two layers of word lines WL are staggered relative to each other in the first direction. Similarly, the bit line contacts BVia of each layer of bit lines BL are all disposed at the stepped bit line arrangement end, so that the bit line contacts BVia of adjacent two layers of bit lines BL are staggered relative to each other in the second direction. This increases the manufacturing process window for word line contacts WVia and bit line contacts BVia, avoids adverse effects on transistors MOS and capacitors C during the manufacturing of word line contacts WVia and bit line contacts BVia, and also facilitates further improvement in memory integration.

[0064] It should be understood that the memory circuit of this embodiment, since its transistors adopt the transistor structure of the present invention, can be fabricated on any substrate, and the stacking of the subsequent memory layer and the previous memory layer does not require bonding processes, etc. The subsequent memory layer can be directly formed on the previous memory layer through a compatible integrated circuit back-end manufacturing process BEOL.

[0065] As an example, the memory in this embodiment can be directly mounted above or below a corresponding multilayer metal interconnect structure (not shown) via the back-end integrated circuit manufacturing process BEOL. The multilayer metal interconnect structure has multiple layers of metal interconnects (not shown) and an inter-metal dielectric layer for insulating and isolating metal interconnects (not shown) between the same layer and different layers. The word line WL of the corresponding memory layer is electrically connected to a corresponding portion of the metal interconnects in the multilayer metal interconnect structure through a corresponding word line contact WVia. The bit line BL of the corresponding memory layer is electrically connected to another corresponding portion of the metal interconnects in the multilayer metal interconnect structure through a corresponding bit line contact BVia.

[0066] As another example, the memory in this embodiment is disposed inside a corresponding multilayer metal interconnect structure (not shown), that is, its word line WL and bit line BL can be formed with the metal interconnects of the corresponding layers of the multilayer metal interconnect structure (not shown) by deposition and etching of the same metal film. Specifically, the multilayer metal interconnect structure has multiple layers of metal interconnects (not shown) and an inter-metal dielectric layer (not shown) for insulating and isolating the metal interconnects between the same layer and different layers. The corresponding memory layer is disposed in the corresponding inter-metal dielectric layer. The word line WL and bit line BL of the memory layer are metal interconnects of different layers in the multilayer metal interconnect structure. The word line WL of the same layer is a metal interconnect of the same layer in the multilayer metal interconnect structure, and the bit line BL of the same layer is a metal interconnect of the same layer in the multilayer metal interconnect structure.

[0067] The memory circuit in this embodiment is compatible with the back-end multilayer metal interconnect process of integrated circuits, enabling a three-dimensional stacked architecture design of multilayer memory layers. This overcomes the current bottleneck in planar memory miniaturization, achieving memory chips with higher storage capacity and lower power consumption. It can achieve a single-layer memory cell with 4F... 2 (F is the minimum lithographic linewidth) While minimizing the area, it also enables the memory to have a longer data retention time.

[0068] Furthermore, it is worth noting that the first direction and the second direction in the above embodiments can be orthogonal or non-orthogonal. For example, the angle between the first direction and the second direction after they intersect is 45°, etc. The present invention does not make specific limitations on this. As long as the intersection of the first direction and the second direction can be beneficial to device miniaturization and improved integration, that is.

[0069] In other embodiments of the present invention, the integrated circuit of the present invention may also include non-memory circuits, which may be logic circuits (e.g., inverters, operational amplifiers, etc.) or read / write control circuits of memory circuits, etc.

[0070] Please refer to Figure 8The non-memory circuit may have only one transistor device layer formed on the substrate 100, and this transistor device layer has at least one transistor of the present invention. When there are multiple transistors in the same transistor device layer, these transistors may be arranged in an array. Optionally, at least one first conductive structure 100a is formed in the substrate 100, and the first conductive structure 100a is electrically connected to the source region of at least one transistor. The shape, structure, and position of the first conductive structure 100a depend on the requirements of the integrated circuit in which the transistor to be formed is located. The material of the first conductive structure 100a can be any suitable conductive material, such as at least one of metal, graphite, doped semiconductor (e.g., doped polycrystalline silicon or doped single-crystal silicon), and metal silicide. The first conductive structure 100a may be a conductive plug, a metal wire, or an ion-doped region, etc. As an example, please refer to Figure 9 The first conductive structure 100a is a strip structure and is arranged at equal intervals. The insulating isolation structure 100b separates the adjacent first conductive structures 100a. The insulating isolation structure 100b can be a shallow trench isolation structure, a local field oxidation isolation structure, or a patterned interlayer dielectric layer, or any other suitable structure.

[0071] Please refer to Figure 9 In other embodiments of the present invention, the non-memory circuit may have at least two transistor device layers, each transistor device layer having at least one transistor of the present invention. Transistors on the same or different layers may be connected in parallel or series using appropriate multilayer metal interconnect processes, rewiring processes, or electrical contact processes to realize the function of the non-memory circuit.

[0072] It should be understood that transistors in different layers of this non-memory circuit may or may not be aligned, and therefore the position, shape, etc. of the transistors depend on the electrical connections required by the integrated circuit.

[0073] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the present invention.

Claims

1. An integrated circuit having transistors, characterized in that, include: Base; A first conductive structure is located on the substrate; A plurality of transistors are located on the first conductive structure, and each of the transistors includes: Oxide insulating core post; An oxide semiconductor layer, surrounding a portion of the height of the insulating core pillar; Gate, the portion of the height surrounding the oxide semiconductor layer; A gate dielectric layer is located between the gate and the oxide semiconductor layer; In this configuration, the oxide semiconductor layer in the gate surrounding region serves as the channel region of the transistor, the oxide semiconductor layer on one side of the channel region serves as the source region of the transistor, the oxide semiconductor layer on the other side of the channel region serves as the drain region of the transistor, and the source region is electrically connected to the first conductive structure.

2. The integrated circuit as described in claim 1, characterized in that, The oxide semiconductor layer is a single-layer film structure or a composite structure of multiple films stacked sequentially. The material of the oxide semiconductor layer includes at least one of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, and indium gallium zinc oxide.

3. The integrated circuit as described in claim 1, characterized in that, The material of the gate dielectric layer includes silicon oxide and / or a high-k dielectric with a dielectric constant k greater than 7, and the material of the gate includes metal and / or doped polysilicon.

4. The integrated circuit as described in claim 1, characterized in that, The multiple transistors are distributed in the same layer or in a three-dimensional stacked multilayer structure.

5. The integrated circuit as described in any one of claims 1 to 4, characterized in that, The integrated circuit includes a memory circuit, the memory circuit having: At least one memory layer having a plurality of memory cells arranged in an array, each memory cell having a transistor, and a data storage structure electrically connected to one of the source and drain regions of the transistor. At least one bit line layer having multiple bit lines extending along a first direction and isolated from each other, each bit line being electrically connected to the other of the source and drain regions of the transistors of multiple memory cells arranged along the first direction in the corresponding memory layer. At least one word line layer having multiple word lines extending along a second direction and isolated from each other, each word line being electrically connected to the gate of a plurality of memory cells arranged along the second direction in a corresponding memory layer; Each memory cell in each memory layer is located at the intersection of the corresponding word line and bit line.

6. The integrated circuit as described in claim 4, characterized in that, The gates of the plurality of memory cells arranged along the second direction in the corresponding memory layer are connected together to form the corresponding word lines.

7. The integrated circuit as described in claim 4, characterized in that, The multiple memory layers are stacked sequentially along a third direction perpendicular to the first direction and the second direction, and one end of the word line of the multiple memory layers is shortened or lengthened layer by layer to form a stepped word line arrangement end, and one end of the bit line of the multiple memory layers is shortened or lengthened layer by layer to form a stepped bit line arrangement end.

8. The integrated circuit as described in claim 7, characterized in that, It also includes word line contacts for electrically leading the corresponding word lines to the outside, and bit line contacts for electrically leading the corresponding bit lines to the outside; wherein the word line contacts of each layer of word lines are disposed at the stepped word line arrangement end in a staggered arrangement, and the bit line contacts of each layer of bit lines are disposed at the stepped bit line arrangement end in a staggered arrangement.

9. The integrated circuit as described in claim 7, characterized in that, The integrated circuit further includes a multilayer metal interconnect structure. The memory circuit is mounted above or below the corresponding multilayer metal interconnect structure. The multilayer metal interconnect structure has multiple metal interconnect lines and an inter-metal dielectric layer for insulating and isolating metal interconnect lines in the same layer and different layers. The word lines of the corresponding memory layer are electrically connected to a corresponding portion of the metal interconnect lines in the multilayer metal interconnect structure through corresponding word line contacts. The bit lines of the corresponding memory layer are electrically connected to another corresponding portion of the metal interconnect lines in the multilayer metal interconnect structure through corresponding bit line contacts. Alternatively, the integrated circuit further includes a multilayer metal interconnect structure, with the memory circuit disposed inside the corresponding multilayer metal interconnect structure. The multilayer metal interconnect structure has multiple layers of metal interconnects and an inter-metal dielectric layer for insulating and isolating metal interconnects between metal interconnects of the same layer and different layers. The corresponding memory layer is disposed in the corresponding inter-metal dielectric layer. The word lines and bit lines of the memory layer are metal interconnects of different layers in the multilayer metal interconnect structure. The word lines of the same layer are metal interconnects of the same layer in the multilayer metal interconnect structure, and the bit lines of the same layer are metal interconnects of the same layer in the multilayer metal interconnect structure.

10. The integrated circuit according to any one of claims 1 to 4, characterized in that, The integrated circuit includes a non-memory circuit having at least one transistor device layer, the transistor device layer having at least one of the aforementioned transistors; the transistors in the same or different layers of the non-memory circuit are connected in series or in parallel.

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