Semiconductor structure and manufacturing method thereof

Abstract

The embodiment of the invention relates to the field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The conductive contact layers are located on part of the surface of the substrate and comprise a plurality of first conductive contact layers and a plurality of second conductive contact layers, and orthographic projections of the first conductive contact layers on the surface of the substrate surround the second conductive contact layers; the plurality of lower electrode layers are positioned on the top surfaces of the plurality of second conductive contact layers; the dielectric layer covers the top surface and part of the side surface of the lower electrode layer, and the region, close to the substrate, of the dielectric layer on the periphery of the lower electrode layer protrudes towards the outer side of the substrate along the direction parallel to the surface of the substrate; the upper electrode layer covers the top surface and the side surface of the dielectric layer; the first insulating layer is located on the surfaces, away from the substrate, of the first conductive contact layers, part of the dielectric layer is located on the part, away from the substrate, of the surface of the first insulating layer, and the first insulating layer is located between the first conductive contact layers and the dielectric layer. And electric leakage can be reduced at least.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a method for manufacturing the same. Background Technology

[0002] With the continuous development of mobile devices, battery-powered mobile devices such as mobile phones, tablets, and wearable devices are increasingly used in our lives. As an indispensable component in mobile devices, memory has generated huge demands for smaller size and integration.

[0003] Currently, Dynamic Random Access Memory (DRAM) is widely used in mobile devices due to its fast transfer speed. DRAM consists of capacitors for storing charge and transistors connected to the capacitors. DRAM stores data by storing charge on the capacitors, requiring the capacitors to be regularly charged and discharged at intervals of several milliseconds.

[0004] However, this semiconductor structure still has some leakage problems. Summary of the Invention

[0005] This disclosure provides a semiconductor structure and a method for manufacturing the same, which at least helps to reduce leakage current in the semiconductor structure.

[0006] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, including: a substrate; a conductive contact layer, the conductive contact layer being located on a portion of the surface of the substrate, and a plurality of the conductive contact layers being discretely disposed on the surface of the substrate, the conductive contact layer including a plurality of first conductive contact layers and a plurality of second conductive contact layers, the orthographic projection of the plurality of first conductive contact layers on the surface of the substrate surrounding the plurality of second conductive contact layers; a plurality of lower electrode layers, the plurality of lower electrode layers being located on a portion of the substrate, and the plurality of lower electrode layers being arranged in an array on the surface of the substrate, the plurality of lower electrode layers being located on the top surface of the plurality of conductive contact layers away from the substrate; and a dielectric layer, the dielectric layer... The dielectric layer, located around the plurality of lower electrode layers, protrudes from the substrate in a direction parallel to the substrate surface toward the direction away from the plurality of lower electrode layers, covering the top surface of the dielectric layer away from the substrate and a portion of the dielectric layer; an upper electrode layer, covering the top surface of the dielectric layer away from the substrate and the side surface of the dielectric layer; a first insulating layer, located on the surface of the plurality of first conductive contact layers away from the substrate, and a portion of the dielectric layer is located on the surface of the first insulating layer away from the substrate, the first insulating layer being located between the plurality of first conductive contact layers and the dielectric layer.

[0007] According to other embodiments of this disclosure, the thickness of the first insulating layer is 20-60 nm.

[0008] According to other embodiments of this disclosure, the upper electrode layer specifically includes: a first upper electrode layer, the first upper electrode layer covering the top surface of the dielectric layer away from the substrate, and the first upper electrode layer covering the side surface of the dielectric layer; a second upper electrode layer, the second upper electrode layer covering the top surface of the first upper electrode layer away from the substrate, and the second upper electrode layer covering the side surface of the first upper electrode layer; wherein the thickness of the second upper electrode layer is greater than the thickness of the first upper electrode layer.

[0009] According to other embodiments of this disclosure, the material of the first upper electrode layer is different from the material of the second upper electrode layer.

[0010] According to other embodiments of this disclosure, it further includes: a second insulating layer covering the side and top surfaces of the upper electrode layer, and the second insulating layer being in contact with the first insulating layer, wherein a region of the second insulating layer near the substrate protrudes in a direction parallel to the surface of the substrate toward a direction away from the plurality of lower electrode layers.

[0011] According to other embodiments of this disclosure, the second insulating layer is made of the same material as the first insulating layer.

[0012] According to other embodiments of this disclosure, the system further includes: a first support layer located above the substrate and filling the gaps between the conductive contact layers, wherein the first insulating layer is located on a portion of the surface of the first support layer; a second support layer located between adjacent lower electrode layers, wherein the vertical distance between the second support layer and the surface of the substrate is less than the vertical distance between the top surface of the lower electrode layer and the surface of the substrate; and a third support layer located between adjacent lower electrode layers, wherein the vertical distance between the third support layer and the surface of the substrate is greater than the vertical distance between the second support layer and the surface of the substrate, wherein the first support layer, the second support layer, and the third support layer constitute a support layer.

[0013] According to other embodiments of this disclosure, it further includes: a dielectric layer located on the surface of the substrate, and the lower electrode layer located on the side of the dielectric layer away from the substrate.

[0014] According to some embodiments of this disclosure, another aspect of this disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a substrate; forming a conductive contact layer, the conductive contact layer being located on a portion of the surface of the substrate, and a plurality of the conductive contact layers being discretely disposed on the surface of the substrate, the conductive contact layer including a plurality of first conductive contact layers and a plurality of second conductive contact layers, the orthographic projection of the plurality of first conductive contact layers on the surface of the substrate surrounding the plurality of second conductive contact layers; forming a first insulating layer, the first insulating layer being located on the surface of the plurality of first conductive contact layers away from the substrate; forming a plurality of lower electrode layers, the plurality of lower electrode layers being located on a portion of the substrate, and the... A plurality of lower electrode layers are arranged in an array on the surface of the substrate, the plurality of lower electrode layers being located on the top surface of the plurality of second conductive contact layers away from the substrate; a dielectric layer is formed, the dielectric layer covering the top surface of the plurality of lower electrode layers away from the substrate and a portion of the side surfaces of the plurality of lower electrode layers, the dielectric layer being located on a portion of the surface of the first insulating layer away from the substrate, and the dielectric layer located around the plurality of lower electrode layers protruding in a direction parallel to the substrate surface toward the direction away from the plurality of lower electrode layers in the region near the substrate; an upper electrode layer is formed, the upper electrode layer covering the top surface of the dielectric layer away from the substrate, and the upper electrode layer covering the side surfaces of the dielectric layer.

[0015] According to other embodiments of this disclosure, forming the first insulating layer specifically includes: forming a first insulating film, the first insulating film being located on the surface of the conductive contact layer away from the substrate, and the orthographic projection of the first insulating film onto the substrate covering the entire surface of the substrate; forming a photoresist layer, the photoresist layer being located on the surface of the first insulating film away from the substrate, and the photoresist layer having an opening located in the central region of the photoresist layer, through which further etching can expose the entire top surface of the plurality of second conductive contact layers away from the substrate; using the photoresist layer as a mask, etching the first insulating film along the opening to obtain the first insulating layer.

[0016] According to other embodiments of this disclosure, forming the upper electrode layer includes: forming a first upper electrode layer, the first upper electrode layer covering the top surface of the dielectric layer away from the substrate, and the first upper electrode layer covering the side surface of the dielectric layer; forming a second upper electrode layer, the second upper electrode layer covering the top surface of the first upper electrode layer away from the substrate, and the second upper electrode layer covering the side surface of the first upper electrode layer; wherein the thickness of the second upper electrode layer is greater than the thickness of the first upper electrode layer.

[0017] According to other embodiments of this disclosure, after forming the upper electrode layer, the method further includes: forming a second insulating layer, the second insulating layer covering the side of the upper electrode layer and in contact with the first insulating layer.

[0018] The technical solution provided in this disclosure has at least the following advantages: In the semiconductor structure technical solution provided in the embodiments of this disclosure, the semiconductor structure includes a substrate, a conductive contact layer located on a portion of the substrate surface, and multiple conductive contact layers are discretely separated on the substrate surface. The conductive contact layer includes multiple first conductive contact layers and multiple second conductive contact layers. The orthographic projection of the multiple first conductive contact layers on the substrate surface surrounds the multiple second conductive contact layers. Multiple lower electrode layers are located on a portion of the substrate, and the multiple lower electrode layers are located on the top surface of the multiple second conductive contact layers away from the substrate. A dielectric layer covers the top surface and a portion of the side surface of the multiple lower electrode layers. The region of the dielectric layer located around the multiple lower electrode layers near the substrate protrudes in a direction parallel to the substrate surface toward a direction away from the multiple lower electrode layers. An upper electrode layer covers the top surface and the side surface of the dielectric layer. A first insulating layer is located on the portion of the multiple first conductive contact layers away from the substrate, and the first insulating layer is located between the multiple first conductive contact layers and the dielectric layer. In related technologies, semiconductor structures do not have a first insulating layer. The portion of the dielectric layer protruding from the substrate towards the direction away from the lower electrode layer directly contacts the surface of the first conductive contact layer. Furthermore, a top electrode layer is located on the top surface of this portion of the dielectric layer, with only one dielectric layer between the top electrode layer and the first conductive contact layer. However, the dielectric layer is relatively thin. During the etching process for manufacturing the semiconductor structure, the edges of the dielectric layer are easily etched open, forming leakage channels. This causes electrical contact between the top electrode layer and the first conductive contact layer, resulting in leakage and affecting the performance of the semiconductor structure. In the semiconductor structure provided by this disclosure, a first insulating layer is disposed on the surface of the first conductive contact layer away from the substrate, and the dielectric layer is located on the portion of the first insulating layer away from the substrate. The first insulating layer is situated between the first conductive contact layer and the dielectric layer. The first insulating layer can isolate the top electrode layer from the first conductive contact layer. Even if the edges of the dielectric layer are etched open during the etching process for manufacturing the semiconductor structure, the top electrode layer and the first conductive contact layer will not make electrical contact, preventing leakage in the semiconductor structure and ensuring its performance is not affected. Attached Figure Description

[0019] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a partial cross-sectional three-dimensional structural diagram of a semiconductor structure; Figure 2This is a cross-sectional perspective view of a semiconductor structure provided in an embodiment of the present disclosure; Figure 3 A partial cross-sectional three-dimensional structural schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure; Figure 4 This is a cross-sectional structural diagram of a semiconductor structure provided in an embodiment of the present disclosure; Figures 5 to 16 This is a cross-sectional structural diagram corresponding to each step of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure. Detailed Implementation

[0021] As can be seen from the background technology, current semiconductor structures have certain leakage problems.

[0022] refer to Figure 1 , Figure 1 This is a partial cross-sectional three-dimensional structural diagram of a semiconductor structure. The semiconductor structure includes: a substrate 10; conductive contact layers 20, which are located on a portion of the surface of the substrate 10, and multiple conductive contact layers 20 are discretely separated on the surface of the substrate 10; multiple lower electrode layers 30, which are located on a portion of the substrate 10, and are discretely separated on the surface of the substrate 10; a dielectric layer 40, which covers the top surface of the multiple lower electrode layers 30 away from the substrate 10 and a portion of the side surfaces of the lower electrode layers 30, and the region of the dielectric layer 40 located around the multiple lower electrode layers 30 near the substrate 10 protrudes in a direction parallel to the substrate 10 toward the direction away from the lower electrode layers 30; and an upper electrode layer 50, which covers the top surface of the dielectric layer 40 away from the substrate 10 and the side surfaces of the dielectric layer 40.

[0023] In manufacturing this semiconductor structure, after forming the substrate 10, conductive contact layer 20, and lower electrode layer 30, a dielectric layer 40 is formed covering the top surface of multiple lower electrode layers 30, parts of the sides of the lower electrode layers 30, and the top surface of the conductive contact layer 20. Then, an upper electrode layer 50 is formed covering the top and sides of the dielectric layer 40. Afterward, the dielectric layer 40 and the upper electrode layer 50 need to be etched so that the dielectric layer 40 and the upper electrode layer 50 only cover the top surface of the conductive contact layer 20 near the lower electrode layer 30. During etching, it is easy to etch the edge region of the dielectric layer 40, forming a side cut. The edge of the dielectric layer 40 located on the surface of the conductive contact layer 20 is partially removed, causing electrical contact between the upper electrode layer 50 above the dielectric layer 40 and the conductive contact layer 20 below the dielectric layer 40, resulting in leakage and affecting the performance of the semiconductor structure.

[0024] Analysis revealed that in the aforementioned semiconductor structure, during the manufacturing process, a portion of the dielectric layer is easily etched away, forming a side cutout. This causes leakage current when the upper electrode layer 50 and the conductive contact layer 20 make electrical contact. If a semiconductor structure could be provided that prevents electrical contact between the upper electrode layer 50 and the conductive contact layer 20 due to the side cutout of the dielectric layer 40, the aforementioned problem could be improved.

[0025] In the semiconductor structure provided in this disclosure, a conductive contact layer and multiple lower electrode layers are provided on a portion of the surface of a substrate. The conductive contact layer includes multiple first conductive contact layers and multiple second conductive contact layers. The orthographic projection of the multiple first conductive contact layers onto the substrate surface surrounds the multiple second conductive contact layers. The multiple lower electrode layers are located on the top surface of the multiple second conductive contact layers away from the substrate. A dielectric layer covers the top surface and part of the side surface of the multiple lower electrode layers. The dielectric layer in the region near the substrate protrudes in a direction parallel to the substrate surface away from the multiple lower electrode layers. An upper electrode layer covers the top surface and side surface of the dielectric layer away from the substrate. Furthermore, the semiconductor structure also includes a first insulating layer located on the surface of the first conductive contact layers away from the substrate, and a dielectric layer located on the portion of the first insulating layer away from the substrate. The first insulating layer is located between the first conductive contact layer and the dielectric layer. The upper electrode layer and the first conductive contact layer are not only separated by a dielectric layer, but also by a first insulating layer. Even when the edge of the dielectric layer is etched away to form a side hole during the manufacturing process of the semiconductor structure, the upper electrode layer and the first conductive contact layer are still separated by a first insulating layer, so that the upper electrode layer and the first conductive contact layer will not make electrical contact, thereby reducing leakage in the semiconductor structure and improving the performance of the semiconductor structure.

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the various embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of the present disclosure to enable the reader to better understand the present disclosure. However, the technical solutions claimed in the present disclosure can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0027] Figures 2 to 3 This is a cross-sectional perspective view of a semiconductor structure provided in an embodiment of the present disclosure, wherein, Figure 3 for Figure 2 A magnified view of a portion of the area, magnified at... Figure 2 It is indicated by a dashed box. Figure 4 This is a schematic cross-sectional view of the semiconductor structure provided in an embodiment of the present disclosure, with the cross-sectional view directed toward the substrate. The top surface of the conductive contact layer is parallel to the surface of the substrate.

[0028] refer to Figures 2 to 4The semiconductor structure includes: a substrate 100; a conductive contact layer 110, which is located on a portion of the surface of the substrate 100, and a plurality of conductive contact layers 110 are discretely disposed on the surface of the substrate 100, the conductive contact layer 110 including a plurality of first conductive contact layers 111 and a plurality of second conductive contact layers 112, the orthographic projection of the plurality of first conductive contact layers 111 on the surface of the substrate 100 surrounding the plurality of second conductive contact layers 112; and a plurality of lower electrode layers 120, which are located on a portion of the substrate 100. Multiple lower electrode layers 120 are arrayed on the surface of the substrate 100, and the multiple lower electrode layers 120 are located on the top surface of the multiple second conductive contact layers 112 away from the substrate 100; a dielectric layer 130 covers the top surface of the multiple lower electrode layers 120 away from the substrate 100 and part of the side surfaces of the multiple lower electrode layers 120, and the region of the dielectric layer 130 located around the multiple lower electrode layers 120 near the substrate 100 protrudes in a direction parallel to the surface of the substrate 100 toward a direction away from the multiple lower electrode layers 120, and the protruding region is formed by... Figure 3 The dashed box in the figure shows: an upper electrode layer 140, which covers the top surface of the dielectric layer 130 away from the substrate 100 and also covers the side surface of the dielectric layer 130; a first insulating layer 150, which is located on the surface of the first conductive contact layer 111 away from the substrate 100, and a portion of the dielectric layer 130 is located on the portion of the first insulating layer 150 away from the substrate 100, and the first insulating layer 150 is located between the first conductive contact layer 111 and the dielectric layer 130.

[0029] In the aforementioned semiconductor structure, a first insulating layer 150 is located between the dielectric layer 130 and the first conductive contact layer 111, and an upper electrode layer 140 is provided on the top surface of the dielectric layer 130 away from the substrate 100. Even during the manufacturing process of the semiconductor structure, if the dielectric layer 130 is partially removed due to etching, resulting in side cuts, the first insulating layer 150 is still provided between the upper electrode layer 140 above the dielectric layer 130 and the first conductive contact layer 111, ensuring that the upper electrode layer 140 and the first conductive contact layer 111 do not make electrical contact. This reduces leakage problems in the semiconductor structure and improves its performance.

[0030] The embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings.

[0031] The substrate 100 may include multiple discrete active regions and isolation structures (not shown) located between adjacent active regions. The multiple discrete active regions may be arranged in an array on the substrate, and the isolation structures may surround the active regions, with an isolation structure between every two adjacent active regions. The active regions may be made of silicon and are used to form transistors in a semiconductor structure in subsequent steps. The isolation structures may include silicon oxide and are used to isolate different active regions. Additionally, the substrate 100 may also have word line structures and bit line structures. The word line structures can act as switches for the transistors in the active regions and are connected to the gates of the transistors. The bit line structures are connected to the drains of the transistors and can be used to read or write the stored state of the basic cells.

[0032] In some embodiments, the semiconductor structure may further include a dielectric layer 160 located on the surface of the substrate 100, and a lower electrode layer 120 located on the side of the dielectric layer 160 away from the substrate 100. The material of the dielectric layer 160 may include SiOC.

[0033] The conductive contact layer 110 covers a portion of the surface of the substrate 100, and multiple conductive contact layers 110 are discretely distributed on the surface of the substrate 100. If the semiconductor structure has a dielectric layer 160, the conductive contact layer 110 covers the surface of the dielectric layer 160 away from the substrate 100. The material of the conductive contact layer 110 is a conductive material, which may include titanium nitride, tungsten, titanium silicide, titanium oxide, or tungsten oxide, etc.

[0034] In some embodiments, the semiconductor structure may include a conductive plug 200, which may be located on the surface of the substrate 100 and electrically connect the substrate 100 to other devices. The material of the conductive plug 200 may be the same as the material of the conductive contact layer 110, and the material of the conductive plug 200 may include titanium nitride.

[0035] refer to Figure 3 as well as Figure 4 The semiconductor structure has multiple discrete lower electrode layers 120. The orthographic projections of the multiple lower electrode layers 120 onto the surface of the substrate 100 are all located in the central region. The orthographic projection of the first conductive contact layer 111 onto the surface of the substrate 100 surrounds the multiple lower electrode layers 120. (Reference) Figure 4 The central area is Figure 4 The area outside the dashed box is the outer region. The lower electrode layer 120 is one electrode of the capacitor structure in the semiconductor structure. The material of the lower electrode layer 120 is a conductive material. The material of the lower electrode layer 120 may include titanium nitride. Multiple lower electrode layers 120, together with the upper electrode layer, form multiple capacitors. When the semiconductor structure is used, multiple capacitors can be charged and discharged simultaneously, thereby increasing the capacitance.

[0036] In some embodiments, the plurality of lower electrode layers 120 may be elongated columnar structures. The height of the plurality of lower electrode layers 120 relative to the surface of the substrate 100 is greater than the thickness of the substrate 100.

[0037] The orthographic projection area of ​​the multiple lower electrode layers 120 on the surface of the substrate 100 can be a circular area, a rectangular area, or an irregularly shaped area. Correspondingly, the orthographic projection area of ​​the first conductive contact layer 111 surrounding the multiple lower electrode layers 120 on the surface of the substrate 100 can be an annular area, a rectangular annular area, or an annular area of ​​other shapes, which will not be listed here.

[0038] The dielectric layer 130 is a semiconductor structure that isolates the lower electrode layer 120 and the upper electrode layer 140. Between adjacent lower electrode layers 120, the dielectric layer 130 can cover the sides of the lower electrode layers 120 and can form a closed dielectric layer 130 connected end-to-end along the region between adjacent lower electrode layers 120. The closed dielectric layer 130 may contain an upper electrode layer. On the outermost side of the lower electrode layer 120, in the region near the substrate 100, the dielectric layer 130 located on the outer surface of the lower electrode layers 120 protrudes in a direction parallel to the substrate surface, moving away from the lower electrode layers 120. That is, the bottom of the dielectric layer 130 covering the outermost surface of the lower electrode layers 120 extends towards the periphery of the substrate 100. This protruding portion of the dielectric layer 130 covers the surface of the first insulating layer 150, and the protruding portion... Figure 3 It is shown in the dashed box.

[0039] In some embodiments, the thickness of the dielectric layer 130 can be 3nm-9nm. For example, the thickness of the dielectric layer 130 can be 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, etc. If the thickness of the dielectric layer 130 is too small, its isolation effect between the upper and lower electrode layers may be weak, affecting the performance of the semiconductor structure. If the thickness of the dielectric layer 130 is too large, it will not only waste material but also increase the size of the semiconductor structure. Therefore, the thickness of the dielectric layer 130 needs to be selected within a suitable range. When the thickness of the dielectric layer 130 is 3nm-9nm, the dielectric layer 130 can provide good isolation between the upper and lower electrode layers without causing waste.

[0040] In some embodiments, the dielectric layer 130 may be made of a high-k material. Using a high-k dielectric material for the dielectric layer 130 can improve the performance of the semiconductor structure, reduce its power consumption, and enhance the charge storage capacity of the capacitor structure. Specifically, in some embodiments, the dielectric layer 130 may include AlO. In other embodiments, the dielectric layer 130 may also include one or more of hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, tantalum oxide, niobium oxide, and strontium oxide.

[0041] The upper electrode layer 140 is the other electrode of the capacitor structure corresponding to the lower electrode layer 120 in the semiconductor structure. The upper electrode layer 140 between adjacent lower electrode layers 120 can be located within a closed dielectric layer 130 between adjacent lower electrode layers 120. That is, between adjacent lower electrode layers 120, the dielectric layer 130 covers the sides of the lower electrode layers 120, the upper electrode layer 140 covers the sides of the dielectric layer 130, and the upper electrode layer 140 fills the gaps between the multiple lower electrode layers 120. The material of the upper electrode layer 140 includes a conductive material.

[0042] In some embodiments, the upper electrode layer 140 may specifically include two layers: a first upper electrode layer 141 and a second upper electrode layer 142. The first upper electrode layer 141 covers the top surface of the dielectric layer 130 away from the substrate 100 and also covers the side surfaces of the dielectric layer 130. The second upper electrode layer 142 covers the top surface of the first upper electrode layer 141 away from the substrate 100 and also covers the side surfaces of the first upper electrode layer 141. The thickness of the second upper electrode layer 142 is greater than the thickness of the first upper electrode layer 141. In other words, the first upper electrode layer 141 is located on the surface of the dielectric layer 130, and the second upper electrode layer 142 is located on the surface of the first upper electrode layer 141.

[0043] Specifically, between adjacent lower electrode layers 120, a first upper electrode layer 141 can cover the side surface of the dielectric layer 130 and can form a closed first upper electrode layer 141 connected end to end along the region between adjacent dielectric layers 130. A second upper electrode layer 142 can be present inside the closed first upper electrode layer 141. The second upper electrode layer 142 is located on the surface of the first upper electrode layer 141 and fills the gaps between adjacent lower electrode layers 120. Outside the outermost lower electrode layer 120, the first upper electrode layer 141 covers all the side surfaces of the dielectric layer 130 and the bottom surface above the lower electrode layers 120. In the region near the substrate 100, the first upper electrode layer 141 also covers the top surface of the dielectric layer 130 protruding away from the lower electrode layers 120. Similarly, outside the outermost lower electrode layer 120, the second upper electrode layer 142 covers all sides of the first upper electrode layer 141 and the bottom surface above the plurality of lower electrode layers 120. In the region near the substrate 100, the second upper electrode layer 142 also covers the top surface of the first upper electrode layer 141 protruding toward the region away from the plurality of lower electrode layers 120.

[0044] In some embodiments, the materials of the first upper electrode layer 141 and the second upper electrode layer 142 may be different. The first upper electrode layer 141 and the second upper electrode layer 142 may be made of two different conductive materials. For example, the materials of the first upper electrode layer 141 and the second upper electrode layer 142 may include titanium nitride, tungsten, titanium silicide, titanium oxide, or tungsten oxide. In some embodiments, the material of the first upper electrode layer 141 may include TiN; and the material of the second upper electrode layer 142 may include SiGe. Dividing the upper electrode layer 140 into two layers—a first upper electrode layer 141 and a second upper electrode layer 142—with different thicknesses and materials can better utilize the role of the upper electrode layer 140 in the capacitor structure, improve the performance of the semiconductor structure, and increase the efficiency of the semiconductor structure.

[0045] The first insulating layer 150 is a structure that covers the top surface of the first conductive contact layer 111 and is located between the first conductive contact layer 111 and the dielectric layer 130. Specifically, the protruding portions of the dielectric layer 130 and the upper electrode layer 140 near the substrate 100 are located on a portion of the top surface of the first insulating layer 150. In a direction perpendicular to the surface of the substrate 100, the first insulating layer 150 is also present between the first conductive contact layer 111, the dielectric layer 130, and the upper electrode layer 140. The first insulating layer 150 can isolate the upper electrode layer 140 from the first conductive contact layer 111, increasing the distance between them, thereby making it difficult for electrical connections to occur between the upper electrode layer 140 and the first conductive contact layer 111, and reducing the likelihood of leakage in the semiconductor structure.

[0046] Specifically, in the fabrication of the dielectric layer 130 and the upper electrode layer 140, a dielectric layer 130 covering the entire surface of the upper electrode layer 140 and the entire surface of the first insulating layer 150 must first be formed. Then, the upper electrode layer 140 is formed on the dielectric layer 130, covering the entire surface of the dielectric layer 130. Next, an etching process is used to remove the dielectric layer 130 in the peripheral region to expose the first insulating layer 150, which covers the first conductive contact layer 111. During the etching process, side cuts can easily occur, creating gaps in the dielectric layer 130, which has a high dielectric constant. However, since the upper electrode layer 140 and the first conductive contact layer 111 are connected not only by the dielectric layer 130 but also by the first insulating layer 150, there is no electrical connection between them, and leakage will not occur.

[0047] In some embodiments, the thickness of the first insulating layer 150 can be 20-60 nm. For example, the thickness of the first insulating layer 150 can be 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, or 60 nm. If the thickness of the first insulating layer 150 is too small, it may not effectively isolate the upper electrode layer 140 and the first conductive contact layer 111. If the thickness of the first insulating layer 150 is too large, it will occupy a large area in contact with the side of the lower electrode layer 120, leaving the dielectric layer 130 and the upper electrode layer 140 in contact with the remaining side of the lower electrode layer 120 with too small an area, affecting the performance of the semiconductor structure. Therefore, the thickness of the first insulating layer 150 needs to be selected within a suitable range. When the thickness of the first insulating layer 150 is 20-60 nm, it can effectively isolate the upper electrode layer 140 and the conductive contact layer 110 while ensuring that the semiconductor structure has superior performance.

[0048] The first insulating layer 150 is made of an insulating material. In some embodiments, the material of the first insulating layer 150 may include SiN. In other embodiments, the material of the first insulating layer 150 may be other materials.

[0049] In some embodiments, a second insulating layer 170 may be included. The second insulating layer 170 covers the sides and top surface of the upper electrode layer 140 and is in contact with the first insulating layer 150. The region of the second insulating layer 170 near the substrate 100 protrudes in a direction parallel to the surface of the substrate 100, moving away from the plurality of lower electrode layers 120. The second insulating layer 170 can isolate the upper electrode layer 140 in the entire capacitor structure from other external components, thus providing insulation.

[0050] In some embodiments, the second insulating layer 170 and the first insulating layer 150 may be made of the same material. Both the second insulating layer 170 and the first insulating layer 150 are made of insulating materials, and both may be made of SiN. In other embodiments, the second insulating layer 170 and the first insulating layer 150 may also be made of different insulating materials.

[0051] In some embodiments, a support layer 180 may be further included, which may include a first support layer 181, a second support layer 182, and a third support layer 183. The first support layer 181 is located above the substrate 100 and fills the gaps between the conductive contact layers 110. A first insulating layer 150 is located on a portion of the surface of the first support layer 181. The first support layer 181 ensures the structural integrity between the conductive contact layers 110 and the lower electrode layer 120 in the semiconductor structure, resulting in higher stability of the semiconductor structure and providing a certain degree of support.

[0052] The second support layer 182 is located between adjacent lower electrode layers 120. The vertical distance between the second support layer 182 and the surface of the substrate 100 is less than the vertical distance between the top surface of the lower electrode layer 120 and the surface of the substrate 100. Because the lower electrode layer 120 is too high relative to the surface of the substrate 100, the middle region of the lower electrode layer 120 is prone to problems of low mechanical strength and poor stability. The second support layer 182 can solve this problem to some extent, improving the mechanical strength of the middle region of the lower electrode layer 120 and enhancing the stability of the semiconductor structure, thus providing a certain degree of support.

[0053] A third support layer 183 is located between adjacent lower electrode layers 120, and the vertical distance between the third support layer 183 and the surface of the substrate 100 is greater than the vertical distance between the second support layer 182 and the surface of the substrate 100. The first support layer 181, the second support layer 182, and the third support layer 183 constitute support layer 180. The third support layer 183 can further improve the mechanical strength and stability of the semiconductor structure, thus supporting the semiconductor structure. The combination of the first support layer 181, the second support layer 182, and the third support layer 183 can achieve better stability of the semiconductor structure.

[0054] The semiconductor structure provided in this disclosure includes a substrate and a plurality of conductive contact layers discretely disposed on a portion of the substrate surface. Each conductive contact layer includes a plurality of first conductive contact layers and a plurality of second conductive contact layers. The orthographic projection of the plurality of first conductive contact layers onto the substrate surface surrounds the plurality of second conductive contact layers. A plurality of lower electrode layers are located on the surfaces of the second conductive contact layers away from the substrate. A dielectric layer covers the top surfaces of the plurality of lower electrode layers away from the substrate and a portion of the side surfaces of the plurality of lower electrode layers. The region of the dielectric layer near the substrate protrudes in a direction parallel to the substrate surface away from the plurality of lower electrode layers. An upper electrode layer covers the top surface of the dielectric layer away from the substrate and the side surfaces of the dielectric layer. A first insulating layer is located on the surface of the first conductive contact layers away from the substrate, and a dielectric layer is located on a portion of the surface of the first insulating layer away from the substrate. The first insulating layer is located between the first conductive contact layers and the dielectric layer. This design can reduce leakage current in the semiconductor structure and improve its performance.

[0055] Accordingly, another embodiment of this disclosure also provides a method for manufacturing a semiconductor structure, which can be used to form the above-mentioned semiconductor structure. The semiconductor structure provided by another embodiment of this disclosure will be described in detail below with reference to the accompanying drawings. For parts that are the same as or corresponding to the previous embodiment, please refer to the corresponding descriptions of the foregoing embodiments; detailed descriptions will not be repeated below.

[0056] Figures 5 to 16 These are schematic cross-sectional views of each step in the manufacturing method of the semiconductor structure provided in this embodiment of the disclosure. Figures 5 to 7 , Figure 9 , Figure 11 , Figures 13 to 16 This is a partial cross-sectional structural diagram corresponding to each step of the semiconductor structure manufacturing process, specifically... Figure 3 The schematic diagram shows a cross-sectional structure of a local surface, with the local area located at... Figure 2 It is indicated by a dashed box. Figure 8 , Figure 10 , Figure 12 This is a top-view structural diagram showing the overall structure corresponding to each step in the semiconductor structure manufacturing process.

[0057] refer to Figure 5 Provides a base of 100.

[0058] The provided substrate 100 may include multiple discrete active regions and isolation structures (not shown) located between adjacent active regions. The multiple discrete active regions may be arranged in an array on the substrate 100, and the isolation structures may surround the active regions, with an isolation structure between every two adjacent active regions. The active regions may be made of silicon and are used to form transistors in a semiconductor structure in subsequent steps. The isolation structures may include silicon oxide and are used to isolate different active regions. Additionally, the substrate may also have word line structures and bit line structures. The word line structures can act as switches for the transistors in the active regions and are connected to the gates of the transistors. The bit line structures are connected to the drains of the transistors and can be used to read or write the stored state of the basic cells.

[0059] refer to Figure 6 A conductive contact layer 110 is formed, which is located on a portion of the surface of the substrate 100, and multiple conductive contact layers 110 are separated from each other on the surface of the substrate 100. The conductive contact layer 110 includes multiple first conductive contact layers 111 and multiple second conductive contact layers 112.

[0060] The steps of forming the conductive contact layer 110 may include: first forming a conductive contact film covering the entire surface of the substrate 100 on the surface of the substrate 100, and then removing part of the conductive contact film to obtain the conductive contact layer 110. In the formed conductive contact layer 110, the orthographic projection of the first conductive contact layer 111 on the substrate surface surrounds the second conductive contact layer 112.

[0061] It should be noted that before forming the conductive contact layer 110, a dielectric layer 160 may be formed, which is located on the surface of the substrate 100.

[0062] refer to Figures 7 to 12 A first insulating layer 150 is formed, which is located on the surface of the first conductive contact layer 111 away from the substrate 100.

[0063] In some embodiments, forming the first insulating layer 150 may specifically include: referencing Figures 7 to 8 , Figure 8 for Figure 7 The top view of the semiconductor structure in the step shows the formation of a first insulating film 151. The first insulating film 151 is located on the surface of the conductive contact layer 110 away from the substrate 100, and the orthographic projection of the first insulating film 151 onto the substrate 100 covers the entire surface of the substrate 100. It can be seen that the first insulating film 151 covers the entire surface of the substrate 100.

[0064] Continue to refer to Figures 7 to 8A photoresist layer 190 is formed, which is located on the surface of the first insulating film 151 away from the substrate 100. The photoresist layer has an opening located in the central region of the photoresist layer. Through the opening, the entire top surface of the plurality of second conductive contact layers 112 away from the substrate 100 can be exposed. Figure 8 The central region is marked by a dashed box, and the other regions outside the dashed box are the outer regions. The second conductive contact layer 112 is located within the central region.

[0065] refer to Figures 9 to 10 , Figure 10 for Figure 9 The top view of the semiconductor structure in this step shows that, using the photoresist layer 190 as a mask, the first insulating film 151 is etched along the opening to obtain the first insulating layer 150. After etching, the first insulating layer 150 is only located in the outer area, which can both isolate the first conductive contact layer 111 from the upper electrode layer 140 and reduce leakage current, and also enable the second conductive contact layer 112 to be electrically connected to the lower electrode layer 120 formed in the subsequent step.

[0066] refer to Figures 11 to 12 , Figure 12 for Figure 11 A top view of the semiconductor structure during the step, showing the removal of the photoresist layer.

[0067] refer to Figure 13 Multiple lower electrode layers 120 are formed, the multiple lower electrode layers 120 are located on a portion of the substrate 100, and the multiple lower electrode layers 120 are arranged in an array on the surface of the substrate 100, the multiple lower electrode layers are located on the top surface of the multiple second conductive contact layers 112 away from the substrate 100.

[0068] The height of the plurality of lower electrode layers 120 is greater than the height of the plurality of second conductive contact layers 112, and the plurality of second conductive contact layers 112 are electrically connected to the plurality of lower electrode layers 120. Each lower electrode layer 120 is in contact with each second conductive contact layer 112.

[0069] refer to Figure 14 A dielectric layer 130 is formed, which covers the top surface of the plurality of lower electrode layers 120 away from the substrate 100 and a portion of the side surfaces of the plurality of lower electrode layers 120. The dielectric layer 130 is located on a portion of the surface of the first insulating layer 150 away from the substrate 100, and the region of the dielectric layer 130 located around the plurality of lower electrode layers 120 near the substrate 100 protrudes in a direction parallel to the surface of the substrate 100 toward a direction away from the plurality of lower electrode layers 120.

[0070] refer to Figure 15An upper electrode layer 140 is formed, which covers the top surface of the dielectric layer 130 away from the substrate 100 and covers the side surface of the dielectric layer 130.

[0071] In some embodiments, forming the upper electrode layer 140 includes: forming a first upper electrode layer 141, the first upper electrode layer 141 covering the top surface of the dielectric layer 130 away from the substrate 100, and the first upper electrode layer 141 covering the side surface of the dielectric layer 130; forming a second upper electrode layer 142, the second upper electrode layer 142 covering the top surface of the first upper electrode layer 141 away from the substrate 100, and the second upper electrode layer 142 covering the side surface of the first upper electrode layer 141; wherein the thickness of the second upper electrode layer 142 is greater than the thickness of the first upper electrode layer 141.

[0072] refer to Figure 16 In some embodiments, after forming the upper electrode layer 140, the method further includes forming a second insulating layer 170, which covers the side of the upper electrode layer 140 and is in contact with the first insulating layer 150.

[0073] It should be noted that after the second insulating layer 170 is formed, a conductive structure connecting the semiconductor structure and external devices can also be formed. The conductive structure can be electrically connected to the first conductive contact layer 111.

[0074] In the semiconductor structure manufacturing method provided in this disclosure, a substrate is first provided, and a conductive contact layer is formed. The conductive contact layer is located on a portion of the substrate surface. Multiple conductive contact layers are discretely separated on the substrate surface. The conductive contact layer includes multiple first conductive contact layers and multiple second conductive contact layers. The orthographic projection of the multiple first conductive contact layers on the substrate surface surrounds the multiple second conductive contact layers. A first insulating layer is formed on the surface of the first conductive contact layers away from the substrate. Multiple lower electrode layers are formed, located on a portion of the substrate, and on the top surface of the second conductive contact layers away from the substrate. The multiple lower electrode layers are discretely separated on the substrate surface to form a dielectric layer. The dielectric layer covers the top surface of the multiple lower electrode layers away from the substrate and a portion of the side surfaces of the lower electrode layers. The dielectric layer is located on the portion of the first insulating layer away from the substrate, and the region of the dielectric layer near the substrate protrudes in a direction parallel to the substrate surface toward a direction away from the multiple lower electrode layers to form an upper electrode layer. The upper electrode layer covers the top surface of the dielectric layer away from the substrate and the side surfaces of the dielectric layer. This method can reduce leakage current in the semiconductor structure and improve the performance of the semiconductor structure.

[0075] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; A conductive contact layer is located on a portion of the surface of the substrate, and a plurality of the conductive contact layers are separated from each other on the surface of the substrate. The conductive contact layer includes a plurality of first conductive contact layers and a plurality of second conductive contact layers, and the orthographic projection of the plurality of first conductive contact layers on the surface of the substrate surrounds the plurality of second conductive contact layers. Multiple lower electrode layers are located on a portion of the substrate and are arranged in an array on the surface of the substrate, with the multiple lower electrode layers located on the top surface of the multiple second conductive contact layers away from the substrate; A dielectric layer covers the top surface of the plurality of lower electrode layers away from the substrate and a portion of the side surfaces of the plurality of lower electrode layers, and the region of the dielectric layer near the substrate located on the periphery of the plurality of lower electrode layers protrudes in a direction parallel to the surface of the substrate toward the direction away from the plurality of lower electrode layers; An upper electrode layer, wherein the upper electrode layer covers the top surface of the dielectric layer away from the substrate, and the upper electrode layer covers the side surface of the dielectric layer; A first insulating layer is located on the surface of the plurality of first conductive contact layers away from the substrate, and a portion of the dielectric layer is located on the portion of the first insulating layer away from the substrate. The first insulating layer is located between the plurality of first conductive contact layers and the dielectric layer. A support layer is located on the substrate, and the support layer includes a first support layer, a second support layer, and a third support layer.

2. The semiconductor structure as described in claim 1, characterized in that, The thickness of the first insulating layer is 20-60 nm.

3. The semiconductor structure as described in claim 1, characterized in that, The upper electrode layer specifically includes: A first upper electrode layer covers the top surface of the dielectric layer away from the substrate, and the first upper electrode layer also covers the side surface of the dielectric layer. The second upper electrode layer covers the top surface of the first upper electrode layer away from the substrate, and the second upper electrode layer covers the side surface of the first upper electrode layer; The thickness of the second upper electrode layer is greater than the thickness of the first upper electrode layer.

4. The semiconductor structure as described in claim 3, characterized in that, The material of the first upper electrode layer is different from the material of the second upper electrode layer.

5. The semiconductor structure as described in claim 1, characterized in that, Also includes: A second insulating layer covers the side and top surfaces of the upper electrode layer and is in contact with the first insulating layer. The region of the second insulating layer near the substrate protrudes in a direction parallel to the surface of the substrate toward the direction away from the plurality of lower electrode layers.

6. The semiconductor structure as described in claim 5, characterized in that, The second insulating layer is made of the same material as the first insulating layer.

7. The semiconductor structure as described in claim 1, characterized in that: The first support layer is located above the substrate and fills the gaps between the conductive contact layers, and the first insulating layer is located on a portion of the surface of the first support layer. The second support layer is located between adjacent lower electrode layers, and the vertical distance between the second support layer and the substrate surface is less than the vertical distance between the top surface of the lower electrode layer and the substrate surface. The third support layer is located between adjacent lower electrode layers, and the vertical distance between the third support layer and the substrate surface is greater than the vertical distance between the second support layer and the substrate surface. The first support layer, the second support layer, and the third support layer constitute a support layer.

8. The semiconductor structure as described in claim 1, characterized in that, Also includes: A dielectric layer is located on the surface of the substrate, and a lower electrode layer is located on the side of the dielectric layer away from the substrate.

9. The semiconductor structure as described in claim 1, characterized in that, The dielectric layer comprises hafnium oxide and / or zirconium oxide.

10. A method for manufacturing a semiconductor structure, characterized in that, include: Provide a base; A conductive contact layer is formed, the conductive contact layer is located on a portion of the surface of the substrate, and a plurality of the conductive contact layers are separated from each other on the surface of the substrate. The conductive contact layer includes a plurality of first conductive contact layers and a plurality of second conductive contact layers, and the orthographic projection of the plurality of first conductive contact layers on the surface of the substrate surrounds the plurality of second conductive contact layers. A first insulating layer is formed on the surface of the plurality of first conductive contact layers away from the substrate; Multiple lower electrode layers are formed, the multiple lower electrode layers are located on a portion of the substrate, and the multiple lower electrode layers are arranged in an array on the surface of the substrate, the multiple lower electrode layers are located on the top surface of the multiple second conductive contact layers away from the substrate; A dielectric layer is formed, which covers the top surface of the plurality of lower electrode layers away from the substrate and a portion of the side surfaces of the plurality of lower electrode layers. The dielectric layer is located on a portion of the surface of the first insulating layer away from the substrate, and the dielectric layer located around the plurality of lower electrode layers protrudes in a direction parallel to the surface of the substrate in a direction away from the plurality of lower electrode layers in the region near the substrate. An upper electrode layer is formed, the upper electrode layer covering the top surface of the dielectric layer away from the substrate, and the upper electrode layer covering the side surface of the dielectric layer; A support layer is formed on the substrate, and the support layer includes a first support layer, a second support layer and a third support layer.

11. The manufacturing method as described in claim 10, characterized in that, The formation of the first insulating layer specifically includes: A first insulating film is formed, the first insulating film being located on the surface of the conductive contact layer away from the substrate, and the orthographic projection of the first insulating film onto the substrate covering the entire surface of the substrate; A photoresist layer is formed on the surface of the first insulating film away from the substrate, and the photoresist layer has an opening located in the central region of the photoresist layer. Etching through the opening can expose the entire top surface of the plurality of second conductive contact layers away from the substrate. Using the photoresist layer as a mask, the first insulating film is etched along the opening to obtain the first insulating layer.

12. The manufacturing method as described in claim 10, characterized in that, The formation of the upper electrode layer includes: A first upper electrode layer is formed, the first upper electrode layer covering the top surface of the dielectric layer away from the substrate, and the first upper electrode layer covering the side surface of the dielectric layer; A second upper electrode layer is formed, which covers the top surface of the first upper electrode layer away from the substrate and also covers the side surface of the first upper electrode layer. The thickness of the second upper electrode layer is greater than the thickness of the first upper electrode layer.

13. The manufacturing method as described in claim 10, characterized in that, After forming the upper electrode layer, the method further includes: A second insulating layer is formed, which covers the side of the upper electrode layer and is in contact with the first insulating layer.

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