Manufacturing method of semiconductor structure

Abstract

The invention provides a method for manufacturing a semiconductor structure, which comprises the following steps of: providing a substrate, sequentially forming a stack structure and a first mask layer on the substrate, then forming a plurality of first sacrificial structures penetrating through the stack structure and the first mask layer, and etching back the first sacrificial structures and filling by taking the first mask layer as a barrier layer, a plurality of second sacrificial structures is formed. And forming a second mask layer and etching the first horizontal opening through the second mask layer to form a plurality of vertical openings penetrating through the stack structure. By arranging the second sacrificial structure, the second sacrificial structure can protect the structure below the second sacrificial structure from being etched, so that the first horizontal opening extending along the first horizontal direction is converted into the plurality of vertical openings arranged at intervals; the problem that the vertical opening hole pattern is poor due to the high aspect ratio in the vertical opening forming process is solved, the etching difficulty is reduced, and the manufacturing precision and reliability of the semiconductor structure are improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a method for fabricating a semiconductor structure. Background Technology

[0002] The scaling of traditional DRAM (Dynamic Random-Access Memory) is nearing its limit, in order to further improve DRAM integration density and achieve smaller manufacturing process capabilities.

[0003] Currently, in the fabrication process of 3D DRAM through stacked layers, pre-placement holes are created in the stacked layers, and related processing is performed using these pre-placement holes to form structures such as bit lines and capacitors. When creating pre-placement holes in the stacked layers, a aperture mask is used to pattern the surface of the stacked layers to form the corresponding pre-placement holes.

[0004] To further increase the storage density of 3D DRAM, the number of stacked layers also increases, which leads to a sharp increase in the aspect ratio of the pre-placement hole etching, thus increasing the processing difficulty of the pre-placement hole. Existing hole-type photomasks cannot meet the processing requirements. Summary of the Invention

[0005] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0006] According to an embodiment of this disclosure, a method for fabricating a semiconductor structure is provided, comprising: A substrate is provided, and a stacked structure and a first mask layer are sequentially formed on the substrate, the stacked structure comprising an alternately stacked sacrificial semiconductor layer and a semiconductor layer; A plurality of first sacrificial structures are formed that penetrate the stacked structure and the first mask layer, and the plurality of first sacrificial structures are arranged at least spaced apart from each other along a first horizontal direction; Using the first mask layer as a barrier layer, multiple first sacrificial structures are etched back to form multiple cavities located in the first mask layer; Multiple second sacrificial structures are formed to fill the multiple cavities respectively; A second mask layer is formed on the surface that covers the first mask layer and the plurality of second sacrificial structures. The second mask layer is patterned to form a first horizontal opening extending along the first horizontal direction, the first horizontal opening exposing the surfaces of a plurality of second sacrificial structures and the surface of the first mask layer; A plurality of second sacrificial structures, the first mask layer, and the stacked structure are etched downward along the first horizontal opening to form a plurality of vertical openings through the stacked structure. The vertical openings are located between two adjacent remaining second sacrificial structures in the first horizontal direction, wherein the first sacrificial structure is covered by the remaining second sacrificial structures.

[0007] In some embodiments, the manufacturing method further includes: The sacrificial semiconductor layer in the stacked structure is etched laterally along the vertical opening to form a first lateral space exposing the semiconductor layer; The semiconductor layer is thinned along the first lateral space via the vertical opening; An interlayer insulating layer is formed covering the surface of the thinned semiconductor layer; A plurality of third sacrificial structures are formed to fill the plurality of said vertical openings, the surfaces of the third sacrificial structures being flush with the surfaces of the remaining second sacrificial structures; The remaining second sacrificial structures and the multiple first sacrificial structures are replaced to form an isolation structure.

[0008] In some embodiments, the manufacturing method further includes: A portion of the interlayer insulating layer is replaced to form a horizontal word line, the horizontal word line being located on the partially thinned semiconductor layer; At least a portion of the third sacrificial structure is replaced to form a vertical bit line, which is located at one end of the thinned semiconductor layer.

[0009] In some embodiments, the stacked structure includes transistor regions and capacitor regions that are adjacent to each other in a second horizontal direction; a plurality of the first sacrificial structures are also arranged at intervals from each other along the second horizontal direction; The manufacturing method further includes: The second mask layer is patterned to form a second horizontal opening extending along the first horizontal direction, the second horizontal opening exposing the surface of the first mask layer, wherein the first horizontal opening is located in the transistor region and the second horizontal opening is located in the capacitor region; The first mask layer and the stacked structure are etched downward along the second horizontal opening to form a vertical trench through the stacked structure, the vertical trench extending along the first horizontal direction and located between two adjacent remaining second sacrificial structures in the second horizontal direction.

[0010] In some embodiments, the manufacturing method further includes: The sacrificial semiconductor layer in the stacked structure is etched laterally along the vertical trench to form a second lateral space that exposes the semiconductor layer; The semiconductor layer is thinned along the second lateral space via the vertical trench; An interlayer insulating layer is formed covering the surface of the thinned semiconductor layer; A fourth sacrificial structure is formed that fills a plurality of the vertical grooves, the surface of the fourth sacrificial structure being flush with the surface of the remaining second sacrificial structure.

[0011] In some embodiments, the manufacturing method further includes: At least a portion of the fourth sacrificial structure is removed to expose the vertical trench; A portion of the thinned semiconductor layer is removed along the vertical trench to form a side cavity, and the remaining thinned semiconductor layer is formed as an active layer; A capacitor is formed in the side cavity, and the capacitor is located at the other end of the thinned semiconductor layer.

[0012] In some embodiments, the fabrication method further includes: forming a plurality of third sacrificial structures filling the plurality of vertical openings, and forming a fourth sacrificial structure filling the plurality of vertical trenches, comprising: A third sacrificial isolation layer is formed, which covers the surface exposed by the interlayer insulation layer, the surface exposed by the vertical opening, the surface exposed by the vertical trench, and the surface of the remaining second mask layer; A third sacrificial filling layer is formed on the surface of the third sacrificial isolation layer located in the vertical opening. The third sacrificial filling layer extends downward along the first horizontal opening and fills the vertical opening to form the third sacrificial structure. A third sacrificial filling layer is formed on the surface of the third sacrificial isolation layer located in the vertical trench, the third sacrificial filling layer extending downward along the second horizontal opening and filling the vertical trench to form the fourth sacrificial structure; Remove the structure located above the surface of the remaining second sacrificial structure.

[0013] In some embodiments, forming a plurality of first sacrificial structures through the stacked structure and the first mask layer includes: A first sacrificial isolation layer is formed in contact with the stacked structure; A first sacrificial fill layer is formed on the surface of the first sacrificial isolation layer, the first sacrificial fill layer being made of the same material as the semiconductor layer in the stacked structure, wherein the first sacrificial isolation layer and the first sacrificial fill layer form the first sacrificial structure.

[0014] In some embodiments, forming a plurality of second sacrificial structures that respectively fill a plurality of said cavities includes: A second sacrificial isolation layer is formed on the surface of the first mask layer exposed in the plurality of cavities and on the surface of the first sacrificial structure; A second sacrificial filler layer is formed on the surface of the second sacrificial isolation layer. Both the second sacrificial isolation layer and the second sacrificial filler layer comprise oxides, and the density of the second sacrificial isolation layer is greater than that of the second sacrificial filler layer.

[0015] In some embodiments, the first mask layer and the second mask layer are made of the same material, and both the first mask layer and the second mask layer are made of nitrides.

[0016] The semiconductor structure fabrication method disclosed herein utilizes second sacrificial structures spaced apart along a first horizontal direction. During the etching process through a first horizontal opening extending along the first horizontal direction, the etchant etches the second sacrificial structures at a slower rate and the first mask layer at a faster rate. Therefore, the second sacrificial structures protect the structure below them from etchant etching, while the remaining portions of the first mask layer and stacked structure within the first horizontal opening are etched. This transforms the first horizontal opening extending along the first horizontal direction into multiple spaced vertical openings. In other words, the embodiments of this disclosure form multiple hole-like vertical openings penetrating the stacked structure through a photolithographic pattern of strip-shaped first horizontal openings. By optimizing the mask pattern and process flow for forming the vertical openings, the embodiments of this disclosure improve the problem of poor vertical opening shape caused by high aspect ratios during vertical opening formation, reducing etching difficulty and improving the fabrication accuracy and reliability of the semiconductor structure.

[0017] After reading and understanding the accompanying diagrams and detailed descriptions, other aspects can be understood. Attached Figure Description

[0018] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment; Figure 2 This is a structural diagram of a semiconductor structure after forming an isolation trench, according to an exemplary embodiment; Figure 3 This is a structural diagram of a semiconductor structure after filling the first sacrificial structure, according to an exemplary embodiment; Figure 4 This is a structural diagram of a semiconductor structure after the first sacrificial structure is etched back to form a cavity, according to an exemplary embodiment. Figure 5 This is a structural diagram of a semiconductor structure after filling with a second sacrificial structure, according to an exemplary embodiment; Figure 6 This is a structural diagram illustrating the semiconductor structure after the formation of the second mask layer, according to an exemplary embodiment; Figure 7 This is a structural diagram of a semiconductor structure after a first horizontal opening and a second horizontal opening are formed in a photoresist layer, according to an exemplary embodiment. Figure 8 This is a top view showing, according to an exemplary embodiment, the formation of a first horizontal opening and a second horizontal opening in the photoresist layer; Figure 9 This is illustrated according to an exemplary embodiment after forming a first horizontal opening. Figure 8 The cross-sectional view at section D-D' is shown; Figure 10 This is illustrated according to an exemplary embodiment after forming the second horizontal opening. Figure 8 The cross-sectional view at section E-E' is shown; Figure 11 This is a structural diagram of a semiconductor structure after etching downwards along a first horizontal opening and a second horizontal opening, according to an exemplary embodiment. Figure 12 This is illustrated in an exemplary embodiment, showing etching downwards along a first horizontal opening. Figure 11 The cross-sectional view at section D-D' is shown; Figure 13 This is an example of etching downwards along the first horizontal opening and the second horizontal opening, as shown in an exemplary embodiment. Figure 11 The cross-sectional view at section C-C' is shown; Figure 14 This is a cross-sectional view at section C-C' after removing the sacrificial semiconductor layer and thinning the semiconductor layer, according to an exemplary embodiment. Figure 15 This is a cross-sectional view at section C-C' after the formation of the interlayer isolation structure and the third sacrificial isolation layer, according to an exemplary embodiment; Figure 16 This is a cross-sectional view at section C-C' after the formation of the third sacrificial filler layer, according to an exemplary embodiment; Figure 17 This is a cross-sectional view at section D-D' after the formation of the third sacrificial filler layer, according to an exemplary embodiment. Figure 18 This is a cross-sectional view at section C-C' after the formation of the third and fourth sacrificial structures, according to an exemplary embodiment. Figure 19 This is a cross-sectional view at section C-C' after the isolation structure has been formed, according to an exemplary embodiment. Figure 20 This is a cross-sectional view at section D-D' after the isolation structure has been formed, according to an exemplary embodiment. Figure 21This is a cross-sectional view at section C-C' after removing part of the third sacrificial structure and part of the interlayer insulation layer, according to an exemplary embodiment. Figure 22 This is a cross-sectional view at section C-C' after the formation of the vertical bit line and the horizontal word line, according to an exemplary embodiment; Figure 23 This is a cross-sectional view at section C-C' after the side cavity is formed, according to an exemplary embodiment; Figure 24 This is a cross-sectional view at the C-C' section after the capacitor is formed, according to an exemplary embodiment. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0020] To further improve the integration density of DRAM, a relatively novel semiconductor structure has gradually become the main improvement route, namely MHC (Multilayer Horizontal Cell), which has multiple horizontally extending active layers stacked vertically and horizontal word lines (HWL). In forming the multiple vertically stacked active layers, it is first necessary to form an alternating stack of semiconductor layers (Si) and sacrificial semiconductor layers (e.g., SiGe) on a substrate (e.g., a silicon substrate). Then, in subsequent fabrication processes, the sacrificial semiconductor layers in the stacked structure are removed, and pre-placement vias are used to achieve channel isolation, word lines, bit lines, and capacitor formation, thereby completing the fabrication of the memory array region. As the number of stacked layers increases, the aspect ratio of the pre-apertures becomes larger. In the embodiments of this disclosure, multiple hole-shaped vertical openings (i.e., pre-placement vias) penetrating the stacked structure are formed through a strip-shaped horizontal opening photolithographic pattern.

[0021] According to an exemplary embodiment of this disclosure, the following is combined with Figures 2 to 24 This embodiment will be described with reference to... Figure 1 This embodiment provides a method for fabricating a semiconductor structure, including: S110. Provide a substrate and sequentially form a stacked structure and a first mask layer on the substrate. The stacked structure includes a sacrificial semiconductor layer and a semiconductor layer that are alternately stacked.

[0022] In step S110, refer to Figure 2 As shown, a stacked structure 2 and a first mask layer 3 are formed above the substrate 1. The stacked structure 2 includes a sacrificial semiconductor layer 21 and a semiconductor layer 22 alternately stacked along the thickness direction of the substrate 1. The material of the sacrificial semiconductor layer 21 can be silicon-germanium (SiGe), and the material of the semiconductor layer 22 can be silicon, pure germanium, etc. The sacrificial semiconductor layer 21 and the semiconductor layer 22 can be formed sequentially on the substrate 1 by an epitaxial growth process. The sacrificial semiconductor layer 21 will be removed later, while the semiconductor layer 22 will be retained.

[0023] The first mask layer 3 can be a composite stacked structure composed of different materials. In one example, the composite stacked structure forms at least one nitride layer, such as a silicon nitride layer, on top of the conventional hard mask layer. The formed nitride layer has a high etch selectivity with the second sacrificial structure formed in subsequent steps (described in detail below), so that the etchant etch rate for the nitride layer is much higher than the etch rate for the second sacrificial structure. In addition to the nitride layer mentioned above, the first mask layer 3 can also include structural layers composed of different materials, such as structural layers (i.e., hard mask layers) formed of hard mask materials containing carbon or nitrogen elements.

[0024] In one example, refer to Figure 2 The composite layer structure (i.e., the first mask layer 3) includes a third layer 34, a second layer 33 and a first layer 32 stacked sequentially from bottom to top along the thickness direction of the substrate 1. The second layer 33 and the third layer 34 can be, for example, a carbon layer, a silicon carbonitride layer, a silicon oxide layer, etc., and the first layer 32 is a silicon nitride layer.

[0025] S120, forming a plurality of first sacrificial structures that penetrate the stacked structure and the first mask layer, wherein the plurality of first sacrificial structures are arranged at least at intervals from each other along a first horizontal direction.

[0026] The thickness direction of substrate 1 is defined as the vertical direction (i.e., Figure 2 The z-direction shown in the figure), the width direction of substrate 1 is defined as the first horizontal direction (i.e., Figure 2 The length direction of substrate 1 is defined as the second horizontal direction (as shown in the y-direction). Figure 2 The x-direction shown in the figure, the vertical direction (z-direction), the first horizontal direction (y-direction), and the second horizontal direction (x-direction) are any two directions that are perpendicular to each other.

[0027] In step S120, refer to Figure 3Multiple first sacrificial structures 4 extending along the z-direction are formed, and multiple opening patterns can be formed on the surface of the first mask layer 3, with the multiple opening patterns extending at least along the first horizontal direction (e.g., ...). Figure 3 The array is arranged in the middle y-direction, and multiple opening patterns can also be arranged along the second horizontal direction (i.e., Figure 3 The array arrangement (shown in the x-direction) and multiple opening patterns define a shallow groove isolation structure (i.e., isolation structure 15, as described below, see [link]). Figure 19 and Figure 20 The position of ). For example Figure 2 and Figure 3 As shown, according to multiple opening patterns, downward etching is performed to form trenches that penetrate the first mask layer 3 and the stacked structure 2, and extend into the substrate 1 to form isolation trenches 111 that penetrate the first mask layer 3 and the stacked structure 2 in a vertical direction and extend into the substrate 1 (see reference). Figure 2 As shown, by depositing sacrificial material into the isolation trench 111, a first sacrificial structure 4 can be formed that penetrates the first mask layer 3 and the stacked structure 2 and extends into the substrate 1. The deposited sacrificial material can be a material such as polysilicon. The top surface of the first sacrificial structure 4 is flush with the top surface of the first mask layer 3.

[0028] In one example, the first sacrificial structure 4 is a single-layer structure, such as the first sacrificial structure 4 formed by depositing polycrystalline silicon material.

[0029] In another example, the first sacrificial structure 4 can also be a multilayer structure. For example, the first sacrificial structure 4 may include a nitride layer with isolation and protection effects. The nitride layer forms a receiving region in the isolation trench 111. The receiving region can be filled with sacrificial material to form a multilayer structure. The sacrificial material filled in the receiving region should be easy to remove in subsequent steps. The sacrificial material may be, for example, polycrystalline silicon.

[0030] S130. Using the first mask layer as a barrier layer, multiple first sacrificial structures are etched back to form multiple cavities located in the first mask layer.

[0031] In step S130, as Figure 4 As shown, after forming the first sacrificial structure 4, the first mask layer 3 is used as a barrier layer. An etchant with high etching efficiency for the first sacrificial structure 4 but a slower etching rate for the nitride layer on the top surface of the first mask layer 3 is selected to etch back the first sacrificial structure 4. That is, during the etch back of the first sacrificial structure 4, in order to avoid etching other parts of the semiconductor structure, the selected etchant has different etching rates for the first sacrificial structure 4 and the first mask layer 3, which must meet a preset etching selectivity ratio to ensure that the first mask layer 3 is etched as little as possible during the etching of the first sacrificial structure 4, thereby ensuring that the first mask layer 3 can protect other parts of the semiconductor structure from being etched.

[0032] By etching back the first sacrificial structure 4, a portion of the structure of the first mask layer 3 is exposed, forming multiple cavities 31 within the first mask layer 3. Each cavity 31 is an independent chamber, and adjacent cavities 31 are isolated by the first mask layer 3. The first mask layer 3 is a stacked structure, including a first layer 32 (nitride layer) at the top, and a second layer 33 and a third layer 34 below the nitride layer. When etching back the first sacrificial structure 3, it can be etched back into the second layer 33 or the third layer 34, but the top surface of the stacked structure 2 cannot be exposed. Cavities 31 can expose all sidewalls of the nitride layer (i.e., the first layer 32). Depending on the location of the etched-back first sacrificial structure 4, it may also expose all or part of the sidewalls of the second layer 33, or part of the sidewalls of the third layer 34.

[0033] In one example, refer to Figure 4 When the first sacrificial structure 4 is etched back, it is etched back to expose the top surface of the third layer 34 of the first mask layer 3, and then the cavity 31 exposes the sidewalls of the first layer 32 and the second layer 33.

[0034] S140, forming multiple second sacrificial structures that respectively fill multiple cavities.

[0035] like Figure 4 and Figure 5 As shown, sacrificial material is filled into each cavity 31 to form a second sacrificial structure 5 in each cavity 31. The second sacrificial structure 5 can be a single-layer or multi-layer structure. Regardless of whether it is a single-layer or multi-layer structure, the material of the second sacrificial structure 5 must ensure that when etched with the same etchant, the etchant has a faster etching rate on the first mask layer 3 and a slower etching rate on the second sacrificial structure 5, and the ratio of the etching rates should meet a preset ratio. This ensures that the second sacrificial structure 5 can protect the semiconductor structure located below it, thereby protecting the vertical opening 8 (see [reference]) on the semiconductor structure. Figure 11 (The location is specified in detail below.)

[0036] In this case, since the material of the uppermost first layer 32 of the first mask layer 3 is silicon nitride, in order to meet the etching rate requirements of the etchant for the first mask layer 3 and the second sacrificial structure 5 mentioned above, the material of the second sacrificial structure 5 includes oxides, such as silicon dioxide, and the etchant can be, for example, hot phosphoric acid.

[0037] In one example, the second sacrificial structure 5 can be a single-layer structure, and the material forming the second sacrificial structure 5 can be, for example, silicon dioxide.

[0038] In another example, refer to Figure 5As shown, the second sacrificial structure 5 can be a multi-layer structure, such as an isolation layer covering the sidewall of cavity 31 with isolation and protection effects, and then the interior of the isolation layer is filled with sacrificial materials such as silicon dioxide.

[0039] S150, A second mask layer is formed on the surface that covers the first mask layer and multiple second sacrificial structures.

[0040] like Figure 6 As shown, in one example, the top surfaces of the second sacrificial structure 5 and the first mask layer 3 formed in step S140 can be flush, that is, they can be located in the same plane, and the formed second mask layer 6 simultaneously covers the top surface of the first mask layer 3 and the top surface of the second sacrificial structure 5.

[0041] In another possible example, the top surfaces of the second sacrificial structure 5 and the first mask layer 3 may not be flush. In this case, the formed second mask layer 6 covers the surface formed by the first mask layer 3 and multiple second sacrificial structures 5. The second mask layer 6 can also flatten the top surface.

[0042] The second mask layer 6 can be formed by deposition, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The second mask layer 6 can be a single-layer structure, and the material on top of the first mask layer 3 can be the same as the material of the second mask layer 6, both including nitrides, such as silicon nitride.

[0043] S160, The patterned second mask layer forms a first horizontal opening extending along a first horizontal direction, the first horizontal opening exposing the surfaces of a plurality of second sacrificial structures and the surface of the first mask layer.

[0044] Reference Figure 6 and Figure 7 As shown, when patterning the second mask layer 6, a photoresist layer 112 is formed on the top surface of the second mask layer 6. First, a strip groove 1121 extending along the first horizontal direction is formed on the photoresist layer 112. The location of the strip groove 1121 is the subsequent first horizontal opening 7 (see...). Figure 8 The location of the first horizontal opening 7 is defined by the strip groove 1121.

[0045] Based on the pattern defined by the photoresist layer 112, a pattern is formed on the second mask layer 6. Figure 8 The first horizontal opening 7 extending in the y-direction shown in the figure (see Figure 8 The first horizontal opening 7 can also be set to multiple, and the multiple first horizontal openings 7 are along... Figure 8 The x-axis spacing shown is configured to form the area to be etched on the second mask layer 6. (Refer to...) Figure 8and Figure 9 As shown, the first horizontal opening 7 on the second mask layer 6 exposes the surfaces of multiple second sacrificial structures 5 and the surface of the first mask layer 3. The area exposed by the second mask layer 6 is the area that needs to be etched later.

[0046] In one example, during the formation of the first horizontal opening 7, the top surface of the second sacrificial structure 5 can be used as the etching stop surface for forming the first horizontal opening 7. (See reference...) Figure 8 and Figure 9 Because the same etchant has a slow etching rate for the material of the second sacrificial structure 5, but a fast etching rate for the nitride layer on top of the second mask layer 6 and the first mask layer 3, when the etchant acts on the second mask layer 6, it etches it rapidly until the top surface of the second sacrificial structure 5 is exposed. At this point, the second mask layer 6 above the second sacrificial structure 5 is basically removed, and the etching rate of the etchant on the top surface of the second sacrificial structure 5 decreases significantly. After the second mask layer 6 at the remaining positions of the first horizontal opening 7 is removed, the top surface of the first mask layer 3 is exposed, and the etchant continues to etch the top surface of the first mask layer 3 at a high rate. The first horizontal opening 7 extends into the first mask layer 3 in the z-direction, resulting in an uneven bottom surface. The bottom surface at the second sacrificial structure 5 is higher, while the bottom surface in the first mask layer 3 is lower. Figure 9 As shown.

[0047] S170. Etch multiple second sacrificial structures, a first mask layer, and a stacked structure downward along the first horizontal opening to form multiple vertical openings penetrating the stacked structure. The vertical openings are located between two adjacent remaining second sacrificial structures in the first horizontal direction, wherein the first sacrificial structure is covered by the remaining second sacrificial structures.

[0048] In step S170, refer to Figure 11 and combined Figure 8 Along the first horizontal opening 7 towards the substrate 1 (i.e. towards) Figure 11 The etching is performed below the first horizontal opening 7. Due to the presence of the second sacrificial structure 5, and the different etching rates of the etchant used during the formation of the vertical opening 8 on the second sacrificial structure 5 and the first mask layer 3, different areas will produce different etching effects during the downward etching process. The area with the second sacrificial structure 5 located in the first horizontal opening 7 (refer to...) Figure 8Since the etching rate of the etchant on the second sacrificial structure 5 is relatively slow, the structure below the second sacrificial structure 5 will be protected from etching and will not be etched, thus serving as a protected area. The area within the first horizontal opening 7 where the second sacrificial structure 5 is not located will be etched away by the etchant due to its faster etching rate, thus serving as the etched area.

[0049] When using the same etchant, the etching rate of the second sacrificial structure 5 is significantly lower than that of the stacked structure 2 and the first mask layer 3. Therefore, under the protection of the second sacrificial structure 5, only a portion of the second sacrificial structure 5 is etched in the z-direction, and the first sacrificial structure 4 located below the second sacrificial structure 5 remains unetched. However, because the etchant has a faster etching rate for the first mask layer 3 and the stacked structure 2, most of the structure in the etched area is removed, forming a vertical opening 8. The vertical opening 8 extends into the substrate 1 and penetrates the stacked structure 2 and the first mask layer 3. (Refer to...) Figure 11 As shown. (Refer to...) Figure 12 As shown, it illustrates Figure 11 The structure on the D-D' section, the area between the two adjacent first sacrificial structures 4 is the region where the vertical opening 8 is located.

[0050] Among them, reference Figure 8 and Figure 11 Since the process of forming the vertical opening 8 is carried out on the basis of the first horizontal opening 7, the etching process of forming the vertical opening 8 will be carried out along the extension direction (y direction) of the first horizontal opening 7. However, since the second sacrificial structure 5 is provided in the area exposed by the first horizontal opening 7, the strip etching extending along the y direction is transformed into etching along the z direction of the etching area defined above, thereby forming the vertical opening 8 located between two adjacent second sacrificial structures 5 in the first horizontal direction (i.e., the y direction).

[0051] By adopting this method, even when the depth-to-width ratio of the vertical opening 8 is large, it is still possible to ensure that the vertical opening 8 has good morphological characteristics. Furthermore, by limiting the position of the vertical opening 8 through the second sacrificial structure 5, it is possible to ensure that the opening position of the vertical opening 8 is more accurate. Since the vertical opening 8 will be used to form the pre-placement holes for word lines and position lines in subsequent processes, i.e., pre-opening holes, the accurate opening position of the vertical opening 8 can ensure that the forming process of word lines and vertical position lines is more reliable.

[0052] In addition, since the vertical opening 8 is formed by etching along the first horizontal opening 7, compared with the method in the related art of etching after patterning the location of the vertical opening 8, the method in this disclosure can obtain a larger etching area, so as to complete the fabrication process of the vertical opening 8 with a high aspect ratio more reliably and conveniently.

[0053] The fabrication method described in this embodiment, on the one hand, adjusts the aperture mask pattern that is not suitable for high aspect ratio etching into a long strip mask pattern, thereby reducing the aspect ratio during the etching process, effectively reducing the etching difficulty, and while taking into account the subsequent processes, the pre-opened aperture shape is better, which is conducive to the subsequent processes.

[0054] In some embodiments, step S120 above may include the following steps during implementation: S121, forming the first sacrificial isolation layer of the contact stack structure.

[0055] S122. A first sacrificial fill layer is formed on the surface of the first sacrificial isolation layer. The first sacrificial fill layer is made of the same material as the semiconductor layer in the stacked structure. The first sacrificial isolation layer and the first sacrificial fill layer form a first sacrificial structure.

[0056] In step S121, refer to Figure 2 and Figure 3 Before forming the first sacrificial isolation layer 41, an isolation trench 111 is first formed that penetrates the stacked structure 2 and the first mask layer 3, extending into the substrate 1. The isolation trench 111 exposes the sidewalls of the substrate 1, the stacked structure 2, and the first mask layer 3.

[0057] A first sacrificial material is deposited in the isolation trench 111 to protect the substrate 1, the stacked structure 2 and the first mask layer 3, forming a first sacrificial isolation layer 41. The first sacrificial material may be, for example, silicon nitride. The first sacrificial isolation layer 41 contacts the surfaces of the substrate 1, the stacked structure 2 and the first mask layer 3 exposed by the isolation trench 111.

[0058] In step S122, a second sacrificial material is deposited into the space enclosed by the first sacrificial isolation layer 41 to form a first sacrificial filling layer 42. The first sacrificial filling layer 42 and the first sacrificial isolation layer 41 together form the first sacrificial structure 4. The material of the second sacrificial material can be the same as the material of the semiconductor layer 22 in the stacked structure 2. The second sacrificial isolation material can be, for example, polycrystalline silicon.

[0059] In one example, the first sacrificial structure 4 is in Figure 3 It extends in the vertical direction z and is spaced apart in the first horizontal direction y and the second horizontal direction x.

[0060] In some embodiments, the process of forming a plurality of second sacrificial structures in step S140 above may include the following steps: S141. A second sacrificial isolation layer is formed on the surface of the first mask layer exposed in the multiple cavities and on the surface of the first sacrificial structure.

[0061] S142. A second sacrificial filling layer is formed on the surface of the second sacrificial isolation layer. Both the second sacrificial isolation layer and the second sacrificial filling layer include oxides, and the density of the second sacrificial isolation layer is greater than that of the second sacrificial filling layer.

[0062] Reference Figure 4 and Figure 5 As shown, after forming a plurality of cavities 31 by etching back the first sacrificial structure 4, in step S141, a second sacrificial isolation layer 51 is formed in each cavity 31. The second sacrificial isolation layer 51 covers the side surface of the first mask layer 3 exposed by the cavity 31 and the top surface of the first sacrificial structure 4.

[0063] In step S142, the second sacrificial isolation layer 51 covers the inner surface of the cavity 31 and encloses it to form a filling cavity, and the second sacrificial filling layer 52 is filled in the surface of the second sacrificial isolation layer 51 (i.e., the filling cavity).

[0064] The second sacrificial isolation layer 51 and the second sacrificial filling layer 52 are made of the same material, such as oxide, but the density of the second sacrificial isolation layer 51 is greater than that of the second sacrificial filling layer 52.

[0065] In one example, the second sacrificial isolation layer 51 is prepared by atomic layer deposition, and the second sacrificial filling layer 52 is prepared by spin-coating oxide, so that the density of the formed second sacrificial isolation layer 51 is greater than the density of the second sacrificial filling layer 52.

[0066] The method for forming the second sacrificial structure 5 in this embodiment, on the one hand, enables the formation of an active layer during subsequent etching processes, especially when thinning the semiconductor layer 22 in the stacked structure 2 along the vertical opening 8 to form an active layer (see reference). Figure 11 and Figure 14 The second sacrificial structure 5 protects the first sacrificial structure 4 located below it, preventing the first sacrificial structure 4 from being exposed and etched, thus avoiding structural damage and consequently damage to the stacked structure 2 located at the edge of the first sacrificial structure 4 and the substrate 1 located at the bottom of the first sacrificial structure 4. On the other hand, by setting the second sacrificial structure 5, the strip-shaped etching groove formed on the stacked structure 2 can be divided into multiple independent and spaced-apart occupiers (i.e., vertical openings 8, see reference 5) by the second sacrificial structure 5 and the first sacrificial structure 4 located below it during subsequent fabrication. Figure 8 and Figure 11 The vertical opening 8 is used to help form word lines and bit lines.

[0067] In this embodiment, the fabrication method adjusts the material of the first mask layer, adds a nitride layer on top, and fills the sacrificial layer at the location of the shallow trench isolation structure (i.e., the location of the first and second sacrificial structures) using a back etching process and a liquid phase dielectric spin coating process to form a second sacrificial structure with a blocking effect. This ensures that the strip photomask etching, in conjunction with the second sacrificial structure with a blocking effect, ultimately forms a hole structure with a better morphology, eliminating the influence of photomask changes in the front-end process and ensuring compatibility with downstream processes.

[0068] In one exemplary embodiment, such as Figures 13 to 20 As shown, the method for fabricating a semiconductor structure also includes: S210, Etch the sacrificial semiconductor layer in the stacked structure laterally along the vertical opening to form a first lateral space that exposes the semiconductor layer.

[0069] S220, The semiconductor layer is thinned along the first transverse space through the vertical opening; S230, Form an interlayer insulating layer covering the surface of the thinned semiconductor layer; S240, forming multiple third sacrificial structures that fill multiple vertical openings, the surface of the third sacrificial structure being flush with the surface of the remaining second sacrificial structure; S250, replace multiple remaining second sacrificial structures and multiple first sacrificial structures to form an isolation structure.

[0070] Before describing the steps in this embodiment, the following explanation is provided, referring to... Figure 13 As shown, and in combination Figure 11 As shown, the semiconductor layer 22 extends along the x-direction. The vertical opening 8 and the vertical trench 116, which will be described in detail later, divide the semiconductor layer 22 into multiple segments. Each segment of the semiconductor layer 22 has its sidewall exposed at one end by the vertical opening 8 and its sidewall exposed at the other end by the vertical trench 116. Lateral etching is performed through the vertical opening 8 to form the corresponding device in transistor region A, and the corresponding device in capacitor region B is formed through the vertical trench 116. In this embodiment, the lateral etching and thinning process through the vertical opening 8 is mainly described, specifically the lateral etching process for transistor region A.

[0071] In step S210, as Figure 13 and Figure 14 As shown, and in combination Figure 11After the vertical opening 8 is formed, the side of the stacked structure 2 exposed in the vertical opening 8 is etched laterally, that is, the sacrificial semiconductor layer 21 is etched laterally from the vertical opening 8 along the x direction.

[0072] In the horizontal direction (i.e.) Figure 13 (As shown in the x-direction) the sacrificial semiconductor layer 21 in the stacked structure 2 is selectively removed to form a first lateral space 91, as shown. Figure 14 This exposes the surface of the semiconductor layer 22, providing space for subsequent thinning of the semiconductor layer 22 and covering of the semiconductor layer 22 with the interlayer insulating layer 10. The process for removing the sacrificial semiconductor layer 21 can be, for example, a dry etching process.

[0073] In step S220, the thickness of the semiconductor layer 22 is reduced through the vertical opening 8. The method for thinning the semiconductor layer 22 can be dry etching, wet etching, etc. By thinning the semiconductor layer 22, more space is reserved between two adjacent semiconductor layers 22 along the z-direction to form the interlayer insulating layer 10 and interlayer isolation layer 23 in subsequent steps. (Refer to...) Figure 15 .

[0074] In step S230, as Figure 15 As shown, by covering the thinned semiconductor layer 22 with an interlayer insulating layer 10 through the vertical opening 8, passivation and protection effects between the thinned semiconductor layers 22 can be achieved, improving the structural stability of the semiconductor structure. The interlayer insulating layer 10 can be formed by processes such as chemical vapor deposition and atomic layer deposition. The material of the interlayer insulating layer 10 can be, for example, a silicon nitride layer.

[0075] It should be noted that, during the formation of the interlayer insulation layer 10, the nitride material used to form the interlayer insulation layer 10 is also applied to the exposed sidewall of the vertical opening 8, forming a first protective layer 24, as shown in the figure. Figure 15 .

[0076] Reference Figure 17 As shown, this figure illustrates a cross-sectional view at section D-D' after the semiconductor layer 22 has been thinned and a third sacrificial fill layer 12 (described in detail below) has been formed. During the formation of the vertical opening 8, a portion of the second sacrificial structure 5 is etched away, but a portion of the second sacrificial structure 5 remains. This remaining portion of the second sacrificial structure 5 is used to form the isolation structure 15 (see Figure 1). Figure 19 and Figure 20 Previously, the first sacrificial structure 4, located below the second sacrificial structure 5, would be protected. Combined with... Figure 14The remaining portion of the second sacrificial structure 5 will protect the first sacrificial structure 4 during the thinning process of the semiconductor layer 22, preventing the first sacrificial structure 4 from being exposed and damaged, thereby preventing damage to the substrate 1 and the structure around the first sacrificial structure 4.

[0077] In step S240, refer to Figure 18 and combined Figure 16 This forms multiple third sacrificial structures 13 that fill multiple vertical openings 8, with the surface of the third sacrificial structure 13 flush with the surface of the remaining second sacrificial structure 5.

[0078] By filling multiple vertical openings 8, a third sacrificial structure 13 is formed that is flush with the surface of the remaining second sacrificial structure 5. This maintains the flatness of the semiconductor structure surface and provides support for subsequent processing. It also makes it easier to open the structure again through the vertical openings 8.

[0079] Reference Figures 15 to 18 As shown, during the formation of the third sacrificial structure 13, the third sacrificial structure 13 can be a composite structure. A portion of the third sacrificial structure 13 enters through the vertical opening 8 between adjacent semiconductor layers 22 in the z-direction and fills the area between the interlayer insulating layer 10 covering the surfaces of the two adjacent semiconductor layers 22, forming an interlayer isolation layer 23. The interlayer isolation layer 23 can be an oxide layer, such as a silicon oxide layer, meaning that a portion of the third sacrificial structure 13 is silicon oxide. This creates a better isolation effect between the two adjacent semiconductor layers 22, preventing device leakage and improving the electrical stability and reliability of the semiconductor structure.

[0080] Since a first protective layer 24 is formed on the sidewalls of the substrate 1 and the first mask layer 3 exposed by the vertical opening 8 during the formation of the interlayer insulating layer 10 in step S230, the third sacrificial structure 13 formed in step S240, located in the vertical opening 8, will cover the first protective layer 24. (Refer to...) Figure 16 As shown.

[0081] In step S250, as Figure 19 and Figure 20 As shown, and in combination Figure 11 By replacing multiple remaining second sacrificial structures 5 and multiple first sacrificial structures 4 with isolation structures 15, the structures in two adjacent vertical openings 8 are isolated, thereby improving the electrical isolation effect and enhancing structural stability.

[0082] Before forming the isolation structure 15, the structure formed in step S240 needs to be chemically mechanically polished to remove part of the third sacrificial structure 13 and the first mask layer 3 covering the second sacrificial structure 5, until the top surface of the second sacrificial structure 5 is exposed. At this time, the top surface of the third sacrificial structure 13 is also exposed to clearly show the position of the third sacrificial structure 13 for protection in subsequent processes. In one example, refer to Figure 18 The first layer 32 of the first mask layer 3 is completely removed, a portion of the second layer 33 is removed, and the third layer 34 is retained.

[0083] When replacing the first sacrificial structure 4 and the remaining second sacrificial structure 5, in order to avoid affecting the third sacrificial structure 13 in the vertical opening 8, a protective structure is set at the location of the vertical opening 8 to protect the third sacrificial structure 13 located in the vertical opening 8. Only the remaining second sacrificial structure 5 and the first sacrificial structure 4 located below the second sacrificial structure 5 are replaced to form an isolation structure 15.

[0084] In this embodiment, the remaining second sacrificial structures 5 and the remaining first sacrificial structures 4 are first etched away by an etching process, and then an isolation material is filled into the original positions of the remaining second sacrificial structures 5 and the remaining first sacrificial structures 4 by a deposition process to form an isolation structure 15.

[0085] In one example, the isolation structure 15 is a single-layer structure, and the material of the single-layer structure is silicon oxide, as shown in the reference. Figure 20 As shown.

[0086] In another example (not shown in the diagram), the isolation structure can be set as an ONO structure. Figure 19 and Figure 20 In the process of forming the isolation structure 15, the first sacrificial structure 4 and the remaining second sacrificial structure 5 can be completely removed first, exposing the surfaces of the substrate 1, the stacked structure 2, and the remaining first mask layer 3. Then, an oxide layer is deposited, followed by a nitride layer. Finally, the remaining area is filled with oxide to form an ONO composite stacked structure. For example, Figure 19 As shown, during the deposition of the first oxide layer, the deposited oxide covers the top surface of the semiconductor structure obtained after chemical mechanical polishing and removal of the remaining surface of the second sacrificial structure 5, forming a second protective layer 16. The second protective layer 16 covers and protects the top surfaces of the third sacrificial structure 13 located in the vertical opening 8 and the plurality of fourth sacrificial structures 14 located in the vertical trenches 116. Subsequently, a second oxide layer is deposited over the second protective layer 16.

[0087] The method for fabricating the semiconductor structure disclosed herein also includes: S310, A patterned second mask layer is formed to form a second horizontal opening extending along a first horizontal direction, the second horizontal opening exposing the surface of the first mask layer.

[0088] S320. The first mask layer and the stacked structure are etched downward along the second horizontal opening to form a vertical trench through the stacked structure. The vertical trench extends along the first horizontal direction and is located between two adjacent remaining second sacrificial structures in the second horizontal direction.

[0089] In step S310, as can be seen from steps S210 to S250 above, referring to... Figure 8 , Figure 11 and Figure 13 As shown, the first horizontal opening 7 is located in transistor region A, and the second horizontal opening 114 is located in capacitor region B. The first mask layer 3 and the stacked structure 2 are etched downwards along the second horizontal opening 114 to form a vertical trench 116 penetrating the first mask layer 3 and the stacked structure 2. The vertical trench 116 extends along the first horizontal direction and is located between two adjacent second sacrificial structures 5 in the second horizontal direction. (Refer to...) Figure 10 As shown, it can be determined that the vertical trench 116 will not pass through the second sacrificial structure 5. The vertical trench 116 is used to subsequently form a capacitor.

[0090] Among them, reference Figures 7 to 8 The way in which the second horizontal opening 114 is formed is the same as the way in which the first horizontal opening 7 is formed, and will not be repeated here.

[0091] In one example, the first horizontal opening 7 and the second horizontal opening 114 can be made independently.

[0092] In another example, the first horizontal opening 7 and the second horizontal opening 114 can be fabricated simultaneously. The same etchant is used to form both the first horizontal opening 7 and the second horizontal opening 114. For example, Figure 7 , Figure 8 As shown, the strip-shaped opening of the photoresist layer 112 covering the second mask layer 6 can also simultaneously define the position of the second horizontal opening 114, referring to... Figure 7 The orientation shown in the figure indicates that the grooves on the left and right sides of the strip groove 1121 are the locations of the second horizontal opening 114.

[0093] like Figure 8 As shown, the first horizontal opening 7 and the second horizontal opening 114 are alternately arranged in the x-direction, and the first horizontal opening 7 and the second horizontal opening 114 divide the stacked structure 2 into multiple relatively independent device regions. Each device region includes a transistor region A and a capacitor region B. (Refer to...) Figure 13 In this embodiment, transistor region A is the region subsequently used to form word lines, bit lines, and other structures, and capacitor region B is the region subsequently used to form capacitors. Specifically, the first horizontal opening 7 and the vertical opening 8 are located in transistor region A of the device region, and the second horizontal opening 114 and the vertical trench 116 are located in capacitor region B.

[0094] In step S320, combined Figure 8 and Figure 11 Along the second horizontal opening 114 towards the substrate 1 (i.e. Figure 11 The etching process is performed below the substrate 1 to form a vertical trench 116 that penetrates the stacked structure 2 and extends into the substrate 1. Since only the first mask layer 3 and the stacked structure 2 are present at the location corresponding to the second horizontal opening 114, as... Figure 10 As shown, during the downward etching process, the vertical trench 116 formed is basically the same in shape and position as the second horizontal opening 114. Based on the second horizontal opening 114, the vertical trench 116 extends along the y-direction and penetrates the stacked structure 2. The vertical opening 8 and the vertical trench 116 can be formed in the same step of the process, forming vertical opening 8 and vertical trench 116 of the same depth, providing a basis for subsequent processing.

[0095] In one exemplary embodiment, the method for fabricating a semiconductor structure further includes: S410, Etch the sacrificial semiconductor layer in the stacked structure laterally along the vertical trench to form a second lateral space that exposes the semiconductor layer.

[0096] S420, the semiconductor layer is thinned along the second lateral space via a vertical trench.

[0097] S430, Form an interlayer insulating layer covering the surface of the thinned semiconductor layer.

[0098] S440, A fourth sacrificial structure is formed that fills multiple vertical grooves, the surface of the fourth sacrificial structure being flush with the surface of the remaining second sacrificial structure.

[0099] The formation of steps S410 to S440 in this embodiment is basically the same as that of steps S210 to S240 in the previous text, and will not be repeated here.

[0100] Among them, reference Figure 14 As shown, the second lateral space 92 formed in step S420 is located at one end of the semiconductor layer 22, while the first lateral space 91 formed in step S210 is located at the other end of the semiconductor layer 22. The first lateral space 91 and the second lateral space 92 will be connected to form a connected space.

[0101] In step S440, the fourth sacrificial structure 14 is formed, as follows: Figure 16 and Figure 18 As shown, during the formation of the interlayer insulating layer 10, a first protective layer 24 is also formed on the exposed surfaces of the substrate 1 and the first mask layer 3, and then a fourth sacrificial structure 14 is formed on the exposed surfaces of the first protective layer 24.

[0102] In an exemplary embodiment, the third sacrificial structure 13 and the fourth sacrificial structure 14 are fabricated simultaneously. The method in this embodiment will be described below. Step S240 includes the following steps during implementation: S241. A third sacrificial isolation layer is formed, which covers the surface exposed by the interlayer insulation layer, the surface exposed by the vertical opening, the surface exposed by the vertical trench, and the surface of the remaining second mask layer.

[0103] like Figure 15 As shown, the third sacrificial isolation layer 11 covers the interlayer insulation layer 10, and the portion located between adjacent interlayer insulation layers 10 serves as the interlayer isolation layer 23. Meanwhile, referring to... Figure 16 and Figure 18 Since the third sacrificial structure 13 and the fourth sacrificial structure 14 are fabricated simultaneously, the third sacrificial isolation layer 11 also covers the surfaces of the stacked structure 2, the first mask layer 3 and the substrate 1 exposed by the vertical opening 8 and the vertical trench 116, as well as the surface of the remaining second mask layer 6.

[0104] The method for fabricating the semiconductor structure in this embodiment further includes: S242. A third sacrificial filling layer is formed on the surface of the third sacrificial isolation layer located in the vertical opening. The third sacrificial filling layer extends downward along the first horizontal opening and fills the vertical opening to form a third sacrificial structure.

[0105] S243. A third sacrificial filling layer is formed on the surface of the third sacrificial isolation layer located in the vertical trench. The third sacrificial filling layer extends downward along the second horizontal opening and fills the vertical trench to form a fourth sacrificial structure.

[0106] S244. Remove the structure above the surface of the remaining second sacrificial structure.

[0107] In steps S242 and S243, as Figure 16 and Figure 18 As shown, a third sacrificial filling layer 12 is formed on the surface of the third sacrificial isolation layer 11, and the third sacrificial filling layer 12 extends downward along the vertical opening 8 (i.e., as shown in the figure). Figure 16The third sacrificial filling layer 12 extends downward along the vertical trench 116 (as shown in the z-direction) and fills the remaining area in the vertical opening 8, forming the final third sacrificial structure 13. Simultaneously, the third sacrificial filling layer 12 extends downward along the vertical trench 116 and fills the remaining area in the vertical trench 116, forming the final fourth sacrificial structure 14. The third sacrificial structure 13 and the fourth sacrificial structure 14 are made of the same material, such as polycrystalline silicon. Therefore, the formed third sacrificial structure 13 and the fourth sacrificial structure 14 are ultimately connected as a single structure on the top surface of the remaining second mask layer 6, ensuring uniformity and density of the filling.

[0108] In step S244, chemical mechanical grinding can be used to remove substances such as... Figure 17 The structure above the surface of the remaining second sacrificial structure 5 is shown. Subsequently, based on the structure obtained in this step, the steps in step S250 are continued to form the isolation structure 15 (see reference). Figure 19 and Figure 20 ).

[0109] In one exemplary embodiment, the method for fabricating a semiconductor structure further includes: S510, Replace part of the interlayer insulating layer to form a horizontal word line, the horizontal word line is located on the partially thinned semiconductor layer.

[0110] S520, at least part of the third sacrificial structure is replaced to form a vertical bit line, which is located at one end of the thinned semiconductor layer.

[0111] After step S250, as Figure 21 As shown, the vertical opening 8 is reopened, and part of the structure within the vertical opening 8 is removed, exposing the sides of the interlayer insulating layer 10 and the interlayer isolation layer 23. This prepares for the subsequent removal of part of the structure of the interlayer insulating layer 10 covering the surface of the thinned semiconductor layer 22. Multiple first vias 17 are formed on the upper surface of the isolation structure 15. The positions of the multiple first vias 17 correspond to the positions of the third sacrificial structure 13 (i.e., the vertical opening 8), and the multiple first vias 17 extend into the third sacrificial structure 13 (part of the third sacrificial structure 13 can be retained to protect the substrate 1). Part of the third sacrificial structure 13 can be removed through the first vias 17 to reopen the vertical opening 8.

[0112] In one example, such as Figure 16 and Figure 19As shown, after the isolation structure 15 is formed, the vertical opening 8 is filled with a third sacrificial structure 13, which is composed of a third sacrificial isolation layer 11 and a third sacrificial filling layer 12. The third sacrificial isolation layer 11 is made of oxide, and the third sacrificial filling layer 12 is made of polycrystalline silicon. When removing part of the structure in the vertical opening 8, both the third sacrificial isolation layer 11 and the third sacrificial filling layer 12 filling the vertical opening 8 need to be removed simultaneously. However, portions of the third sacrificial isolation layer 11 and the third sacrificial filling layer 12 located in the substrate 1 and those closer to the substrate 1 in the stacked structure 2 can be retained, thus protecting the substrate 1.

[0113] Reference Figure 21 and Figure 22 As shown, an etchant with high etching efficiency for the interlayer insulating layer 10 but low etching efficiency for the third sacrificial isolation layer 11 and the interlayer isolation layer 23 is selected to perform lateral etching on the interlayer insulating layer 10, thereby exposing a portion of the thinned semiconductor layer 22 near the vertical opening 8. A gate oxide layer covering the surface of the semiconductor layer 22 and a metal layer covering the gate oxide layer are formed in the channel region of the semiconductor layer 22, together forming the horizontal word line 19.

[0114] After the horizontal word line 19 is formed, a third protective layer 25 will be formed at the end of the semiconductor layer 22 near the vertical opening 8, that is, the first source / drain region of the semiconductor layer 22, covering the surface of the first source / drain region. The third protective layer 25 can be a nitride layer, thereby playing a role in protecting and insulating the first source / drain region.

[0115] In one example, the third protective layer 25 can be directly applied to the surface of the first source / drain region of the semiconductor layer 22.

[0116] In another example (not shown in the figure), the gate oxide layer formed during the formation of the horizontal word line 19 can be applied to the surface of the first source / drain region, and then the third protective layer 25 can be applied to the gate oxide layer located in the first source / drain region.

[0117] In step S520, refer to Figure 22 As shown, after completing the above steps, the surface exposed by the vertical opening 8 will be covered with the same nitride layer as the third protective layer 25. It is necessary to remove the nitride layer and reopen the vertical opening 8, and form a vertical bit line 18 in the vertical opening 8.

[0118] In one exemplary embodiment, reference is made to Figure 23 and Figure 24 As shown, the method for fabricating a semiconductor structure also includes: S610, at least part of the fourth sacrificial structure is removed to expose the vertical trench.

[0119] S620. A portion of the thinned semiconductor layer is removed along the vertical trench to form a side cavity, and the remaining thinned semiconductor layer is formed as an active layer.

[0120] S630, forming a capacitor in the side cavity.

[0121] In step S610, after the horizontal character line 19 and the vertical character line 18 have been created, the vertical groove 116 can be reopened.

[0122] The semiconductor layer 22 is exposed by removing the end of the interlayer insulating layer 10 exposed in the vertical trench 116. The exposed semiconductor layer 22 is then etched through the vertical trench 116 to remove a portion of the semiconductor layer 22, forming a side cavity 40. An upper plate, a capacitor dielectric, and a lower plate are sequentially formed in the side cavity 40, together constituting the capacitor 20. The remaining portion of the semiconductor layer 22 forms the second source / drain region, with the first and second source / drain regions located at opposite ends of the semiconductor layer 22 along the second horizontal direction. It should be noted that the active layer 30 is formed based on the thinned semiconductor layer 22; removing a portion of the thinned semiconductor layer 22 yields the active layer 30. (Refer to...) Figure 24 As shown, capacitor 20 and vertical bit line 18 are located at both ends of the thinned semiconductor layer 22, or they can be considered as being located at both ends of the active layer 30.

[0123] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0124] In the description of this specification, references to the terms "embodiment," "exemplary embodiment," "some implementation," "illustrated implementation," "example," etc., refer to specific features, structures, materials, or characteristics described in connection with an implementation or example that are included in at least one implementation or example of this disclosure.

[0125] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0126] In the description of this disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0127] It is understood that the terms "first," "second," etc., as used in this disclosure may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

[0128] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.

[0129] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, and a stacked structure and a first mask layer are sequentially formed on the substrate, the stacked structure comprising an alternately stacked sacrificial semiconductor layer and a semiconductor layer; A plurality of first sacrificial structures are formed that penetrate the stacked structure and the first mask layer, and the plurality of first sacrificial structures are arranged at least spaced apart from each other along a first horizontal direction; Using the first mask layer as a barrier layer, multiple first sacrificial structures are etched back to form multiple cavities located in the first mask layer; Multiple second sacrificial structures are formed to fill the multiple cavities respectively; A second mask layer is formed on the surface that covers the first mask layer and the plurality of second sacrificial structures. The second mask layer is patterned to form a first horizontal opening extending along the first horizontal direction, the first horizontal opening exposing the surfaces of a plurality of second sacrificial structures and the surface of the first mask layer; A plurality of second sacrificial structures, the first mask layer, and the stacked structure are etched downward along the first horizontal opening to form a plurality of vertical openings through the stacked structure. The vertical openings are located between two adjacent remaining second sacrificial structures in the first horizontal direction, wherein the first sacrificial structure is covered by the remaining second sacrificial structures.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The manufacturing method further includes: The sacrificial semiconductor layer in the stacked structure is etched laterally along the vertical opening to form a first lateral space exposing the semiconductor layer; The semiconductor layer is thinned along the first lateral space via the vertical opening; An interlayer insulating layer is formed covering the surface of the thinned semiconductor layer; A plurality of third sacrificial structures are formed to fill the plurality of said vertical openings, the surfaces of the third sacrificial structures being flush with the surfaces of the remaining second sacrificial structures; The remaining second sacrificial structures and the multiple first sacrificial structures are replaced to form an isolation structure.

3. The method for fabricating a semiconductor structure according to claim 2, characterized in that, The manufacturing method further includes: A portion of the interlayer insulating layer is replaced to form a horizontal word line, the horizontal word line being located on the partially thinned semiconductor layer; At least a portion of the third sacrificial structure is replaced to form a vertical bit line, which is located at one end of the thinned semiconductor layer.

4. The method for fabricating a semiconductor structure according to claim 2 or 3, characterized in that, The stacked structure includes transistor regions and capacitor regions that are adjacent to each other in the second horizontal direction; Multiple first sacrificial structures are also arranged at intervals along the second horizontal direction; The manufacturing method further includes: The second mask layer is patterned to form a second horizontal opening extending along the first horizontal direction, the second horizontal opening exposing the surface of the first mask layer, wherein the first horizontal opening is located in the transistor region and the second horizontal opening is located in the capacitor region; The first mask layer and the stacked structure are etched downward along the second horizontal opening to form a vertical trench through the stacked structure, the vertical trench extending along the first horizontal direction and located between two adjacent remaining second sacrificial structures in the second horizontal direction.

5. The method for fabricating a semiconductor structure according to claim 4, characterized in that, The manufacturing method further includes: The sacrificial semiconductor layer in the stacked structure is etched laterally along the vertical trench to form a second lateral space that exposes the semiconductor layer; The semiconductor layer is thinned along the second lateral space via the vertical trench; Forming the interlayer insulating layer covering the surface of the thinned semiconductor layer; A fourth sacrificial structure is formed that fills a plurality of the vertical grooves, the surface of the fourth sacrificial structure being flush with the surface of the remaining second sacrificial structure.

6. The method for fabricating a semiconductor structure according to claim 5, characterized in that, The manufacturing method further includes: At least a portion of the fourth sacrificial structure is removed to expose the vertical trench; A portion of the thinned semiconductor layer is removed along the vertical trench to form a side cavity, and the remaining thinned semiconductor layer is formed as an active layer; A capacitor is formed in the side cavity, and the capacitor is located at the other end of the thinned semiconductor layer.

7. The method for fabricating a semiconductor structure according to claim 5, characterized in that, The formation of a plurality of third sacrificial structures filling the plurality of said vertical openings, and the formation of a fourth sacrificial structure filling the plurality of said vertical trenches, include: A third sacrificial isolation layer is formed, which covers the surface exposed by the interlayer insulation layer, the surface exposed by the vertical opening, the surface exposed by the vertical trench, and the surface of the remaining second mask layer; A third sacrificial filling layer is formed on the surface of the third sacrificial isolation layer located in the vertical opening. The third sacrificial filling layer extends downward along the first horizontal opening and fills the vertical opening to form the third sacrificial structure. A third sacrificial filling layer is formed on the surface of the third sacrificial isolation layer located in the vertical trench, the third sacrificial filling layer extending downward along the second horizontal opening and filling the vertical trench to form the fourth sacrificial structure; Remove the structure located above the surface of the remaining second sacrificial structure.

8. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The formation of a plurality of first sacrificial structures penetrating the stacked structure and the first mask layer includes: A first sacrificial isolation layer is formed in contact with the stacked structure; A first sacrificial fill layer is formed on the surface of the first sacrificial isolation layer, the first sacrificial fill layer being made of the same material as the semiconductor layer in the stacked structure, wherein the first sacrificial isolation layer and the first sacrificial fill layer form the first sacrificial structure.

9. The method for fabricating a semiconductor structure according to claim 1 or 8, characterized in that, The formation of a plurality of second sacrificial structures that respectively fill a plurality of said cavities includes: A second sacrificial isolation layer is formed on the surface of the first mask layer exposed in the plurality of cavities and on the surface of the first sacrificial structure; A second sacrificial filler layer is formed on the surface of the second sacrificial isolation layer. Both the second sacrificial isolation layer and the second sacrificial filler layer comprise oxides, and the density of the second sacrificial isolation layer is greater than that of the second sacrificial filler layer.

10. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The first mask layer and the second mask layer are made of the same material, and both the first mask layer and the second mask layer are made of nitrides.

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