Terminal structure of power device and manufacturing method thereof

Abstract

The embodiment of the invention relates to a manufacturing method of a terminal structure of a power device and the terminal structure of the power device, and the method comprises the steps: preparing a terminal region main body structure which is composed of a substrate layer and an epitaxial layer located at one side of the substrate layer; performing groove etching on the epitaxial layer to form a first groove and a second groove; depositing an oxide layer in the first groove and the second groove; removing the oxide layer to form an ion implantation window, and performing ion implantation on the ion implantation window to form a deep junction and a field limiting ring; filling polycrystalline silicon in the first groove and the second groove to form a polycrystalline silicon layer; depositing a high dielectric constant material above the epitaxial layer to form a field plate; and polycrystalline silicon is deposited on a part of the field plate, the notch of the first groove and the notch of the second groove to form a metal connection layer. By adopting the design of the groove field limiting ring and the field plate, the withstand voltage of the terminal structure is improved, and the reliability of the power device is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a terminal structure for a power device and a method for manufacturing the terminal structure for a power device. Background Technology

[0002] With continuous technological advancements, the performance of power VDMOS (Vertical Double-diffused Metal Oxide Semiconductor Field Effect Transistor) has been continuously improving, leading to its increasingly widespread application in power electronics. The working principle of power VDMOS is similar to that of MOSFETs, both controlling the channel current through gate voltage. Power VDMOS employs a vertical current path design, primarily forming a vertical structure consisting of an N-type substrate, a P-type diffusion layer, an N-type epitaxial layer, and an N+ type channel layer through vertical diffusion. When the gate voltage is zero, a PN junction is formed between the substrate and the epitaxial layer, and an NPN transistor is formed between the P-type diffusion layer and the N+ channel layer. When the gate voltage is positive, the PN junction is reverse-biased, the NPN transistor conducts, and the channel current begins to flow.

[0003] In the termination structure of power devices, the field ring process is relatively simple and can be implanted together with the main junction. However, in existing technologies, due to the small diffusion coefficient of silicon carbide, deep junctions cannot be obtained through diffusion. Increasing the implantation energy will damage the lattice on the surface of silicon carbide, which cannot be fully restored even with annealing, thus affecting the stability of the device and reducing its reliability. Summary of the Invention

[0004] Therefore, in order to overcome at least some of the defects and deficiencies of the prior art, the present invention proposes a method for manufacturing the terminal structure of a power device to improve the reliability of the power device.

[0005] On one hand, an embodiment of the present invention proposes a method for manufacturing a terminal structure of a power device, comprising: preparing a terminal region main structure, the terminal region main structure being composed of a substrate layer and an epitaxial layer located on one side of the substrate layer; performing trench etching on the epitaxial layer to form a first trench and a second trench on the epitaxial layer, wherein the bottom of the first trench and the bottom of the second trench are arc-shaped; depositing an oxide layer into the first trench and the second trench, such that the oxide layer covers the bottom inner wall of the first trench and the second trench; removing the first trench and the second trench... An oxide layer is applied to the bottom of the trench to form an ion implantation window, and ion implantation is performed into the ion implantation window to form a deep junction at the bottom of the first trench and a field limiting ring at the bottom of the second trench; polysilicon is filled in the first trench and the second trench to form a polysilicon layer; a high dielectric constant material is deposited over the epitaxial layer, and a trench mask is etched between the first trench and the second trench to form a field plate; polysilicon is deposited at portions of the field plate, the trench opening of the first trench, and the trench opening of the second trench to form a metal interconnect layer.

[0006] Secondly, another embodiment of the present invention provides a terminal structure for a power device, comprising a main structure consisting of a substrate layer and an epitaxial layer, wherein the epitaxial layer has a first trench and a second trench, the bottom of the first trench and the bottom of the second trench being arc-shaped; a P-type deep junction corresponding to the first trench and located at the bottom of the first trench; wherein the bottom of the P-type deep junction is arc-shaped; a P-type field limiting ring corresponding to the second trench and located at the bottom of the second trench; a polysilicon layer filling the first trench and the second trench; a field plate covering the epitaxial layer and located between the openings of the first trench and the second trench, the field plate being connected to the polysilicon layer; and a metal interconnect layer deposited and covering a portion of the field plate and the openings of the trenches; the metal interconnect layer being connected to the field plate and the P-type polysilicon layer respectively.

[0007] As can be seen from the above, the technical features of the present invention can have the following beneficial effects: This application adjusts the field limiting ring terminal structure by first performing ion implantation at the bottom of the first trench to form a deep junction, and then performing ion implantation at the bottom of the second trench to form a field limiting ring, thereby expanding the width of the depletion region. Secondly, a high dielectric constant material is deposited on the epitaxial layer, and a trench mask between the first trench and the second trench is etched to form a field plate. This forms a trench field limiting ring plus field plate design, and polysilicon is deposited everywhere above part of the field plate and the trench opening as a metal connection layer to facilitate the control of impurity charge, making the terminal structure more resistant to high voltage, thereby improving the reliability of the power device. Attached Figure Description

[0008] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is a schematic flowchart illustrating a method for manufacturing a terminal structure of a power device according to an embodiment of the present invention.

[0010] Figure 2 for Figure 1 The flowchart shown is a diagram of the additional steps following step S17.

[0011] Figures 3-8 for Figure 1 The diagram shows the intermediate flow of the manufacturing process involved in the manufacturing method of the terminal structure of the power device.

[0012] Figure 9 This is a cross-sectional view of the terminal structure of the power device according to an embodiment of the present invention.

[0013] [Explanation of Identifiers in the Attached Image]

[0014] S11-S17: Manufacturing method of terminal structure for power devices;

[0015] 101: Substrate layer; 102: Epitaxial layer; 103: Oxide layer; 104: P-type deep junction; 105: P-type field confinement ring; 106: Polysilicon layer; 107: Field plate; 108: Metal interconnect layer; 109: Isolation layer; 111: First trench; 112: Second trench. Detailed Implementation

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0017] In this embodiment, the power device may be, for example, a power VDMOS device, which is a vertical MOSFET device. The following embodiments will be described using a power VDMOS device as an example.

[0018] like Figure 1 As shown, this embodiment of the invention provides a method for manufacturing a terminal structure of a power device. Specifically, the method provided by this embodiment includes, for example, the following steps:

[0019] S11. Prepare the main structure of the terminal region, wherein the main structure of the terminal region consists of a substrate layer and an epitaxial layer located on one side of the substrate layer.

[0020] Specifically, the main structure of the terminal area can be, for example, the terminal structure of a power device, such as... Figure 3 and Figure 4 As shown, the main structure of the terminal region can, for example, consist of a substrate layer 101 and an epitaxial layer 102. The substrate layer 101 is, for example, a base layer made of silicon carbide material, and the epitaxial layer 102 is, for example, a silicon carbide layer grown on a silicon carbide substrate. The substrate layer 101 is located at the bottom layer of the main structure of the terminal region, and the epitaxial layer 102 is located at the top layer of the main structure of the terminal region. In this embodiment, the epitaxial layer 102 can, for example, be an N-type drift epitaxial layer. Of course, in other embodiments, the epitaxial layer 102 can also be, for example, a P-type epitaxial layer. The specific type of the epitaxial layer 102 can be set to an N-type epitaxial layer or a P-type epitaxial layer according to the actual situation; no specific limitation is made here.

[0021] S12. Trench etching is performed on the epitaxial layer to form a first trench and a second trench on the epitaxial layer, wherein the bottom of the first trench and the bottom of the second trench are arc-shaped.

[0022] Specifically, such as Figure 3 As shown, trench etching is performed on the upper surface of the epitaxial layer 102 away from the substrate layer 101. For example, a hard mask layer can be grown first on the upper surface of the epitaxial layer 102 as a barrier layer for trench etching. The material of the hard mask can be silicon dioxide or silicon nitride, etc., and then trench etching is performed. The final structure is as shown. Figure 3 As shown. The trench etching can be performed using wet etching, resulting in rounded edges at the first trench 111 and the second trench 112, thus making the bottoms of the first trench 111 and the second trench 112 arc-shaped. That is, the bottoms of the first trench 111 and the second trench 112 have a certain degree of curvature.

[0023] S13. Deposit an oxide layer into the first trench and the second trench such that the oxide layer covers the bottom inner wall of the first trench and the second trench.

[0024] like Figure 3 As shown, an oxide layer 103 is deposited in the first trench 111 and the second trench 112, such that the bottom inner wall of the first trench 111 and the bottom inner wall of the second trench 112 are both filled with the oxide layer 103. This results in a thin film on the surface of the epitaxial layer 102, the bottom inner wall of the first trench 111, and the bottom inner wall of the second trench 112, which can serve as a mask layer for subsequent ion implantation. The resulting structure is as follows. Figure 3 As shown. The oxide layer 103 can be, for example, a material such as silicon nitride or silicon oxynitride.

[0025] S14. Remove the oxide layer covering the bottom of the first trench and the second trench to form an ion implantation window, and perform ion implantation into the ion implantation window to form a deep junction at the bottom of the first trench and a field confinement ring at the bottom of the second trench.

[0026] Specifically, a dry etching process can be performed to remove the oxide layer 103 covering the bottom inner wall of the first trench 111 and the bottom inner wall of the second trench 112, thereby forming an ion implantation window, which can be, for example, a P-ring ion implantation window. Ion implantation is then performed through the ion implantation window, followed by thermal diffusion, activation, and impurity propagation to form a deep junction at the bottom of the first trench 111 and a field confinement ring at the bottom of the second trench 112, as shown in the specific structure. Figure 4 As shown. The implanted ions can be, for example, metal ions, such as aluminum ions. By implanting metal ions into the ion implantation window of the P-ring, a P-type deep junction 104 is formed at the bottom of the first trench 111, and a P-type field-limiting ring 105 is formed at the bottom of the second trench 112. Forming the P-type deep junction 104 at the bottom of the first trench 111 expands the width of the depletion region. Since the bottom of the first trench 111 is curved during etching, the bottom of the P-type deep junction 104 is also arc-shaped. The arc-shaped bottom of the P-type deep junction 104 avoids electric field concentration at right angles, preventing corner breakdown and thus affecting the reliability of the manufactured power device.

[0027] S15. Fill the first trench and the second trench with polysilicon to form a polysilicon layer.

[0028] Specifically, such as Figure 5 As shown, polysilicon is filled in the first trench 111 and the second trench 112 to form a polysilicon layer 106 in the first trench 111 and the second trench 112. The polysilicon is, for example, P-type polysilicon, which can be combined with an N-type silicon carbide epitaxial layer to form a PN junction with higher voltage resistance, thereby improving the reliability of the device.

[0029] S16. A high dielectric constant material is deposited over the epitaxial layer, and a groove mask between the first trench and the second trench is etched to form a field plate.

[0030] Specifically, such as Figure 6As shown, a high dielectric constant material is deposited on the upper surface of the epitaxial layer 102, and then the groove mask between the first trench 111 and the second trench 112 is etched to form the field plate 107. The high dielectric constant material is one of hafnium dioxide, silicon nitride, tantalum pentoxide, tungsten dioxide, yttrium oxide and lanthanum oxide.

[0031] S17. Polysilicon is deposited at the openings of the field plate, the first trench, and the second trench to form a metal interconnect layer.

[0032] Specifically, after forming the field plate 107, polysilicon is deposited at portions of the field plate 107, the openings of the first trench 111, and the openings of the second trench 112 to form a metal interconnect layer 108, such as... Figure 7 As shown. The polysilicon is, for example, P-type polysilicon. Since impurities are often introduced during device manufacturing, and the impurity charge can affect the stability of the device, in this embodiment, by using a pad of polysilicon as a metal interconnect layer 108, the impurity charge can be controlled, reducing the impact of the impurity charge on the device and improving the reliability of the device.

[0033] In existing technologies, the termination structure of power devices typically employs a field-limiting ring (FCR) design. The FCR is formed by ion implantation along with the main junction within the termination structure. However, existing termination structures generally use silicon carbide (SiC) to fabricate power devices. Due to its low diffusion coefficient, SiC cannot form deep junctions through thermal diffusion. Increasing the implantation energy to form a deep junction easily damages the SiC surface lattice, and even after a return process, the lattice cannot be restored, leading to reduced reliability of the power device. This application addresses this issue by performing trench etching on the epitaxial layer 102 followed by ion implantation to obtain a deep junction and FCR, thereby expanding the width of the depletion region. Polycrystalline silicon and a high-dielectric-constant material are used in this application. The materials are used to fill trenches in the deep junction and field limiting ring respectively, and a field plate 107 is formed by a high dielectric constant material. Then, polysilicon is deposited as a metal interconnect layer 108 on the field plate 107, the first trench 111 and the second trench 112. This allows the structure of deep junction 104, field limiting ring 105 and field plate 107 to be formed on the silicon carbide epitaxial layer 102 without affecting the surface lattice of silicon carbide. The metal interconnect layer 108 can also control the influence of impurity charge on power devices, thereby improving the voltage withstand capability of the terminal structure and increasing the reliability of power devices.

[0034] Furthermore, such as Figure 2 As shown, after step S17, the method further includes:

[0035] S18. A high dielectric constant material is deposited over the non-metallic bonding layer of the field plate to form an isolation layer; wherein the upper surface of the isolation layer is flush with the upper surface of the metallic bonding layer.

[0036] Specifically, such as Figure 8 As shown, a high dielectric constant material is deposited on top of the unpadded metal bonding layer 108 of a portion of the field plate 107 to form an isolation layer 109. The isolation layer 109 can be used for isolation and smoothing, wherein the smoothing effect can be achieved by the upper surface of the isolation layer 109 being flush with the upper surface of the metal bonding layer 108.

[0037] The following reference Figures 3-8 The manufacturing process of the terminal structure of the power device is described in detail with reference to a specific embodiment. The following description is merely illustrative and should not be construed as limiting the specific implementation of the present invention.

[0038] First, trench etching is performed on the main structure of the terminal region to obtain a first trench 111 and multiple second trenches 112. The main structure of the terminal region consists of a substrate layer 101 and an epitaxial layer 102 located on one side of the substrate layer 101. The substrate layer is an N-type silicon carbide substrate, and the epitaxial layer 102 is an N-type silicon carbide drift epitaxial layer. The number of field-limiting rings in the main structure of the terminal region is between 2 and 30, meaning the number of second trenches 112 is between 2 and 30. The first field ring (the second trench 112 closest to the first trench 111) is 0.8-1.2 micrometers away from the main junction (first trench 111). Subsequently, the distance between each second trench 112 increases by 0.08-0.12 micrometers, meaning the distance between each second trench 112 is 0.08-0.12 micrometers. The depth of the trench etching is between 0.1 and 10 micrometers. After trench etching, a first trench 111 and multiple second trenches 112 are obtained. The bottoms of the first trench 111 and the multiple second trenches 112 all have a certain curvature, such as... Figure 3 As shown, carbon dioxide is then deposited on the surface of the silicon carbide epitaxial layer 102 to oxidize it. A silicon dioxide film is obtained at the bottom of the epitaxial layer 102, the first trench 111 and the second trench 112 to serve as a mask layer for subsequent ion implantation.

[0039] The oxide layer covering the bottom of the first and second trenches is removed using a dry etching process to form a P-ring ion implantation window. Aluminum ions are then implanted into the first trench 111 through this window. Thermal diffusion, activation, and impurity propagation are then performed to form a P-type deep junction 104 at the bottom of the first trench 111. The implantation depth of the aluminum ions is between 0.1 and 10 micrometers. The formation of the P-type deep junction 104 by implanting aluminum ions expands the depletion region width. The bottom of the P-type deep junction 104 is rounded to prevent electric field concentration at right angles, which could lead to corner breakdown. Figure 4 As shown. Simultaneously, aluminum ions are injected into the second trench 112 through the P-ring particle injection window to form a P-type field confinement ring 105 at the bottom of the second trench 112. The width of the P-type deep junction 104 formed in the first trench 111 is 0.1-10 micrometers, and the width of the P-type field confinement ring 105 formed in each second trench 112 is 0.5-2 micrometers.

[0040] like Figure 5 As shown, P-type polysilicon is used to fill the first trench 111 and multiple second trenches 112 to obtain a P-type polysilicon layer 106. The P-type polysilicon layer 106 can form a PN junction with the N-type drift epitaxial layer 102, thereby making the manufactured terminal structure more resistant to voltage.

[0041] like Figure 6 As shown, a compound of hafnium dioxide with a high dielectric constant is deposited on the epitaxial layer 102 as a field plate, and the field plate is etched so that the field plate is located between the openings of the first trench 111 and the second trench 112 and is connected to the polysilicon layer 106.

[0042] like Figure 7 As shown, a P-type polysilicon layer 108 is then deposited above the epitaxial layer and the field plate as a metal interconnect layer 108. This metal interconnect layer 108 covers a portion of the field plate 107, the opening of the first trench 111, and the opening of the second trench 112. The metal interconnect layer 108 is connected to both the field plate 107 and the P-type polysilicon layer 106 to regulate impurity charges and improve device reliability.

[0043] like Figure 8 As shown, hafnium dioxide is deposited on a portion of the non-metallic bonding layer of the field plate 107 to obtain an isolation layer 109, which can be used for isolation and smoothing.

[0044] The terminal structure of the power device is obtained through the above specific process flow. After trench etching on the epitaxial layer 102, ion implantation is performed to obtain a deep junction and a field limiting ring to expand the width of the depletion region. Polycrystalline silicon and a high dielectric constant material are used to fill the trenches of the deep junction and the field limiting ring, respectively. A field plate 107 is formed by the high dielectric constant material. Then, polycrystalline silicon is deposited as a metal interconnect layer 108 on the field plate 107, the first trench 111 and the second trench 112. This allows the structure of deep junction 104, field limiting ring 105 and field plate 107 to be formed on the silicon carbide epitaxial layer 102 without affecting the surface lattice of silicon carbide. The influence of impurity charge on the power device can also be controlled by the metal interconnect layer 108, thereby improving the voltage withstand capability of the terminal structure and increasing the reliability of the power device.

[0045] like Figure 9 As shown, this embodiment provides a terminal structure for a power device, which includes, for example, a main structure, a P-type deep junction 104, a P-type field limiting ring 105, a polysilicon layer 106, a field plate 107, and a metal interconnect layer 108.

[0046] Specifically, the main structure consists of a substrate layer 101 and an epitaxial layer 102. The epitaxial layer 102 has a first trench 111 and a second trench 112. The bottom of the first trench 111 and the bottom of the second trench 112 are arc-shaped.

[0047] The P-type deep junction 104 corresponds to the first trench 111 and is located at the bottom of the first trench 111; wherein the bottom of the P-type deep junction 104 is arc-shaped.

[0048] The P-type field limiting ring 105 corresponds to the second groove 112 and is located at the bottom of the second groove 112.

[0049] The polycrystalline silicon layer 106 fills the first trench 111 and the second trench 112.

[0050] The field plate 107 covers the epitaxial layer 102 and is located between the openings of the first trench 111 and the second trench 112. The field plate 107 is connected to the P-type polycrystalline silicon layer 106.

[0051] The metal bonding layer 108 is deposited and covers a portion of the field plate 107 and the slot; the metal bonding layer 108 is connected to the field plate 107 and the P-type polysilicon layer 106 respectively.

[0052] In existing technologies, the termination structure of power devices typically employs a field-limiting ring (FCR) design. The FCR is formed by ion implantation along with the main junction within the termination structure. However, existing termination structures generally use silicon carbide (SiC) to fabricate power devices. Due to its low diffusion coefficient, SiC cannot form deep junctions through thermal diffusion. Increasing the implantation energy to form a deep junction easily damages the SiC surface lattice, and even after a return process, the lattice cannot be restored, leading to reduced reliability of the power device. This application addresses this issue by performing trench etching on the epitaxial layer 102 followed by ion implantation to obtain a deep junction and FCR, thereby expanding the width of the depletion region. Polycrystalline silicon and a high-dielectric-constant material are used in this application. The materials are used to fill trenches in the deep junction and field limiting ring respectively, and a field plate 107 is formed by a high dielectric constant material. Then, polysilicon is deposited as a metal interconnect layer 108 on the field plate 107, the first trench 111 and the second trench 112. This allows the structure of deep junction 104, field limiting ring 105 and field plate 107 to be formed on the silicon carbide epitaxial layer 102 without affecting the surface lattice of silicon carbide. The metal interconnect layer 108 can also control the influence of impurity charge on power devices, thereby improving the voltage withstand capability of the terminal structure and increasing the reliability of power devices.

[0053] Furthermore, the terminal structure of the device also includes, for example, an isolation layer 109.

[0054] The isolation layer 109 is deposited on the non-metallic connecting layer of the field plate 107 and is connected to the metallic connecting layer 108; wherein the surface of the isolation layer 109 away from the field plate 107 is flush with the surface of the metallic connecting layer 108 away from the field plate 107.

[0055] Furthermore, the depth of the first trench 111 is 0.1-10 micrometers.

[0056] Furthermore, the spacing between the first trench 111 and the second trench 112 ranges from 0.8 to 1.2 micrometers.

[0057] Furthermore, the second trench 112 includes a plurality of trenches, and the spacing between the plurality of second trenches 112 ranges from 0.08 to 0.12 micrometers.

[0058] In this embodiment, the specific effects of each structure can be referred to the beneficial effects of each structure described in the manufacturing method of the terminal structure of the power device described above, and will not be repeated here.

[0059] Furthermore, it is understood that the foregoing embodiments are merely illustrative examples of the present invention. Provided that the technical features do not conflict, the structure is not contradictory, and the purpose of the invention is not violated, the technical solutions of the various embodiments can be arbitrarily combined and used.

[0060] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a terminal structure for a power device, characterized in that, include: A terminal region main structure is prepared, the terminal region main structure being composed of a substrate layer and an epitaxial layer located on one side of the substrate layer; Trench etching is performed on the epitaxial layer to form a first trench and a second trench on the epitaxial layer, wherein the bottom of the first trench and the bottom of the second trench are arc-shaped; An oxide layer is deposited in the first trench and the second trench such that the oxide layer covers the bottom inner wall of the first trench and the second trench; Remove the oxide layer covering the bottom of the first trench and the second trench to form an ion implantation window, and perform ion implantation into the ion implantation window to form a deep junction at the bottom of the first trench and a field confinement ring at the bottom of the second trench; Polysilicon is filled into the first trench and the second trench to form a polysilicon layer; A high dielectric constant material is deposited over the epitaxial layer, and a trench mask between the first trench and the second trench is etched to form a field plate; Polycrystalline silicon is deposited at portions of the field plate, the opening of the first trench, and the opening of the second trench to form a metal interconnect layer.

2. The method for manufacturing the terminal structure of the power device according to claim 1, characterized in that, The epitaxial layer is an N-type drift epitaxial layer.

3. The method for manufacturing the terminal structure of the power device according to claim 2, characterized in that, The ion implantation window is a P-ring ion implantation window, the deep junction is a P-type deep junction, and the field confinement ring is a P-type field confinement ring.

4. The method for manufacturing the terminal structure of the power device according to claim 2, characterized in that, After depositing polysilicon at portions of the field plate, the opening of the first trench, and the opening of the second trench to form a metal interconnect layer, the method further includes: A high dielectric constant material is deposited over the non-metallic bonding layer of the field plate to form an isolation layer; wherein the upper surface of the isolation layer is flush with the upper surface of the metallic bonding layer.

5. The method for manufacturing the terminal structure of the power device according to any one of claims 1-4, characterized in that, The high dielectric constant material is one of hafnium dioxide, silicon nitride, tantalum pentoxide, tungsten dioxide, yttrium oxide, and lanthanum oxide.

6. A termination structure for a power device, characterized in that, include: The main structure consists of a substrate layer (101) and an epitaxial layer (102). The epitaxial layer (102) has a first trench (111) and a second trench (112). The bottom of the first trench (111) and the bottom of the second trench (112) are arc-shaped. A P-type deep junction (104) corresponds to the first trench (111) and is located at the bottom of the first trench (111); wherein the bottom of the P-type deep junction (111) is arc-shaped. The P-type field limiting ring (105) corresponds to the second groove (112) and is located at the bottom of the second groove (112); A polycrystalline silicon layer (106) is filled in the first trench (111) and the second trench (112); A field plate (107) covers the epitaxial layer (102) and is located between the openings of the first trench (111) and the second trench (112). The field plate (107) is connected to the P-type polycrystalline silicon layer (106). A metal bonding layer (108) is deposited and covers a portion of the field plate (107) and the slot; the metal bonding layer (108) is connected to the field plate (107) and the P-type polysilicon layer (106), respectively.

7. The termination structure of the power device according to claim 6, characterized in that, The terminal structure of the device further includes an isolation layer (109), which is deposited on the non-metallic connection layer of the field plate (107) and connected to the metallic connection layer (108); wherein the surface of the isolation layer (109) away from the field plate (107) is flush with the surface of the metallic connection layer (108) away from the field plate (107).

8. The termination structure of the power device according to claim 6, characterized in that, The depth of the first trench (111) is 0.1-10 micrometers.

9. The termination structure of the power device according to claim 6, characterized in that, The spacing between the first trench (111) and the second trench (112) ranges from 0.8 to 1.2 micrometers.

10. The termination structure of the power device according to claim 9, characterized in that, The second trench (112) comprises a plurality of trenches, and the spacing between the plurality of second trenches (112) ranges from 0.08 to 0.12 micrometers.

Images