MOS device and manufacturing method thereof

Abstract

The invention relates to an MOS (Metal Oxide Semiconductor) device and a manufacturing method thereof. The method comprises the following steps: forming a target injection region through ion injection; covering the substrate and the gate structure with a side wall material; the side wall material is etched, and the remaining side wall material on the two sides of the gate structure forms a first side wall; a source and drain region is formed in the substrate through ion implantation, the first side wall and the gate structure serve as a barrier layer of ion implantation, and the part, not overlapped with the source and drain region, of the target implantation region serves as an LDD region; performing surface treatment on the first side wall through dry etching; and performing dry etching on the residual side wall material after the surface treatment to obtain a second side wall. According to the method, an etching-injection-etching mode is adopted, etching is firstly carried out to form the wider first side wall, then source-drain injection is carried out to obtain a wider LDD region, secondary etching is carried out after injection is completed, connecting strips and residues of side wall materials are eliminated, a clean and complete substrate surface is obtained, and HCI reliability can be improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a MOS device, and also to a method for manufacturing a MOS device. Background Technology

[0002] 5V MOS devices are widely used in semiconductor I / O (input / output) circuits. Whether it is an earlier process with a feature size >1 micrometer or an advanced process with a size <28nm, 5V I / O circuits can be seen everywhere.

[0003] As the feature size of core devices continues to shrink, various secondary effects are making the reliability issues of 5V I / O devices increasingly prominent. Among these, the HCI (hot carrier injection) reliability assessment of 5V MOS is particularly evident, and NMOS devices, due to the more reactive electrons in their channel carriers, face even greater HCI assessment risks during device development. When the minimum size of 5V NMOS devices shrinks to 0.6 micrometers and below, HCI risk has become a critical factor that cannot be ignored in device development. Taking HCI assessment data from a 0.11-micrometer process as an example, when the 5V NMOS device size is set to 0.6 micrometers, 0.55 micrometers, and 0.5 micrometers, the exemplary 5V NMOS HCI assessment results are 0.19 years, 0.16 years, and 0.08 years, respectively (SPEC requirement > 0.2 years). It is evident that as the size shrinks, the HCI risk increases dramatically. Summary of the Invention

[0004] Therefore, it is necessary to provide a MOS device and its manufacturing method that can improve the HCI reliability of the device.

[0005] A method for manufacturing a MOS device, characterized by comprising: forming target implantation regions in a substrate below a gate structure and located on both sides of the gate structure by ion implantation, the gate structure including a gate dielectric layer and a gate on the gate dielectric layer; covering the substrate and the gate structure with sidewall material; etching the sidewall material, the remaining sidewall material on both sides of the gate structure forming a first sidewall; forming source / drain regions in the substrate by ion implantation, the first sidewall and the gate structure serving as ion implantation blocking layers, the source / drain regions partially overlapping with the target implantation regions, the portion of the target implantation regions not overlapping with the source / drain regions serving as an LDD region; the implantation dose of the ion implantation forming the target implantation regions being less than the implantation dose of the ion implantation forming the source / drain regions, the conductivity type of the target implantation regions being the same as that of the source / drain regions; performing surface treatment on the first sidewall by dry etching; performing dry etching on the remaining sidewall material after the surface treatment to obtain a second sidewall; the width of the second sidewall being less than the width of the first sidewall.

[0006] The aforementioned MOS device manufacturing method employs an etch-implant-etch approach. First, a relatively wide first sidewall is etched. Then, source / drain implantation is performed using the first sidewall and gate structure as an implantation barrier layer. After implantation, a second etching process is performed to obtain the second sidewall and remove any strands and residues of the sidewall material, resulting in a clean and complete substrate surface. Because the width of the first sidewall, serving as the source / drain implantation barrier layer, is wider than the final formed second sidewall, the source / drain region is smaller and the LDD region is larger compared to the scheme using the second sidewall and gate structure as the implantation barrier layer. Since the LDD region forms a doping concentration gradient between the source / drain region and the conductive channel, the resulting gradually changing junction effectively reduces the peak electric field and improves HCI. A larger LDD region results in better HCI reliability. Therefore, a larger LDD region improves HCI reliability. Furthermore, the second etching process uses a two-step etching step. The first etching step performs surface treatment, releasing charge and removing surface impurities to prevent device defects.

[0007] In one embodiment, the step of dry etching the remaining sidewall material after the surface treatment uses an etching power greater than that used in the step of surface treatment of the first sidewall by dry etching.

[0008] In one embodiment, the step of surface treatment of the first sidewall by dry etching is to perform dry etching using CF4 and O2 as etching gases.

[0009] In one embodiment, after the step of forming the source / drain region in the substrate by ion implantation and before the step of surface treating the first sidewall by dry etching, a step of heat-treating the source / drain region and the LDD region is further included.

[0010] In one embodiment, the heat treatment employs a rapid thermal annealing process. In one embodiment, the heat treatment temperature is 1000 degrees Celsius.

[0011] In one embodiment, the MOS device is a CMOS device, or the MOS device is an NMOS device, or the MOS device is a PMOS device.

[0012] In one embodiment, prior to forming the target injection region, the step of forming a well region in the substrate is further included, wherein the target injection region is formed in the well region and the conductivity type of the well region is opposite to that of the target injection region.

[0013] In one embodiment, the step of forming a shallow trench isolation structure is included before the step of forming a well region in the substrate.

[0014] In one embodiment, after obtaining the second sidewall, the method further includes the step of forming metal silicide on the upper surface of the source / drain region and the upper surface of the gate.

[0015] A MOS device includes: a substrate; a gate structure located on the substrate, including a gate dielectric layer and a gate on the gate dielectric layer; a second sidewall located on both sides of the gate structure; a source / drain region located in the substrate; and an LDD region located below the second sidewall, extending on one side below the gate structure and on the other side to the source / drain region; the MOS device is manufactured according to the manufacturing method of the MOS device according to any of the foregoing embodiments.

[0016] The MOS devices described above are manufactured using the manufacturing method of the MOS devices described in any of the preceding embodiments, and therefore have better HCI reliability.

[0017] In one embodiment, a metal silicide layer is further formed on the upper surface of the source / drain region and the upper surface of the gate.

[0018] In one embodiment, the feature size of the MOS device is no greater than 0.6 micrometers.

[0019] In one embodiment, the feature size of the MOS device is from 0.45 micrometers to 0.6 micrometers. Attached Figure Description

[0020] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0021] Figure 1 This is a flowchart of a method for manufacturing a MOS device according to an embodiment of this application.

[0022] Figures 2a to 2e According to one embodiment of this application Figure 1 The diagram shows a cross-sectional view of the MOS device during the manufacturing process using the method shown.

[0023] Figure 3 This is a flowchart of a method for manufacturing a MOS device in one embodiment of this application, prior to step S110. Detailed Implementation

[0024] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0026] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0027] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0028] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0029] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0030] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0031] Taking a 1.5V / 5V CMOS EN process with a feature size of 0.11 micrometers as an example, its products are mainly used in digital feedback circuits, analog power amplifiers, etc. The core device, operating at 1.5V, functions as logic circuits, while the 5V device functions as I / O (input / output) circuits. The process adopts the 0.11-micrometer standard design rules, with a minimum feature size of 0.11 micrometers for the core device, 0.5 micrometers for the 5V I / O device, a polysilicon gate thickness of 1600 Å, and a gate oxide thickness of 130 Å for the 5V device.

[0032] The analysis reveals the high risk of high-level collisional interference (HCI) in 5V CMOS devices as their size shrinks: The mechanism of HCI involves collisional ionization under a strong electric field, generating a large number of electron-hole pairs. High-energy electrons or holes are injected into the gate oxide and field oxide, leading to device degradation. The strongest electric field in the device occurs at the interface near the active region at the drain, and the electric field is depleted along the channel direction from the drain to the source. However, the Lightly Doped Drain (LDD) implantation process can form a lightly doped buffer zone below the gate boundary and between the source and drain. This buffer zone (i.e., the LDD region) creates a doping concentration gradient between the source / drain and the channel, thus forming a gradually changing junction that effectively reduces the peak electric field and improves HCI.

[0033] The above analysis shows that the larger the length of the conductive channel (feature size) and the longer the depletion region of the electric field, the lower the risk of high-frequency interference (HCI). A larger LDD region results in better HCI reliability. However, with the miniaturization of device dimensions, the depletion region of the electric field becomes shorter; on the other hand, the thinning of the polysilicon gate thickness also leads to a continuous decrease in the width of the gate sidewall (spacer). Since the size of the LDD region mainly depends on the width of the spacer, this results in an increasingly smaller buffer region for the LDD, making HCI an increasingly prominent problem.

[0034] One way to improve HCI reliability is to increase the spacer width to expand the LDD region. Given a polysilicon gate size, the spacer width primarily depends on the thickness of the spacer film deposition and the over-etch (OE) time of the spacer etching. A thicker film deposition results in a larger spacer width; a shorter OE time also results in a larger spacer width. However, in practical processes, the room for adjustment of these two factors is very limited. Both increasing the film thickness and decreasing the OE time introduce the risk of spacer material residue or even chains in the source / drain regions, LDD region, and above the gate. During subsequent metallization, the areas containing residue or chains cannot form metallization, leading to interconnect failure.

[0035] The size of the LDD region can also be adjusted by adding a special photomask, or even by adding a special drift region layer to weaken the electric field, but this would greatly increase the cost of research and development.

[0036] This application innovatively proposes a novel self-aligned structure and process to address the issue of HCI reliability testing failures for 5V MOS devices with feature sizes below 0.6 micrometers. This structure can be adapted to 5V MOS devices of different sizes, greatly enhancing HCI reliability and reducing the risk of HCI testing during device development. Figure 1This is a flowchart of a method for manufacturing a MOS device according to an embodiment of this application, including the following steps:

[0037] S110, the target implantation region is formed by ion implantation.

[0038] See Figure 2a Ion implantation is performed on the wafer to form target implantation regions 222 located in the substrate 210 below the gate structure 230 and on both sides of the gate structure 230. The gate structure 230 includes a gate dielectric layer 232 and a gate 234 on the gate dielectric layer 232.

[0039] In one embodiment of this application, the substrate 210 is a semiconductor substrate, and its material can be undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc., or it can be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors. Figure 2a In the embodiment shown, the substrate 210 is made of monocrystalline silicon.

[0040] In one embodiment of this application, the gate dielectric layer 232 may comprise conventional dielectric materials such as silicon oxides, nitrides, and oxynitrides having a dielectric constant from about 4 to about 20 (measured in vacuum), or the gate dielectric layer 232 may comprise a generally higher dielectric material having a dielectric constant from about 20 to at least about 100. Such higher dielectric materials may include, but are not limited to, hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs).

[0041] In one embodiment of this application, the gate 234 is made of polysilicon. In other embodiments, metals, metal nitrides, metal silicides, or similar compounds may also be used as the material of the gate 234.

[0042] See Figure 3 In one embodiment of this application, the following steps are included before step S110:

[0043] S102 forms a shallow trench isolation structure.

[0044] Shallow trench isolation structure (STI) 240 is formed on substrate 210 to distinguish the active region.

[0045] S104 forms a well region in the substrate.

[0046] Well region 212 is formed by ion implantation. In one embodiment of this application, the target implantation region 222 has a first conductivity type, and step S110 involves implanting ions of the first conductivity type; well region 212 has a second conductivity type, and step S104 involves implanting ions of the second conductivity type. In one embodiment of this application, Figure 2a The MOS device to be formed is an NMOSFET, with N-type as the first conductivity type and P-type as the second conductivity type; in other embodiments... Figure 2a The MOS device to be formed can also be a PMOSFET, with the first conductivity type being P-type and the second conductivity type being N-type.

[0047] S106 forms the gate structure.

[0048] In one embodiment of this application, a dielectric material layer is formed on a substrate 210, and then polysilicon is deposited on the dielectric material layer. A gate structure 230 is then formed by photolithography and etching using a gate photomask.

[0049] After step S106 is completed, proceed to step S110. After step S110 is completed, proceed to step S120.

[0050] S120 has sidewall material covering the substrate and gate structure.

[0051] In one embodiment of this application, sidewall material is deposited on the front side of the wafer to form a sidewall material layer 250, see [link to relevant documentation]. Figure 2b As mentioned earlier, the thicker the sidewall material is deposited, the wider the sidewall will be. Therefore, in order to form a wider sidewall in the next step, step S120 requires depositing a thicker sidewall material than in conventional methods.

[0052] S130, Etching the sidewall material to form the first sidewall.

[0053] After etching, the remaining sidewall material on both sides of the gate structure 230 forms the first sidewall 252. The boundary between the LDD region and the source / drain region is located near the first sidewall 252, so the design width of the first sidewall 252 can be obtained based on the design width of the LDD region. In this embodiment, a wider LDD region than conventional solutions is desired, therefore the design width of the first sidewall 252 is also larger than that of the sidewall (spacer) in conventional solutions. Due to the large width of the first sidewall 252, the over-etching time in step S130 is very short (the over-etching time can be planned based on the design width of the first sidewall 252), which can easily lead to residues and / or connections on the structure surface. Figure 2c The residual and the connecting strip are represented by a star-shaped structure. In one embodiment of this application, the etching in step S130 is performed using a dry etching process.

[0054] S140 forms source / drain regions in the substrate through ion implantation.

[0055] In one embodiment of this application, a first sidewall 252 and a gate structure 230 are used as a barrier layer for ion implantation. Ions of a first conductivity type are implanted to form a source / drain region 224 in the well region 212. The source / drain region 224 and the target implantation region 222 ( Figure 2d (Not marked in the text) The portion of the target injection region 222 that does not overlap with the source / drain region 224 is designated as LDD region 222a, and the width d of LDD region 222a is as follows: Figure 2d As shown. The doping concentration of the source / drain region 224 is greater than that of the LDD region 222a, therefore the implantation dose in step S140 is less than the implantation dose in step S110.

[0056] Because residues or chains may remain after etching in step S130, hindering source / drain implantation in step S140, step S140 employs a higher implantation energy than conventional source / drain implantation techniques. This ensures sufficient implantation depth and doping concentration in the source / drain regions 224, guaranteeing the device's operating current reaches the required value. In one embodiment of this application, after step S140, a heat treatment step is included for the source / drain regions 224 and the LDD region 222a. This heat treatment results in a more uniform distribution of the implanted impurities. Figure 2d In the embodiment shown, the source / drain region 224 is an N+ region, and the well region 212 is a deep P-well.

[0057] S150, the first sidewall is surface-treated by dry etching.

[0058] After step S140, the sidewall material is etched in two steps, with step S150 being the first etching step. In one embodiment of this application, the first etching step uses a lower etching power to perform surface treatment on the wafer, perform charge release, and remove impurities such as moisture from the wafer surface, thereby avoiding device defects and measurement errors caused by charge.

[0059] S160, dry etching is performed on the remaining sidewall material to obtain the second sidewall.

[0060] Step S160 is the second etching step. In one embodiment of this application, the same etching process parameters as in step S130 can be used for etching, but the etching power is greater than that used in step S150. This etching step aims to remove any remaining residue and connecting stripes as much as possible. After etching, the first sidewall 252 is shortened to the second sidewall 252a, as shown in the reference. Figure 2e .

[0061] The aforementioned MOS device manufacturing method employs an etch-implant-etch approach. First, a relatively wide first sidewall 252 is etched. Then, source / drain implantation is performed using the first sidewall 252 and the gate structure 230 as implantation barriers. After implantation, a second etching process is performed to obtain the second sidewall 252a, eliminating any strands and residues of the sidewall material, resulting in a clean and complete substrate surface. Since the width of the first sidewall 252, serving as the source / drain implantation barrier, is wider than the final formed second sidewall 252a, the source / drain region 224 is smaller and the LDD region 222a is larger compared to the scheme using the second sidewall 252a and the gate structure 230 as implantation barriers. Because the LDD region 222a forms a doping concentration gradient between the source / drain region 224 and the conductive channel, the resulting gradual junction effectively reduces the peak electric field and improves HCI. A larger LDD region 222a results in better HCI reliability. Therefore, a larger LDD region 222a improves HCI reliability. Furthermore, the second etching process employs a two-step etching method. The first etching step (i.e., step S150) is used for surface treatment, charge release, and removal of surface impurities to prevent defects in the device.

[0062] In one embodiment of this application, step S150 uses CF4 and O2 as etching gases for dry etching, which has a better surface treatment effect, that is, the effect of charge release and removal of surface moisture and other impurities is more ideal.

[0063] In one embodiment of this application, the heat treatment step is performed after step S140 and before step S150. Specifically, it may involve performing rapid thermal annealing (RTA) on the wafer after step S140 and before step S150, at a temperature of approximately 1000 degrees Celsius.

[0064] In one embodiment of this application, after step S160, a step of forming metal silicides on the upper surface of the source / drain region 224 and the upper surface of the gate 234 is further included. Metal silicides are also formed on the upper surface of the LDD region 222a that is not shielded by the second sidewall 252a and the gate dielectric layer 232. The metal silicides may include materials such as CoSix, NiSix, and PtSix, or combinations thereof. By thoroughly removing the residue and ties through a second etching (steps S150 and S160), it is ensured that the metal silicides are formed at predetermined locations, ensuring good ohmic contacts in the device.

[0065] Regardless of whether it's an NMOS, PMOS, or CMOS structure, the aforementioned MOS device manufacturing methods can be used. By first forming a wider first sidewall 252, and then using source-drain optimized implantation, a wider LDD region 222a is defined. After implantation, a second etching is performed to eliminate bridging and residue, resulting in a clean and complete substrate surface, allowing subsequent processes to continue. Ultimately, the operating current and inter-connection remain unaffected. Since a larger first sidewall 252 results in a larger LDD region 222a, the width of the first sidewall 252 can be autonomously adjusted by changing the thickness of the sidewall material layer 250 deposited in step S120 and / or the etching duration in step S130. This allows for autonomous adjustment of the size of the LDD region 222a, enabling adaptation to 5V MOS devices of different sizes. Since 5V MOS devices with feature sizes below 0.6 micrometers are prone to failing HCI reliability tests, the above-mentioned MOS device manufacturing method is particularly suitable for MOS devices with feature sizes below 0.6 micrometers. MOS devices with feature sizes above 0.45 micrometers (e.g., 0.6 micrometers, 0.55 micrometers, 0.5 micrometers, etc.) manufactured using the above-mentioned MOS device manufacturing method can all pass the HCI reliability test.

[0066] Reference Figures 2a to 2e This application correspondingly provides a MOS device, including:

[0067] 210 substrate;

[0068] The gate structure 230 is located on the substrate 210 and includes a gate dielectric layer 232 and a gate 234 on the gate dielectric layer 232.

[0069] The second sidewall 252a is located on both sides of the gate structure 230;

[0070] Source / drain region 224 is located in substrate 210;

[0071] LDD region 222a is located below the second sidewall 252a, and extends to the bottom of the gate structure 230 on one side and to the source / drain region 224 on the other side; the conductivity type of LDD region 222a is the same as that of source / drain region 224, but the doping concentration is lower than that of source / drain region 224.

[0072] The MOS device is manufactured according to the manufacturing method of the MOS device described in any of the foregoing embodiments.

[0073] In one embodiment of this application, the MOS device further includes a shallow trench isolation structure.

[0074] In one embodiment of this application, the MOS device further includes a well region 212 located in the substrate 210, and a source / drain region 224 and an LDD region 222a located in the well region 212. The source / drain region 224 and the LDD region 222a have a first conductivity type, and the well region 212 has a second conductivity type. In one embodiment of this application, the MOS device is an NMOSFET, with the first conductivity type being N-type and the second conductivity type being P-type; in other embodiments, the MOS device may also be a PMOSFET, with the first conductivity type being P-type and the second conductivity type being N-type.

[0075] In one embodiment of this application, the MOS device further includes a metal silicide layer formed on the upper surface of the source / drain region 224 and the upper surface of the gate 234.

[0076] It should be understood that although the steps in the flowchart of this application are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart of this application may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0077] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0078] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0079] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for manufacturing a MOS device, characterized in that, include: Target implantation regions are formed in the substrate below the gate structure and on both sides of the gate structure by ion implantation. The gate structure includes a gate dielectric layer and a gate on the gate dielectric layer. Sidewall material is applied to the substrate and the gate structure; The sidewall material is etched, and the remaining sidewall material on both sides of the gate structure forms the first sidewall; Source / drain regions are formed in the substrate by ion implantation, the first sidewall and gate structure serve as barrier layers for ion implantation, the source / drain regions partially overlap with the target implantation region, and the portion of the target implantation region that does not overlap with the source / drain regions serves as the LDD region. The implantation dose of ion implantation forming the target implantation region is less than the implantation dose of ion implantation forming the source / drain region, and the conductivity type of the target implantation region is the same as that of the source / drain region; The first sidewall is surface-treated by dry etching; The remaining sidewall material after the surface treatment is subjected to dry etching to obtain a second sidewall; the width of the second sidewall is smaller than the width of the first sidewall.

2. The method for manufacturing a MOS device according to claim 1, characterized in that, The step of surface treatment of the first sidewall by dry etching is to use CF4 and O2 as etching gases for dry etching.

3. The method for manufacturing a MOS device according to claim 1, characterized in that, After the step of forming the source / drain region in the substrate by ion implantation and before the step of surface treatment of the first sidewall by dry etching, the method further includes a step of heat treatment of the source / drain region and the LDD region.

4. The method for manufacturing a MOS device according to claim 3, characterized in that, The heat treatment employs a rapid thermal annealing process; and / or The heat treatment temperature is 1000 degrees Celsius.

5. The method for manufacturing a MOS device according to claim 1, characterized in that, The MOS device is a CMOS device, or the MOS device is an NMOS device, or the MOS device is a PMOS device.

6. The method for manufacturing a MOS device according to claim 1, characterized in that, Before forming the target injection region, the method further includes the step of forming a well region in the substrate, wherein the target injection region is formed in the well region and the conductivity type of the well region is opposite to that of the target injection region.

7. The method for manufacturing a MOS device according to claim 1, characterized in that, The step of dry etching the remaining sidewall material after the surface treatment uses an etching power greater than that used in the step of surface treatment of the first sidewall by dry etching.

8. The method for manufacturing a MOS device according to claim 1, characterized in that, After obtaining the second sidewall, the process further includes the step of forming metal silicide on the upper surface of the source / drain region and the upper surface of the gate.

9. A MOS device, characterized in that, include: Base; A gate structure, located on the substrate, includes a gate dielectric layer and a gate on the gate dielectric layer; The second sidewall is located on both sides of the gate structure; The source / drain regions are located in the substrate; The LDD region is located below the second sidewall, with one side extending below the gate structure and the other side extending to the source / drain region; The MOS device is manufactured using the method for manufacturing a MOS device according to any one of claims 1-8.

10. The MOS device according to claim 9, characterized in that, It also includes metal silicide layers formed on the upper surfaces of the source / drain regions and the upper surface of the gate.

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