Formation method of semiconductor structure
By forming a protective layer on top of the isolation structure of the FinFET and controlling the etching process, the problem of excessive oxide etching in the source and drain region etching trenches is solved, ensuring the reliability of the semiconductor structure and the integrity of the interconnect structure.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING INTPROP OPERATION MANAGEMENT CO LTD
- Filing Date
- 2024-11-14
- Publication Date
- 2026-05-15
AI Technical Summary
In the semiconductor manufacturing process, during the fabrication of FinFETs, excessive etching of the oxide in the isolation structure (STI region) during the source and drain region etching trenches can lead to oxide loss, forming voids that affect the deposition of subsequent interlayer dielectric layers and the reliability of the interconnect structure.
A protective layer is formed in the second trench at the top of the isolation structure. By controlling the etching process, the etching of the isolation structure is reduced, the aspect ratio of the second trench is lowered, and voids are avoided.
This effectively avoids excessive etching of the isolation structure, ensures the integrity of the interlayer dielectric layer, prevents short circuits between the interconnect structure and the matrix, and improves the reliability of the semiconductor structure.
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Figure CN122054620A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Technology
[0002] As integrated circuit manufacturing processes continue to evolve and dimensions shrink further, improving carrier mobility has become a pressing issue. In the fabrication of FinFETs, trenches are etched in the source and drain regions to deposit germanium-silicon composites and phosphorus-silicon composites, thereby increasing carrier mobility by creating different stresses.
[0003] However, with the increasing complexity of patterns and the diversification of deposited films, during the etching of trenches in the source and drain regions, not only the active (AA) region is etched, but also the oxide in the shallow trench isolation (STI) region. If too much oxide is missing, the opening formed by the etching in the STI region will be too deep. As a result, when the interlayer medium layer is deposited in the subsequent process, voids may be formed inside the interlayer medium layer deposited at the opening. When the contact hole is etched in the subsequent process, due to the presence of voids, the matrix located at the bottom of the STI region may be etched, which may cause a short circuit between the interconnect structure and the matrix.
[0004] Therefore, a method for forming semiconductor structures is needed to avoid over-etching of the oxide in the STI region during the etching of trenches in the source and drain regions. Summary of the Invention
[0005] The purpose of this application is to provide a method for forming a semiconductor structure to avoid over-etching of the oxide in the STI region during the etching of trenches in the source and drain regions.
[0006] This application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, wherein a plurality of fins are formed on the semiconductor substrate; an isolation structure for isolating adjacent fins and having its top surface lower than the top surface of the fins; a plurality of dummy gate structures located on the surface of the isolation structure and covering the sidewalls and top surface of the fins; a first trench and a second trench are formed between adjacent dummy gate structures; the first trench exposes the top surface of the fins; and the second trench exposes the isolation structure; forming a sidewall layer covering the sidewalls and top of the dummy gate structures and the bottom of the first trench and the second trench; and forming a top protective layer located at the bottom of the second trench and covering the sidewall layer.
[0007] In some embodiments, a method of forming a protective layer at the bottom of the second trench covering the top surface of the sidewall layer includes: forming a protective layer in the first trench and the second trench and on the surface of the sidewall layer, the protective layer filling the first trench and the second trench; planarizing the protective layer so that the top surface of the protective layer is at the same height; and etching the protective layer until the protective layer in the first trench is completely removed and the protective layer in the second trench is partially retained.
[0008] In some embodiments, the method of forming the semiconductor structure further includes etching the sidewall layer at the bottom of the first trench into the fin to form a first opening.
[0009] In some embodiments, after etching the sidewall layer at the bottom of the first trench to form a first opening in the fin, the depth-to-width ratio of the second trench is less than or equal to (6-7):1.
[0010] In some embodiments, the method of etching the sidewall layer at the bottom of the first trench into the fin to form a first opening includes: performing a first etching to remove the sidewall layer at the bottom of the first trench, exposing the fin, and simultaneously removing the sidewall layer at the top of the dummy gate structure; performing a second etching to partially etch the top surface of the fin exposed by the first trench to form the first opening; performing a third etching to deepen the first opening; and performing a fourth etching to increase the depth of the first opening to a set depth.
[0011] In some embodiments, during the etching of the sidewall layer at the bottom of the first trench to form a first opening in the fin, the bottom of the second trench is simultaneously etched, and after the first etching is completed, the protective layer in the second trench is still retained.
[0012] In some embodiments, the protective layer in the second trench is completely removed after the second etching is completed.
[0013] In some embodiments, the method of forming the semiconductor structure further includes: growing a germanium-silicon composite or a phosphorus-silicon composite in the first opening; and forming an interlayer dielectric layer that fills the first trench, the second trench and covers the top surface of the second hard mask layer and the top surface of the sidewall layers located on both sides of the second hard mask layer.
[0014] In some embodiments, the material of the protective layer includes polycrystalline silicon.
[0015] The beneficial effects of the semiconductor structure formation method provided in this application embodiment include, but are not limited to:
[0016] The semiconductor structure formation method provided in this application can avoid excessive etching of the protective structure when etching the source and drain regions of the fins by forming a protective layer of a certain thickness in the second trench located above the protective structure. This reduces the aspect ratio of the second trench after etching and thus avoids the formation of voids at the opening of the protective structure when depositing the interlayer dielectric layer in the subsequent process. Attached Figure Description
[0017] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale.
[0018] in:
[0019] Figures 1-3 These are schematic diagrams illustrating the steps involved in forming some semiconductor structures.
[0020] Figures 4-29 This is a schematic diagram of the steps of a method for forming a semiconductor structure according to some embodiments of this application. Detailed Implementation
[0021] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.
[0022] Figure 1 This is a schematic diagram of a semiconductor structure during the fabrication of a FinFET device. The semiconductor structure includes: a semiconductor substrate 10; a plurality of fins 11 located on the surface of the semiconductor substrate 10; an isolation structure 12 located on the surface of the semiconductor substrate 10 between adjacent fins 11 for isolating adjacent fins 11, the top surface of the isolation structure being lower than the top surface of the fins 11; a dummy gate structure 13 located on the surface of the isolation structure 12 and covering the sidewalls and top surface of the fins; a first trench 14 exposing the top surface of the fins 11; a second trench 15 exposing the isolation structure 12; and a sidewall layer 16 covering the sidewalls and top of the first trench 14 and the second trench 15, as well as the top surface of the dummy gate structure 15.
[0023] refer to Figure 2 During the fabrication of the FinFET device, a first opening 14a is etched in the source / drain region of the fin 11 to deposit germanium-silicon composite and phosphorus-silicon composite. However, while etching the fin 11, the isolation structure 12 is also etched, forming a second opening 15a. This results in an excessively large aspect ratio of the second trench 15 after etching. (Refer to...) Figure 3 During the subsequent deposition of the interlayer dielectric layer 17, voids 18 may be formed inside the interlayer dielectric layer 17 deposited in the second trench 15. During the subsequent etching of contact holes, due to the presence of voids 18, the substrate 10 located at the bottom of the isolation structure 12 may be etched, thereby causing a short circuit between the interconnect structure and the substrate 10.
[0024] Therefore, a method for forming a semiconductor structure and a semiconductor structure are needed to avoid over-etching of the isolation structure when etching the source and drain regions of the fins.
[0025] This application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, wherein a plurality of fins are formed on the semiconductor substrate; an isolation structure for isolating adjacent fins and having its top surface lower than the top surface of the fins; a plurality of dummy gate structures located on the surface of the isolation structure and covering the sidewalls and top surface of the fins; a first trench and a second trench are formed between adjacent dummy gate structures; the first trench exposes the top surface of the fins; and the second trench exposes the isolation structure; a sidewall layer is formed on the sidewalls and bottom of the first trench and the second trench and on the top surface of the dummy gate structures; and a protective layer is formed in the second trench.
[0026] The semiconductor structure formation method provided in this application fills a protective layer in a second trench located on top of the isolation structure. During the etching process of the fins, the protective layer will preferentially etch the isolation structure, thereby reducing the etching depth of the isolation structure and avoiding over-etching of the isolation structure.
[0027] The method for forming the semiconductor structure provided in this application will be described in detail below with reference to the embodiments and accompanying drawings.
[0028] It should be noted that the specification describes various operations sequentially as multiple discrete operations in a manner most conducive to understanding this application; however, the order of description should not be interpreted as implying that these operations must depend on the order. More specifically, these operations do not need to be performed in the order described.
[0029] Figure 4 This is a schematic diagram of a semiconductor structure according to an embodiment of this application; Figure 5 for Figure 4 The cross-sectional view of the semiconductor structure shown is along the AA direction; and Figure 6 for Figure 4 The accompanying diagram shows a cross-sectional view of the semiconductor structure along the BB direction. It should be noted that the diagram showing the cross-sectional variation of the semiconductor structure along the AA direction is labeled AA at the bottom, and the diagram showing the cross-sectional variation of the semiconductor structure along the BB direction is labeled BB at the bottom.
[0030] refer to Figures 4-6 A semiconductor substrate 100 is provided, wherein a plurality of fins 110 are formed on the surface of the semiconductor substrate 100, and an isolation structure 120 is located between adjacent fins 110 and the top surface of the semiconductor substrate is lower than the top surface of the fins 110.
[0031] In some embodiments, the material of the semiconductor substrate 100 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or silicon on insulator (SOI) or (iv) a combination thereof.
[0032] In some embodiments, the fin 110 is integrated with the semiconductor substrate 100.
[0033] In some embodiments, the method of forming the fin 110 may include: growing an epitaxial layer on the semiconductor substrate 100; forming a patterned mask layer on the epitaxial layer; and using the patterned mask layer as a mask to etch the epitaxial layer and the semiconductor substrate 100 to form the fin 110. For example, the etching may be performed using a dry etching process, a wet etching process, or a combination thereof.
[0034] In some embodiments, the material of the isolation structure 120 includes silicon oxide.
[0035] refer to Figure 7 and 8 A plurality of dummy grid structures 130 are formed to cover the surface of the isolation structure 120 and the sidewalls and top surface of the fin 110. A first groove 140 and a second groove 150 are formed between adjacent dummy grid structures 130. The first groove 140 exposes the top surface of the fin 110, and the second groove 150 exposes the isolation structure 120.
[0036] In some embodiments, the dummy gate structure 130 includes a polysilicon layer 130a, a first hard mask layer 130b, and a second hard mask layer 130c stacked sequentially on the surfaces of the fin 110 and the isolation structure 120.
[0037] In some embodiments, the material of the first hard mask layer 130b includes silicon nitride; and the material of the second hard mask layer 130c includes silicon oxide.
[0038] In some embodiments, the methods for forming the polysilicon layer 130a, the first hard mask layer 130b, and the second hard mask layer 130c include, but are not limited to, chemical vapor deposition, atomic layer deposition, physical vapor deposition, and sputtering processes.
[0039] refer to Figure 9 and Figure 10 A sidewall layer 160 is formed that covers the sidewalls and top of the dummy grid structure 130 and the bottom of the first trench 140 and the second trench 150.
[0040] The sidewall layer 160 is used to form sidewalls on the sidewalls of the dummy gate structure 130. The sidewall layer 160 can be a single layer or a double layer. In some embodiments, the sidewall layer 160 includes an inner sidewall layer and an outer sidewall layer stacked sequentially on the sidewalls and top of the dummy gate structure 130 and at the bottom of the first trench 140 and the second trench 150. The material of the inner sidewall layer includes a low-K material, which refers to a dielectric material with a dielectric constant less than 3.9. The material of the outer sidewall layer includes silicon nitride.
[0041] refer to Figure 11 and Figure 12 A protective layer 170 is formed in the first trench 140 and the second trench 150 and on the surface of the sidewall layer 160, the protective layer 170 filling the first trench 140 and the second trench 150.
[0042] In some embodiments, the protective layer 170 is made of polycrystalline silicon. The polycrystalline silicon and the silicon nitride of the second sidewall layer have significantly different physicochemical properties, making them easily distinguishable during the etching process and reducing the amount of the protective layer 170 etched when etching the second sidewall layer. In some embodiments, the etching selectivity ratio of the polycrystalline silicon to the silicon nitride is 1:(4-6), optionally, it is 1:4, 1:5, or 1:6.
[0043] In some embodiments, the method for forming the protective layer 170 in the first trench 140 and the second trench 150 and on the surface of the sidewall layer 160 includes vapor phase deposition, solution deposition, solidification deposition, or a combination thereof. In some embodiments, the method for forming the protective layer 170 in the first trench 140 and the second trench 150 and on the surface of the sidewall layer 160 is plasma-enhanced chemical vapor deposition (PECVD).
[0044] refer to Figure 13 and Figure 14 The protective layer 170 is flattened so that the top surface of the protective layer 170 is at the same height (i.e., the top surface is flat).
[0045] In some embodiments, the method for planarizing the protective layer 170 includes chemical mechanical polishing (CMP).
[0046] refer to Figure 15 and Figure 16 The protective layer 170 is etched until it is completely removed from the first trench 140, while a portion of the protective layer 170 is retained in the second trench 150. The retained portion of the protective layer 170 can reduce the etching of the isolation structure 120 at the bottom of the second trench 150 when the first trench 140 is further etched.
[0047] In some embodiments, the method of etching the protective layer 170 includes a dry etching process, a wet etching process, or a combination thereof.
[0048] In some embodiments, after retaining a portion of the protective layer 170 within the second trench 150, the method further includes etching the sidewall layer 160 of the bottom 140 of the first trench to form a first opening 141 in the fin.
[0049] In conventional processes, without the protective layer 170, during the etching of the bottom of the first trench 140, the isolation structure 120 located in the second trench 150 will also be etched, forming a second opening 151 in the isolation structure 120. This results in an excessively large aspect ratio of the second trench 150, making it easy for voids to form when depositing the interlayer medium layer in the second trench 150 later. By setting the protective layer 170, the amount of etching of the isolation structure 120 during the etching of the bottom of the first trench 140 can be reduced, thereby reducing the aspect ratio of the second trench 150 after etching and avoiding void defects when depositing the interlayer medium layer in the second trench 150 later.
[0050] In some embodiments, after etching the sidewall layer at the bottom of the first trench to form a first opening in the fin, the depth-to-width ratio of the second trench is less than or equal to (6-7):1. It should be noted that the second trench 150 here includes the second opening 151.
[0051] To more clearly illustrate the role of the protective layer 170 in the etching process, the following will describe in detail the etching of the protective layer 170 located in the second trench 150 and the isolation structure 120 located at the bottom of the second trench 150 during the etching of the bottom of the first trench 140.
[0052] Specifically, in some embodiments, etching the bottom of the first trench 140 to form a first opening on the top surface of the fin includes the following steps:
[0053] Step S1, refer to Figure 17 and Figure 18 The first etching is performed to remove the sidewall layer 160 at the bottom of the first trench 140. During this process, the sidewall layer 160 on the top surface of the dummy grid structure 130 is also removed, and the protective layer 170 in the second trench 150 is partially removed.
[0054] In conventional processes, without a protective layer, the sidewall layer 160 at the bottom of the second trench 150 would also be etched away. However, in the technical solution of this application, the protective layer 170 is used as a sacrificial material for etching allowance protection, so only a portion of the protective layer 170 is etched away, and the sidewall layer 160 at the bottom of the second trench 150 is not etched at this step. Furthermore, the thickness of the protective layer 170 satisfies the following conditions:
[0055] T>h s *A1,
[0056] Where T represents the thickness of the protective layer; h s A1 represents the thickness of the sidewall layer 160; A1 represents the etching selectivity ratio of etching the protective layer 170 to etching the sidewall layer 160 in step S1.
[0057] In some embodiments, in step S1, the etching selectivity ratio of etching the protective layer 170 to etching the sidewall layer 160 is (0.18 to 0.22):1. Optionally, the etching selectivity ratio of etching the protective layer 170 to etching the sidewall layer 160 is 0.18:1, 0.2:1, or 0.22:1.
[0058] Because the thickness of the protective layer 170 satisfies T>hs*A1, after etching away the sidewall layer 160 at the bottom of the first trench 140, a portion of the protective layer 170 remains to continue protecting the sidewall layer 160 at the bottom of the second trench 150 and the isolation structure 120.
[0059] Step S2, refer to Figure 19 and Figure 20 A second etching process is performed, in which the top surface of the fin 110 exposed by the first trench 140 is partially etched to form a first opening 141. During this process, the protective layer 170 in the second trench 150 is completely removed, and the thickness of the protective layer 170 satisfies the following conditions:
[0060] T≤h s *A 1+ h1*A2,
[0061] Where T represents the thickness of the protective layer 170; h s A1 represents the thickness of the sidewall layer 160; A1 represents the etching selectivity ratio of etching the protective layer 170 to etching the sidewall layer 160 in step S1; h1 represents the depth of the first opening 141 obtained by etching the fin 110 in step S2; A2 represents the etching selectivity ratio of etching the protective layer 170 to etching the fin 110 in step S2.
[0062] In some embodiments, the etching selectivity ratio of etching the protective layer 170 to etching the fin 110 in step S2 is (0.18 to 0.22):1. Optionally, the etching selectivity ratio of etching the protective layer 170 to etching the fin 110 is 0.18:1, 0.2:1, or 0.22:1.
[0063] When the thickness T of the protective layer 170 is h s When *A1+h1*A2, after the second etching is completed, the protective layer 170 is exactly completely removed; when the thickness T of the protective layer 170... <h s When *A1+h1*A2, after the second etching is completed, the sidewall layer 160 at the bottom of the second trench 150 is partially etched.
[0064] Step S3, refer to Figure 21 and Figure 22 Then, the third etching is performed to deepen the first opening 141.
[0065] In some embodiments, after the third etching is completed, the sidewall layer 160 at the bottom of the second trench 150 is completely removed, specifically,
[0066] The thickness of the sidewall layer 160 satisfies:
[0067] h s ≤h2*A3,
[0068] Among them, h s h1 is the thickness of the sidewall layer 160 in step S2; h2 is the depth to which the first opening 141 is further etched in step S3; and A3 is the etching selectivity ratio between etching the sidewall layer 160 and etching the fin 110 in step S3.
[0069] In some embodiments, the etching selectivity ratio of etching the sidewall layer 160 to etching the fin 110 in step S3 is (0.8 to 1.2):1. Optionally, the etching selectivity ratio of etching the sidewall layer 160 to etching the fin 110 is 0.8:1, 1:1, or 1.2:1.
[0070] Step S4, refer to Figure 23 and Figure 24 A fourth etching process is performed to increase the depth of the first opening 141 to a set depth. During this process, the isolation structure 120 exposed by the second trench 150 is etched to form a second opening 151. Taking the end of step S3 when the sidewall layer 160 on the top surface of the isolation structure 120 is just completely etched as an example, the depth of the second opening 151 is...
[0071] H = h³ * A⁴
[0072] Wherein, H represents the depth of the second opening 151 after step S4; h3 is the depth to which the first opening 141 is further etched in step S4; and A4 represents the etching selectivity ratio between etching the isolation structure 120 and etching the fin 110 in step S4.
[0073] In some embodiments, the etching selectivity ratio of etching the isolation structure 120 to etching the fin 110 in step S4 is (0.8 to 1.2):1. Optionally, the etching selectivity ratio of etching the isolation structure 120 to etching the fin 110 is 0.8:1, 1:1, or 1.2:1.
[0074] It should be noted that:
[0075] h0 = h1 + h2 + h3,
[0076] h0 represents the set depth of the first opening 141; h1 represents the depth of the first opening 141 obtained by etching the fin 110 in step S2; h2 is the depth to which the first opening 141 is further etched in step S3; and h3 is the depth to which the first opening 141 is further etched in step S4.
[0077] In some embodiments, when step S2 is completed and the protective layer 170 in the second trench 150 is completely removed; and when step S3 is completed and the sidewall layer 160 in the second trench 150 is completely removed, then when the first opening 141 is etched to a set depth, the relationship between the depth of the second opening 151 and the thickness of the protective layer 170 is as follows:
[0078] H = (h0 - h1 - h2) * A4
[0079] =[h0-(Th s *A1) / A2-h s / A3]*A4
[0080] =(h0+h s *A1 / A2-h s / A3)*A4-A4 / A2*T
[0081] = a - bT;
[0082] Where a is a constant, a = (h0 + h) s *A1 / A2-h s / A3)*A4; b is a constant, b=A4 / A2; h0 represents the set depth of the first opening 141; h1 represents the depth of the first opening 141 obtained by etching the fin 110 in step S2; h2 is the depth to which the first opening 141 is further etched in step S3; h s A1 represents the thickness of the sidewall layer 160; A2 represents the etching selection ratio of etching the protective layer 170 to etching the sidewall layer 160 in step S1; A3 represents the etching selection ratio of etching the protective layer 170 to etching the fin 110 in step S2; and A4 represents the etching selection ratio of etching the isolation structure 120 to etching the fin 110 in step S4.
[0083] In other embodiments, the thickness of the protective layer 170 satisfies:
[0084] T≥h s *A1+h1*A2+h2*A3'+h3*A4',
[0085] T represents the thickness of the protective layer 170; hs represents the thickness of the sidewall layer 160; A1 represents the etching selectivity ratio of etching the protective layer 170 to etching the sidewall layer 160 in step S1; h1 represents the depth of the first opening 141 obtained by etching the fin 110 in step S2; A2 represents the etching selectivity ratio of etching the protective layer 170 to etching the fin 110 in step S2; h2 is the depth to which the first opening 141 is further etched in step S3; A3' represents the etching selectivity ratio of etching the protective layer 170 to etching the fin 110 in step S3; h3 is the depth to which the first opening 141 is further etched in step S4; and A4' represents the etching selectivity ratio of etching the protective layer 170 to etching the fin 110 in step S4.
[0086] When T>hs*A1+h1*A2+h2*A3'+h3*A4', the protective layer 170 is not completely removed after the first opening 141 is etched to the set depth; when T=hs*A1+h1*A2+h2*A3'+h3*A4', the protective layer 170 is just completely removed after the first opening 141 is etched to the set depth.
[0087] In summary, in the technical solution of this application, providing the protective layer 170 in the second trench 150 can reduce the etching of the sidewall layer 160 and the isolation structure 120 at the bottom of the second trench 150. Furthermore, by setting an appropriate thickness for the protective layer 170, the etching condition at the bottom of the second trench 150 can be precisely controlled, thereby controlling the depth and aspect ratio of the second trench 150 after etching, thus enabling the realization of corresponding semiconductor structures according to specific requirements.
[0088] In some embodiments, after etching the bottom of the first trench 140 and forming the first opening 141 on the top surface of the fin 110, the method further includes: referencing Figure 25 and Figure 26 A source / drain doped layer 180 is grown in the first opening 141, the source / drain doped layer 180 comprising a germanium-silicon composite or a phosphorus-silicon composite; and
[0089] refer to Figure 27 and 28 An interlayer dielectric layer 190 is formed, which fills the first trench 140 and the second trench 150.
[0090] In some embodiments, the method for forming the interlayer dielectric layer 190 includes, but is not limited to, processes such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, and sputtering. Because the depth of the second opening 151 is controlled to be shallower, the aspect ratio of the second trench 150 is reduced, thus the second trench 150 is easily filled and will not form voids.
[0091] refer to Figure 29 Remove the dummy gate structure 130 and form a gate opening (not shown) between the sidewall layers 160; form a gate structure 130' within the gate opening.
[0092] In some embodiments, the gate structure 130' includes: a gate dielectric layer (not shown), a gate layer (not shown) located on the gate dielectric layer, and a protective layer (not shown) located on the gate layer.
[0093] In some embodiments, the material of the gate dielectric layer includes a high-k dielectric material.
[0094] In some embodiments, the material of the gate layer includes a metal, which includes at least one selected from aluminum, copper, titanium, silver, gold, lead, and nickel.
[0095] In some embodiments, the protective layer is made of silicon nitride.
[0096] Continue to refer to Figure 29An interconnect layer 200 electrically connected to the source / drain doped layer 180 is formed above the source / drain doped layer 180.
[0097] In some embodiments, the material of the interconnect layer 200 includes at least one of copper and nickel.
[0098] The beneficial effects of the semiconductor structure formation method provided in this application embodiment include, but are not limited to:
[0099] The semiconductor structure formation method provided in this application provides a protective layer of a certain thickness in a second trench located above the protective structure. This can avoid excessive etching of the protective structure when etching the source and drain regions of the fins, thereby avoiding the formation of voids at the openings of the protective structure during subsequent deposition of the interlayer dielectric layer.
[0100] It should be noted that different embodiments may produce different beneficial effects. In different embodiments, the beneficial effects may be any one or a combination of the above, or any other possible beneficial effects.
[0101] The basic concepts have been described above. Obviously, for those skilled in the art, the detailed disclosure above is merely illustrative and does not constitute a limitation of this specification. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and corrections to this application. Such modifications, improvements, and corrections are suggested in this specification, and therefore remain within the spirit and scope of the exemplary embodiments of this application.
[0102] It should be noted that, in the description of this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; a mechanical connection or an electrical connection; a rotating connection or a sliding connection; a direct connection or an indirect connection through an intermediate medium; or the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application in light of the specific circumstances.
[0103] Furthermore, when the terms "first," "second," "third," etc., are used in this application specification to describe various features, these terms are only used to distinguish these features and should not be construed as indicating or implying the correlation or relative importance between features or implicitly indicating the number of features indicated.
[0104] In addition, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Therefore, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. Thus, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shapes of the regions of the device, nor to limit the scope of the exemplary embodiments.
[0105] Furthermore, this application uses specific terms to describe embodiments of this specification. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic related to at least one embodiment of this application. Therefore, it should be emphasized and noted that "an embodiment," "one embodiment," or "an alternative embodiment" mentioned twice or more in different locations in this application do not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of this application can be appropriately combined.
[0106] Similarly, it should be noted that, in order to simplify the description of the present application and thus aid in the understanding of one or more embodiments of the invention, the foregoing description of the embodiments of the present application sometimes combines multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of the application requires more features than those mentioned in the claims. In fact, the embodiments contain fewer features than all the features of the single embodiments disclosed above.
[0107] Finally, it should be understood that the embodiments described in this application are merely illustrative of the principles of the embodiments of this application. Other modifications may also fall within the scope of this application. Therefore, alternative configurations of the embodiments of this application are considered as examples and not limitations, and are regarded as consistent with the teachings of this application. Accordingly, the embodiments of this application are not limited to the embodiments explicitly described and illustrated in this application.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A semiconductor substrate is provided, on which a plurality of fins are formed, an isolation structure for isolating adjacent fins and having its top surface lower than the top surface of the fins, and a plurality of dummy gate structures located on the surface of the isolation structure and covering the sidewalls and top surface of the fins, wherein a first trench and a second trench are formed between adjacent dummy gate structures, the first trench exposing the top surface of the fins, and the second trench exposing the isolation structure; A sidewall layer is formed covering the sidewalls and top of the dummy grid structure, as well as the bottom of the first trench and the second trench; A protective layer is formed on the top surface of the second trench, covering the sidewall layer.
2. The method for forming a semiconductor structure according to claim 1, characterized in that, A method for forming a protective layer covering the top surface of the sidewall layer at the bottom of the second trench includes: A protective layer is formed in the first trench and the second trench and on the surface of the sidewall layer, the protective layer filling the first trench and the second trench; Planarize the protective layer so that the top surface of the protective layer is at the same height; and The protective layer is etched into the first trench, where the protective layer is completely removed, while the protective layer in the second trench is partially retained.
3. The method for forming a semiconductor structure according to claim 1, characterized in that, Also includes: The sidewall layer at the bottom of the first trench is etched into the fin to form a first opening.
4. The method for forming a semiconductor structure according to claim 3, characterized in that, After etching the sidewall layer at the bottom of the first trench to form a first opening in the fin, the depth-to-width ratio of the second trench is less than or equal to (6-7):
1.
5. The method for forming a semiconductor structure according to claim 3, characterized in that, The method of etching the sidewall layer at the bottom of the first trench into the fin to form the first opening includes: Perform the first etching to remove the sidewall layer at the bottom of the first trench, exposing the fins, and simultaneously remove the sidewall layer at the top of the dummy grid structure; A second etching is performed, in which the top surface of the fin exposed by the first trench is partially etched to form the first opening; Perform a third etching to deepen the first opening; and Perform a fourth etching to increase the depth of the first opening to a set depth.
6. The method for forming a semiconductor structure according to claim 5, characterized in that, During the process of etching the sidewall layer at the bottom of the first trench to form the first opening in the fin, the bottom of the second trench is simultaneously etched, and the protective layer in the second trench is still retained after the first etching is completed.
7. The method for forming a semiconductor structure according to claim 6, characterized in that, After the second etching is completed, the protective layer in the second trench is completely removed.
8. The method for forming a semiconductor structure according to claim 3, characterized in that, Also includes: A germanium-silicon composite or a phosphorus-silicon composite is grown in the first opening. as well as An interlayer dielectric layer is formed, which fills the first trench and the second trench and covers the top surface of the second hard mask layer and the top surface of the sidewall layers located on both sides of the second hard mask layer.
9. The method for forming a semiconductor structure according to claim 1, characterized in that, The material of the protective layer includes polycrystalline silicon.