Preparation method of GaN HEMT (High Electron Mobility Transistor) with special source field plate structure

Abstract

The invention provides a preparation method of a GaN HEMT with a special source field plate structure, relates to the field of GaN HEMT devices, and aims to simplify the process and improve the process efficiency by optimizing the field plate process of the device. The device comprises a substrate, an epitaxial layer, a protection layer medium, a passivation layer, a source electrode, a grid electrode and a drain electrode. According to the device, SiN is activated in active regions on the two sides through ion implantation and high temperature, ohmic contact windows of a gate pin, a source electrode and a drain electrode are formed in the corresponding positions of a passivation layer through etching, and then gate metal is evaporated and passivated through a medium; and after ohmic contact windows of the source electrode and the drain electrode are etched, the source electrode field plate and the drain electrode with special structures are prepared through a one-step evaporation / electroplating process. According to the method for preparing the source field plate in one step, the technological process is effectively simplified, and the technological cost is reduced. The method has the characteristics of simple manufacturing process and high manufacturing efficiency.

Description

Technical Field

[0001] This invention relates to the field of semiconductor and semiconductor manufacturing technology, and in particular to a method for fabricating a GaN HEMT with a special source field plate structure. Background Technology

[0002] High electron mobility transistors (HEMTs) possess advantages such as high frequency, high voltage, and high temperature. GaN, a third-generation semiconductor material, has become a current research hotspot due to its large bandgap (3.4 eV), high electron saturation velocity (2 × 10⁷ cm / s), high breakdown electric field (~3 × 10¹⁰ V / cm), high thermal conductivity, corrosion resistance, and radiation resistance, showing broad application prospects. In particular, AlGaN / GaN heterojunction HEMTs offer advantages such as high frequency, high power density, and high operating temperature, demonstrating significant advantages in high-temperature devices and high-power microwave devices. This has attracted considerable research in the pursuit of high-frequency, high-voltage, and high-power devices.

[0003] To ensure that GaN HEMT devices can maximize the superior characteristics of their wide bandgap material, the design of the field plate is crucial. Currently, most common field plate fabrication routes are separate from the OM metal (source and drain metals) fabrication process. This involves first creating trenches to fabricate the gate metal, then creating passivation layer openings to fabricate the source and drain metals, and finally fabricating the field plate. Due to the intricate structure and stringent linewidth requirements of gallium nitride devices, conventional field plate fabrication methods place higher demands on the device's process technology. This patent, however, proposes a method to fabricate the source and field plate in a single process. Compared to conventional methods, this invention innovatively uses a single photolithography step to fabricate both the source and the source field plate. This effectively reduces overlay steps, lowers rework rates, and reduces process costs. Therefore, by optimizing the field plate design and simplifying the process steps, the goal of improving process efficiency is achieved. Summary of the Invention

[0004] To address the aforementioned issues, this invention provides a method for fabricating GaN HEMTs with a special source field plate structure that optimizes field plate design and simplifies process steps to improve process efficiency.

[0005] This invention provides a method for fabricating GaN HEMTs with a special source field plate structure, comprising the following steps: S1. An epitaxial wafer having a SiC substrate, a GaN epitaxial layer and a protective dielectric layer, wherein the SiN layer is activated in the active regions at the source and drain by B ion or Si ion implantation and high-temperature activation. S2. Deposit a SiNx passivation layer, and then simultaneously etch out the gate pin, source ohmic contact window and drain ohmic contact window, or only etch out the gate pin. Open a hole in the SiNx passivation layer to the GaN epitaxial layer to create the area where the metal needs to be evaporated. S3. Perform gate cap photolithography and then prepare gate metal through evaporation process. Remove the photoresist, and then deposit a passivation layer to encapsulate the gate metal. S4. Open a window in the ohmic contact area between the source and drain, and open the SiNx passivation layer and passivation layer through an etching process, and etch the source ohmic contact window and drain ohmic contact window to expose the source region and drain region. S5. The drain and source field plates are prepared by metal evaporation. During evaporation, the drain region evaporates the drain electrode separately, while the source region and the field plate region above the gate metal evaporate the metal together. The evaporated source electrode and field plate form a whole, namely the source field plate.

[0006] Furthermore, it also includes the following steps: S6. Passivate the source and drain electrodes with SiNx.

[0007] Furthermore, the source field plate extends from the source towards the gate metal, covering at least a portion of the gate metal.

[0008] Furthermore, there is a gap between the drain and source field plates.

[0009] Furthermore, a dielectric layer exists between the source field plate and the gate metal.

[0010] Compared with the prior art, the present invention has the following advantages and effects: 1. Simplify the process flow; 2. Reduced process costs; 3. The manufacturing process is simple and efficient. Attached Figure Description

[0011] Figure 1 The diagram shows an epitaxial wafer consisting of a SiC substrate, a GaN epitaxial layer, and a protective dielectric layer.

[0012] Figure 2 This is a schematic diagram of ion implantation in the active regions at the source and drain of an epitaxial wafer.

[0013] Figure 3 This is a schematic diagram of gate dielectric growth.

[0014] Figure 4 This is a schematic diagram of the gate pin etching process.

[0015] Figure 5 This is a schematic diagram of the photolithography of the grid cap.

[0016] Figure 6 This is a schematic diagram of gate metal evaporation.

[0017] Figure 7 This is a schematic diagram of gate passivation.

[0018] Figure 8 This is a schematic diagram of the etching of the source and drain regions.

[0019] Figure 9 This is a schematic diagram of the source electrode field plate and the drain electrode evaporation.

[0020] Label Explanation: 11-Source ohmic contact window; 12-Gate pin; 13-Drain ohmic contact window; 14-Gate cap; 15-Source region; 16-Drain region; 17 - Gap; 18 - Source electrode; 19 - Field plate; 100 - SiC substrate; 101 - GaN epitaxial layer; 102 - Protective dielectric layer; 201 - Active region; 301-SiNx passivation layer; 302-passivation layer; 401 - Gate metal; 402 - Source field plate; 403 - Drain; 501 - Photoresist. Detailed Implementation

[0021] The present invention will be further described in detail below through embodiments. The following embodiments are explanations of the present invention, and the present invention is not limited to the following embodiments.

[0022] In this embodiment, the steps are as follows: Step S1, as follows Figure 1 , Figure 2 As shown, on an epitaxial wafer having a SiC substrate 100, a GaN epitaxial layer 101 and a protective dielectric layer 102, the SiN layer is activated in the active regions 201 at the source and drain by B ion implantation and high-temperature activation.

[0023] Other ion implantation or other activation methods can also be used to activate the SiN layer.

[0024] Step S2, as follows Figure 3 , Figure 4 As shown, a SiNx passivation layer 301 is deposited on the SiN layer after activation in step S1, and then the gate pin 12, the source ohmic contact window 11 and the drain ohmic contact window 13 are etched simultaneously, or only the gate pin 12 is etched; holes are opened on the SiNx passivation layer to the GaN epitaxial layer to create the area where the metal needs to be evaporated. In this step, the gate pin 12, the source ohmic contact window 11, and the drain ohmic contact window 13 can be etched simultaneously, or only the gate pin 12 can be etched.

[0025] Step S3, as follows Figure 5 , Figure 6 , Figure 7 As shown, after etching in step S2, photolithography is performed on the gate cap 14, and then the gate metal 401 is prepared by evaporation. Then, the photoresist 501 is removed and a passivation layer 302 is deposited to encapsulate the gate metal 401. The passivation layer 302 in this step is not the same as the SiNx passivation layer 301 in step S2.

[0026] Step S4, as follows Figure 8 As shown, a window is opened in the region of the source and drain ohmic contact. The SiNx passivation layer 301 and passivation layer 302 are opened by etching. The source ohmic contact window 11 and the drain ohmic contact window 13 are etched to expose the source region 15 and the drain region 16.

[0027] Step S5, as follows Figure 9 As shown, the drain electrode 403 and the source electrode field plate 402 are prepared by metal evaporation. During evaporation, the drain electrode region 16 evaporates the drain electrode 403 separately, while the source electrode region 15 and the field plate region above the gate metal 401 evaporate the metal together. The evaporated source electrode 18 and field plate 19 form a whole, namely the source electrode field plate 402.

[0028] In existing preparation methods, the source electrode 18, drain electrode 403, and field plate 19 are prepared by evaporation separately. However, in the present invention, the source electrode 18 and field plate 19 are evaporated at the same time and evaporated into a whole, namely the source electrode field plate 402, so that the source electrode 18 and field plate 19 in GaN HEMT are integrated into a whole region, while the drain electrode 403 forms another region.

[0029] In other embodiments, after completing the above steps, the source field plate 402 and drain 403 can be further passivated with SiNx.

[0030] In other embodiments, the source field plate 402 is integrally evaporated from the source 18 and the field plate 19, and extends from the source 18 toward the direction above the gate metal 401, at least covering part of the gate metal, or completely covering the gate metal 401, or completely covering the gate metal 401 and then continuing to extend toward the drain 403.

[0031] In other embodiments, the source field plate 402 extends toward the drain 403, but there must be a gap 17 between the source field plate 402 and the drain 403, that is, the source field plate 402 and the drain 403 cannot come into contact.

[0032] There is a dielectric layer between the source field plate 402 and the gate metal 401, and the two cannot be in contact.

[0033] Furthermore, it should be noted that the shapes and names of the parts and components described in the specific embodiments described in this specification may differ. All equivalent or simple variations made to the structure, features, and principles described in this patent concept are included within the protection scope of this patent. Those skilled in the art to which this invention pertains may make various modifications or additions to the described specific embodiments or use similar methods to replace them, as long as they do not depart from the structure of this invention or exceed the scope defined in these claims, they should all fall within the protection scope of this invention.

Claims

1. A method for fabricating a GaN HEMT with a special source field plate structure, characterized in that, Includes the following steps: S1. An epitaxial wafer having a SiC substrate, a GaN epitaxial layer and a protective dielectric layer, wherein the SiN layer is activated in the active regions at the source and drain by B ion or Si ion implantation and high-temperature activation. S2. Deposit a SiNx passivation layer, and then simultaneously etch out the gate pin, source ohmic contact window and drain ohmic contact window, or only etch out the gate pin. Open a hole in the SiNx passivation layer to the GaN epitaxial layer to create the area where the metal needs to be evaporated. S3. Perform gate cap photolithography and then prepare gate metal through evaporation process. Remove the photoresist, and then deposit a passivation layer to encapsulate the gate metal. S4. Open a window in the ohmic contact area between the source and drain, and open the SiNx passivation layer and passivation layer through an etching process, and etch the source ohmic contact window and drain ohmic contact window to expose the source region and drain region. S5. The drain and source field plates are prepared by metal evaporation. During evaporation, the drain region evaporates the drain electrode separately, while the source region and the field plate region above the gate metal evaporate the metal together. The evaporated source electrode and field plate form a whole, namely the source field plate.

2. The method for fabricating a GaN HEMT with a special source field plate structure according to claim 1, characterized in that, It also includes the following steps: S6. Passivate the source and drain electrodes with SiNx.

3. The method for fabricating a GaN HEMT with a special source field plate structure according to claim 1 or 2, characterized in that, The source field plate extends from the source towards the gate metal and covers at least a portion of the gate metal.

4. The method for fabricating a GaN HEMT with a special source field plate structure according to claim 1 or 2, characterized in that, There is a gap between the drain and source field plates.

5. The method for fabricating a GaN HEMT with a special source field plate structure according to claim 1 or 2, characterized in that, A dielectric layer exists between the source field plate and the gate metal.

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