Gallium nitride bidirectional switching device and preparation method thereof

Abstract

The gallium nitride bidirectional switching device comprises a substrate, a nucleating layer and a buffer layer which are sequentially arranged from bottom to top, the buffer layer is provided with a P-GaN buried layer, a GaN channel layer is arranged above the buffer layer and the P-GaN buried layer, an AlGaN barrier layer is arranged above the GaN channel layer, and the AlGaN barrier layer is arranged above the P-GaN buried layer. The GaN channel layer and the AlGaN barrier layer are both of a stepped structure and are embedded with each other, and a first P-GaN layer, a first HfO2 layer and a first grid electrode are sequentially arranged on one side of the AlGaN barrier layer from bottom to top; a second P-GaN layer, a second HfO2 layer and a second grid electrode are sequentially arranged on the other side of the AlGaN barrier layer from bottom to top. According to the invention, by using the source electrode symmetric stepped field plate and the AlGaN / GaN heterojunction structure, the channel peak electric field is effectively dispersed, the thermal management of the device is optimized, and the voltage endurance capability of the device is obviously improved; the precise current control and high-frequency alternating current chopping functions are achieved in a bidirectional conduction / blocking and unidirectional conduction mode by means of a double-gate cooperative regulation and control mechanism, and a new path is developed for development of efficient bidirectional power switch devices of a power electronic system.

Description

Technical Field

[0001] This invention relates to a gallium nitride bidirectional switching device and its fabrication method, belonging to the field of semiconductor technology. Background Technology

[0002] Against the backdrop of increasingly prominent global energy supply and demand contradictions, power electronic devices, as the core carriers of energy conversion and regulation, have seen their performance upgrades become crucial for overcoming bottlenecks in energy utilization efficiency. Gallium nitride (GaN)-based high electron mobility transistors (HEMTs), with their inherent advantages such as high carrier surface density, high electron mobility, and high breakdown electric field, have rapidly become the core of research in the field of power electronics.

[0003] However, traditional GaN-based HEMTs still face multiple technical constraints: First, the two-dimensional electron gas (2DEG) at the AlGaN / GaN heterojunction interface causes the device to operate in a normally-on mode, which not only increases the complexity of the driving circuit design but also significantly increases energy conversion losses, severely restricting circuit safety. Second, the gate electric field concentration effect and buffer layer leakage problems are prominent, making the device breakdown voltage far lower than the theoretical limit of GaN material, which greatly limits its application in high-voltage scenarios. Third, the existing technical paths to achieve normally-off characteristics all have obvious defects: the threshold voltage (Vth) obtained by groove gate and polarization doping technology is too low, the p-GaN cap layer technology requires high hole concentration doping but is difficult to achieve, and the fluorine plasma implantation technology faces high-temperature reliability problems and cannot meet the needs of practical applications.

[0004] Therefore, it is urgent to break through the existing structural design bottlenecks and develop a gallium nitride bidirectional switching device and its fabrication method that can synergistically improve threshold voltage, breakdown voltage and conduction characteristics. Summary of the Invention

[0005] To address the aforementioned issues, this invention provides a gallium nitride bidirectional switching device and its fabrication method, which can synergistically improve threshold voltage, breakdown voltage, and conduction characteristics.

[0006] In a first aspect, the present invention provides a gallium nitride bidirectional switching device, comprising a substrate, a nucleation layer, and a buffer layer disposed sequentially from bottom to top. The buffer layer has a P-GaN buried layer. A GaN channel layer is disposed above the buffer layer and the P-GaN buried layer. An AlGaN barrier layer is disposed above the GaN channel layer. Both the GaN channel layer and the AlGaN barrier layer are stepped structures and interlocked. A first P-GaN layer, a first HfO2 layer, and a first gate are disposed sequentially from bottom to top on one side of the AlGaN barrier layer. A second Si3N4 layer is disposed on the side of the first P-GaN layer, the first HfO2 layer, and the first gate away from the AlGaN barrier layer. The second Si3N4 layer is disposed on the AlGaN barrier layer. A step is disposed on the side of the second Si3N4 layer away from the first P-GaN layer. The first source electrode; on the other side of the AlGaN barrier layer, from bottom to top, a second P-GaN layer, a second HfO2 layer, and a second gate electrode are sequentially disposed. A third Si3N4 layer is disposed on the side of the second P-GaN layer, the second HfO2 layer, and the second gate electrode away from the AlGaN barrier layer. The third Si3N4 layer is disposed on the AlGaN barrier layer. A second source electrode is disposed on the side of the third Si3N4 layer away from the second P-GaN layer. A first Si3N4 layer is disposed above the AlGaN barrier layer. The first Si3N4 layer is disposed between the first gate electrode and the second gate electrode. The first source electrode and the second source electrode are disposed on the GaN channel layer and form an ohmic contact with the GaN channel layer. The first gate electrode forms a Schottky contact with the first HfO2 layer, and the second gate electrode forms a Schottky contact with the second HfO2 layer.

[0007] In one embodiment of the present invention, the first P-GaN layer and the second P-GaN layer, the first HfO2 layer and the second HfO2 layer, the first gate and the second gate, the second Si3N4 layer and the third Si3N4 layer are all symmetrically arranged on the AlGaN barrier layer; the first source and the second source are symmetrically arranged on the GaN channel layer.

[0008] In one embodiment of the present invention, the substrate is made of one or more combinations of silicon, sapphire, and silicon carbide; the nucleation layer and the buffer layer are made of one or more combinations of AlN, GaN, AlGaN, and InGaN; the thickness of the nucleation layer is 1-100 nm; and the thickness of the buffer layer is 1-500 nm.

[0009] In one embodiment of the present invention, the materials of the first source electrode, the second source electrode, the first gate electrode, and the second gate electrode are one or more combinations of Ti, Al, Ni, and Au.

[0010] In one embodiment of the present invention, the thickness Tb of the P-GaN buried layer is 1-100 nm; the thickness of the AlGaN barrier layer is 1-100 nm; and the thickness of the first Si3N4 layer is 1-100 nm.

[0011] In one embodiment of the present invention, the stepped structure of the GaN channel layer is a three-layer structure, including an upper layer structure, an intermediate layer structure and a bottom layer structure, wherein the thickness Hs of the upper layer structure is 1-500nm, the length Ls2 of the intermediate layer structure is 1-10nm, and the length Ls1 of the bottom layer structure is 1-10nm.

[0012] In one embodiment of the present invention, the thickness of the first HfO2 layer and the second HfO2 layer is 1-50 nm; the thickness of the first P-GaN layer and the second P-GaN layer is 1-500 nm.

[0013] Secondly, the present invention provides a method for fabricating a gallium nitride bidirectional switching device, comprising the following steps: Step 1: Provide a substrate; Step 2: A core layer and a buffer layer are grown sequentially on the substrate, and an ion implantation process is used to form a p-GaN buried layer in the middle region above the buffer layer. Step 3: A GaN channel layer is grown above the p-GaN buried layer using MOCVD process, and the GaN channel layer is etched to form a stepped structure. Step 4: An AlGaN barrier layer is grown above the GaN channel layer using MOCVD technology, and the AlGaN barrier layer is etched to form a stepped structure. Step 5: The first P-GaN layer and the second P-GaN layer are grown on the etched AlGaN barrier layer using the MOCVD process, and then the first HfO2 layer and the second HfO2 layer are grown on the first P-GaN layer and the second P-GaN layer respectively using the PEALD process. Step 6: The first Si3N4 layer is grown on the AlGaN barrier layer using PECVD process, and the first Si3N4 layer is etched by ICP etching process to form electrode windows corresponding to the first source, second source, first gate, and second gate. Step 7: Deposit the metal layers corresponding to the first and second source electrodes in the region corresponding to the electrode window using an electron beam evaporation process; Step 8: Above the first HfO2 layer and the second HfO2 layer, deposit the first gate and the second gate respectively using an electron beam evaporation process, so that a Schottky contact is formed between the first gate and the first HfO2 layer and between the second gate and the second HfO2 layer. At the same time, the metal layer is deposited to extend to the surface of the adjacent first Si3N4 layer to form a gate field plate structure, thus completing the fabrication of the device.

[0014] In one embodiment of the present invention, in step one, the substrate needs to be pretreated and cleaned: the substrate is placed in 1% ammonium fluoride buffer (BOE) to remove the surface oxide layer and inorganic impurities, and then rinsed with pure water; then it is soaked in acetone and isopropanol in sequence, and ultrasonically cleaned for 3-5 minutes each to remove organic contaminants; finally, it is rinsed with pure water and dried with a nitrogen gun for later use. In step two, the nucleation layer is grown using organic chemical vapor deposition (MOCVD) at a temperature of 200°C with a thickness of 2µm; the buffer layer is grown using MOCVD at a temperature of 800°C with a thickness of 100nm; the p-GaN buried layer has a thickness of 100nm, and the ion implantation process uses Mg... + As the dopant ion, the implantation dose is controlled to achieve a hole concentration of 3 × 10⁻⁶ in the p-GaN buried layer. 17 cm -3 After injection, it undergoes rapid thermal annealing at 850℃ for 30 seconds in a nitrogen gas stream. In step three, the growth temperature of the GaN channel layer is 1000℃ and the thickness is 0.4μm; the etching adopts the ICP dry etching process, and the thickness Hs of the upper structure in the stepped structure of the GaN channel layer is 100nm. In step four, the growth temperature of the AlGaN barrier layer is 1000℃ and the thickness is 20nm; the etching adopts the ICP dry etching process. In step five, the first and second P-GaN layers are made of p-type GaN, with a growth thickness of 100 nm and a hole concentration of 2 × 10⁻⁶. 17 cm -3 The first HfO2 layer and the second HfO2 layer are made of HfO2, grown at a temperature of 250℃, and have a thickness of 10nm. During the growth process, the deposition temperature and precursor flow rate are adjusted to reduce the interface state density between the first HfO2 layer, the second HfO2 layer and the underlying first P-GaN layer, and the second P-GaN layer, thereby improving the gate's control over the channel. In step six, the material of the first Si3N4 layer is Si3N4, the growth temperature is 300℃, and the thickness is 50nm. After etching, the windows corresponding to the first source and the second source are etched to the surface of the GaN channel layer, and the windows corresponding to the first gate and the second gate are etched to the surface of the first HfO2 layer and the second HfO2 layer. The first Si3N4 layer is grown using PECVD process, and then the first Si3N4 layer is patterned by ICP etching process. The etching uses Cl2 as the main etching gas and BCl3 as the auxiliary gas to remove surface residues and form electrode windows corresponding to the first source, the second source, the first gate, and the second gate, so as to avoid damaging the underlying AlGaN barrier layer and the first P-GaN layer and the second P-GaN layer during the etching process. In step seven, the deposition process of the first source electrode and the second source electrode uses argon as the protective gas; then, a high-temperature annealing treatment of 850°C is carried out in a nitrogen atmosphere for 30 seconds to form an ohmic contact with the underlying GaN channel layer. In step eight, argon is used as the protective gas for the deposition of the first gate and the second gate; the extension length of the gate field plate is 2 μm. In steps three and four, the etching of the GaN channel layer and AlGaN barrier layer uses Cl2 or BCl3 as the main etching gas, and O2 or SF6 is added to adjust the etching profile.

[0015] Thirdly, the present invention provides a method for fabricating a gallium nitride bidirectional switching device, comprising the following steps: Step 1: Provide a substrate; The substrate material is SiC, which needs to be pre-treated and cleaned: the RCA standard cleaning process is used to remove surface contaminants, and then high-temperature pretreatment is carried out in a hydrogen atmosphere to remove the surface oxide layer and obtain an atomically flat surface. Step 2: A nucleation layer and a buffer layer are grown sequentially on the substrate. Low-temperature AlN nucleation combined with superlattice strain buffer layer technology is used. Then, a p-GaN buried layer is directly epitaxially grown in the middle region above the buffer layer using an in-situ Mg-doped MOCVD process. The nucleation layer is made of AlN and is grown using a two-step MOCVD method. The low-temperature layer is grown at 550℃ and the high-temperature layer at 1100℃, with a total thickness of 150nm. The buffer layer is a strain buffer layer composed of 10-period AlN / GaN superlattices to reduce dislocation density. The p-GaN buried layer is 80nm thick and achieves a high hole concentration and steep doping interface by precisely controlling the flow ratio of triethylgallium to Cp2Mg precursor. Step 3: A GaN channel layer is grown above the p-GaN buried layer using MOCVD process, and the GaN channel layer is etched using a low-damage ICP etching process based on BCl3 / SF6 mixed gas to form a steep and smooth step structure. The GaN channel layer was grown at 1050℃ with a thickness of 0.3 μm. Immediately after etching, N2O plasma treatment was performed, followed by thermal atomic layer deposition of 2 nm thick SiN on the etched sidewalls and surface. x Passivation is performed to further reduce the interface state density; Step 4: An AlGaN barrier layer is grown above the GaN channel layer using MOCVD technology, and the AlGaN barrier layer is etched by a combination of photolithography and selective wet etching to form a precisely fitted step structure. The aluminum composition of the AlGaN barrier layer is Al0. 30 Ga0. 70 N, with a growth temperature of 1020℃ and a thickness of 25nm; Step 5: Selectively grow the first P-GaN layer and the second P-GaN layer on the etched AlGaN barrier layer using MOCVD process; before growing P-GaN, deposit a 0.5 nm MgO layer in situ as an interface dipole layer to adjust the work function and energy band alignment; then use spatially separated ALD process to grow the first HfO2 layer and the second HfO2 layer on top of the first P-GaN layer and the second P-GaN layer, respectively. The thickness of the first P-GaN layer and the second P-GaN layer is 80 nm, and the hole concentration is 3 × 10¹. 7 cm - ³; The growth temperature of the first HfO2 layer and the second HfO2 layer is 200℃, and the thickness is 15nm; Step 6: The first Si3N4 layer is grown on the AlGaN barrier layer using inductively coupled plasma chemical vapor deposition (ICP-CVD), and the first Si3N4 layer is etched using reactive ion etching (RIE) to form an electrode window. The first Si3N4 layer is grown at a temperature of 250℃ and has a thickness of 70nm to enhance its stress matching characteristics as a passivation layer. Step 7: Deposit the metal layers corresponding to the first source electrode and the second source electrode in the region corresponding to the electrode window using a magnetron sputtering process; The first and second source electrodes are deposited with Ta / Al / Mo / Au stacked metals. After deposition, they are subjected to rapid thermal annealing in a nitrogen atmosphere at 900°C for 15 seconds to form a contact resistance lower than 1×10⁻⁶. -6 Ohmic contact with Ω·cm²; Step 8: Above the first HfO2 layer and the second HfO2 layer, the first gate and the second gate are deposited respectively by electron beam evaporation process to form Schottky contacts, and the gate metal is extended to the first Si3N4 layer to form a composite field plate structure.

[0016] The beneficial effects of this invention are as follows: 1. This invention provides a gallium nitride bidirectional switching device and its fabrication method. By integrating a stepped channel / barrier interlocking structure, a P-GaN buried layer, and a dual-gate dielectric / field plate design, it synergistically achieves high electron mobility, high breakdown voltage, and low leakage current. The device utilizes the source-symmetric stepped field plate (SFP) and the electric field optimization effect of the AlGaN / GaN heterojunction to effectively disperse the peak electric field of the channel, thereby improving the device's breakdown voltage and thermal management characteristics.

[0017] 2. The bidirectional switch architecture proposed in this invention has clear advantages in circuit integration: the two gates can be driven independently, achieving bidirectional symmetrical conduction and blocking, making it suitable for bidirectional energy flow control in high-frequency AC choppers, AC / AC converters, or H-bridge circuits. Compared with traditional back-to-back HEMT solutions, this structure achieves bidirectional functionality on a single chip, helping to reduce parasitic parameters, simplify circuit layout, and improve system power density and reliability. Furthermore, two of the aforementioned bidirectional switches can be integrated on the same chip to form a half-bridge power unit, providing a new path for compact power module design.

[0018] 3. This invention innovatively introduces a collaborative working mechanism of optical control and electrical control. The first gate adopts a photosensitive Schottky structure, which modulates the barrier height by illumination to achieve optical triggering, optical threshold drift compensation, or optoelectronic hybrid modulation; the second gate maintains electrical control, and the two work together to flexibly switch between various modes such as bidirectional conduction, unidirectional selection, and optocoupler isolation drive, enhancing the device's application potential in intelligent power control, optoelectronic device integration, and isolation drive circuits. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the gallium nitride bidirectional switching device of the present invention; Figure 2 This is a comparison diagram of the electric field distribution simulation of the present invention; Figure 3 This is a schematic diagram of the circuit application of the present invention; Figure 4This is a breakdown characteristic test curve of the present invention.

[0021] In the figure: 1. Substrate; 2. Nucleation layer; 3. Buffer layer; 4. p-GaN buried layer; 5. GaN channel layer; 6. AlGaN barrier layer; 7. First Si3N4 layer; 8. First source; 9. Second source; 10. Second Si3N4 layer; 11. Third Si3N4 layer; 12. First P-GaN layer; 13. Second P-GaN layer; 14. First HfO2 layer; 15. Second HfO2 layer; 16. First gate; 17. Second gate. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this invention clearer, the embodiments of this invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0023] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The terms "first position" and "second position" refer to two different positions.

[0024] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections or detachable connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components. Those skilled in the art can understand the specific meaning of these terms in this invention based on the specific circumstances.

[0025] Example 1 like Figure 1As shown, this embodiment provides a gallium nitride bidirectional switching device, including a substrate 1, a nucleation layer 2, and a buffer layer 3 arranged sequentially from bottom to top. The buffer layer 3 is provided with a P-GaN buried layer 4. A GaN channel layer 5 is arranged above the buffer layer 3 and the P-GaN buried layer 4. An AlGaN barrier layer 6 is arranged above the GaN channel layer 5. Both the GaN channel layer 5 and the AlGaN barrier layer 6 are stepped structures and are interlocked. A first P-GaN layer 12, a first HfO2 layer 14, and a first gate 16 are arranged sequentially from bottom to top on one side of the AlGaN barrier layer 6. A second Si3N4 layer 10 is arranged on the side of the first P-GaN layer 12, the first HfO2 layer 14, and the first gate 16 away from the AlGaN barrier layer 6. The second Si3N4 layer 10 is disposed on the AlGaN barrier layer 6. A first source 8 is arranged on the side of the second Si3N4 layer 10 away from the first P-GaN layer 12. On the other side of the AlGaN barrier layer 6, from bottom to top, a second P-GaN layer 13, a second HfO2 layer 15, and a second gate 17 are sequentially disposed. On the side of the second P-GaN layer 13, the second HfO2 layer 15, and the second gate 17 away from the AlGaN barrier layer 6, a third Si3N4 layer 11 is disposed. The third Si3N4 layer 11 is disposed on the AlGaN barrier layer 6, and a second source 9 is disposed on the side of the third Si3N4 layer 11 away from the second P-GaN layer 13. A first Si3N4 layer 7 is disposed above the AlGaN barrier layer 6, and the first Si3N4 layer 7 is disposed between the first gate 16 and the second gate 17. The first source 8 and the second source 9 are disposed on the GaN channel layer 5 and form an ohmic contact with the GaN channel layer 5. The first gate 16 forms a Schottky contact with the first HfO2 layer 14, and the second gate 17 forms a Schottky contact with the second HfO2 layer 15.

[0026] Optionally, the first P-GaN layer 12 and the second P-GaN layer 13, the first HfO2 layer 14 and the second HfO2 layer 15, the first gate 16 and the second gate 17, the second Si3N4 layer 10 and the third Si3N4 layer 11 are all symmetrically arranged on the AlGaN barrier layer 6; the first source 8 and the second source 9 are symmetrically arranged on the GaN channel layer 5.

[0027] Optionally, the substrate 1 is made of one or more combinations of silicon, sapphire, and silicon carbide.

[0028] Optionally, the materials of the nucleation layer 2 and the buffer layer 3 are one or more combinations of AlN, GaN, AlGaN and InGaN.

[0029] Optionally, the thickness of the nucleation layer 2 is 1-100 nm.

[0030] Optionally, the thickness of the buffer layer 3 is 1-500 nm.

[0031] Optionally, the materials of the first source 8, the second source 9, the first gate 16, and the second gate 17 are one or more combinations of Ti, Al, Ni, and Au.

[0032] Optionally, the thickness Tb of the P-GaN buried layer 4 is 1-100 nm.

[0033] Optionally, the stepped structure of the GaN channel layer 5 is a three-layer structure, including an upper layer structure, an intermediate layer structure and a bottom layer structure, wherein the thickness Hs of the upper layer structure is 1-500nm, the length Ls2 of the intermediate layer structure is 1-10nm, and the length Ls1 of the bottom layer structure is 1-10nm.

[0034] Optionally, the thickness of the AlGaN barrier layer 6 is 1-100 nm.

[0035] Optionally, the thickness of the first Si3N4 layer 7 is 1-100 nm.

[0036] Optionally, the thickness of the first HfO2 layer 14 and the second HfO2 layer 15 is 1-50 nm.

[0037] Optionally, the thickness of the first P-GaN layer 12 and the second P-GaN layer 13 is 1-500 nm.

[0038] This invention uses a dual-gate structure based on the GaN / AlN superlattice structure and utilizes single-crystal silicon to realize the optical control operation of the device.

[0039] Example 2 This embodiment provides a method for fabricating a gallium nitride bidirectional switching device according to Embodiment 1, comprising the following steps: Step 1: Provide a substrate 1; The substrate 1 is made of Si and requires pretreatment and cleaning: the substrate 1 is placed in 1% ammonium fluoride buffer (BOE) to remove the surface oxide layer and inorganic impurities, and then rinsed with pure water; then it is soaked in acetone and isopropanol in sequence, and ultrasonically cleaned for 3-5 minutes each to remove organic contaminants; finally, it is rinsed with pure water and dried with a nitrogen gun for later use. Step 2: On substrate 1, a core layer 2 and a buffer layer 3 are grown sequentially, and a p-GaN buried layer 4 is formed in the middle region above the buffer layer 3 using a pulsed doping ion implantation process. The nucleation layer 2 is made of AlN, grown using organic chemical vapor deposition (MOCVD) at 200℃, with a thickness of 2µm; the buffer layer 3 is made of GaN, grown using MOCVD at 800℃, with a thickness of 100nm; the p-GaN buried layer 4 has a thickness of 100nm, and the ion implantation process uses Mg... + As dopant ions, δ-doping distribution was achieved through pulsed injection and dose gradient control, resulting in a hole concentration of 3 × 10¹ in the p-GaN buried layer 4. 7 cm - ³ and evenly distributed, after injection, it undergoes rapid heat annealing at 850℃ for 30s in a nitrogen gas stream; Step 3: A GaN channel layer 5 is grown on top of the p-GaN buried layer 4 using MOCVD process, and the GaN channel layer 5 is etched using ICP dry etching process with Cl2 / BCl3 mixed gas to form a stepped structure. The GaN channel layer 5 is grown at a temperature of 1000℃ and has a thickness of 0.4μm. The upper structure of the stepped structure of the GaN channel layer 5 formed after etching has a thickness Hs of 100nm. After etching, an ultrathin Al2O3 layer (1-3nm thick) is grown on the etched sidewall using atomic layer deposition (ALD) technology to passivate the sidewall in situ and suppress leakage current caused by surface states. Step 4: An AlGaN barrier layer 6 is grown on top of the GaN channel layer 5 using MOCVD process, and the AlGaN barrier layer 6 is etched using ICP dry etching process with Cl2 / BCl3 mixed gas to form a stepped structure that is interlocked with the GaN channel layer 5. The material of AlGaN barrier layer 6 is Al0. 24 Ga0. 76 N, with a growth temperature of 1000℃ and a thickness of 20nm; after etching, Al2O3 sidewall passivation was also performed using ALD technology to ensure interface quality; Step 5: A first P-GaN layer 12 and a second P-GaN layer 13 are grown on the etched AlGaN barrier layer 6 using MOCVD. Before growth, the surface of the AlGaN barrier layer 6 is pretreated with NH3 plasma to reduce the interface state density. Then, a first HfO2 layer 14 and a second HfO2 layer 15 are grown on the first P-GaN layer 12 and the second P-GaN layer 13, respectively, using plasma-enhanced atomic layer deposition (PEALD). The first P-GaN layer 12 and the second P-GaN layer 13 are made of p-type GaN, with a growth thickness of 100 nm and a hole concentration of 2 × 10¹. 7 cm -³; The first HfO2 layer 14 and the second HfO2 layer 15 are made of HfO2, grown at a temperature of 250℃, and have a thickness of 10nm. Through NH3 plasma interface pretreatment and precise control of the PEALD process, the interface state density (Dit) between HfO2 and p-GaN is significantly reduced, thereby improving the gate control efficiency and the long-term stability of the threshold voltage (Vth). Step 6: The first Si3N4 layer 7 is grown on the AlGaN barrier layer 6 using PECVD process, and the first Si3N4 layer 7 is etched by ICP etching process to form electrode windows corresponding to the first source 8, the second source 9, the first gate 16, and the second gate 17. The first Si3N4 layer 7 is made of Si3N4, grown at a temperature of 300℃, and has a thickness of 50nm. After etching, the windows corresponding to the first source 8 and the second source 9 are etched to the surface of the GaN channel layer 5, and the windows corresponding to the first gate 16 and the second gate 17 are etched to the surface of the first HfO2 layer 14 and the second HfO2 layer 15. The etching uses Cl2 as the main etching gas and BCl3 as the auxiliary gas to remove surface residues and strictly avoid damaging the underlying AlGaN barrier layer 6 and P-GaN layer. Step 7: Deposit the metal layers corresponding to the first source electrode 8 and the second source electrode 9 in the region corresponding to the electrode window using an electron beam evaporation process; Among them, the deposited metals of the first source electrode 8 and the second source electrode 9 are Ti / Al / Ni / Au stacks, and the deposition process uses argon as a protective gas; then, a high-temperature annealing treatment of 850℃ is carried out in a nitrogen atmosphere for 30s, forming a low-resistance ohmic contact with the underlying GaN channel layer 5. Step 8: Above the first HfO2 layer 14 and the second HfO2 layer 15, deposit the first gate 16 and the second gate 17 respectively using an electron beam evaporation process, so that a Schottky contact is formed between the first gate 16 and the first HfO2 layer 14, and between the second gate 17 and the second HfO2 layer 15. At the same time, the metal layer is extended and deposited to the surface of the adjacent first Si3N4 layer 7 to form a gate field plate structure, thus completing the fabrication of the device.

[0040] The first gate 16 and the second gate 17 are deposited with Ni / Au metal, and argon is used as the protective gas during the deposition process; the extension length of the gate field plate is 2μm.

[0041] Example 3 This embodiment provides another method for fabricating a gallium nitride bidirectional switching device according to Embodiment 1. The core of this method lies in using a silicon carbide (SiC) substrate, optimizing the stepped etching morphology, and introducing an interface dipole layer to further improve the high-frequency and high-temperature characteristics of the device. Specifically, it includes the following steps: Step 1: Provide a substrate 1; The substrate 1 is made of 4H-SiC and requires pretreatment cleaning: the RCA standard cleaning process is used to remove surface contaminants, followed by high temperature (1100°C) pretreatment for 5 minutes in a hydrogen atmosphere to remove the surface oxide layer and obtain an atomically flat surface. Step 2: On substrate 1, nucleation layer 2 and buffer layer 3 are grown sequentially. Low-temperature AlN nucleation combined with superlattice strain buffer layer technology is used. Then, p-GaN buried layer 4 is directly epitaxially grown in the middle region above buffer layer 3 by in-situ Mg-doped MOCVD process. The nucleation layer 2 is made of AlN and grown using a two-step MOCVD method. The low-temperature layer is grown at 550℃, the high-temperature layer at 1100℃, and the total thickness is 150nm. The buffer layer 3 is a strain buffer layer composed of 10 periods of AlN / GaN superlattice (period thickness 5nm) to reduce dislocation density. The p-GaN buried layer 4 has a thickness of 80nm and achieves a high hole concentration (5×10¹) by precisely controlling the flux ratio of triethylgallium (TMGa) to Cp₂Mg precursor. 7 cm - ³) and a steep doping interface; Step 3: A GaN channel layer 5 is grown on top of the p-GaN buried layer 4 using MOCVD process, and the GaN channel layer 5 is etched using a low-damage ICP etching process based on BCl3 / SF6 mixed gas to form a steep and smooth step structure. The GaN channel layer 5 was grown at 1050℃ with a thickness of 0.3μm. Immediately after etching, it underwent N2O plasma treatment, followed by thermal atomic layer deposition (thermal ALD) to deposit a 2nm thick SiN layer on the etched sidewalls and surface. x Passivation is performed to further reduce the interface state density; Step 4: An AlGaN barrier layer 6 is grown above the GaN channel layer 5 using MOCVD process, and the AlGaN barrier layer 6 is etched by a combination of photolithography and selective wet etching (hot phosphoric acid solution) to form a precisely fitted step structure. The aluminum composition of AlGaN barrier layer 6 is Al0. 30 Ga0. 70 N, with a growth temperature of 1020℃ and a thickness of 25nm; Step 5: Selectively grow a first P-GaN layer 12 and a second P-GaN layer 13 on the etched AlGaN barrier layer 6 using MOCVD process; before growing P-GaN, deposit a 0.5 nm MgO layer in situ as an interface dipole layer to adjust the work function and energy band alignment; then use spatial ALD process to grow a first HfO2 layer 14 and a second HfO2 layer 15 on top of the first P-GaN layer 12 and the second P-GaN layer 13, respectively. The thickness of the first P-GaN layer 12 and the second P-GaN layer 13 is 80 nm, and the hole concentration is 3 × 10¹. 7 cm - ³; The growth temperature of the first HfO2 layer 14 and the second HfO2 layer 15 is 200℃, and the thickness is 15nm. By introducing an MgO interface layer and a low-temperature Spatial ALD process, a lower gate leakage current (Jg @ 5V < 10) is achieved. -7 A / cm²) and higher dielectric constant (k>22); Step 6: The first Si3N4 layer 7 is grown on the AlGaN barrier layer 6 using inductively coupled plasma chemical vapor deposition (ICP-CVD) process, and the first Si3N4 layer 7 is etched by reactive ion etching (RIE) process to form an electrode window. The first Si3N4 layer 7 is grown at a temperature of 250℃ and has a thickness of 70nm to enhance its stress matching characteristics as a passivation layer. Step 7: Deposit the metal layers corresponding to the first source electrode 8 and the second source electrode 9 in the region corresponding to the electrode window using a magnetron sputtering process; The first source electrode 8 and the second source electrode 9 are deposited with Ta / Al / Mo / Au stacked metals. After deposition, they are treated with rapid thermal annealing (RTA) at 900°C in a nitrogen atmosphere for 15 seconds to form a specific contact resistance of less than 1×10⁻⁶. -6 Ohmic contact with Ω·cm²; Step 8: Above the first HfO2 layer 14 and the second HfO2 layer 15, the first gate 16 and the second gate 17 are deposited respectively by electron beam evaporation to form Schottky contacts, and the gate metal is extended to the first Si3N4 layer 7 to form a composite field plate structure with a length of 3μm to further optimize the electric field distribution.

[0042] The deposited metals of the first gate 16 and the second gate 17 are Pt / Au.

[0043] Figure 2 This is a comparison diagram of the electric field distribution simulation of the present invention. Figure 2It can be seen that the introduction of the stepped device structure and p-GaN buried layer in this invention significantly reduces the electron concentration of the channel layer and buffer layer; Figure 3 This is a schematic diagram of the circuit application of the present invention, used in a bidirectional DC converter; Figure 4 This is a breakdown characteristic test curve of the present invention, obtained through... Figure 4 It can be seen that the field plate and the buried p-GaN layer of the present invention can effectively improve the breakdown characteristics of the device.

[0044] In summary, this invention provides a gallium nitride bidirectional switching device and its fabrication method. Utilizing a source-symmetric stepped field plate (SFP) and an AlGaN / GaN heterojunction structure, it effectively disperses the peak electric field in the channel, optimizes device thermal management, and significantly improves the device's breakdown voltage. By leveraging a dual-gate collaborative control mechanism, it achieves precise current control and high-frequency AC chopping functions in both bidirectional conduction / blocking and unidirectional conduction modes, opening a new path for the development of high-efficiency bidirectional power switching devices for power electronic systems.

[0045] This document uses specific embodiments to illustrate the principles and implementation methods of the present invention. The descriptions of these embodiments are merely for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make various improvements and modifications to the present invention without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A gallium nitride bidirectional switching device, characterized in that, The structure includes a substrate (1), a nucleation layer (2), and a buffer layer (3) arranged sequentially from bottom to top. A P-GaN buried layer (4) is disposed on the buffer layer (3). A GaN channel layer (5) is disposed above the buffer layer (3) and the P-GaN buried layer (4). An AlGaN barrier layer (6) is disposed above the GaN channel layer (5). Both the GaN channel layer (5) and the AlGaN barrier layer (6) are stepped structures and interlocked. A first P-GaN nucleation layer is disposed sequentially from bottom to top on one side of the AlGaN barrier layer (6). -GaN layer (12), first HfO2 layer (14) and first gate (16), the first P-GaN layer (12), the first HfO2 layer (14) and the first gate (16) are provided with a second Si3N4 layer (10) on the side away from the AlGaN barrier layer (6), the second Si3N4 layer (10) is provided on the AlGaN barrier layer (6), and a first source (8) is provided on the side of the second Si3N4 layer (10) away from the first P-GaN layer (12); the AlGaN barrier layer ( On the other side of 6), from bottom to top, a second P-GaN layer (13), a second HfO2 layer (15), and a second gate (17) are sequentially arranged. On the side of the second P-GaN layer (13), the second HfO2 layer (15), and the second gate (17) away from the AlGaN barrier layer (6), a third Si3N4 layer (11) is arranged. The third Si3N4 layer (11) is disposed on the AlGaN barrier layer (6). On the side of the third Si3N4 layer (11) away from the second P-GaN layer (13), a second HfO2 layer (15), and a second gate (17) are arranged. Two source electrodes (9); a first Si3N4 layer (7) is disposed above the AlGaN barrier layer (6), the first Si3N4 layer (7) is disposed between the first gate (16) and the second gate (17); the first source electrode (8) and the second source electrode (9) are disposed on the GaN channel layer (5) and form an ohmic contact with the GaN channel layer (5), the first gate electrode (16) forms a Schottky contact with the first HfO2 layer (14), and the second gate electrode (17) forms a Schottky contact with the second HfO2 layer (15).

2. The gallium nitride bidirectional switching device according to claim 1, characterized in that, The first P-GaN layer (12) and the second P-GaN layer (13), the first HfO2 layer (14) and the second HfO2 layer (15), the first gate (16) and the second gate (17), the second Si3N4 layer (10) and the third Si3N4 layer (11) are all symmetrically arranged on the AlGaN barrier layer (6); the first source (8) and the second source (9) are symmetrically arranged on the GaN channel layer (5).

3. A gallium nitride bidirectional switching device according to claim 1, characterized in that, The substrate (1) is made of one or more of silicon, sapphire and silicon carbide; the nucleation layer (2) and the buffer layer (3) are made of one or more of AlN, GaN, AlGaN and InGaN; the thickness of the nucleation layer (2) is 1-100 nm; and the thickness of the buffer layer (3) is 1-500 nm.

4. A gallium nitride bidirectional switching device according to claim 1, characterized in that, The materials of the first source electrode (8), the second source electrode (9), the first gate electrode (16), and the second gate electrode (17) are one or more combinations of Ti, Al, Ni, and Au.

5. A gallium nitride bidirectional switching device according to claim 1, characterized in that, The thickness Tb of the P-GaN buried layer (4) is 1-100 nm; the thickness of the AlGaN barrier layer (6) is 1-100 nm; and the thickness of the first Si3N4 layer (7) is 1-100 nm.

6. A gallium nitride bidirectional switching device according to claim 1, characterized in that, The stepped structure of the GaN channel layer (5) is a three-layer structure, including an upper layer structure, an intermediate layer structure and a bottom layer structure. The thickness Hs of the upper layer structure is 1-500nm, the length Ls2 of the intermediate layer structure is 1-10nm, and the length Ls1 of the bottom layer structure is 1-10nm.

7. A gallium nitride bidirectional switching device according to claim 1, characterized in that, The thickness of the first HfO2 layer (14) and the second HfO2 layer (15) is 1-50 nm; the thickness of the first P-GaN layer (12) and the second P-GaN layer (13) is 1-500 nm.

8. A method for fabricating a gallium nitride bidirectional switching device according to any one of claims 1-7, characterized in that, Includes the following steps: Step 1: Provide a substrate (1); Step 2: A core layer (2) and a buffer layer (3) are grown sequentially on the substrate (1), and an ion implantation process is used to form a p-GaN buried layer (4) in the middle region above the buffer layer (3). Step 3: A GaN channel layer (5) is grown on top of the p-GaN buried layer (4) using MOCVD process, and the GaN channel layer (5) is etched to form a stepped structure. Step 4: An AlGaN barrier layer (6) is grown above the GaN channel layer (5) using MOCVD process, and the AlGaN barrier layer (6) is etched to form a stepped structure. Step 5: The first P-GaN layer (12) and the second P-GaN layer (13) are grown on the etched AlGaN barrier layer (6) by MOCVD process, and then the first HfO2 layer (14) and the second HfO2 layer (15) are grown on the first P-GaN layer (12) and the second P-GaN layer (13) respectively by PEALD process. Step 6: The first Si3N4 layer (7) is grown on the AlGaN barrier layer (6) using PECVD process, and the first Si3N4 layer (7) is etched by ICP etching process to form electrode windows corresponding to the first source (8), the second source (9), the first gate (16), and the second gate (17); Step 7: Deposit the metal layers corresponding to the first source electrode (8) and the second source electrode (9) in the region corresponding to the electrode window using an electron beam evaporation process; Step 8: On top of the first HfO2 layer (14) and the second HfO2 layer (15), the first gate (16) and the second gate (17) are deposited respectively by electron beam evaporation process, so that Schottky contacts are formed between the first gate (16) and the first HfO2 layer (14) and between the second gate (17) and the second HfO2 layer (15). At the same time, the metal layer is extended and deposited to the surface of the adjacent first Si3N4 layer (7) to form a gate field plate structure, thus completing the fabrication of the device.

9. The method for fabricating a gallium nitride bidirectional switching device according to claim 8, characterized in that, In step one, the substrate (1) needs to be pre-treated and cleaned: the substrate (1) is placed in 1% ammonium fluoride buffer (BOE) to remove the surface oxide layer and inorganic impurities, and then rinsed with pure water; then it is soaked in acetone and isopropanol in sequence, and ultrasonically cleaned for 3-5 minutes each to remove organic contaminants; finally, it is rinsed with pure water and dried with a nitrogen gun for later use. In step two, the nucleation layer (2) is grown using organic chemical vapor deposition (MOCVD) at a temperature of 200°C and a thickness of 2µm; the buffer layer (3) is grown using MOCVD at a temperature of 800°C and a thickness of 100nm; the p-GaN buried layer (4) has a thickness of 100nm, and the ion implantation process uses Mg + As dopant ions, the implantation dose is controlled to achieve a hole concentration of 3 × 10⁻⁶ in the p-GaN buried layer (4). 17 cm -3 After injection, it undergoes rapid thermal annealing at 850℃ for 30 seconds in a nitrogen gas stream. In step three, the growth temperature of the GaN channel layer (5) is 1000℃ and the thickness is 0.4μm; The etching process uses ICP dry etching, and the thickness Hs of the upper structure in the stepped structure of the GaN channel layer (5) is 100 nm. In step four, the growth temperature of the AlGaN barrier layer (6) is 1000℃ and the thickness is 20nm; the etching adopts the ICP dry etching process. In step five, the first P-GaN layer (12) and the second P-GaN layer (13) are made of p-type GaN, with a growth thickness of 100 nm and a hole concentration of 2 × 10⁻⁶. 17 cm -3 The first HfO2 layer (14) and the second HfO2 layer (15) are made of HfO2, grown at a temperature of 250°C, and have a thickness of 10nm. During the growth process, the deposition temperature and precursor flow rate are adjusted to reduce the interface state density between the first HfO2 layer (14), the second HfO2 layer (15) and the first P-GaN layer (12) and the second P-GaN layer (13) below, thereby improving the gate's control over the channel. In step six, the material of the first Si3N4 layer (7) is Si3N4, the growth temperature is 300℃, and the thickness is 50nm. After etching, the windows corresponding to the first source (8) and the second source (9) are etched to the surface of the GaN channel layer (5), and the windows corresponding to the first gate (16) and the second gate (17) are etched to the surface of the first HfO2 layer (14) and the second HfO2 layer (15). The first Si3N4 layer (7) is grown by PECVD process, and then the first Si3N4 layer (7) is patterned by ICP etching process. The etching uses Cl2 as the main etching gas and BCl3 as the auxiliary gas to remove surface residues and form electrode windows corresponding to the first source (8), the second source (9), the first gate (16), and the second gate (17), so as to avoid damage to the AlGaN barrier layer (6) and the first P-GaN layer (12) and the second P-GaN layer (13) under the etching process. In step seven, the deposition process of the first source electrode (8) and the second source electrode (9) is carried out with argon as the protective gas; then, a high-temperature annealing treatment of 850°C is carried out in a nitrogen atmosphere for 30 seconds to form an ohmic contact with the underlying GaN channel layer (5). In step eight, the deposition process of the first gate (16) and the second gate (17) uses argon as the protective gas; the extension length of the gate field plate is 2μm; In steps three and four, the etching of the GaN channel layer (5) and AlGaN barrier layer (6) uses Cl2 or BCl3 as the main etching gas, and O2 or SF6 is added to adjust the etching profile.

10. A method for fabricating a gallium nitride bidirectional switching device according to any one of claims 1-7, characterized in that, Includes the following steps: Step 1: Provide a substrate (1); Among them, the substrate (1) is made of SiC and needs to be pre-treated and cleaned: the RCA standard cleaning process is used to remove surface contaminants, and then high temperature pretreatment is carried out in hydrogen atmosphere to remove the surface oxide layer and obtain an atomically flat surface. Step 2: A nucleation layer (2) and a buffer layer (3) are grown sequentially on the substrate (1). Low-temperature AlN nucleation combined with superlattice strain buffer layer technology is used. Then, a p-GaN buried layer (4) is directly epitaxially grown in the middle region above the buffer layer (3) using in-situ Mg-doped MOCVD process. Among them, the nucleation layer (2) is made of AlN and is grown by MOCVD two-step method. The temperature of the low temperature layer is 550℃, the temperature of the high temperature layer is 1100℃, and the total thickness is 150nm; the buffer layer (3) is a strain buffer layer composed of 10 periods of AlN / GaN superlattice to reduce dislocation density; the thickness of the p-GaN buried layer (4) is 80nm. By precisely controlling the flow ratio of triethylgallium to Cp2Mg precursor, a high hole concentration and steep doping interface are achieved. Step 3: A GaN channel layer (5) is grown above the p-GaN buried layer (4) by MOCVD process, and the GaN channel layer (5) is etched by a low-damage ICP etching process based on BCl3 / SF6 mixed gas to form a steep and smooth step structure. The GaN channel layer (5) was grown at a temperature of 1050℃ and had a thickness of 0.3μm. After etching, it was immediately subjected to N2O plasma treatment, followed by thermal atomic layer deposition of 2nm thick SiN on the etched sidewalls and surface. x Passivation is performed to further reduce the interface state density; Step 4: An AlGaN barrier layer (6) is grown above the GaN channel layer (5) using MOCVD process, and the AlGaN barrier layer (6) is etched by a combination of photolithography and selective wet etching to form a precisely fitted step structure. The aluminum composition of the AlGaN barrier layer (6) is Al0. 30 Ga0. 70 N, with a growth temperature of 1020℃ and a thickness of 25nm; Step 5: Selectively grow a first P-GaN layer (12) and a second P-GaN layer (13) on the etched AlGaN barrier layer (6) using MOCVD process; before growing P-GaN, deposit a 0.5 nm MgO layer in situ as an interface dipole layer to adjust the work function and energy band alignment; then use spatially separated ALD process to grow a first HfO2 layer (14) and a second HfO2 layer (15) on top of the first P-GaN layer (12) and the second P-GaN layer (13) respectively. The thickness of the first P-GaN layer (12) and the second P-GaN layer (13) is 80 nm, and the hole concentration is 3 × 10¹. 7 cm - ³; The growth temperature of the first HfO2 layer (14) and the second HfO2 layer (15) is 200℃, and the thickness is 15nm; Step 6: The first Si3N4 layer (7) is grown on the AlGaN barrier layer (6) using inductively coupled plasma chemical vapor deposition (ICP-CVD). The first Si3N4 layer (7) is etched by reactive ion etching (RIE) to form an electrode window. The first Si3N4 layer (7) is grown at a temperature of 250°C and has a thickness of 70 nm to enhance its stress matching characteristics as a passivation layer. Step 7: Deposit the metal layers corresponding to the first source electrode (8) and the second source electrode (9) in the region corresponding to the electrode window by magnetron sputtering process; The deposited metals of the first source electrode (8) and the second source electrode (9) are Ta / Al / Mo / Au stacks. After deposition, they are subjected to rapid thermal annealing in a nitrogen atmosphere at 900°C for 15 seconds to form a specific contact resistance of less than 1×10⁻⁶. -6 Ohmic contact with Ω·cm²; Step 8: Above the first HfO2 layer (14) and the second HfO2 layer (15), the first gate (16) and the second gate (17) are deposited respectively by electron beam evaporation process to form Schottky contacts, and the gate metal is extended to the first Si3N4 layer (7) to form a composite field plate structure.

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