Silicon carbide power semiconductor device surface transverse dielectric cylinder super junction terminal structure
By introducing a lateral dielectric pillar superjunction termination structure on the surface of silicon carbide power semiconductor devices, the problems of excessively large device termination area and high forward conduction loss in existing technologies are solved, achieving high withstand voltage and low loss of the devices, making them suitable for mass production.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NANJING UNIV OF POSTS & TELECOMM
- Filing Date
- 2026-01-07
- Publication Date
- 2026-05-15
AI Technical Summary
Existing power semiconductor devices have excessively large terminal structures in high-voltage scenarios, resulting in increased forward conduction losses. They are also sensitive to interface charges, have poor process repeatability, and are not suitable for mass production.
A lateral dielectric pillar superjunction termination structure is adopted on the surface of silicon carbide power semiconductor devices. By introducing the lateral dielectric pillar superjunction structure between the field limiting rings, the doping concentration of the N-type pillar region is increased, the peak surface electric field is reduced, and the electric field distribution is optimized.
It improves the reverse withstand voltage of the device, reduces the forward conduction loss, shrinks the terminal area, simplifies the manufacturing process, and is suitable for mass production.
Smart Images
Figure CN122054655A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of power semiconductor device technology, and in particular to a surface lateral dielectric pillar superjunction termination structure for a silicon carbide power semiconductor device. Background Technology
[0002] The breakdown voltage and low loss of power semiconductor devices are their core performance indicators, and the design of the edge termination structure directly determines the final performance of the device. Among the existing termination technologies, the field-limited ring (FLR) structure and its process are simple, but a large number of floating rings are required in high-voltage scenarios, resulting in an excessively large termination area, increased forward conduction loss, and the low-doped drift region is susceptible to surface inversion due to interface charge. The junction termination extension (JTE) structure optimizes the electric field through gradient light doping, but it is sensitive to interface charge, has poor process repeatability, and is not conducive to large-scale production.
[0003] To further address the premature breakdown problem caused by curvature effects, reduce electric field concentration due to abnormal charge accumulation on the device surface, decrease the device termination area, and comprehensively improve the performance of power devices in terms of breakdown voltage, on-resistance, and area, this invention proposes a surface-mount lateral dielectric pillar superjunction termination structure for SiC power semiconductor devices. The proposed termination structure consists of a P-type field-limiting ring and lateral dielectric pillar superstructures distributed between the field-limiting rings. High-k dielectrics (such as HfO2, Al2O3, etc.) possess characteristics of high dielectric constant, high breakdown field strength, and low interface state density. Applying these high-k dielectrics to the key semiconductor doping regions of the aforementioned surface-mount lateral dielectric pillar superjunction structure reduces the impact of impurity charge balance on the superjunction structure, further lowers the peak electric field on the device surface, promotes more effective depletion of the drift region between the field-limiting rings, improves the breakdown voltage per unit length of the device termination, reduces the device termination area, and further optimizes breakdown voltage, area, and reliability. Summary of the Invention
[0004] The technical problem this invention aims to solve is to address the shortcomings of the prior art by providing a lateral dielectric pillar superjunction termination structure for a silicon carbide power semiconductor device. This lateral dielectric pillar superjunction termination structure, by introducing a lateral dielectric pillar superjunction structure between the field-limiting rings on the device's termination surface, can further increase the doping concentration of the N-type pillar region, thereby promoting more efficient depletion of the drift region between the field-limiting rings. Furthermore, the lateral dielectric pillar superjunction structure can further reduce the peak surface electric field. This termination structure can further improve the reverse breakdown voltage of the device, reduce forward conduction losses, and reduce the termination area.
[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: A surface-mount lateral dielectric pillar superjunction termination structure for a silicon carbide power semiconductor device includes an N-type doped drift region, a P-type doped ground ring, several P-type doped field confinement rings, and a lateral dielectric pillar superjunction.
[0006] P-type doped grounding rings and several P-type doped field confinement rings are sequentially arranged on top of the N-type doped drift region.
[0007] Dielectric rings are formed between the P-type doped grounding ring and the adjacent P-type doped field confinement ring, as well as between two adjacent P-type doped field confinement rings; each dielectric ring contains a plurality of the aforementioned transverse dielectric pillar superjunctions.
[0008] Each transverse dielectric pillar superjunction includes a phase-contacted high-K dielectric block and an N-type doped pillar region.
[0009] The radial width of the transverse dielectric column superjunction is equal to the radial width of the dielectric ring.
[0010] All medium rings have the same radial width.
[0011] In the direction away from the P-type doped grounding ring, the radial width of the dielectric ring gradually increases.
[0012] If the circumferential length of the transverse dielectric pillar superjunctions in all dielectric rings is equal and they are uniformly distributed, then as the radius of the dielectric ring increases, the number of transverse dielectric pillar superjunctions gradually increases, and the transverse dielectric pillar superjunctions in adjacent dielectric rings are staggered.
[0013] If the number of transverse dielectric pillar superjunctions in all dielectric rings is equal and their radial positions are aligned, then the circumferential length of the transverse dielectric pillar superjunctions gradually increases as the radius of the dielectric ring increases.
[0014] On the other side of the P-type doped grounding ring away from the P-type doped field confinement ring, a P-type doped well region is set at the top of the N-type doped drift region, and an N+ source region is set at the top of the P-type doped well region; the doping concentration of the N-type doped pillar region is greater than that of the N-type doped drift region but less than that of the P-type doped field confinement ring.
[0015] All high-K dielectric blocks have the same longitudinal depth, and all are less than the longitudinal depth of the P-type doped grounding ring or the P-type doped field confinement ring.
[0016] The vertical depths of the P-type doped grounding ring and the P-type doped field confinement ring are equal, and the vertical depth of the high-K dielectric block does not exceed half the vertical depth of the P-type doped field confinement ring.
[0017] The dielectric constant of the high-K dielectric block is not less than 20.
[0018] The present invention has the following beneficial effects: 1. The transverse dielectric pillar superjunction structure provided in this invention can promote more effective depletion of the drift region between field limiting rings, reduce the field limiting ring spacing, reduce the device terminal area, and lower the device manufacturing cost.
[0019] 2. The application of high-k dielectric blocks in the transverse dielectric pillar superjunction structure proposed in this invention makes the superjunction structure less affected by impurity charge balance, reduces the control requirements for doping concentration in the N-type pillar region, and simplifies the device manufacturing process.
[0020] 3. The high-k dielectric block in the transverse dielectric pillar superjunction structure proposed in this invention can significantly reduce the on-resistance of the device and reduce the on-loss of the device.
[0021] 4. The P-type grounding ring and P-type doped field limiting ring provided in this invention can increase the radius of curvature of the main junction in the active region of the device, thereby optimizing the electric field distribution within the device. Attached Figure Description
[0022] Figure 1 This is a schematic diagram of the lateral dielectric pillar superjunction termination structure on the surface of the silicon carbide power semiconductor device in Example 1.
[0023] Figure 2 This is a schematic diagram of a traditional field-limiting loop termination structure for power semiconductor devices.
[0024] Figure 3 This is a schematic diagram of the lateral dielectric pillar superjunction termination structure on the surface of the silicon carbide power semiconductor device in Example 2.
[0025] Figure 4 This is a schematic diagram of the lateral dielectric pillar superjunction termination structure on the surface of the silicon carbide power semiconductor device in Example 3.
[0026] Figure 5 This is a schematic diagram showing the result after step one of the preparation steps in Example 1 is completed.
[0027] Figure 6 This is a schematic diagram showing the result after step two of the preparation process in Example 1.
[0028] Figure 7 This is a schematic diagram showing the result after step three of the preparation process in Example 1.
[0029] Figure 8 This is a schematic diagram showing the result after step four of the preparation process in Example 1.
[0030] Figure 9 This is a schematic diagram showing the result after step five of the preparation process in Example 1 is completed.
[0031] Figure 10 This is a schematic diagram showing the result after step six of Example 1 is completed.
[0032] Figure 11 This is a schematic diagram showing the result after step seven of Example 1 is completed.
[0033] Figure 12 This is a schematic diagram showing the result after step eight of the preparation process in Example 1.
[0034] Figure 13 This is a schematic diagram showing the result after step nine of Example 1 has been completed.
[0035] Figure 14 This is a schematic diagram showing the result after step ten of Example 1 is completed.
[0036] Among them are: 1. Drain; 2. Substrate; 3. N-type doped drift region; 4. P-type doped well region; 5. N+ source region; 6. First source contact region; 7. Source; 8. Gate dielectric layer; 9. Gate; 10. Second source contact region; 11. Ground source; 12. P-type doped ground ring; 13. High-K dielectric passivation layer; 14. N-type doped pillar region; 15. High-K dielectric block; 16. P-type doped field-limiting ring; 17. N-type heavily doped electric field cutoff ring. Detailed Implementation
[0037] The present invention will now be described in further detail with reference to the accompanying drawings and specific preferred embodiments.
[0038] In the description of this invention, it should be understood that the terms "left side," "right side," "upper part," "lower part," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. "First," "second," etc., do not indicate the importance of the components, and therefore should not be construed as a limitation of this invention. The specific dimensions used in this embodiment are only for illustrating the technical solution and do not limit the scope of protection of this invention. Example 1
[0039] like Figure 1 As shown, this embodiment provides a surface lateral dielectric pillar superjunction termination structure for a silicon carbide power semiconductor device, including a drain 1, an N-type heavily doped substrate 2, and an N-type doped drift region 3 arranged sequentially from bottom to top.
[0040] The top of the N-type doped drift region 3 is provided with, from left to right, a P-type doped well region 4, a P-type doped ground ring 12, several equally spaced P-type doped field limiting rings 16, and an N-type heavily doped electric field cutoff ring 17. In this embodiment, the longitudinal depths of the P-type doped ground ring and the P-type doped field limiting ring are preferably equal.
[0041] The top of the P-type doped well region is provided with a first source contact region 6 and an N+ source region 5, which are heavily doped with P-type elements, arranged from left to right. A source electrode is arranged on the top surface of the first source contact region and is in contact with the N+ source region.
[0042] A gate dielectric layer 8 is disposed on the top surface of the N-type doped drift region between the P-type doped well region 4 and the P-type doped ground ring 12, and the gate dielectric layer is in contact with the N+ source region. A gate 9 is disposed on the top surface of the gate dielectric layer.
[0043] A second source contact region 10 heavily doped with P-type is provided on the top left side of the P-type doped grounding ring 12, and a grounding source 11 is arranged on the top surface of the second source contact region.
[0044] A high-K dielectric passivation layer 13 is also provided on the top surface of the N-type doped drift region, covering the surface of the terminal portion.
[0045] Dielectric rings are formed between the P-type doped grounding ring and the adjacent P-type doped field confinement ring, as well as between two adjacent P-type doped field confinement rings. Several transverse dielectric pillar superjunctions are evenly distributed within each dielectric ring. Each transverse dielectric pillar superjunction includes a high-K dielectric block 15 and an N-type doped pillar region 14 in contact with each other.
[0046] All dielectric rings have the same radial width, and the radial width of the transverse dielectric pillar superjunction is equal to that of the dielectric rings. Therefore, the high-K dielectric blocks are all in contact with the adjacent N-type doped pillar region, P-type doped ground ring, or P-type doped field confinement ring.
[0047] If the number of transverse dielectric pillar superjunctions in all dielectric rings is equal and their radial positions are aligned, then the circumferential length of the transverse dielectric pillar superjunctions gradually increases as the radius of the dielectric ring increases.
[0048] Furthermore, the doping concentration of the N-type doped pillar region is greater than that of the N-type doped drift region but less than that of the P-type doped field confinement ring, which is beneficial for the expansion of the depletion region.
[0049] Furthermore, the longitudinal depth of all high-K dielectric blocks is equal and less than the longitudinal depth of the P-type doped grounding ring or the P-type doped field confinement ring, preferably not exceeding half the longitudinal depth of the P-type doped field confinement ring.
[0050] Furthermore, the aforementioned high-k dielectric block, gate dielectric layer, and high-k dielectric passivation layer are all high-k dielectric materials with a dielectric constant of not less than 20.
[0051] The working principle of this invention is as follows: The junction termination structure proposed in this embodiment forms a three-dimensional, field-adjustable termination structure on top of the N-type doped drift region between the P-type doped ground ring 12 and the N-type heavily doped electric field cutoff ring 17. This termination structure, mainly composed of a lateral dielectric pillar superjunction and a P-type doped field-limiting ring, further increases the doping concentration of the N-type pillar region by introducing a lateral dielectric pillar superjunction between the field-limiting rings on the device termination surface, thereby promoting more efficient depletion of the drift region between the field-limiting rings. Furthermore, the high-k dielectric bulk has a higher dielectric constant than SiC, which further reduces the peak surface electric field. This termination structure can further transfer breakdown from the device surface to the bulk, improving the reverse breakdown voltage, reducing forward conduction losses, and minimizing the termination area.
[0052] Traditional field-limited loop terminal structure, such as Figure 2 As shown, in contrast, the superjunction termination structure provided in this embodiment further reduces the peak electric field on the device surface due to the presence of the high-K dielectric block and N-type doped pillar region between the field confinement rings, and improves the termination's ability to resist passivation layer interface charge.
[0053] like Figures 5 to 14 As shown, a method for fabricating a lateral dielectric pillar superjunction terminal structure on the surface of a silicon carbide power semiconductor device preferably includes the following steps.
[0054] Step 1: Select a SiC semiconductor substrate and epitaxially grow an epitaxial layer of a certain thickness on the substrate to form an N-type doped drift region, such as... Figure 5 As shown.
[0055] Step 2: Etching Grooves. Several grooves of equal depth are etched at the center of the top of the epitaxial layer. The grooves protrude to form semiconductor islands in the epitaxial layer. Figure 6 As shown.
[0056] Step 3: Fill the grooves. Using a dielectric deposition process, deposit a high-k dielectric in each groove and planarize it to form a high-k dielectric block 15, such as... Figure 7 As shown. In this embodiment, the number of transverse dielectric pillar superjunctions in all dielectric rings is equal and their radial positions are aligned. Therefore, as the radius of the dielectric ring increases, the circumferential length of the transverse dielectric pillar superjunction gradually increases. That is, as the radius of the dielectric ring increases, the circumferential length of the groove gradually increases.
[0057] Step 4: Simultaneously fabricate the P-type doped field confinement ring 16, the P-type doped ground ring 12, and the P-type doped well region 4 using the same process. Use photoresist as a mask to lithographically obtain the patterns of the P-type doped field confinement ring, the P-type doped ground ring, and the P-type doped well region. Perform P-type doping in the predetermined regions using ion implantation, such as... Figure 8 As shown.
[0058] Step 5: Simultaneously fabricate the first source contact region 6 and the second source contact region 10 using the same process. Use photoresist as a mask to lithographically obtain the patterns of the first and second source contact regions. Perform P-type heavy doping in the preset areas using ion implantation, such as... Figure 9 As shown.
[0059] Step Six: Fabricate N-type doped pillar regions 14 alternating with the high-k dielectric block. Use photoresist as a mask to lithographically obtain the N-type doped pillar pattern. Perform N-type doping in the preset regions using ion implantation, such as... Figure 10 As shown.
[0060] Step 7: Simultaneously fabricate the N+ source region 5 and the heavily doped N-type electric field cutoff ring 17 using the same process. Use photoresist as a mask to lithographically obtain the N+ source region and the heavily doped N-type electric field cutoff ring patterns. Perform N-type doping in the preset region using ion implantation, such as... Figure 11 As shown.
[0061] Step 8: Fabricate the gate dielectric layer 8 and the high-K dielectric passivation layer 13 using a dielectric deposition process on the N-type dielectric. - A layer of the same high-k dielectric as in step three is deposited on the surface of the drift region and planarized. Then, excess material is removed by dry etching. It should be ensured that the thickness of the gate dielectric layer 8 is less than the thickness of the high-k dielectric passivation layer 13. Figure 12 As shown.
[0062] Step 9: Fabricate surface metal electrodes. Deposit metal on the top surface of the first source contact region 6, the second source contact region 10, and the gate dielectric layer 8, respectively, and anneal them to form the source 7, the ground source 11, and the gate 9, as shown below. Figure 13 As shown.
[0063] Step 10: Fabricate the back metal electrode. Deposit metal on the back side of the substrate and anneal it to form the drain electrode, such as... Figure 14 As shown. Example 2
[0064] like Figure 3 As shown, the only difference between this example and Example 1 is that the spacing between the P-type doped field confinement rings is redistributed in this example. Therefore, the radial width of the dielectric ring is rearranged, with the spacing between the P-type doped field confinement rings gradually increasing in the direction away from the main junction (i.e., away from the direction of the P-type doped ground ring). At this time, the radial width of the dielectric ring gradually increases; however, the increase is not limited to arithmetic progression or indefinite increments. By adjusting the field confinement ring spacing, the electric field distribution can be further optimized, and the terminal area can be reduced. Example 3
[0065] like Figure 4As shown, the only difference between this example and Example 1 is that the circumferential length of the transverse dielectric pillar superjunctions in all dielectric rings is equal and uniformly distributed. As the radius of the dielectric ring increases, the number of transverse dielectric pillar superjunctions gradually increases, and the transverse dielectric pillar superjunctions in adjacent dielectric rings are staggered.
[0066] The lateral dielectric pillar superjunction structure in this invention is less affected by impurity charge balance, allowing for a further increase in the doping concentration of the N-type pillar region, thus promoting more efficient depletion of the drift region between field-limiting rings. Furthermore, the lateral dielectric pillar superjunction structure can further reduce the peak surface electric field. Compared to traditional field-limiting ring termination structures, this invention, while further optimizing the device's electric field distribution and improving reverse breakdown voltage, also reduces forward conduction resistance and termination area, making it suitable for large-scale mass production and high-density integration requirements.
[0067] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present invention, various equivalent transformations can be made to the technical solutions of the present invention, and these equivalent transformations all fall within the protection scope of the present invention.
Claims
1. A surface-mount lateral dielectric pillar superjunction termination structure for a silicon carbide power semiconductor device, characterized in that: This includes an N-type doped drift region, a P-type doped grounding ring, several P-type doped field confinement rings, and a lateral dielectric pillar superjunction. P-type doped grounding rings and several P-type doped field confinement rings are sequentially arranged on top of the N-type doped drift region; Dielectric rings are formed between the P-type doped grounding ring and the adjacent P-type doped field limiting ring, as well as between two adjacent P-type doped field limiting rings; each dielectric ring contains a plurality of the aforementioned transverse dielectric pillar superjunctions. Each transverse dielectric pillar superjunction includes a phase-contacted high-K dielectric block and an N-type doped pillar region.
2. The surface lateral dielectric pillar superjunction termination structure of the silicon carbide power semiconductor device according to claim 1, characterized in that: The radial width of the transverse dielectric column superjunction is equal to the radial width of the dielectric ring.
3. The surface lateral dielectric pillar superjunction termination structure of the silicon carbide power semiconductor device according to claim 2, characterized in that: All medium rings have the same radial width.
4. The surface lateral dielectric pillar superjunction termination structure of the silicon carbide power semiconductor device according to claim 1, characterized in that: In the direction away from the P-type doped grounding ring, the radial width of the dielectric ring gradually increases.
5. The surface lateral dielectric pillar superjunction termination structure of the silicon carbide power semiconductor device according to claim 1, characterized in that: If the circumferential length of the transverse dielectric pillar superjunctions in all dielectric rings is equal and they are uniformly distributed, then as the radius of the dielectric ring increases, the number of transverse dielectric pillar superjunctions gradually increases, and the transverse dielectric pillar superjunctions in adjacent dielectric rings are staggered.
6. The surface lateral dielectric pillar superjunction termination structure of the silicon carbide power semiconductor device according to claim 1, characterized in that: If the number of transverse dielectric pillar superjunctions in all dielectric rings is equal and their radial positions are aligned, then the circumferential length of the transverse dielectric pillar superjunctions gradually increases as the radius of the dielectric ring increases.
7. The surface lateral dielectric pillar superjunction termination structure of the silicon carbide power semiconductor device according to claim 1, characterized in that: On the other side of the P-type doped grounding ring away from the P-type doped field confinement ring, a P-type doped well region is set at the top of the N-type doped drift region, and an N+ source region is set at the top of the P-type doped well region; the doping concentration of the N-type doped pillar region is greater than that of the N-type doped drift region but less than that of the P-type doped field confinement ring.
8. The surface lateral dielectric pillar superjunction termination structure of the silicon carbide power semiconductor device according to claim 1, characterized in that: All high-K dielectric blocks have the same longitudinal depth, and all are less than the longitudinal depth of the P-type doped grounding ring or the P-type doped field confinement ring.
9. The surface lateral dielectric pillar superjunction termination structure of the silicon carbide power semiconductor device according to claim 8, characterized in that: The vertical depths of the P-type doped grounding ring and the P-type doped field confinement ring are equal, and the vertical depth of the high-K dielectric block does not exceed half the vertical depth of the P-type doped field confinement ring.
10. The surface lateral dielectric pillar superjunction termination structure of the silicon carbide power semiconductor device according to claim 1, characterized in that: The dielectric constant of the high-K dielectric block is not less than 20.