Manufacturing method of integrated structure of metal gate MOS (Metal Oxide Semiconductor) transistor

Abstract

The invention discloses a manufacturing method of an integrated structure of a metal gate MOS (Metal Oxide Semiconductor) transistor. The manufacturing method comprises the following steps of: defining a high-resistance MOS device gate structure region positioned in a high-resistance device region and a high-voltage MOS device gate structure region positioned in a high-voltage device region through photoetching; when the grid polycrystalline silicon is etched, the whole grid structure region of the high-voltage MOS device is reserved, and a slot is not formed in the grid structure region of the MOS device; a side wall is formed through self-alignment etching, and a side wall process photomask is not needed; and the etching of the high-resistance layer and the etching of the slot of the gate structure region of the high-voltage MOS device adopt the same layer of photomask. According to the manufacturing method, few photomasks are used, the gate structure of the high-voltage MOS device is healthier, the process window is larger, the electrical property of the device is better, and the reliability is higher; in addition, the etching process of the contact hole is simpler, and the resistance of the contact hole is smaller.

Description

Technical Field

[0001] This invention relates to semiconductor manufacturing technology, and in particular to a method for manufacturing an integrated structure of a metal gate MOS transistor. Background Technology

[0002] Moving down from the 28nm node, high-performance processes employ high-k dielectric (High-K, HK) dielectrics paired with metal gates to improve device performance. Low-voltage, medium-voltage, and high-voltage devices using the 28HV (28nm high-voltage) process all utilize HKMG (high-k dielectric metal gate) technology. The large area of ​​the high-voltage gate leads to metal gate dishing during chemical mechanical polishing (CMP) of the metal gate (e.g., Figure 1 As shown, an oxide slot needs to be made in the metal gate to prevent chemical mechanical polishing (CMP) from forming a metal gate dishing. At the same time, a spacer process photomask needs to be added to prevent the oxide in the high-voltage metal gate slot from being affected by the subsequent spacer process, which could cause potential reliability failures.

[0003] The 28HV uses the HKMG process, which has a low metal gate resistance (less than 30 ohms / sqr). A high-resistivity process needs to be added before the contact hole (CT) process to create a high-resistivity gate. The high-resistivity process introduces a separate photomask, as well as a matching photolithography and etching process.

[0004] Existing methods for manufacturing integrated structures of metal-gate MOS transistors require two photomasks—a sidewall photomask and a high-resistance (HiR) layer photomask—to meet the reliability requirements of high-voltage devices and the demands of high-resistance gate MOS transistors. Furthermore, the formation of the high-voltage metal gate slot necessitates polysilicon etching of the central portion of the gate structure, which carries the risk of reduced reliability. Additionally, to achieve the high-resistance gate of a high-resistance MOS device, an interlayer dielectric layer (ILD) and a high-resistance (HiR) layer must be sequentially formed above the polysilicon gate. The thicker ILD increases the length of the contact vias (CTs) on the active region (AA), making CT etching more difficult and increasing CT resistance. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a method for manufacturing an integrated structure of a metal gate MOS transistor, which uses fewer photomasks, results in a healthier gate structure for high-voltage MOS devices, a larger process window, a simpler etching process for contact holes (CTs), and lower contact hole (CT) resistance.

[0006] To solve the above-mentioned technical problems, the present invention provides a method for manufacturing an integrated structure of a metal gate MOS transistor, which includes the following steps:

[0007] S1. An active region process is performed on the silicon substrate 100, so that the silicon substrate 100 is divided into a high voltage device region 101 and a high resistance device region 102 by a shallow trench isolation 104; a pad oxide layer 105 is also covered on the silicon substrate 100 of the high voltage device region 101 and the high resistance device region 102.

[0008] S2. Deposit the gate polysilicon layer 106, and then coat the first photoresist 107;

[0009] S3. Photolithography defines the high-resistivity MOS device gate structure region located in the high-resistivity device region 102 and the high-voltage MOS device gate structure region located in the high-voltage device region 101. Etching removes the gate polysilicon layer 106 and pad oxide layer 105 outside the gate structure region and exposes the silicon substrate 100 and the upper surface of the shallow trench isolation 104, while retaining the gate polysilicon layer 106 and pad oxide layer 105 of the entire high-resistivity MOS device gate structure region and the high-voltage MOS device gate structure region.

[0010] S4. Remove the first photoresist 107 to generate the sidewall dielectric layer 108;

[0011] S5. Self-aligned etching of the sidewall dielectric layer 108 exposes the upper surface of the gate polysilicon layer 106 and the upper surface of the silicon substrate 100 and the shallow trench isolation 104 between the sidewalls, forming the sidewalls of the high-resistivity MOS device gate structure and the high-voltage MOS device gate structure.

[0012] S6. Form the first interlayer dielectric layer 109, and then perform chemical mechanical polishing to expose the gate polysilicon layer 106 of the high-resistivity MOS device gate structure and the high-voltage MOS device gate structure.

[0013] S8. Deposit a high-resistivity layer 110;

[0014] S9. Coat the second photoresist 111, and use photolithography to define the gate structure of the high-resistivity MOS device and its sidewall region, and define multiple high-voltage MOS device gate sub-structure regions spaced apart on the gate structure of the high-voltage MOS device.

[0015] S10. Etching: Remove the high resistance layer 110 outside the gate structure and sidewall region of the high resistance MOS device and the gate sub-structure region of each high voltage MOS device, and remove the gate polysilicon layer 106 outside the gate structure and the gate sub-structure region of each high voltage MOS device, exposing the pad oxide layer 105, and forming multiple high voltage MOS device gate sub-structures spaced by slots in the gate structure region of the high voltage MOS device.

[0016] S11. Remove the second photoresist 111, deposit the gate metal layer 112, and then chemically and mechanically polish it until it is flush with the high resistance layer 110;

[0017] S12. Generate the second interlayer dielectric layer 113;

[0018] S13. Form contact hole 114; the lower end of the contact hole of the high-resistivity MOS device is connected to the top surface of the high-resistivity layer 110 on the gate structure of the high-resistivity MOS device.

[0019] Preferably, after step S6, step S7 is performed to wet-etch the top of the gate polysilicon layer 106 of the high-resistivity MOS device gate structure and the high-voltage MOS device gate structure, and then step S8 is performed.

[0020] Preferably, in step S1, the silicon substrate 100 is divided into a high-voltage device region 101, a high-resistance device region 102 and a low-voltage device region 103 by a shallow trench isolation 104; and a pad oxide layer 105 is covered on the silicon substrate 100 of the high-voltage device region 101, the high-resistance device region 102 and the low-voltage device region 103.

[0021] In step S3, the low-voltage MOS device gate structure region located in the low-voltage device region 103 is defined by photolithography, the gate polysilicon layer 106 and the pad oxide layer 105 outside the gate structure region are etched away, and the silicon substrate 100 and the upper surface of the shallow trench isolation 104 are exposed, while retaining the gate polysilicon layer 106 and the pad oxide layer 105 of the entire low-voltage MOS device gate structure region, high-resistivity MOS device gate structure region and high-voltage MOS device gate structure region.

[0022] In step S5, the gate structure of the low-voltage MOS device, the gate structure of the high-resistivity MOS device, and the sidewalls of the gate of the high-voltage MOS device are formed.

[0023] In step S6, after chemical mechanical polishing, the gate polysilicon layer 106 of the low-voltage MOS device gate structure, the high-resistivity MOS device gate structure, and the high-voltage MOS device gate structure is exposed.

[0024] In step S7, wet etching is used to remove the top of the gate polysilicon layer 106 of the gate structure of the low-voltage MOS device, the gate structure of the high-resistivity MOS device, and the gate structure of the high-voltage MOS device.

[0025] In step S9, photolithography defines the gate structure and its sidewall region of the low-voltage MOS device, the gate structure and its sidewall region of the high-resistivity MOS device, and defines multiple high-voltage MOS device gate sub-structure regions spaced apart on the gate structure of the high-voltage MOS device.

[0026] In step S10, etching is performed to remove the high-resistivity layer 110 outside the gate structure and sidewall region of the low-voltage MOS device, the gate structure and sidewall region of the high-resistivity MOS device, and the gate sub-structure region of each high-voltage MOS device. The gate polysilicon layer 106 outside the gate structure of the low-voltage MOS device, the gate structure of the high-resistivity MOS device, and the gate sub-structure region of each high-voltage MOS device is also removed, exposing the pad oxide layer 105. Multiple high-voltage MOS device gate sub-structures spaced by slots are formed in the gate structure region of the high-voltage MOS device.

[0027] Preferably, in step S5, the gate structure of the low-voltage MOS device, the gate structure of the high-resistivity MOS device, and the sidewalls of the gate of the high-voltage MOS device are formed, and then lightly doped drain 120 ions are implanted into the low-voltage MOS device and the high-resistivity MOS device.

[0028] Ideally, the operating voltage of a low-voltage MOS device should be less than 2V.

[0029] Preferably, the high-resistance MOS device is a medium-voltage MOS device, and the operating voltage of the medium-voltage MOS device is 6V-10V.

[0030] Preferably, the operating voltage of the high-voltage MOS device is 20V-32V.

[0031] Preferably, in step S1, a high-voltage silicon trench is formed on the upper part of the silicon substrate 100 of the high-voltage device region 101 and filled with oxide; a medium-voltage silicon trench is formed on the upper part of the silicon substrate 100 of the high-resistivity device region 102 and filled with oxide.

[0032] The depth of the medium-pressure silicon groove in the silicon substrate 100 is less than the depth of the high-pressure silicon groove in the silicon substrate 100;

[0033] A pad oxide layer 105 covers the oxide in the silicon substrate 100 and the silicon trench.

[0034] Preferably, the depth of the high-voltage silicon trench in the silicon substrate 100 is [insert depth here].

[0035] The depth of the medium-pressure silicon trench in the silicon substrate 100 is

[0036] Preferably, in step S12, a second interlayer dielectric layer is formed by in-situ water vapor generation and thermal oxidation.

[0037] Preferably, the high resistance is made of titanium nitride, tantalum nitride, or tungsten nitride.

[0038] The manufacturing method of the integrated structure of the metal gate MOS transistor of the present invention defines the high-resistivity MOS device gate structure region located in the high-resistivity device region 102 and the high-voltage MOS device gate structure region located in the high-voltage device region 101 by photolithography; when performing gate polysilicon etching, the entire high-voltage MOS device gate structure region is retained, and no slot is formed in the MOS device gate structure region; sidewalls are formed by self-aligned etching, and no sidewall process photomask is required; the etching of the high-resistivity (HiR) layer 110 and the slot etching of the high-voltage MOS device gate structure region are performed using the same photomask. This manufacturing method, through adjustments to existing processes, can reduce the use of one photomask layer. Simultaneously, through structural adjustments, the bottom pad oxide layer 105 of the high-voltage device is continuously covered throughout the entire process, resulting in a healthier gate structure for the high-voltage MOS device, unaffected by process variations, a larger process window, better device electrical performance, and higher reliability. Furthermore, this manufacturing method eliminates the need to sequentially form an interlayer dielectric layer (ILD) and a high-resistance (HiR) layer above the gate polysilicon of the high-resistance MOS device. The ILD thickness can be reduced, the etching process for the contact holes (CT) is simpler, and the contact hole (CT) resistance is lower, offering electrical advantages. Attached Figure Description

[0039] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figures 1 to 13 This is a schematic cross-sectional view of the manufacturing process of an embodiment of the manufacturing method of the integrated structure of the metal gate MOS transistor of the present invention.

[0041] Explanation of reference numerals in the attached figures:

[0042] 100. Silicon substrate; 101. High voltage device region; 102. High resistance device region; 103. Low voltage device region; 104. Shallow trench isolation; 105. Pad oxide layer; 106. Gate polysilicon layer; 107. First photoresist; 108. Sidewall dielectric layer; 109. First interlayer dielectric layer; 110. High resistance layer; 111. Second photoresist; 112. Gate metal layer; 113. Second interlayer dielectric layer; 114. Contact hole; 120. LDD. Detailed Implementation

[0043] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] The terms "first," "second," and similar words used in this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Words such as "including" or "comprising" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," "right," "front," and "back" are used only to indicate relative positional relationships; these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0045] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0046] Example 1

[0047] A method for manufacturing an integrated structure of a metal gate MOS transistor includes the following steps:

[0048] S1. An active region (AA) process is performed on the silicon substrate 100, dividing the silicon substrate 100 into a high-voltage device region 101 and a high-resistivity device region 102 by shallow trench isolation (STI) 104; a pad oxide layer 105 is also applied to the silicon substrate 100 of the high-voltage device region 101 and the high-resistivity device region 102, as shown. Figure 1 As shown;

[0049] S2. Deposit the gate polysilicon layer 106, and then coat the first photoresist 107, as shown. Figure 2 As shown;

[0050] S3. Photolithography defines the high-resistivity MOS device gate structure region located in the high-resistivity device region 102 and the high-voltage MOS device gate structure region located in the high-voltage device region 101. Etching removes the gate polysilicon layer 106 and pad oxide layer 105 outside the gate structure regions, exposing the silicon substrate 100 and the upper surface of the shallow trench isolation 104. The gate polysilicon layer 106 and pad oxide layer 105 are retained throughout both the high-resistivity MOS device gate structure region and the high-voltage MOS device gate structure region. Figure 3 As shown;

[0051] S4. Remove the first photoresist 107 to generate the sidewall dielectric layer 108, as shown. Figure 4 As shown;

[0052] S5. Self-aligned etching of the sidewall dielectric layer 108 exposes the upper surface of the gate polysilicon layer 106, and exposes the upper surface of the silicon substrate 100 and shallow trench isolation (STI) 104 between the sidewalls, forming the sidewalls of the high-resistivity MOS device gate structure and the high-voltage MOS device gate structure, such as... Figure 5 As shown;

[0053] S6. Form the first interlayer dielectric layer 109, then perform chemical mechanical polishing (CMP) to expose the gate polysilicon layer 106 of the high-resistivity MOS device gate structure and the high-voltage MOS device gate structure, as shown. Figure 6 As shown;

[0054] S7. Wet etching to remove the top of the gate polysilicon layer 106 of the gate structure of the high-resistivity MOS device and the gate structure of the high-voltage MOS device, such as... Figure 7 As shown;

[0055] S8. Deposit a high resistivity (HiR) layer 110, such as Figure 8 As shown;

[0056] S9. Apply the second photoresist 111, and use photolithography to define the gate structure and sidewall region of the high-resistivity MOS device, and define multiple high-voltage MOS device gate sub-structure regions spaced apart on the gate structure, such as... Figure 9 As shown;

[0057] S10. Etching: Remove the high-resistivity layer (HiR) 110 outside the gate structure and sidewall region of the high-resistivity MOS device, and the gate polysilicon layer 106 outside the gate structure and the gate sub-structure region of each high-voltage MOS device, exposing the pad oxide layer 105. Multiple high-voltage MOS device gate sub-structures spaced by slots are formed in the high-voltage MOS device gate structure region, such as... Figure 10 As shown;

[0058] S11. Remove the second photoresist 111, deposit the gate metal layer 112, and then chemically mechanically polish (CMP) until flush with the high-resistivity (HiR) layer 110, as shown. Figure 11 As shown;

[0059] S12. Generate the second interlayer dielectric layer 113, as follows Figure 12 As shown;

[0060] S13. Form contact hole (CT) 114; the lower end of the contact hole of the high-resistivity MOS device is connected to the top surface of the high-resistivity (HiR) layer 110 on the gate structure of the high-resistivity MOS device, such as Figure 13 As shown.

[0061] The manufacturing method of the integrated structure of the metal gate MOS transistor in Example 1 defines the high-resistivity MOS device gate structure region located in the high-resistivity device region 102 and the high-voltage MOS device gate structure region located in the high-voltage device region 101 by photolithography; when performing gate polysilicon etching, the entire high-voltage MOS device gate structure region is preserved, and no slot is formed in the MOS device gate structure region; the sidewall is formed by self-aligned etching, and no sidewall process photomask is required; the etching of the high-resistivity (HiR) layer 110 and the slot etching of the high-voltage MOS device gate structure region are performed using the same photomask.

[0062] The manufacturing method of the integrated structure of the metal gate MOS transistor in Example 1 can reduce the use of one less photomask by adjusting the existing process. At the same time, through structural adjustment, the bottom pad oxide layer 105 of the high voltage device is continuously covered throughout the process, resulting in a healthier gate structure of the high voltage MOS device that is not affected by the process, a larger process window, better device electrical performance, and higher reliability.

[0063] In addition, this manufacturing method does not require the sequential formation of an interlayer dielectric layer (ILD) and a high-resistance (HiR) layer on top of the gate polysilicon of the high-resistance MOS device. The thickness of the interlayer dielectric layer (ILD) can be reduced, the etching process of the contact hole (CT) is simpler, and the contact hole (CT) resistance is lower, which has electrical advantages.

[0064] Example 2

[0065] In the manufacturing method of the integrated structure of the metal gate MOS transistor based on Embodiment 1, in step S1, the silicon substrate 100 is divided into a high-voltage device region 101, a high-resistance device region 102, and a low-voltage device region 103 by a shallow trench isolation (STI) 104; a pad oxide layer 105 is also covered on the silicon substrate 100 of the high-voltage device region 101, the high-resistance device region 102, and the low-voltage device region 103. Figure 1 As shown;

[0066] In step S3, the low-voltage MOS device gate structure region located in the low-voltage device region 103 is defined by photolithography. The gate polysilicon layer 106 and pad oxide layer 105 outside the gate structure region are etched away, exposing the silicon substrate 100 and the upper surface of the shallow trench isolation (STI) 104. The gate polysilicon layer 106 and pad oxide layer 105 of the low-voltage MOS device gate structure region, the high-resistivity MOS device gate structure region, and the high-voltage MOS device gate structure region are retained as a whole. Figure 3 As shown;

[0067] In step S5, the gate structure of the low-voltage MOS device, the gate structure of the high-resistivity MOS device, and the sidewalls of the gate of the high-voltage MOS device are formed, such as... Figure 5 As shown;

[0068] In step S6, after chemical mechanical polishing (CMP), the gate polysilicon layer 106 of the low-voltage MOS device gate structure, the high-resistivity MOS device gate structure, and the high-voltage MOS device gate structure is exposed, as shown below. Figure 6 As shown;

[0069] In step S7, wet etching is used to remove the top of the gate polysilicon layer 106 of the low-voltage MOS device gate structure, the high-resistivity MOS device gate structure, and the high-voltage MOS device gate structure, as shown below. Figure 7 As shown;

[0070] In step S9, photolithography defines the gate structure and its sidewall region of the low-voltage MOS device, the gate structure and its sidewall region of the high-resistivity MOS device, and defines multiple high-voltage MOS device gate sub-structure regions spaced apart on the gate structure of the high-voltage MOS device, such as... Figure 9 As shown;

[0071] In step S10, etching is performed to remove the high-resistivity (HiR) layer 110 outside the gate structure and sidewall region of the low-voltage MOS device, the gate structure and sidewall region of the high-resistivity MOS device, and the gate sub-structure regions of each high-voltage MOS device. The gate polysilicon layer 106 outside the gate structure and gate sub-structure regions of the low-voltage MOS device, the high-resistivity MOS device, and the gate sub-structure regions of each high-voltage MOS device is also removed, exposing the pad oxide layer 105. Multiple high-voltage MOS device gate sub-structures spaced by slots are formed in the high-voltage MOS device gate structure region, such as... Figure 10 As shown.

[0072] Preferably, in step S5, the gate structure of the low-voltage MOS device, the gate structure of the high-resistivity MOS device, and the sidewalls of the gate of the high-voltage MOS device are formed, and then lightly doped drain (LDD) 120 ion implantation is performed on the low-voltage MOS device and the high-resistivity MOS device, such as... Figure 5 As shown.

[0073] Ideally, the operating voltage of the low-voltage MOS device needs to meet the requirements of low voltage (less than 2V, for example, a few tenths of a volt or a few volts) and high speed.

[0074] Preferably, the high-impedance MOS device is a medium-voltage (MV) MOS device, which can be used in current drive circuits. The operating voltage of the medium-voltage MOS device is 6V-10V.

[0075] Preferably, the operating voltage of a high-voltage (HV) MOS device is 20V-32V.

[0076] Example 3

[0077] In the manufacturing method of the integrated structure of the metal gate MOS transistor based on Embodiment 1, in step S1, a high-voltage silicon recess (Si-Recess) is formed on the upper part of the silicon substrate 100 of the high-voltage device region 101 and filled with oxide; a medium-voltage silicon recess (Si-Recess) is formed on the upper part of the silicon substrate 100 of the high-resistivity device region 102 and filled with oxide.

[0078] The depth of the medium-pressure silicon groove in the silicon substrate 100 is less than the depth of the high-pressure silicon groove in the silicon substrate 100;

[0079] A pad oxide layer 105 covers the oxide in the silicon substrate 100 and the silicon recess (Si-Recess).

[0080] Preferably, the depth of the high-voltage silicon recess (Si-Recess) in the silicon substrate 100 is approximately (For example );

[0081] The depth of the medium-pressure silicon recess (Si-Recess) in the silicon substrate 100 is approximately (For example ).

[0082] Preferably, in step S12, the second interlayer dielectric layer 113 is formed by in-situ water vapor generation (ISSG) and thermal oxidation.

[0083] Preferably, the high resistivity (HiR) is made of materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (W2N, WN, WN2 or mixtures thereof).

[0084] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for manufacturing an integrated structure of a metal-gate MOS transistor, characterized in that, Includes the following steps: S1. An active region process is performed on a silicon substrate (100) to separate the silicon substrate (100) into a high voltage device region (101) and a high resistance device region (102) by shallow trench isolation (104); a pad oxide layer (105) is also covered on the silicon substrate (100) of the high voltage device region (101) and the high resistance device region (102); S2. Deposit a gate polysilicon layer (106), and then coat the first photoresist (107); S3. Photolithography defines the gate structure region of the high-resistivity MOS device located in the high-resistivity device region (102) and the gate structure region of the high-voltage MOS device located in the high-voltage device region (101). Etching removes the gate polysilicon layer (106) and pad oxide layer (105) outside the gate structure region and exposes the silicon substrate (100) and the upper surface of the shallow trench isolation (104). The gate polysilicon layer (106) and pad oxide layer (105) of the high-resistivity MOS device gate structure region and the high-voltage MOS device gate structure region are retained. S4. Remove the first photoresist (107) to generate the sidewall dielectric layer (108); S5. Self-aligned etching of the sidewall dielectric layer (108) exposes the upper surface of the gate polysilicon layer (106) and the upper surface of the silicon substrate (100) and shallow trench isolation (104) between the sidewalls, forming the sidewalls of the high-resistivity MOS device gate structure and the high-voltage MOS device gate structure. S6. Form the first interlayer dielectric layer (109), and then perform chemical mechanical polishing to expose the gate polysilicon layer of the high-resistivity MOS device gate structure and the high-voltage MOS device gate structure (106). S8. Deposit a high-resistivity layer (110); S9. Coat the second photoresist (111), and use photolithography to define the gate structure of the high-resistivity MOS device and its sidewall region, and define multiple high-voltage MOS device gate sub-structure regions spaced apart on the gate structure of the high-voltage MOS device. S10. Etching: Remove the high resistance layer (110) outside the gate structure and sidewall region of the high resistance MOS device and the gate sub-structure region of each high voltage MOS device, and remove the gate polysilicon layer (106) outside the gate structure and the gate sub-structure region of each high voltage MOS device, exposing the pad oxide layer (105), and forming multiple high voltage MOS device gate sub-structures spaced by slots in the gate structure region of the high voltage MOS device. S11. Remove the second photoresist (111), deposit the gate metal layer (112), and then chemically and mechanically polish it until it is flush with the high-resistivity layer (110); S12. Generate the second interlayer dielectric layer (113); S13. Form a contact hole (114); the lower end of the contact hole of the high-resistivity MOS device is connected to the top surface of the high-resistivity layer (110) on the gate structure of the high-resistivity MOS device.

2. The method for manufacturing the integrated structure of the metal gate MOS transistor according to claim 1, characterized in that, After step S6, step S7 is performed, where wet etching is used to remove the top of the gate polysilicon layer (106) of the gate structure of the high-resistivity MOS device and the gate structure of the high-voltage MOS device, and then step S8 is performed.

3. The method for manufacturing the integrated structure of the metal gate MOS transistor according to claim 2, characterized in that, In step S1, the silicon substrate (100) is separated into a high-voltage device region (101), a high-resistance device region (102), and a low-voltage device region (103) by shallow trench isolation (104); a pad oxide layer (105) is also covered on the silicon substrate (100) of the high-voltage device region (101), the high-resistance device region (102), and the low-voltage device region (103); In step S3, the low-voltage MOS device gate structure region located in the low-voltage device region (103) is defined by photolithography, the gate polysilicon layer (106) and pad oxide layer (105) outside the gate structure region are etched away and the silicon substrate (100) and the upper surface of the shallow trench isolation (104) are exposed, and the gate polysilicon layer (106) and pad oxide layer (105) of the low-voltage MOS device gate structure region, the high-resistivity MOS device gate structure region and the high-voltage MOS device gate structure region are retained. In step S5, the gate structure of the low-voltage MOS device, the gate structure of the high-resistivity MOS device, and the sidewalls of the gate of the high-voltage MOS device are formed. In step S6, after chemical mechanical polishing, the gate polysilicon layer (106) of the low-voltage MOS device gate structure, the high-resistivity MOS device gate structure and the high-voltage MOS device gate structure is exposed. In step S7, wet etching is used to remove the top of the gate polysilicon layer (106) of the gate structure of the low-voltage MOS device, the gate structure of the high-resistivity MOS device, and the gate structure of the high-voltage MOS device. In step S9, photolithography defines the gate structure and its sidewall region of the low-voltage MOS device, the gate structure and its sidewall region of the high-resistivity MOS device, and defines multiple high-voltage MOS device gate sub-structure regions spaced apart on the gate structure of the high-voltage MOS device. In step S10, etching is performed to remove the high-resistivity layer (110) outside the gate structure and sidewall region of the low-voltage MOS device, the gate structure and sidewall region of the high-resistivity MOS device, and the gate sub-structure region of each high-voltage MOS device. The gate polysilicon layer (106) outside the gate structure of the low-voltage MOS device, the gate structure of the high-resistivity MOS device, and the gate sub-structure region of each high-voltage MOS device is also removed, exposing the pad oxide layer (105). Multiple high-voltage MOS device gate sub-structures with slot spacing are formed in the gate structure region of the high-voltage MOS device.

4. The method for manufacturing the integrated structure of the metal gate MOS transistor according to claim 3, characterized in that, In step S5, the gate structure of the low-voltage MOS device, the gate structure of the high-resistivity MOS device, and the sidewalls of the gate of the high-voltage MOS device are formed, and then lightly doped drain (120) ion implantation is performed on the low-voltage MOS device and the high-resistivity MOS device.

5. The method for manufacturing the integrated structure of the metal gate MOS transistor according to claim 3, characterized in that, The operating voltage of low-voltage MOS devices is less than 2V.

6. The method for manufacturing the integrated structure of the metal gate MOS transistor according to claim 3, characterized in that, High-resistance MOS devices are medium-voltage MOS devices, and the operating voltage of medium-voltage MOS devices is 6V-10V.

7. The method for manufacturing the integrated structure of the metal gate MOS transistor according to claim 3, characterized in that, The operating voltage of high-voltage MOS devices is 20V-32V.

8. The method for manufacturing the integrated structure of the metal gate MOS transistor according to claim 3, characterized in that, In step S1, a high-voltage silicon trench is formed on the upper part of the silicon substrate (100) of the high-voltage device region (101) and filled with oxide; a medium-voltage silicon trench is formed on the upper part of the silicon substrate (100) of the high-resistivity device region (102) and filled with oxide. The depth of the medium-pressure silicon groove in the silicon substrate (100) is less than the depth of the high-pressure silicon groove in the silicon substrate (100); A pad oxide layer (105) covers the oxide in the silicon substrate (100) and the silicon trench.

9. The method for manufacturing the integrated structure of the metal gate MOS transistor according to claim 8, characterized in that, The depth of the high-voltage silicon trench in the silicon substrate (100) is The depth of the medium-pressure silicon trench in the silicon substrate (100) is 10. The method for manufacturing the integrated structure of the metal gate MOS transistor according to claim 1, characterized in that, In step S12, a second interlayer medium layer is formed by in-situ water vapor generation and thermal oxidation.

11. The method for manufacturing the integrated structure of the metal gate MOS transistor according to claim 1, characterized in that, The high resistance is achieved using titanium nitride, tantalum nitride, or tungsten nitride.

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