Chip module cutting method
By performing chamfering and secondary cutting processes on the interposer wafer, the mechanical reliability problem of large-size silicon interposers was solved, the structural integrity and yield of the chip module were improved, and the manufacturing of larger-size silicon interposers was realized to meet the needs of high-performance computing and artificial intelligence computing.
Patent Information
- Application Number
- CN202610199828.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2025-12-01
- Filing Date
- 2026-02-11
- Publication Date
- 2026-05-15
AI Technical Summary
Large-size silicon interposers have poor mechanical reliability and are prone to cracking, leading to product scrapping and making it difficult to meet the memory bandwidth and high chip integration requirements of high-performance computing and artificial intelligence computing.
The interposer cells of the interposer wafer are chamfered, including etching and grinding, to eliminate stress concentration points. Chip modules are formed through conductive bonding and die bonding. A secondary cutting process is used to avoid damage caused by uneven stress.
This improves the mechanical reliability and manufacturing yield of chip modules, enabling the manufacture of larger silicon interposers to accommodate more high-performance processors and high-bandwidth memory, thereby enhancing computing power.
Smart Images
Figure CN122054936A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a method for cutting chip modules. Background Technology
[0002] With the development of high-performance computing (HPC) and artificial intelligence (AI) technologies, the demand for chip computing power, energy efficiency, and data bandwidth is growing exponentially. Traditional monolithic integrated manufacturing processes are limited by factors such as photolithography area, manufacturing yield, and power density, making it difficult to meet the requirements of memory bandwidth and high chip integration for scenarios such as large model training and scientific computing.
[0003] Driven by the continuous growth of computing power, COWOS (Chip-on-Wafer-on-Substrate) packaging technology has emerged. COWOS integrates processors (such as GPUs and AI accelerators) and multiple high-bandwidth memory (HBM) chips side-by-side on a silicon interposer, utilizing through-silicon vias (TSVs) on the interposer to achieve ultra-high-density interconnects, significantly shortening data transmission paths, increasing bandwidth, and reducing latency and power consumption. To accommodate more powerful processors and more high-bandwidth memory, further improving computing power, the area of the silicon interposer is increased to accommodate larger processors and more high-bandwidth memory. However, excessively large silicon interposers can lead to problems such as warping and stress concentration. The larger the silicon interposer, the worse its mechanical reliability, making it prone to cracking and resulting in product failure. Therefore, a chip module cutting method is urgently needed to solve the mechanical reliability problem of large-size silicon interposers. Summary of the Invention
[0004] To address the mechanical reliability issues of large-size silicon interposers, this application provides the following technical solution: A method for cutting a chip module is provided, comprising: The interposer cells disposed on the interposer wafer are chamfered, wherein the interposer wafer includes a plurality of interposer cells; The conductive part is bonded to the back side of the chamfered interposer unit, and the grain is bonded to the surface of the chamfered interposer unit; The interposer wafer is diced to obtain an independent chip module, wherein the chip module includes a chamfered interposer unit and a die disposed on the surface of the chamfered interposer unit.
[0005] Furthermore, the interposer cells disposed on the interposer wafer are chamfered, including: Etch along the chamfered path from the surface of the intermediate layer cell to a preset depth; Grinding is performed on the back side of the interposer wafer to remove material of a preset thickness, causing the corners of the interposer cells to fall off. The corners of the interposer cells are marked by chamfering trajectories.
[0006] Furthermore, the sum of the preset depth and the preset thickness is greater than or equal to the original thickness of the interposer wafer before the back side of the interposer wafer is ground.
[0007] Furthermore, the chamfer trajectory is set as follows: perpendicular to the angle bisector of the corner, and at a distance of S from the vertex of the corresponding corner. C = S – S S , among which, S C S represents the distance from the chamfer trajectory to the vertex of the corresponding corner, and S represents the closest distance from the grain to the vertex of the corresponding corner. S This indicates the minimum safe distance between the chamfer trajectory and the corresponding grain.
[0008] Furthermore, the method of etching from the surface of the intermediate layer unit to a predetermined depth along the chamfered trajectory includes at least: plasma etching.
[0009] Furthermore, the interposer wafer is diced to obtain individual chip modules, including: Material is removed from the surface of the dicing groove to a first depth with a first width along the dicing groove provided on the surface of the interposer wafer; Following the trace left after material removal, the material is removed from the first depth to the second depth with a second width to obtain an independent chip module, wherein the first width is greater than the second width.
[0010] Furthermore, the method of removing material includes at least one of the following: removing material by mechanical cutting, removing material by laser cutting, or removing material by plasma etching.
[0011] Furthermore, bonding the conductive portion to the back side of the chamfered interposer cell includes: Photoresist is applied to the back side of the beveled intermediate layer unit; Photolithography is used to expose conductive leads disposed on the back side of the interposer unit; The conductive part is bonded to the exposed conductive lead.
[0012] Furthermore, the die includes processor die and high-bandwidth memory die; Bonding grains to the surface of the beveled interposer unit includes: The processor die and high-bandwidth memory die are bonded to the surface of the interposer unit.
[0013] Furthermore, after bonding the grains to the surface of the beveled interposer unit, the process also includes: The die is encapsulated on the surface of the chamfered interposer unit.
[0014] By implementing the chip module cutting method provided in this application embodiment, the four corners of the chip module interposer are chamfered to eliminate stress concentration points, improve the mechanical stress problem of large-size high-density interposers, and improve product manufacturing yield; thereby, it is possible to manufacture larger-size silicon interposers to accommodate high-performance processors and more high-bandwidth memory, further improving computing power; the use of a secondary cutting process in the cutting of interposer units can avoid damage to the silicon interposer caused by uneven stress at the dielectric interface. Attached Figure Description
[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0016] Figure 1 This is a schematic diagram of a chip module cutting method provided in an embodiment of this application; Figure 2 This is a top view of the interposer wafer before chamfering of the interposer cells provided in the embodiments of this application; Figure 3 This is a top view of the structure of a single chip module before chamfering, provided in an embodiment of this application; Figure 4 This is a schematic diagram of the chamfer trajectory provided in an embodiment of this application; Figure 5 This is a schematic diagram of etching and grinding along the chamfer trajectory provided in an embodiment of this application; Figure 6 This is a top view of the beveled interposer wafer provided in an embodiment of this application; Figure 7 This is a top view of the structure of a single chip module after beveling, provided in an embodiment of this application; Figure 8 This is a schematic diagram of the cutting tape and bracket provided in an embodiment of this application; Figure 9 This is a schematic cross-sectional view along the cutting depth of the dicing groove provided in an embodiment of this application. Detailed Implementation
[0017] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0018] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The numbers in the accompanying drawings are only used to distinguish individual functional parts or modules and do not indicate logical relationships between parts or modules. The terms “comprising,” “including,” or “including,” and similar terms mean that the element or object preceding the term encompasses the element or object listed following the term and its equivalents, without excluding other elements or objects. The terms “connected,” “linked,” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. “Above,” “below,” “left,” “right,” etc., are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0019] The various embodiments according to this disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that in the drawings, the same reference numerals are assigned to components having substantially the same or similar structure and function, and repeated descriptions of them will be omitted.
[0020] To address the issues of poor mechanical reliability and low processing yield of large-size silicon interposers, this application provides the following technical solution: In some embodiments, such as Figure 1 As shown, a chip module cutting method includes: S100: Chamfering is performed on the interposer cells disposed on the interposer wafer, wherein the interposer wafer includes a plurality of interposer cells.
[0021] S200: The conductive part is bonded to the back side of the chamfered interposer unit, and the grain is bonded to the surface of the chamfered interposer unit.
[0022] S300: Cut the interposer wafer to obtain an independent chip module, wherein the chip module includes a chamfered interposer unit and a die disposed on the surface of the chamfered interposer unit.
[0023] The chip module cutting method provided in this application is applicable to the cutting of chip modules during the manufacturing process of chip modules using COWOS process.
[0024] Chip modules manufactured using the COWOS process are formed by encapsulating the die in an interposer unit, creating a chip module suitable for high-performance computing and artificial intelligence computing.
[0025] The die includes processor units and high-bandwidth memory units. The processor units include graphics processing units (GPUs), systems-on-chip (SoCs), AI accelerators, etc., used to perform high-speed calculations. High-bandwidth memory (HBM) units are used to meet the data throughput requirements of high-performance computing.
[0026] Interposer cells refer to the interposer layer that forms a single, independent chip module with the die. Typically, interposer cells are obtained by dicing an interposer wafer. A single interposer wafer contains several interposer cells. Before dicing the interposer wafer to obtain individual interposer cells, the die is encapsulated on the surface of each interposer cell. This application does not limit the process of encapsulating the die with the interposer or the selection of the die.
[0027] On the surface of the interposer wafer, dicing grooves are provided between adjacent interposer cells. A dicing device is used to cut along these grooves to obtain individual interposer cells. For interposer cells that have completed die packaging, the result after cutting is a single, independent chip module.
[0028] Figure 2 This diagram shows a schematic of a dielectric wafer before chamfering of the dielectric cells. The dielectric wafer includes several dielectric cells, and dicing grooves are provided between adjacent dielectric cells. Figure 2 (represented by dashed lines), allowing the wafer to be cut along the dicing groove to obtain individual interposer cells. Figure 2 The diagram only illustrates the distribution of the interposer units on the interposer wafer and does not specify the exact size and relative position of the interposer wafer and the interposer units.
[0029] Figure 3 The diagram schematically illustrates a top-down view of a single, independent chip module (the intermediate layer cells shown are not chamfered). For ease of explanation, Figure 3The diagram schematically illustrates a single, independent chip module with a processor and six high-bandwidth memory chips mounted on an interposer layer. However, this application does not limit the number of high-bandwidth memory chips mounted on the interposer layer. Chip module 100 includes an interposer layer 110 and a die 120, with the die 120 disposed on the surface of the interposer layer 110. High-density wiring (not shown) is provided on the interposer layer 110 to support high-speed interconnection between the dies packaged thereon.
[0030] For chip modules suitable for high-performance computing and artificial intelligence computing scenarios, silicon is used as the interposer layer. The interposer layer material can also be SiC, GaN, GaAs, SiGe, InP, or glass, etc. This application does not limit the interposer layer material.
[0031] Individual chip modules packaged from interposer units without chamfering are rectangular or square. Stress concentration easily occurs at the four right corners of the interposer, leading to cracking. This stress concentration is particularly pronounced when attempting to increase the interposer area to accommodate more chips and thus improve computing power, resulting in decreased mechanical reliability. Chamfering the four corners of the interposer units eliminates stress concentration points, improves the mechanical stress problem of large-size expensive interposers, and increases product manufacturing yield. This allows for the manufacture of larger interposers, increasing the number of processors and high-bandwidth memory that can be integrated, further enhancing computing power.
[0032] The chip module cutting method provided in this application first bevels the interposer units in the interposer wafer, then completes double-sided bonding of the conductive part and the die, and finally cuts to obtain an independent chip module. This method can avoid interposer cracking due to stress concentration during the cutting process after the chip module is fabricated, thus improving the structural integrity and yield of the chip module.
[0033] Specifically, chamfering is performed on the interposer cells disposed on the interposer wafer, including: Etch along the chamfered path from the surface of the intermediate layer cell to a preset depth; Grinding is performed on the back side of the interposer wafer to remove material of a preset thickness, causing the corners of the interposer cells to fall off. The corners of the interposer cells are marked by chamfering trajectories.
[0034] Figure 4 This diagram illustrates the positional relationship between the interposer unit, the chamfer trajectory, and the corners of the interposer unit. 100a, 100b, 100c, and 100d represent the corners of the interposer unit in the chip module. The dashed lines corresponding to each corner represent the respective chamfer trajectory.
[0035] The chamfer trajectory is set as follows: perpendicular to the angle bisector of the corner, and at a distance of S from the corresponding vertex of the corner.C = S – S S , among which, S C S represents the distance from the chamfer trajectory to the vertex of the corresponding corner, and S represents the closest distance from the grain to the vertex of the corresponding corner. S This indicates the minimum safe distance between the chamfer trajectory and the corresponding grain.
[0036] The minimum safe distance refers to the distance that will not affect the nearest grain during the cutting process.
[0037] Setting the chamfer trajectory ensures that the chamfer area is far away from the effective circuit area of the die, preventing etching damage to the functional structure of the die, while maximizing the stress release space.
[0038] It should be noted that, in Figure 4 The diagram illustrates the bonding positions between the grain and the interposer unit. During the chamfering process of the interposer unit, the grain has not yet bonded to the interposer unit.
[0039] Preferably, the sum of the preset depth and the preset thickness is greater than or equal to the original thickness of the interposer wafer before the back side of the interposer wafer is ground.
[0040] The sum of the preset depth and preset thickness is greater than or equal to the original thickness of the interposer wafer, which ensures that the amount of removal by etching and grinding is sufficient to completely separate the corners and avoid stress concentration caused by the corners remaining in the interposer cells.
[0041] Figure 5 Part (a) shows a cross-sectional view perpendicular to the chamfer path and the etching direction, where H D H represents the preset depth, and H represents the original thickness of the interposer wafer.
[0042] Figure 5 Part (b) shows a cross-sectional view perpendicular to the chamfer path and the etching direction, where H T This indicates the preset thickness. The dashed line represents the material removed by grinding.
[0043] By first etching along the chamfer path from the surface to a preset depth, and then grinding away the material of a preset thickness from the back, the corners are removed. This combination of etching and grinding is used to chamfer the interposer unit without mechanical impact, avoiding edge chipping or micro-cracks caused by traditional cutting. It is especially suitable for ultra-thin interposers.
[0044] Preferably, the method of etching from the surface of the intermediate layer unit to a predetermined depth along the chamfered trajectory includes at least: plasma etching.
[0045] Taking silicon interposers as an example, the plasma etching process is briefly described below: High-energy active ions and free radicals are used to physically sputter and chemically react with the silicon surface to generate volatile products (such as SiF4), thereby achieving material removal. Fluorine-containing gases (such as SF6, CF4, C4F8, etc.) are usually selected as etching gases. The gas is ionized by radio frequency or microwave energy to form a plasma containing ions, electrons, and free radicals, so that the F free radicals react chemically with the silicon interlayer: Si + 4F → SiF4↑.
[0046] However, during the process, bias voltage is used to accelerate ions to bombard the surface of the interposer vertically, enhancing directionality; at the same time, a polymer protective layer is formed on the sidewall to suppress lateral etching.
[0047] By leveraging the high directionality and controllability of plasma etching, precise and low-damage etching of interposer units can be achieved.
[0048] Figure 6 This diagram shows a schematic of an interposer wafer after the interposer cells disposed on the interposer wafer have been chamfered. Figure 6 The chamfering trajectory is represented by dashed lines, and the scribe lines represent the scribe grooves. When chamfering the interposer cells using a combination of front-side etching and back-side grinding, the etching along the chamfering trajectory needs to extend to the scribe grooves. Thus, after back-side grinding, a hollowed-out portion is created along the chamfering trajectory. In subsequent processes, after cutting and separating individual interposer cells along the scribe grooves, an "octagonal" interposer cell is obtained. Figure 6 The diagram only illustrates the distribution of the interposer units on the interposer wafer and does not specify the exact size and relative position of the interposer wafer and the interposer units.
[0049] Specifically, bonding the conductive portion to the back side of the chamfered interposer unit includes: Photoresist is applied to the back side of the beveled intermediate layer unit; Photolithography is used to expose conductive leads disposed on the back side of the interposer unit; The conductive part is bonded to the exposed conductive lead.
[0050] Photolithography is used to precisely position the conductive leads on the back side, ensuring reliable connection of conductive parts (such as solder balls and RDLs) and improving the consistency of electrical performance.
[0051] Specifically, the chips include processor chips and high-bandwidth memory chips; Bonding grains to the surface of the beveled interposer unit includes: The processor die and high-bandwidth memory die are bonded to the surface of the interposer unit.
[0052] Preferably, after bonding the grains to the surface of the chamfered interposer unit, the method further includes: The die is encapsulated on the surface of the chamfered interposer unit.
[0053] Encapsulation further protects the die and improves the long-term reliability of the chip module under thermal cycling and mechanical shock.
[0054] Preferably, the encapsulation material on the surface of the die is removed by planarization to optimize the heat dissipation performance of the die.
[0055] Figure 7 A top view of the chip module after chamfering and die bonding is shown. Corners 100a, 100b, 100c, and 100d have been removed. Figure 7 (The middle part is indicated by a dashed line).
[0056] It should be noted that the bonding and packaging manufacturing processes described in this application are intended to emphasize their sequential relationship with the interposer cell chamfering process. This application does not limit the specific content of the bonding and packaging processes, which are mature semiconductor process technologies.
[0057] Cutting the interposer wafer to obtain independent chip modules, including: Material is removed from the surface of the dicing groove to a first depth with a first width along the dicing groove provided on the surface of the interposer wafer; Following the trace left after material removal, the material is removed from the first depth to the second depth with a second width to obtain an independent chip module, wherein the first width is greater than the second width.
[0058] Preferably, before dicing the interposer wafer, the interposer wafer needs to be attached to the surface of the dicing tape 200 with its front side facing upwards. The dicing tape 200 is an auxiliary material used in the wafer dicing stage; it is adhesive and is typically placed on the support 300 to form a support structure. Optionally, the support 300 is made of metal or plastic. Preferably, the support 300 is circular in shape, such as... Figure 8 As shown. However, this application does not limit the material or shape of the bracket.
[0059] During the cutting process, the cutting tape prevents the chip or chip module from shifting, splashing, or cracking. After cutting, each interposer unit or chip module adheres to the surface of the cutting tape, and by stretching the tape, it can be accurately grasped by a robotic arm in subsequent processes. The cutting tape has a certain thickness, illustratively ranging from 80μm to 200μm.
[0060] Because the mechanical properties of each layer of the interposer wafer differ, in order to safely cut the interposer wafer, it is preferable to use a layer-by-layer cutting method to cut the interposer wafer.
[0061] A passivation layer exists on the surface of the interposer wafer, and the interposer material lies beneath the passivation layer, such as... Figure 9 As shown. The first depth h1 extends from the surface of the passivation layer to the interface between the passivation layer and the interposer material. The second depth h2 extends from the interface between the passivation layer and the interposer material into the interior of the cutting tape (in the cross-sectional direction), so that the chip module is completely separated and attached to the surface of the cutting tape.
[0062] The specific values of the first depth h1, the second depth h2, the first width Z1, and the second width Z2 are usually set according to the interposer wafer processed in the process. This application does not limit the specific values of the above parameters.
[0063] For interposer wafers, a two-stage, variable-width dicing method is adopted: in the first stage, a shallow cut with a larger width is made to reduce dicing resistance and vibration; in the second stage, a deep cut with a smaller width is made to improve dicing accuracy and reduce the scribe width, thereby increasing the yield per unit wafer chip.
[0064] Optionally, the material removal method includes at least one of the following: removing the material by mechanical cutting, removing the material by laser cutting, or removing the material by plasma etching.
[0065] Material removal methods include at least one of the following: mechanical cutting, laser cutting, or plasma etching. Laser stealth cutting utilizes picosecond or femtosecond lasers to focus the material within the interposer layer, rather than on its surface. This causes nonlinear absorption at the focal point within the interposer layer, creating microvoids, lattice damage, and a modified layer of localized melting and resolidification. Laser stealth cutting is a non-contact process with no tool wear. It offers advantages such as smooth cutting edges, high mechanical strength, and no need for secondary polishing. It is suitable for cutting ultra-thin materials such as flexible glass and silicon wafers that are tens of micrometers thick.
[0066] Employing laser stealth dicing technology, it achieves a resolution of 50nm, focusing on a specific depth within the wafer, resulting in a chip-free and debris-free dicing process. It is suitable for manufacturing CPUs, GPUs, AI chips, and high-bandwidth memory; and for dicing SiC and GaN semiconductor materials.
[0067] The interposer wafer is compatible with a variety of cutting processes, and the cutting method can be flexibly selected according to equipment conditions and material characteristics, which increases the applicability of this application.
[0068] By implementing the chip module cutting method provided in this application, the four corners of the silicon interposer before bonding are chamfered to eliminate stress concentration points, improve the mechanical stress problem of large-size expensive interposers, and increase product manufacturing yield. In the chamfering process, an etching-grinding method is used to avoid edge chipping or microcracks caused by mechanical impact from traditional cutting. Chamfering before interposer bonding avoids damage to the interposer caused by stress concentration during subsequent processes. This allows for the manufacture of larger silicon interposers to accommodate high-performance processors and more high-bandwidth memory, further improving computing power. A secondary cutting process is used during the cutting of interposer units to avoid damage to the silicon interposer caused by uneven stress at the dielectric interface. Furthermore, the chip module cutting method provided in this application is highly applicable and can be used with various cutting processes.
[0069] All of the above-mentioned optional technical solutions can be combined in any way to form the optional embodiments of this application, and will not be described in detail here.
[0070] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments. Many other equivalent embodiments may be included without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
[0071] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0072] Specifically, according to embodiments of this application, the processes described above with reference to the flowcharts can be implemented as steps controlled by a computer software program. For example, embodiments of this application include a computer program product comprising a computer program loaded on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from memory, or installed from ROM. When the computer program is executed by an external processor, it performs the functions defined in the methods of embodiments of this application.
[0073] It should be noted that the computer-readable medium in the embodiments of this application can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In the embodiments of this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In the embodiments of this application, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (Radio Frequency), etc., or any suitable combination thereof.
[0074] The aforementioned computer-readable medium may be included in the aforementioned server; or it may exist independently and not assembled into the server. The aforementioned computer-readable medium carries one or more programs that, when executed by the server, cause the server to: in response to detecting that the peripheral mode of the terminal is not activated, acquire the frame rate of the application on the terminal; when the frame rate meets the screen-off condition, determine whether the user is acquiring the terminal's screen information; and in response to the determination that the user is not acquiring the terminal's screen information, control the screen to enter an immediate dimming mode.
[0075] Computer program code for performing the operations of the embodiments of this application can be written in one or more programming languages or a combination thereof. Programming languages include object-oriented programming languages—such as Java, Smalltalk, and C++—and conventional procedural programming languages—such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).
[0076] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for system or system embodiments, since they are basically similar to method embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions in the method embodiments. The systems and system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.
[0077] The technical solutions provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only intended to help understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.
[0078] The data storage method, device, and storage medium provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. These embodiments are merely preferred embodiments of this application, used to help understand the method and its core ideas, and are not intended to limit this application. It should be noted that for those skilled in the art, any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application without departing from its principles are also within the protection scope of the claims of this application.
Claims
1. A method for cutting a chip module, characterized in that, include: The interposer cells disposed on the interposer wafer are chamfered, wherein the interposer wafer includes a plurality of interposer cells; The conductive portion is bonded to the back side of the chamfered interposer unit, and the grain is bonded to the surface of the chamfered interposer unit; The interposer wafer is diced to obtain an independent chip module, wherein the chip module includes the chamfered interposer unit and a die disposed on the surface of the chamfered interposer unit.
2. The chip module cutting method according to claim 1, characterized in that, The chamfering of the interposer cells disposed on the interposer wafer includes: Etch along the chamfered trajectory from the surface of the intermediate layer unit to a predetermined depth; Grinding is performed on the back side of the interposer wafer to remove material of a preset thickness, causing the corners of the interposer unit to fall off, wherein the corners of the interposer unit are marked by the chamfering trajectory.
3. The chip module cutting method according to claim 2, characterized in that, The sum of the preset depth and the preset thickness is greater than or equal to the original thickness of the interposer wafer before the back side of the interposer wafer is ground.
4. The chip module cutting method according to claim 2, characterized in that, The chamfering trajectory is set as follows: perpendicular to the angle bisector of the corner, and at a distance of S from the vertex of the corresponding corner. C = S – S S , wherein the S C S represents the distance from the chamfered trajectory to the vertex of the corresponding corner, and S represents the closest distance from the grain to the vertex of the corresponding corner. S This indicates the minimum safe distance between the chamfered trajectory and the corresponding grain.
5. The chip module cutting method according to claim 2, characterized in that, The method of etching from the surface of the intermediate layer unit to a preset depth along the chamfered trajectory includes at least: plasma etching.
6. The chip module cutting method according to claim 1, characterized in that, The process of cutting the interposer wafer to obtain an independent chip module includes: Material is removed from the surface of the dicing groove to a first depth with a first width along the dicing groove provided on the surface of the interposer wafer; Following the trace left after material removal, the material is removed from the first depth to the second depth with a second width to obtain an independent chip module, wherein the first width is greater than the second width.
7. The chip module cutting method according to claim 6, characterized in that, The method of removing the material includes at least one of the following: removing the material by mechanical cutting, removing the material by laser cutting, or removing the material by plasma etching.
8. The chip module cutting method according to claim 1, characterized in that, The bonding of the conductive portion to the back side of the chamfered interposer unit includes: Photoresist is applied to the back side of the intermediate layer unit after the chamfering. Photolithography is used to expose the conductive leads disposed on the back side of the interposer unit; The conductive part is bonded to the exposed conductive lead.
9. The chip module cutting method according to claim 1, characterized in that, The die includes processor die and high-bandwidth memory die; The process of bonding grains to the surface of the beveled interposer unit includes: The processor die and the high-bandwidth memory die are bonded to the surface of the interposer unit.
10. The chip module cutting method according to claim 1, characterized in that, After bonding the grains to the surface of the chamfered interposer unit, the process further includes: The die is encapsulated on the surface of the chamfered intermediate layer unit.