Manufacturing method of semiconductor structure, semiconductor device and electronic equipment

Abstract

The embodiment of the invention provides a manufacturing method of a semiconductor structure, a semiconductor device and electronic equipment. The manufacturing method of the semiconductor structure comprises the steps of providing a substrate; forming a hard mask layer covering the substrate; the hard mask layer comprises a first mask layer and a second mask layer which are stacked; using the hard mask layer to etch the substrate so as to form a patterned substrate; grinding and removing the hard mask layer; wherein the grinding rate of the first mask layer is different from that of the second mask layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure, a semiconductor device, and an electronic device. Background Technology

[0002] In the manufacturing process of semiconductor devices, a series of etching processes are frequently used. These etching processes typically employ a hard mask (HM). The hard mask is formed on various material layers (e.g., semiconductor layers) within the semiconductor device to pattern those layers. Normally, the hard mask is removed after the etching process using chemical mechanical polishing (CMP) to allow it to proceed to the next process. However, due to process limitations, the surface of the material layer to be patterned may be uneven. This results in some hard mask residue remaining on the surface of the material layer after CMP removal. This residue can potentially affect subsequent processes, thereby impacting the performance of the semiconductor device. Summary of the Invention

[0003] In view of the above, this disclosure provides a method for manufacturing a semiconductor structure, a semiconductor device, and an electronic device.

[0004] To achieve the above objectives, the technical solution disclosed herein is implemented as follows:

[0005] In a first aspect, embodiments of this disclosure provide a method for manufacturing a semiconductor structure, the method comprising:

[0006] Provide a base;

[0007] A hard mask layer is formed covering the substrate; the hard mask layer includes a first mask layer and a second mask layer stacked together;

[0008] The substrate is etched using the hard mask layer to form a patterned substrate;

[0009] The hard mask layer is ground and removed; wherein the grinding rate of the first mask layer is different from the grinding rate of the second mask layer.

[0010] In some embodiments, forming the hard mask layer covering the substrate includes:

[0011] The first mask layer is deposited on the surface of the substrate;

[0012] The second mask layer is deposited on the surface of the first mask layer.

[0013] In some embodiments, prior to etching the substrate using the hard mask layer to form a patterned substrate, the manufacturing method further includes:

[0014] The first mask layer and the second mask layer are etched using a photomask to form the patterned hard mask layer.

[0015] In some embodiments, the substrate includes a dummy gate, the top of which is flush with the surface of the substrate; the etching of the substrate using the hard mask layer to form a patterned substrate includes:

[0016] The dummy gate in the first portion is removed by etching using the hard mask layer; wherein the location of the dummy gate in the first portion is used to form a single diffusion region cut-off structure.

[0017] In some embodiments, after grinding and removing the hard mask layer, the manufacturing method further includes:

[0018] The dummy gate in the second part is replaced with a gate to form a gate; the second part is different from the first part.

[0019] In some embodiments, the polishing rate of the first mask layer is greater than the polishing rate of the second mask layer;

[0020] The grinding rate of the substrate is less than the grinding rate of the second mask layer.

[0021] In some embodiments, the material of the first mask layer includes silicon oxide, and the material of the second mask layer includes silicon nitride.

[0022] In some embodiments, the thickness of the first mask layer is less than the thickness of the second mask layer.

[0023] In a second aspect, embodiments of this disclosure provide a semiconductor device, the semiconductor device comprising:

[0024] At least one semiconductor structure formed by the manufacturing method described in the above embodiments.

[0025] Thirdly, embodiments of this disclosure provide an electronic device, the electronic device comprising:

[0026] Memory and / or processor;

[0027] The memory and / or processor include at least one semiconductor structure formed by the manufacturing method described in the above embodiments.

[0028] This disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a substrate; forming a hard mask layer covering the substrate; the hard mask layer comprising a first mask layer and a second mask layer stacked together; etching the substrate using the hard mask layer to form a patterned substrate; and grinding and removing the hard mask layer; wherein the grinding rate of the first mask layer is different from that of the second mask layer. In this disclosure, because the grinding rate of the first mask layer and the second mask layer in the hard mask are different, the grinding rate increases when the second mask layer is removed and grinding reaches the first mask layer during the CMP process to remove the hard mask layer. This allows the CMP process to remove more of the hard mask layer as the grinding rate drops to zero after the polishing slurry contacts the substrate, effectively reducing the residual hard mask layer on the substrate surface and minimizing the impact of the residual hard mask layer on subsequent processes. Attached Figure Description

[0029] Figures 1A to 1B A step diagram illustrating a method for fabricating a semiconductor structure as an example;

[0030] Figure 2 This is a schematic diagram illustrating the change of grinding rate over time in a CMP process in an example.

[0031] Figure 3 A flowchart illustrating a method for fabricating a semiconductor structure according to embodiments of this disclosure;

[0032] Figures 4A to 4B A step diagram illustrating the method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0033] Figure 5 This is a schematic diagram illustrating the change of grinding rate over time in the CMP process according to an embodiment of this disclosure;

[0034] Figures 6A to 6B This is a step-by-step diagram of a semiconductor structure fabrication method in a specific example.

[0035] Figures 7A to 7B This is a flowchart illustrating the steps of a semiconductor structure fabrication method in a specific embodiment of this disclosure. Detailed Implementation

[0036] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0037] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0038] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0039] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0040] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0041] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0042] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0043] In the manufacturing process of semiconductor devices, a hard mask layer is often formed on the surface of a substrate and used to pattern the substrate underneath. After the patterning process is complete, this hard mask layer needs to be removed. CMP (Ceramic Polishing) is typically used to remove the hard mask layer from the substrate surface. However, due to the inherent unevenness of the substrate surface and the non-uniformity of the CMP process itself, some areas of the substrate surface are prone to retaining residual hard mask layer. This residual hard mask layer may affect subsequent processes, thereby impacting the performance of the semiconductor device.

[0044] Figures 1A to 1B A step diagram illustrating the fabrication process of a semiconductor structure as an example.

[0045] like Figure 1A As shown, a hard mask layer 102 is formed on the surface of the substrate 101, which can be used to pattern the substrate 101. It should be noted that the hard mask layer 102 is a single-layer structure, and the material of the hard mask layer 102 includes silicon nitride.

[0046] like Figure 1BAs shown, after the patterning process is completed, the hard mask layer 102 located on the surface of the substrate 101 is removed using a CMP process. In a specific example, the CMP process can be performed using a polishing machine. Here, since the polishing rate of the substrate 101 is lower than the polishing rate of the hard mask layer 102, the substrate 101 can serve as a polishing stop layer for the CMP process. That is, during the CMP process, when polishing reaches the surface of the substrate 101, the polishing rate decreases rapidly. At this point, most of the hard mask layer 102 is removed, and the surface of the substrate 101 is exposed. It is understandable that, ideally, the CMP process can completely remove the hard mask layer 102 located on the surface of the substrate 101. However, in actual operation, due to the unevenness of the surface of the substrate 101 and the inherent inhomogeneity of the CMP polishing process, some areas on the surface of the substrate 101 are prone to residual hard mask layer 102, such as... Figure 1B As shown.

[0047] Figure 2 This is a schematic diagram illustrating the change in grinding rate over time in a CMP process, as shown in the example.

[0048] like Figure 2 As shown, the CMP process can be divided into two stages based on the polishing rate. Specifically, the CMP process can be divided into a first stage and a second stage. In the first stage, the hard mask layer is polished until the substrate surface is reached. During this process, the polishing rate is maintained at approximately V1. It can be understood that at the end of the first stage, most of the hard mask layer is removed; however, due to process limitations, a small amount of hard mask layer may still remain on the substrate surface. In the second stage, the remaining hard mask layer is polished. However, since the substrate surface is now exposed, and the substrate polishing rate is much lower than the hard mask layer polishing rate, the polishing rate drops sharply from the initial V1 to 0. It should be noted that during the sharp drop in polishing rate from V1 to 0, the polishing machine still removes a portion of the hard mask layer and simultaneously removes a portion of the substrate. Figure 2 The shaded area represents the amount of hard mask layer removed in the second stage. However, only a small amount of hard mask layer is removed as the polishing rate decreases from V1 to 0. In cases of poor substrate flatness, a significant amount of hard mask layer may still remain on the substrate surface after the CMP process.

[0049] Figure 3 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure. Figure 3 As shown, this disclosure provides a method for manufacturing a semiconductor structure, the method comprising:

[0050] Step S301: Provide a substrate;

[0051] Step S302: Form a hard mask layer covering the substrate; the hard mask layer includes a first mask layer and a second mask layer stacked together;

[0052] Step S303: Use a hard mask layer to etch the substrate to form a patterned substrate;

[0053] Step S304: Grind and remove the hard mask layer; wherein the grinding rate of the first mask layer is different from that of the second mask layer.

[0054] In this embodiment of the disclosure, the substrate includes a semiconductor substrate, such as a wafer. Various circuit or device structures with different functions can be formed in the substrate. In some embodiments, the substrate material may include semiconductor materials, conductive materials, and insulating materials, etc.

[0055] Figures 4A to 4B A step diagram illustrating the method for fabricating a semiconductor structure according to an embodiment of this disclosure.

[0056] like Figure 4A As shown, in some embodiments, forming a hard mask layer 402 covering a substrate 401 includes: depositing a first mask layer 403 on the surface of the substrate 401; and depositing a second mask layer 404 on the surface of the first mask layer 403. The first mask layer 403 and the second mask layer 404 are made of different materials, and their polishing rates are also different. In some embodiments, the material of the first mask layer 403 includes, but is not limited to, silicon oxide, and the material of the second mask layer 404 includes, but is not limited to, silicon nitride. Thus, the hard mask layer 402 formed on the surface of the substrate 401 is a two-layer hard mask layer 402.

[0057] In this embodiment of the disclosure, the deposition process for forming the first mask layer 403 and the second mask layer 404 includes, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0058] In some embodiments, before etching the substrate 401 using the hard mask layer 402 to form a patterned substrate 401, the manufacturing method further includes: etching the first mask layer 403 and the second mask layer 404 using a photomask to form a patterned hard mask layer 402.

[0059] It is understandable that before etching the substrate 401 using the hard mask layer 402, the hard mask layer 402 needs to be patterned. That is, a series of etching processes are required to remove at least a portion of the hard mask layer 402 located on the substrate surface, exposing a portion of the surface of the substrate 401 while the remaining area on the surface of the substrate 401 remains covered by the hard mask layer 402. Thus, in subsequent etching processes, the exposed area of ​​the substrate 401 surface can be etched away, while the area covered by the hard mask layer 402 is retained. In one embodiment, the patterning of the hard mask layer 402 can be achieved using photolithography. Specifically, photoresist can be spin-coated onto the hard mask layer 402, and a photomask can be placed above the photoresist. The photomask, as a pattern master in the photolithography process, is formed by an opaque light-blocking film on a transparent substrate, and is used to transfer the pattern onto the photoresist through exposure. In other words, the photoresist can be patterned using a photomask. Subsequently, patterned photoresist can be used to pattern the hard mask layer 402 in the following etching process to transfer the pattern on the photoresist back onto the hard mask layer 402. It should be noted that in the etching process of the hard mask layer 402, the etching depth is equal to the thickness of the hard mask layer 402. That is, in the etching process of the hard mask layer 402, both the first mask layer 403 and the second mask layer 404 are etched to expose at least a portion of the surface of the substrate 401. In this embodiment, the etching process of the hard mask layer 402 includes, but is not limited to, dry etching.

[0060] In this embodiment of the disclosure, after forming a hard mask layer 402 covering the substrate 401, the substrate 401 can be etched using the hard mask layer 402 to pattern the surface of the substrate 401. In some embodiments, the hard mask layer 402 can be used to etch regions of the substrate 401 that have circuit structures. In other embodiments, the hard mask layer 402 can be used to etch regions of the substrate 401 that do not have circuit structures. In this embodiment of the disclosure, the process of etching the substrate 401 using the hard mask layer 402 includes, but is not limited to, dry etching.

[0061] In this embodiment of the disclosure, after etching the substrate 401 using the hard mask layer 402, the hard mask layer 402 is ground and removed, such as... Figure 4B As shown. Here, the process of grinding and removing the hard mask layer 402 includes a CMP process.

[0062] In this embodiment, the polishing rate of the substrate 401 can be lower than the polishing rate of the hard mask layer 402. Specifically, the polishing rate of the substrate 401 can be lower than the polishing rate of the second mask layer 404 in the hard mask layer 402. Therefore, the substrate 401 can serve as a polishing stop layer in the CMP process. That is, during the CMP process, when polishing reaches the surface of the substrate 401, the polishing rate rapidly decreases to 0. At this point, most of the hard mask layer 402 is removed, and the surface of the substrate 401 is exposed.

[0063] Figure 5 This is a schematic diagram illustrating the change of grinding rate over time in the CMP process according to an embodiment of this disclosure.

[0064] like Figure 5 As shown, since the polishing rates of the first mask layer and the second mask layer are different, and the polishing rate of the substrate is lower than that of the hard mask layer, the entire CMP process can be divided into three stages according to the polishing rate. Specifically, the CMP process can be divided into a first stage, a second stage, and a third stage. In some embodiments, the polishing rate of the first mask layer is greater than that of the second mask layer. Below, the polishing rates of each stage in the CMP process will be specifically explained for the case where the polishing rate of the first mask layer is greater than that of the second mask layer, and the polishing rate of the second mask layer is greater than that of the substrate.

[0065] Specifically, in the first stage, the polishing machine polishes the second mask layer in the hard mask layer until it reaches the surface of the first mask layer. During this process, the polishing rate remains approximately V1. In the second stage, the hard mask layer continues to be polished until the substrate surface is reached. During this process, the polishing machine can polish the first mask layer within the hard mask layer. Here, because the polishing rate of the first mask layer is greater than that of the second mask layer, the polishing rate gradually increases from V1 to V2; that is, the second stage is a polishing acceleration process. It can be understood that at the end of the second stage, most of the first mask layer is removed; however, due to process defects, a small amount of the first mask layer may still remain on the substrate surface. In the third stage, the remaining small amount of the first mask layer continues to be polished. At this point, since the substrate surface has been reached and the substrate polishing rate is much lower than the hard mask layer polishing rate, the polishing rate will drop sharply from V2 to 0. It should be noted that during the process of the polishing rate dropping sharply from V2 to 0, the polishing machine will still remove a portion of the first mask layer and simultaneously remove a portion of the substrate. Figure 5 The shaded area in the image represents the amount of grinding applied to the hard mask layer in the third stage.

[0066] Below, in conjunction with Figures 1A to 5The two schemes described above are compared and explained.

[0067] exist Figure 1A In the example shown, since the material of the hard mask layer 102 includes silicon nitride, the hard mask layer 102 can be approximated as in the embodiments of this disclosure. Figure 4A The second mask layer 404 is shown in the diagram. Combined with... Figure 2 and Figure 5 In this embodiment of the disclosure, since the first mask layer 403 has a higher polishing rate than the second mask layer 404, therefore, compared to Figure 2 The process of the grinding rate decreasing from V1 to 0, Figure 5 As the grinding rate decreases from V2 to 0, the number of grinding revolutions of the grinding disc in the grinder increases, resulting in an increase in the amount of material ground. This increase in the amount of material ground leads to a decrease in the amount of hard mask residue. Therefore, compared to... Figures 1A to 1B In the example scheme described above, the embodiments of this disclosure can more effectively remove the hard mask layer 402 located on the surface of the substrate 401, thereby reducing the risk of residual hard mask layer 402. In other words, the embodiments of this disclosure offer a larger process window for removing the hard mask layer 402. For details, please refer to... Figure 4B , Figure 4B The hard mask layer 402 located on the surface of the substrate 401 is essentially removed.

[0068] It should be noted that since the grinding rate drops sharply after the abrasive contacts the substrate surface, simply extending the grinding time cannot solve the problem of hard mask layer residue. However, the embodiments of this disclosure introduce a grinding acceleration process in the CMP process by setting a first mask layer 403 in the hard mask layer 402, thereby effectively reducing the residue of the hard mask layer 402.

[0069] Continue to refer to Figure 4A In this embodiment, the first mask layer 403 can be used to accelerate grinding in a CMP process. Therefore, the first mask layer 403 needs to have a certain thickness so that the grinding rate can be increased from V1 to V2, which meets the design requirements, in the second stage of the CMP process. In this embodiment, the thickness of the first mask layer 403 can be set according to specific needs. In some embodiments, the thickness of the first mask layer 403 can be less than the thickness of the second mask layer 404. In a specific embodiment, the thickness of the first mask layer 403 includes 30 angstroms to 80 angstroms.

[0070] As can be seen from the above, Figure 1A The hard mask layer 102 in the example has a single-layer structure, which poses a significant risk of residue after the CMP process, and the residual hard mask layer 102 can have a substantial impact on subsequent processes. In contrast, the hard mask layer 402 in this embodiment has a double-layer structure, such as... Figure 4A As shown. The hard mask layer 402 has a low risk of residue after the CMP process, which can effectively reduce the impact of residual hard mask layer 402 on subsequent processes. Below, we analyze the specific impact on subsequent processes for two cases: the use of a single-layer hard mask layer 102 in the example and the use of a double-layer hard mask layer 402 in the embodiments of this disclosure.

[0071] Figures 6A to 6B This is a step diagram illustrating the fabrication process of a semiconductor structure in a specific example.

[0072] like Figure 6A As shown, in one example, substrate 601 is a substrate 601 present during the semiconductor device manufacturing process, in which multiple transistors can be formed and located on the surface of substrate 601. Here, the transistors formed in substrate 601 include FinFETs (Fin Field-Effect Transistors). A hard mask layer 602 is formed on the surface of substrate 601. The hard mask layer 602 corresponds to... Figure 1AThe hard mask layer 602 has a single-layer structure. Here, a Single Diffusion Break (SDB) process is introduced in the transistor formation process to reduce the area of ​​the semiconductor device and improve its performance. Specifically, the SDB process includes: defining a photoresist pattern by photolithography; etching the hard mask layer 602 using patterned photoresist to pattern the hard mask layer 602, at which time a portion of the surface of the dummy gate 603 located within the substrate 601 and on the substrate surface is exposed. It should be noted that the dummy gate 603 is divided into multiple portions in a direction parallel to the surface of the substrate 601. In one example, the multiple portions include at least a first portion and a second portion. The first portion is different from the second portion, and the first portion and the second portion do not overlap. Here, the exposed portion of the dummy gate 603 can be the dummy gate 603 of the first portion; therefore, the dummy gate 603 of the first portion can be removed in a subsequent etching process, while the dummy gate 603 of the second portion will not be removed. It should be noted that while removing the exposed portion of the dummy gate 603 using the etching process, a portion of the substrate 601 below the first portion of the dummy gate 603 is also removed. Specifically, the portion of the buried fin 604 located below the first portion of the dummy gate 603 is removed. Thus, a recessed region with a depth greater than the dummy gate 603 is formed in the substrate 601 at the location corresponding to the first portion of the dummy gate 603. Furthermore, in subsequent processes, dielectric material can be filled into this recessed region to form an SDB isolation structure 605, which is used to isolate two adjacent fin field-effect transistors. In other words, the patterned hard mask layer 602 at this time serves as the hard mask layer for forming the SDB isolation structure 605.

[0073] like Figure 6BAs shown, after etching a portion of the dummy gate 603 using a hard mask layer 602 to form an SDB isolation structure 605, a CMP process is used to remove the hard mask layer 602 and a portion of the SDB isolation structure 605, so that the surface of the SDB isolation structure 605 is flush with the surface of the substrate 601. It should be noted that, firstly, the surface of the substrate 601 has a certain degree of unevenness. Secondly, the density of the SDB isolation structure 605 varies in different regions of the substrate, and this difference in density corresponds to a difference in the polishing rate of the hard mask layer 602 during the CMP process. Specifically, the higher the density of the SDB isolation structure 605 in a region, the higher the polishing rate of the hard mask layer 602. Conversely, the lower the density of the SDB isolation structure 605 in a region, the lower the polishing rate of the hard mask layer 602. Therefore, after the CMP process, a portion of the hard mask layer 602 will remain on the surface of regions with lower SDB isolation structure 605 density in the substrate 601. Here, the region with higher density of the SDB isolation structure 605 corresponds to the region where the first part of the dummy gate 603 is located, and the region with lower density of the SDB isolation structure 605 corresponds to the region where the second part of the dummy gate 603 is located. Thus, after the CMP process, a hard mask layer 602 residue is easily formed on the surface of the second part of the dummy gate 603, such as... Figure 6B As shown. In a specific example, the region where the second portion of the dummy gate 603 is located is the region in the substrate 601 used to form SRAM. This region has a low density of SDB isolation structures 605, therefore, the hard mask layer 602 located above this region is easily left behind after the CMP process. It should be noted that the second portion of the dummy gate 603 in the substrate 601 needs to be completely removed in the subsequent gate replacement process of CMP to form a metal gate, thereby forming a transistor structure.

[0074] However, the hard mask layer 602 remaining on the surface of the substrate 601 may cover the surface of the dummy gate 603 in the second part, thereby affecting the removal of the dummy gate 603 and consequently affecting the height of the subsequently formed metal gate. In other words, the hard mask layer 602 remaining on the surface of the substrate 601 may lead to incomplete removal of the dummy gate 603, resulting in abnormalities in the subsequently formed metal gate.

[0075] Here, since the residue of the hard mask layer 602 can affect subsequent processes, in another example, the hard mask layer can be completely removed by over-grinding the substrate. However, using this method leads to a reduction in the height of the dummy gate, which is detrimental to the control of the height of the subsequently formed metal gate. In view of this, embodiments of the present disclosure use a hard mask layer with a two-layer structure to pattern the substrate to reduce the impact on the height of the dummy gate in the gate replacement process.

[0076] Figures 7A to 7B This is a flowchart illustrating the steps of a semiconductor structure fabrication method in a specific embodiment of this disclosure.

[0077] like Figure 7A As shown, in some embodiments, the substrate 701 includes a dummy gate 705, the top of which is flush with the surface of the substrate 701. The structure of the substrate 701 can be referenced. Figure 6A This will not be elaborated upon here. A hard mask layer 702 is formed on the surface of the substrate 701. The hard mask layer 702 includes a first mask layer 703 and a second mask layer 704 located on the first mask layer 703. The hard mask layer 702 can be a patterned hard mask layer 702. That is, the hard mask layer 702 corresponds to... Figure 4A The hard mask layer 402 in the middle has a double-layer structure. It should be noted that, compared with... Figure 6A Similarly, Figure 7A The SDB process was also introduced in this paper, and the following is a brief explanation of the SDB process.

[0078] Figure 7A In this structure, the dummy gate 705 is divided into multiple portions in a direction parallel to the surface of the substrate 701. In one example, the multiple portions include at least a first portion and a second portion. The first portion is distinct from the second portion, and the first and second portions do not overlap. During the formation of the SDB isolation structure 706, the dummy gate 705 of the first portion is etched away using a patterned hard mask layer 702, while the dummy gate 705 of the second portion is not removed. Thus, a recessed region can be formed in the substrate 701 at the location corresponding to the dummy gate 705 of the first portion, and this recessed region can extend to the buried fin 707 in the substrate 701. A description of the structure of the recessed region can be found here. Figure 6A Subsequently, dielectric material can be filled in the recessed region to form an SDB isolation structure 706, which is used to isolate two adjacent fin field-effect transistors. That is, the patterned hard mask layer 702 serves as the hard mask layer for forming the SDB isolation structure 706. In other words, the location of the dummy gate 705 in the first portion is used to form the single-diffusion cutoff structure SDB isolation structure 706. In some embodiments, the dielectric material forming the SDB isolation structure 706 includes silicon nitride and oxide, wherein the oxide includes porous silicon oxide. In some embodiments, the SDB isolation structure 706 can be formed in the aforementioned recessed region using an ALD process.

[0079] In some embodiments, the dummy gate 705 is made of polycrystalline silicon.

[0080] like Figure 7BAs shown, after etching the dummy gate 705 using the hard mask layer 702 to form the SDB isolation structure 706, the hard mask layer 702 and part of the SDB isolation structure 706 are removed using a CMP process, so that the surface of the SDB isolation structure 706 is flush with the surface of the substrate 701. As can be seen from the above, since the polishing rate of the first mask layer 703 is greater than that of the second mask layer 704, there is a polishing acceleration phase during the polishing process. Therefore, after the CMP process is completed, the areas containing the first and second parts of the dummy gate 705 are unlikely to have any residue of the hard mask layer 702, resulting in virtually no residue of the hard mask layer 702 on the surface of the substrate 701. Thus, the surface of the second part of the dummy gate 705 is not covered by the hard mask layer 702, and the height of the subsequently formed metal gate is not affected by the residue of the dummy gate 705.

[0081] In some embodiments, after grinding and removing the hard mask layer 702, the method of manufacturing the semiconductor structure further includes: replacing the dummy gate 705 of the second portion with a gate to form a gate, which may be a metal gate.

[0082] As can be seen from the above, since the hard mask layer 702 on the surface of the substrate 701 is basically removed after the CMP process, the second part of the dummy gate 705 can be completely removed in the subsequent process, thereby effectively reducing the impact of the hard mask layer 702 residue on the subsequent gate replacement process, which is beneficial to the height control of the metal gate.

[0083] In some embodiments, the process of removing the second portion of the dummy gate 705 in the gate replacement process includes, but is not limited to, dry etching or wet etching.

[0084] It should be noted that the embodiments disclosed herein only specifically illustrate the optimization of the SDB process by a hard mask layer with a dual-layer structure. However, the application scenarios of the hard mask layer with a dual-layer structure in the embodiments of this disclosure are not limited to the SDB process. It is understood that in other embodiments, other semiconductor structures may also suffer from incomplete hard mask layer removal after the CMP process. Therefore, during the manufacturing process of this semiconductor structure, the use of the hard mask layer with a dual-layer structure can reduce the hard mask layer residue after the CMP process, thereby optimizing subsequent processes.

[0085] This disclosure provides a semiconductor device, the semiconductor device comprising:

[0086] At least one semiconductor structure formed by the manufacturing method described in the above embodiments.

[0087] This disclosure provides an electronic device, which includes a memory and / or a processor; wherein the memory and / or processor includes at least one semiconductor structure formed by the manufacturing method described in the above embodiments.

[0088] In this embodiment of the disclosure, the memory includes ferromagnetic random access memory (FRAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, magnetic surface memory, optical disc, or compact disc read-only memory (CD-ROM), etc.

[0089] In this disclosure, the processor can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processors include, but are not limited to, central processing units (CPUs), graphics processing units (GPUs), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, digital signal processors (DSPs), and any suitable processor, controller, microcontroller, etc.

[0090] This disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a substrate; forming a hard mask layer covering the substrate; the hard mask layer comprising a first mask layer and a second mask layer stacked together; etching the substrate using the hard mask layer to form a patterned substrate; and grinding and removing the hard mask layer; wherein the grinding rate of the first mask layer is different from that of the second mask layer. In this disclosure, because the grinding rate of the first mask layer is different from that of the second mask layer, the grinding rate increases when the second mask layer is removed and the grinding reaches the first mask layer during the CMP process for removing the hard mask layer. This allows for the removal of more hard mask layers during the grinding process, as the grinding rate drops to zero after the polishing slurry contacts the substrate, effectively reducing the residual hard mask layer on the substrate surface and minimizing the impact of the residual hard mask layer on subsequent processes.

[0091] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0092] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: Provide a base; Form a hard mask layer covering the substrate; The hard mask layer includes a first mask layer and a second mask layer stacked together; The substrate is etched using the hard mask layer to form a patterned substrate; The hard mask layer is ground and removed; wherein the grinding rate of the first mask layer is different from the grinding rate of the second mask layer.

2. The manufacturing method according to claim 1, characterized in that, The formation of the hard mask layer covering the substrate includes: The first mask layer is deposited on the surface of the substrate; The second mask layer is deposited on the surface of the first mask layer.

3. The manufacturing method according to claim 1, characterized in that, Before etching the substrate using the hard mask layer to form a patterned substrate, the manufacturing method further includes: The first mask layer and the second mask layer are etched using a photomask to form the patterned hard mask layer.

4. The manufacturing method according to claim 1, characterized in that, The substrate includes a dummy gate, the top of which is flush with the surface of the substrate; the etching of the substrate using the hard mask layer to form a patterned substrate includes: The dummy gate in the first portion is removed by etching using the hard mask layer; wherein the location of the dummy gate in the first portion is used to form a single diffusion region cut-off structure.

5. The manufacturing method according to claim 4, characterized in that, After grinding and removing the hard mask layer, the manufacturing method further includes: The dummy gate in the second part is replaced with a gate to form a gate; the second part is different from the first part.

6. The manufacturing method according to any one of claims 1 to 5, characterized in that, The polishing rate of the first mask layer is greater than the polishing rate of the second mask layer; The grinding rate of the substrate is less than the grinding rate of the second mask layer.

7. The manufacturing method according to any one of claims 1 to 5, characterized in that, The material of the first mask layer includes silicon oxide, and the material of the second mask layer includes silicon nitride.

8. The manufacturing method according to claim 1, characterized in that, The thickness of the first mask layer is less than the thickness of the second mask layer.

9. A semiconductor device, characterized in that, The semiconductor device includes: At least one semiconductor structure formed by the manufacturing method according to any one of claims 1 to 8.

10. An electronic device, characterized in that, The electronic device includes: Memory and / or processor; The memory and / or processor include at least one semiconductor structure formed by the manufacturing method according to any one of claims 1 to 8.

Images