Manufacturing method of semiconductor structure and semiconductor structure
By designing a large aperture at the top of the through-silicon via (TSV) to form a cap structure, the problem of void corrosion after tungsten metal filling was solved, thus achieving the stability and reliability of the semiconductor structure.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI INTEGRATED CIRCUIT EQUIPMENT & MATERIALS INDUSTRY INNOVATION CENTER CO LTD
- Filing Date
- 2024-11-14
- Publication Date
- 2026-05-15
AI Technical Summary
In existing technologies, the Via middle scheme, under a high aspect ratio design, is prone to premature sealing at the top of the TSV after tungsten metal filling, forming voids, which leads to HF corrosion of the metal interconnect layer and interlayer open circuit phenomenon.
The through-silicon via (TSV) design features a larger aperture at the top than the rest, forming a cap structure to prevent the escape of corrosive gases. By filling the TSV with metallic material, voids are prevented from corroding the metal interconnect layer.
It effectively prevents corrosive gases from escaping from the cavities, avoids open circuits between layers, and improves the reliability and stability of the semiconductor structure.
Smart Images
Figure CN122054983A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure. Background Technology
[0002] In the semiconductor technology field, the response speed of IC circuits is related to the connection distance between devices on the chip. For the signal to be transmitted, the shorter the link distance, the faster the circuit device operates. Since the vertical distance between adjacent layers can be much smaller than the width of a single-layer chip, IC circuits with three-dimensional structures can shorten the connection distance between devices on the chip. Therefore, when designing chips with vertical packaging structures in 3D IC solutions, their operating speed can be improved. To integrate different devices into a single stacked chip structure, dies need to be interconnected to electrically connect devices on each layer. Through-Silicon Vias (TSVs) are one of the new semiconductor technologies developed for this purpose. By producing devices that meet the market trend of "light, thin, short, and small" through 3D stacking technology, TSV technology also provides wafer-level packaging for microelectromechanical systems (MEMS), optoelectronics, and electronic devices. After manufacturing TSVs, wafers or dies are stacked together so that their conductive paths are interconnected to provide electrical connections between wafers or dies, thus obtaining a 3D stacked IC structure. However, as TSV requirements become more stringent, the challenges encountered in integrating TSV processes with different devices also increase. Currently, the mainstream TSV technologies include the Via-middle and Via-last solutions. The former completes the TSV process after the transistor fabrication process but before the copper interconnects, while the latter completes the TSV process after the copper interconnects. Because the Via-last solution needs to penetrate through the copper and metal interconnect layers, it requires a large amount of clearance area, which greatly increases the chip area. Therefore, the Via-middle solution is currently the better TSV solution.
[0003] The existing Via-middle approach involves performing the TSV process after the front-end transistor fabrication and contact (CT) vias are completed. In high aspect ratio designs, traditional copper filler is insufficient, necessitating the use of tungsten chemical vapor deposition (CVD). However, because tungsten filling is achieved through the reduction reaction of WF6 with H2, the rapid reaction rate at the top leads to premature sealing at the top of the TSV, resulting in HF-filled voids within. Subsequently, during the high-temperature back-end copper interconnect process, the HF within these voids can easily escape and corrode the interconnect layers, causing open circuits between layers. Summary of the Invention
[0004] The purpose of this invention is to provide a method for manufacturing a semiconductor structure and a semiconductor structure in order to solve one or more problems in the prior art.
[0005] To solve the above-mentioned technical problems, the present invention provides a method for manufacturing a semiconductor structure, comprising:
[0006] Provide a substrate, and form an interlayer dielectric layer on the substrate;
[0007] The interlayer dielectric layer and the substrate are etched to form a through-silicon via (TSV), wherein the diameter of the top portion of the TSV is larger than the diameter of the remaining portion.
[0008] The through-silicon via is filled with a metallic material; and,
[0009] A metal interconnect layer is formed on the interlayer dielectric layer.
[0010] Optionally, in the semiconductor structure manufacturing method, the substrate is a substrate that has completed the front-end transistor fabrication process;
[0011] The manufacturing method further includes:
[0012] Etching the substrate to form contact holes; and,
[0013] The contact hole is filled with metallic material.
[0014] Optionally, in the semiconductor structure manufacturing method, before the step of forming the contact hole is performed, an initial through-silicon via (TSV) with the same aperture is first formed, and then, when forming the contact hole, the top portion of the initial TSV is simultaneously etched to obtain the TSV.
[0015] Optionally, in the method for manufacturing the semiconductor structure, the method for forming the contact hole and the through-silicon via includes:
[0016] A patterned hard mask layer is formed on the interlayer dielectric layer. The patterned hard mask layer defines a contact hole pattern and a through-silicon via (TSV) pattern. The TSV pattern is located above the initial TSV, and the diameter of the TSV pattern is larger than the aperture of the initial TSV.
[0017] The interlayer dielectric layer is etched using the patterned hard mask layer as a mask to form contact holes within the interlayer dielectric layer, and to form through-silicon vias within the interlayer dielectric layer with the top portion having a larger aperture than the rest.
[0018] Optionally, in the semiconductor structure manufacturing method, the material of the hard mask layer includes amorphous carbon, spin-coated carbon, or silicon oxynitride.
[0019] Optionally, in the semiconductor structure manufacturing method, the distance between the top portion of the through-silicon via and the adjacent contact hole is 0.1 μm to 1.0 μm.
[0020] Optionally, in the semiconductor structure manufacturing method, the diameter of the top portion of the through-silicon via is D1, and the value of D1 ranges from 200nm to 500nm; the diameter of the contact hole is D2, and the value of D2 ranges from 50nm to 100nm.
[0021] Optionally, in the method for manufacturing the semiconductor structure, before filling the contact holes and the through-silicon vias with metal material, the method further includes:
[0022] An adhesive layer and a barrier layer are deposited on the bottom and sidewalls of the contact hole and the through-silicon via, the barrier layer covering the adhesive layer.
[0023] Optionally, in the semiconductor structure manufacturing method, the depth of the top portion of the through-silicon via is 80 nm to 150 nm.
[0024] The present invention also provides a semiconductor structure, which is manufactured using the manufacturing method described in any of the preceding claims.
[0025] In summary, this invention provides a method for manufacturing a semiconductor structure and a semiconductor structure, comprising: providing a substrate and forming an interlayer dielectric layer on the substrate, the interlayer dielectric layer covering the substrate; etching the interlayer dielectric layer and the substrate to form a through-silicon via (TSV), wherein the diameter of the top portion of the TSV is larger than the diameter of the remaining portion; filling the TSV with a metal material; and forming a metal interconnect layer on the interlayer dielectric layer. In the manufacturing method provided by this invention, the TSV adopts a design where the diameter is wider at the top and narrower at the bottom. Thus, after filling the TSV with metal material, a cap structure is formed at the top portion. This cap structure can prevent corrosive gases in the internal cavity from escaping and corroding the metal interconnect layer, thereby avoiding interlayer open circuits. Attached Figure Description
[0026] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor structure provided in an embodiment of the present invention;
[0027] Figures 2-7 for Figure 1 Schematic diagrams of the device structures corresponding to each step in the process;
[0028] The labels in the attached figures are explained as follows:
[0029] 11-Substrate; 12-Interlayer dielectric layer; 13-Through silicon via; 13'-Initial through silicon via; 14-Insulating dielectric layer; 131-Top portion; 132-Remaining portion; 15-Hard mask layer; 16-Contact hole; 17-Metallic material; 18-Metallic interconnect layer. Detailed Implementation
[0030] To make the objectives, advantages, and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different proportions are sometimes used in the drawings to show different emphases. It should be understood that relative terms such as "above," "below," "top," "bottom," and "over" shown in the drawings can be used to describe the relationships between various elements. These relative terms are intended to cover different orientations of elements other than those depicted in the drawings. For example, if the device is inverted relative to the view in the drawings, an element described, for example, as being "above" another element would now be below that element.
[0031] Please see Figure 1 This invention provides a method for manufacturing a semiconductor structure, comprising:
[0032] S1, providing a substrate and forming an interlayer dielectric layer on the substrate;
[0033] S2, Etching the interlayer dielectric layer and the substrate to form a through-silicon via (TSV), wherein the diameter of the top portion of the TSV is larger than the diameter of the remaining portion;
[0034] S3, fill the through-silicon via with metallic material;
[0035] S4, a metal interconnect layer is formed on the interlayer dielectric layer.
[0036] The manufacturing method provided in this embodiment of the invention uses a through-silicon via (TSV) with a wider top and narrower bottom. When the TSV is filled with metal material, it is equivalent to forming a cap structure at the top. This cap structure can prevent corrosive gases in the internal cavity from escaping and corroding the metal interconnect layer, thus avoiding interlayer open circuits.
[0037] The following is in conjunction with the appendix Figures 2-7 The steps described above will be further described.
[0038] First, please see Figure 2 Step S1 is performed, a substrate 11 is provided, and an interlayer dielectric layer 12 is formed on the substrate 11.
[0039] The substrate 11 may be a substrate that has completed the front-end transistor fabrication process. For example, the substrate 11 may have an active region and a drain region formed by ion implantation, and a gate structure may be formed on the substrate 11, with the source region and the drain region located on both sides of the gate structure. The materials of the substrate 11 and the interlayer dielectric layer 12 may be suitable materials well known in the art, and will not be described in detail here.
[0040] Next, perform step S2, please refer to [link / reference]. Figure 5 The interlayer dielectric layer 12 and the substrate 11 are etched to form a through-silicon via 13, wherein the diameter of the top portion 131 of the through-silicon via 13 is larger than the diameter of the remaining portion 132.
[0041] Since the substrate 11 can be a substrate that has completed the front-end transistor manufacturing process as described in step S1, the manufacturing method provided in this embodiment further includes the following step: etching the substrate 11 to form contact holes 16.
[0042] Preferably, the through-silicon via 13 is initially formed before the contact hole 16 is formed, and then the final through-silicon via 13 is formed simultaneously during the formation of the contact hole 16. Specifically, before the step of forming the contact hole 16 is performed, an initial through-silicon via 13' with the same aperture is formed first. Then, during the formation of the contact hole 16, the top portion 131 of the initial through-silicon via 13' is simultaneously etched to obtain the through-silicon via 13. At this time, the aperture of the bottom portion of the through-silicon via 13 is larger than the aperture of the rest of the through-silicon via 13. That is, by etching the initial through-silicon via 13' simultaneously with the etching of the contact hole 16, the top aperture of the finally formed through-silicon via 13 is enlarged.
[0043] Since the diameter of a typical contact hole 16 is much smaller than that of the through-silicon via 13, by adjusting the etching conditions, the contact hole 16 region can be fully opened and the through-silicon via 13 region can be partially opened. That is, the contact hole 16 penetrates the interlayer dielectric layer 12, while the enlarged portion of the top diameter of the through-silicon via 13 does not penetrate the interlayer dielectric layer 12.
[0044] Please see Figure 4 and Figure 5 The apertures of the through-silicon via 13 and the contact hole 16 can be defined by a patterned hard mask layer 15. Specifically, after forming the initial through-silicon via 13', the contact hole 16 and the through-silicon via 13 can be formed by the following steps:
[0045] S21, a hard mask layer 15 is formed on the interlayer dielectric layer 12, and then a photolithography process is performed on the hard mask layer 15 to obtain a patterned hard mask layer 15. The patterned hard mask layer 15 defines a contact hole pattern and a through-silicon via (TSV) pattern. The TSV pattern is located above the initial TSV 13', and the diameter of the TSV pattern is larger than the aperture of the initial TSV 13'. Preferably, both the contact hole pattern and the TSV pattern are circular.
[0046] S22, using the patterned hard mask layer 15 as a mask, the interlayer dielectric layer 12 is etched to form a contact hole 16 in the interlayer dielectric layer 12, and a through-silicon via 13 is formed in the interlayer dielectric layer 12 with the top portion 131 having a larger aperture than the remaining portion 132.
[0047] In this embodiment, the diameter of the top portion 131 of the through-silicon via 13 is D1, and the diameter of the contact hole 16 is D2. The value range of D1 is 200nm to 500nm, and the value range of D2 is 50nm to 100nm.
[0048] Additionally, as described in step S1, the aperture of the top portion 131 of the through-silicon via 13 is larger than the aperture of the remaining portion 132, so that the top portion 131 of the through-silicon via 13 can form a cap structure. However, if the distance between the through-silicon via 13 and the contact hole 16 is too close, it will affect the device performance. Therefore, when defining the aperture of the top portion 131 of the through-silicon via 13, it is preferable to design the distance between the top portion 131 of the through-silicon via 13 and the adjacent contact hole 16 to be 0.1 μm to 1.0 μm. Furthermore, in order to ensure the protective function of the cap structure, it is preferable to design the depth of the top portion 131 of the through-silicon via 13 to be 80 nm to 150 nm.
[0049] In this embodiment, the hard mask layer 15 can be made of amorphous carbon. Due to the poor step coverage of amorphous carbon, when the silicon via size is small, the amorphous carbon will be deposited conformally on the top of the silicon via, thus sealing it in advance. In other embodiments, the hard mask layer 15 can also be made of spin-on carbon (SOC) or silicon oxynitride (SiON), etc.
[0050] Please see Figure 3 Before forming the patterned hard mask layer 15, the manufacturing method of this embodiment may further include:
[0051] An insulating dielectric layer 14 is deposited on the bottom and sidewalls of the initial silicon via 13', and the insulating dielectric layer 14 extends to cover the surface of the silicon substrate 11. The material of the insulating dielectric layer 14 may be silicon oxide, silicon nitride, etc.
[0052] Next, please see Figure 6 Then, step S3 is performed, filling the through-silicon via 13 with metal material 17. Preferably, this step can also be performed simultaneously by filling the contact hole 16 with metal material 17. That is, the steps of filling the through-silicon via 13 and the contact hole 6 with metal material 17 are performed concurrently, thus saving process steps and reducing process costs.
[0053] The metal material 17 is generally tungsten, generated by the reduction reaction of WF6 and H2. This reaction is faster above the contact hole, so it is easy to seal it in advance and form a void. The void will be filled with HF generated by the reduction reaction of WF6 and H2. In this embodiment, since the diameter of the top part 131 of the through-silicon via 13 is larger than the diameter of the rest part 132, it is not easy to seal the wide opening in advance. Therefore, the void will be formed below the top part 131 of the through-silicon via 13. The metal material 17 filled in the top part 131 of the through-silicon via 13 constitutes a cap structure, which plays a role in preventing HF from escaping from the void below.
[0054] Before filling the contact hole 16 and the through-silicon via 13 with metal material 17, the manufacturing method provided in this embodiment of the invention may further include: depositing an adhesive layer (not shown) and a barrier layer (not shown) on the bottom wall and sidewall of the contact hole 16 and the through-silicon via 13, wherein the barrier layer covers the adhesive layer. The material of the adhesive layer may be titanium (Ti), and the material of the barrier layer may be titanium nitride (TiN).
[0055] Finally, please see Figure 7 Step S4 is performed to form a metal interconnect layer 18 on the interlayer dielectric layer 12.
[0056] After the contact hole 16 and the through silicon via 13 are filled with metal material 17, the contact hole 16 structure and the through silicon via 13 structure are formed respectively. Both the contact hole 16 structure and the through silicon via 13 structure are in electrical contact with the metal interconnect layer 18.
[0057] Preferably, before forming the metal interconnect layer 18 on the interlayer dielectric layer 12, the manufacturing method provided in this embodiment of the invention further includes: performing chemical mechanical polishing to remove the metal material 17 from the surface of the interlayer dielectric layer 12.
[0058] Furthermore, this embodiment of the invention also provides a semiconductor structure obtained using the manufacturing method described in this embodiment. Therefore, the semiconductor structure provided by this embodiment does not exhibit interlayer open circuits caused by HF escaping from voids and corroding the metal interconnect layer.
[0059] In summary, this invention provides a method for manufacturing a semiconductor structure and a semiconductor structure, comprising: providing a substrate and forming an interlayer dielectric layer on the substrate, the interlayer dielectric layer covering the substrate; etching the interlayer dielectric layer and the substrate to form a through-silicon via (TSV), wherein the diameter of the top portion of the TSV is larger than the diameter of the remaining portion; filling the TSV with a metal material; and forming a metal interconnect layer on the interlayer dielectric layer. In the manufacturing method provided by this invention, the TSV adopts a design where the diameter is wider at the top and narrower at the bottom. Thus, after filling the TSV with metal material, a cap structure is formed at the top portion. This cap structure can prevent corrosive gases in the internal cavity from escaping and corroding the metal interconnect layer, thereby avoiding interlayer open circuits.
[0060] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments with equivalent changes, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that, include: Provide a substrate, and form an interlayer dielectric layer on the substrate; The interlayer dielectric layer and the substrate are etched to form a through-silicon via (TSV), wherein the diameter of the top portion of the TSV is larger than the diameter of the remaining portion. The through-silicon via is filled with a metallic material; and, A metal interconnect layer is formed on the interlayer dielectric layer.
2. The method for manufacturing a semiconductor structure as described in claim 1, characterized in that, The substrate is a substrate that has completed the front-end transistor manufacturing process; The manufacturing method further includes: The substrate is etched to form contact holes; as well as, The contact hole is filled with metallic material.
3. The method for manufacturing a semiconductor structure as described in claim 2, characterized in that, Before the step of forming the contact hole is performed, an initial through-silicon via (TSV) with the same aperture is first formed. Then, when forming the contact hole, the top portion of the initial TSV is simultaneously etched to obtain the TSV.
4. The method for manufacturing a semiconductor structure as described in claim 3, characterized in that, The method for forming the contact hole and the through silicon via includes: A patterned hard mask layer is formed on the interlayer dielectric layer. The patterned hard mask layer defines a contact hole pattern and a through-silicon via (TSV) pattern. The TSV pattern is located above the initial TSV, and the diameter of the TSV pattern is larger than the aperture of the initial TSV. The interlayer dielectric layer is etched using the patterned hard mask layer as a mask to form contact holes within the interlayer dielectric layer, and to form through-silicon vias within the interlayer dielectric layer with the top portion having a larger aperture than the rest.
5. The method for manufacturing a semiconductor structure as described in claim 4, characterized in that, The material of the hard mask layer includes amorphous carbon, spin-coated carbon, or silicon oxynitride.
6. The method for manufacturing a semiconductor structure as described in claim 2, characterized in that, The distance between the top portion of the through-silicon via and the adjacent contact hole is 0.1 μm to 1.0 μm.
7. The method for manufacturing a semiconductor structure as described in claim 2, characterized in that, The diameter of the top portion of the through-silicon via is D1, with a value ranging from 200nm to 500nm. The diameter of the contact hole is D2, with a value ranging from 50nm to 100nm.
8. The method for manufacturing a semiconductor structure as described in claim 2, characterized in that, Before filling the contact hole and the through-silicon via with metallic material, the method further includes: An adhesive layer and a barrier layer are deposited on the bottom and sidewalls of the contact hole and the through-silicon via, the barrier layer covering the adhesive layer.
9. The method for manufacturing a semiconductor structure as described in claim 1, characterized in that, The depth of the top portion of the through-silicon via is 80nm to 150nm.
10. A semiconductor structure, characterized in that, The semiconductor structure is manufactured using the manufacturing method described in any one of claims 1 to 9.