Photonic integrated circuit and optoelectronic system

Abstract

The present invention relates to a photonic integrated circuit and an optoelectronic system, the photonic integrated circuit (1) comprising a bond pad (19), a radio frequency component (20), a first stack (4) having a doped epitaxial semiconductor layer (5), a second stack (8) associated with the first stack, and a first set of extended traces (18a, 18b) of electrically conductive material, the first stack (4) having a doped epitaxial semiconductor layer (5), the second stack (8) being connected to the first stack (4), and the first set of extended traces (18a, 18b) being connected to the radio frequency component (20). A first set of extension traces (18a, 18b) of conductive material is associated with the second stack, and the first set of extension traces (18a, 18b) of conductive material can carry radio frequency signals between the bond pad and the radio frequency component when the photonic integrated circuit is in use. The second stack comprises an electrically grounded shield (12) sandwiched between the first dielectric layer (9) and the second dielectric layer (15). In use of a photonic integrated circuit, an electrically grounded shield minimizes or prevents overlap between an electric field caused by the radio frequency signal and the doped epitaxial semiconductor layer.

Description

Technical Field

[0001] This invention relates to a photonic integrated circuit. It also relates to an optoelectronic system comprising the photonic integrated circuit according to the invention. The optoelectronic system according to the invention can, for example but not exclusively, be used in telecommunications applications, optical detection and ranging (LIDAR), or sensor applications. Background Technology

[0002] The ongoing development of new and improved optoelectronic systems (which can be used, for example but not exclusively, in telecommunications applications, optical detection and ranging (LIDAR) or sensor applications) is primarily driven by two factors: on the one hand, optimizing module bandwidth (bit rate) to meet market demands, and on the other hand, increasing the complexity of photonic chips to reduce costs and utilize smaller module form factors. Consequently, interesting challenges arise in designing the required radio frequency (RF) photonic integrated circuits and associated optoelectronic systems. For example, in the case of a typical traveling-wave modulator system, simply designing the RF modulator, drive electronics, and RF terminals is insufficient. It is equally important to carefully consider the impedance of the extended metal traces used as on-chip electrical interconnects or feeders to maximize the performance of the traveling-wave modulator system as a whole. Failure to do so will result in electrical reflections and losses, which prevent the achievement of the desired maximum performance of the traveling-wave modulator system as a whole.

[0003] In photonic integrated circuits, on-chip electrical interconnects or feeds are typically configured as extended metal traces arranged along the surface of the photonic integrated circuit. These extended metal traces interconnect bonding pads and radio frequency (RF) components. Unlike off-chip electrical interconnects, which are typically designed for low-loss printed circuit boards, on-chip electrical interconnects or feeds must be designed to account for the negative impact of the doped semiconductor layer beneath the on-chip electrical interconnect on RF signals, which are carried by the on-chip electrical interconnect in the case of photonic integrated circuits. Therefore, on-chip electrical interconnects or feeds for high-bandwidth photonic integrated circuits preferably have the shortest possible length to reduce electrical insertion loss.

[0004] While this design approach can be successful for photonic integrated circuits with simple layouts, it is not feasible for photonic integrated circuits with increasingly complex layouts. For example, in photonic integrated circuits with more complex designs, limitations regarding the permissible location of electrical interfaces around the photonic integrated circuit relative to the RF components that need to be electrically connected to said interfaces may necessitate implementing on-chip electrical interconnects or feeds as extended metal traces. Furthermore, optical routing constraints may require on-chip electrical interconnects or feeds to cross on-chip optical waveguides. This can lead to increased losses of the RF signals carried by the on-chip electrical interconnects when the photonic integrated circuit is used.

[0005] Typical approaches to reducing the aforementioned problems associated with the design of on-chip electrical interconnects or feeders for photonic integrated circuits with increasingly complex layouts include the deposition of thick electrically insulating polymer layers, the removal of doped semiconductor layers, and the application of air bridges.

[0006] Depositing a thick, electrically insulating polymer layer with a low dielectric constant between the on-chip electrical interconnects or feedlines of photonic integrated circuits and the underlying doped semiconductor layer can reduce insertion loss. However, a drawback of this approach is the limited number of suitable polymers that can withstand semiconductor manufacturing processes (e.g., dry etching, wet etching, temperature ranges, etc.). Therefore, the range of suitable dielectric constants is limited. Another drawback is that extremely thick polymer layers increase the topology that on-chip electrical interconnects or feedlines must traverse to establish electrical contacts with the underlying photonic components. Yet another drawback of thick polymer layers is that they can introduce strain into the photonic integrated circuit. These drawbacks pose yield and reliability challenges for photonic integrated circuits and associated optoelectronic systems in which photonic integrated circuits are applied. For longer feed pipelines, the aforementioned drawbacks of applying thick polymer layers become increasingly pronounced, as the negative impacts become more significant as the surface area of ​​the feed pipeline increases.

[0007] The removal of the doped semiconductor layer beneath on-chip electrical interconnects or feeders can be achieved by etching trenches in the doped semiconductor layer, which provide a pathway to the underlying semi-insulating substrate of the photonic integrated circuit. While this method can reduce the aforementioned losses of radio frequency signals carried by the on-chip electrical interconnects when the photonic integrated circuit is used, it introduces manufacturing problems. For example, a disadvantage of this method is that providing large trenches can negatively impact the etching load during processing. Furthermore, providing large trenches can cause photoresist pooling, which negatively affects lithographic resolution. Removal of the doped semiconductor layer cannot be employed in areas of the photonic integrated circuit where on-chip electrical interconnects or feeders need to traverse on-chip optical waveguides.

[0008] To enable on-chip electrical interconnects or feeds to cross on-chip optical waveguides, at least a portion of the on-chip electrical interconnect or feed crossing the on-chip optical waveguide can be arranged as an air bridge, i.e., a suspended conductive structure. A disadvantage associated with air bridges is that their fabrication involves the removal of sacrificial electrical insulation support material, initially positioned beneath at least a portion of the on-chip electrical interconnect that must cross, for example, the on-chip optical waveguide, to obtain the at least partially suspended on-chip electrical interconnect or feed, referred to as an air bridge. Another disadvantage associated with air bridges is that the bridging distance is very short due to the structural limitations of the air bridge. Yet another disadvantage of using air bridges is that they can cause yield and reliability issues, for example, due to breakage of the air bridge during the removal of the sacrificial electrical insulation support material.

[0009] In light of the foregoing, it is clear that each typical approach to mitigating the aforementioned problems associated with the design and implementation of on-chip electrical interconnects or feeds in photonic integrated circuits with increasingly complex layouts is advantageous in specific circumstances and therefore does not provide a so-called universal solution. Furthermore, typical approaches may cause yield and reliability issues in the photonic integrated circuits to which they are applied. Therefore, there is a need to provide a photonic integrated circuit, including structural features that can proactively circumvent or at least reduce the aforementioned and / or other disadvantages associated with the design and implementation of on-chip electrical interconnects or feeds in increasingly complex high-bandwidth photonic integrated circuits. Summary of the Invention

[0010] The object of the present invention is to provide a photonic integrated circuit, including structural features that can preemptively circumvent or at least reduce at least one of the above and / or other disadvantages associated with the design and implementation of on-chip electrical interconnects or feeders in increasingly complex high-bandwidth photonic integrated circuits.

[0011] Another object of the present invention is to provide an optoelectronic system comprising a photonic integrated circuit according to the present invention. The optoelectronic system according to the present invention can, for example but not exclusively, be used in telecommunications applications, LIDAR, or sensor applications.

[0012] Various aspects of the invention are set forth in the appended independent and dependent embodiments. Features from the dependent embodiments may be suitably combined with features from the independent embodiments, and not merely as explicitly stated in the embodiments. Furthermore, all features may be replaced by other technically equivalent features.

[0013] At least one of the above objectives is achieved by a photonic integrated circuit, which includes: - An indium phosphide (InP-based) substrate having a first surface; - A first stack, the first stack including a doped epitaxial semiconductor layer, the first stack configured and arranged to provide optical functionality when used in the photonic integrated circuit, the first stack having: • A second surface, which is associated with the first surface of the indium phosphide substrate; and • A third surface, the third surface being arranged facing away from the second surface; and - A second stack, configured and arranged to provide electrical functionality when the photonic integrated circuit is used, the second stack comprising: • A first dielectric layer, wherein the first dielectric layer has: ○ A fourth surface, which is associated with the third surface of the first stack; and ○ A fifth surface, which is arranged to face away from the fourth surface; • An electrically grounding shield, wherein the electrically grounding shield has: ○ A sixth surface, which is associated with the fifth surface of the first dielectric layer; and ○ A seventh surface, which is arranged to face away from the sixth surface; • A second dielectric layer, the second dielectric layer having: ○ An eighth surface, which is associated with the seventh surface of the electrically grounded shield; and ○ A ninth surface, which is arranged to face away from the eighth surface; - A first set of elongated tracks of conductive material, associated with the ninth surface of the second dielectric layer of the second stack, the first set of elongated tracks of conductive material being configured and arranged to carry radio frequency signals when used in the photonic integrated circuit; and - At least one electrical bonding pad and at least one radio frequency component, wherein at least one of the electrical bonding pads and at least one of the radio frequency components are electrically connected to each other via the first set of extended traces of conductive material; Wherein, the first dielectric layer of the second stack is configured and arranged to provide DC isolation between the electrically grounded shield and the first stack when the photonic integrated circuit is used, and wherein the electrically grounded shield is configured and arranged to minimize or prevent the overlap between the electric field caused by the radio frequency signal and the doped epitaxial semiconductor layer of the first stack when the photonic integrated circuit is used.

[0014] In this way, the photonic integrated circuit according to the invention includes on-chip electrical interconnects or feeders implemented using a shielded on-chip electrical interconnect or feeder scheme. It should be noted that, from the description of the above embodiments of the photonic integrated circuit according to the invention, it is clear that the extended traces in the first set of extended traces of conductive material electrically interconnect at least one bonding pad of the photonic integrated circuit and at least one radio frequency component, and will be interpreted as on-chip electrical interconnects or feeders.

[0015] Shielded on-chip interconnects or feeders are applied to photonic integrated circuits according to the present invention to minimize or prevent overlap between the doped epitaxial semiconductor layer of the photonic integrated circuit and the electric field of the radio frequency signal carried by the on-chip interconnects or feeders when the photonic integrated circuit is used, without the need for at least one of the aforementioned disruptive isolation trenches, thick polymer layers that are difficult to implement, and fragile air bridges. Shielded on-chip interconnects or feeders enable the realization of long (i.e., in the range of 0.5 mm to 5 mm), low-loss on-chip interconnects or feeders with desired impedance for use in photonic integrated circuits with increasingly complex layouts. Long shielded on-chip interconnects or feeders can be routed on photonic components (such as on-chip optical waveguides) without any performance loss. It should be noted that the shielded on-chip electrical interconnects or feeders of the photonic integrated circuit according to the present invention are suitable for use with any kind of radio frequency components, such as Mach-Zehnder modulators (MZMs), electro-absorption modulators (EAMs), and radio frequency photodiodes (RF PDs).

[0016] The conductive material used for the extension traces of the first set of extension traces can be any kind of conductive material with any suitable composition and size, as long as it can carry high-quality radio frequency signals between the bonding pads and radio frequency components of the photonic integrated circuit when used in the photonic integrated circuit. It should be noted that the composition and size of the extension traces of the first set of extension traces of conductive material are determined by the desired impedance and manufacturing process tolerances of the on-chip electrical interconnects or feeders. A practical example is using electroplated gold as the conductive material to fabricate the extension traces of the first set of extension traces. The gold-plated traces of the first set of extension traces can have a first width (W1) of 10 μm and a first thickness (T1) of 3 μm, as seen in a direction parallel to the indium phosphide substrate, to achieve an on-chip electrical interconnect or feeder with a 55-ohm impedance. It should be noted that any other size and composition of the conductive material can be envisioned depending on the specific technical requirements of the photonic integrated circuit. It should be noted that the shielding performance of the electrical grounding shield is not affected by the size and / or composition of the extension traces of the first set of extension traces of conductive material. The electrical grounding shield can have a second thickness (T2), as seen in a direction perpendicular to the indium phosphide substrate. The second thickness (T2) can range from 50 nm to 4 μm. A disadvantage of electrically grounding shields with a second thickness (T2) greater than 4 μm is the potential for topology and / or reliability issues without any performance improvement. A disadvantage of electrically grounding shields with a second thickness (T2) less than 50 nm is that performance is compromised due to excessively high resistivity.

[0017] It should be noted that the degree of coupling between the electrically grounded shield and the electric field associated with the radio frequency signal (carried by the first set of extended traces of the conductive material when used in the photonic integrated circuit) may be affected by the composition of the second dielectric layer and the third thickness (T3) (as seen in the direction perpendicular to the indium phosphide substrate), the second dielectric layer being disposed on the electrically grounded shield, the second dielectric layer, and the extended traces of the first set of extended traces of the conductive material according to the above embodiment of the photonic integrated circuit according to the invention. For example, if the extended traces of the first set of extended traces of the conductive material have a first thickness (T1) of, for example, 3 μm, and the second dielectric layer comprises benzocyclobutene (BCB) with a third thickness (T3) of, for example, 3 μm, then the electric field associated with the radio frequency signal (carried by the first set of extended traces of the conductive material when used in the photonic integrated circuit) can be considered to be tightly coupled to the electrically grounded shield. Additionally, it should be noted that the composition of the second dielectric layer and the third thickness (T3) can affect the impedance of on-chip electrical interconnects or feeders. Therefore, the composition and / or thickness (T3) of the second dielectric layer need to be carefully selected and / or controlled. The example described above, containing benzocyclobutene (BCB) and having a third dielectric layer (T3) of 3 μm, can be used to implement on-chip electrical interconnects or feeds with a 55-ohm impedance. It will be clear that the impedance value of the on-chip electrical interconnect or feed, and therefore the composition and size of the second dielectric layer, depends on the specific application of the photonic integrated circuit.

[0018] As described above, when the photonic integrated circuit is used, the first dielectric layer provides DC isolation between the electrically grounded shield and the first stack including the doped epitaxial semiconductor layer. While a fourth thickness (T4) of, for example, 20 nm as seen in a direction perpendicular to the indium phosphide substrate would be sufficient, a fourth thickness (T4) of, for example, 3 μm would be advantageous for planarization purposes. Therefore, the first dielectric layer will also have a planarization function that can improve the yield and reliability of the photonic integrated circuit.

[0019] Based on all the foregoing, it is clear that the photonic integrated circuit according to the present invention, including on-chip interconnects or feeds already implemented according to a shielded on-chip interconnect or feed scheme, avoids the aforementioned problems associated with typical methods used to reduce the problems mentioned above associated with implementing on-chip interconnects or feeds in photonic integrated circuits with increasingly complex layouts. In particular, it should be understood that the shielded on-chip interconnect or feed scheme allows for easier fabrication of photonic integrated circuits. Furthermore, the shielded on-chip interconnect or feed scheme provides a general solution for the specific situations described above, such as on-chip interconnects disposed on doped epitaxial semiconductor layers, and / or on-chip interconnects that must span on-chip optical waveguides.

[0020] In an embodiment of the photonic integrated circuit according to the present invention, the electrically grounded shield of the second stack is configured as a continuous sheet of conductive material.

[0021] A continuous sheet of conductive material is the simplest implementation of an electrically grounded shield, providing the required electrical shielding of the first set of extended traces of conductive material (i.e., on-chip electrical interconnects or feeds) relative to the doped epitaxial semiconductor layer of the first stack of the photonic integrated circuit according to the invention. However, the application of the conductive material constituting the electrically grounded shield as a continuous sheet can introduce reliability issues. In particular, if the continuous sheet has an area covering most or all of the underlying layer, outgassed material from the underlying layer beneath the continuous sheet becomes trapped, potentially leading to points of failure that impair the yield and reliability of the photonic integrated circuit.

[0022] It should be noted that any kind of conductive material with any suitable composition and size can be used to establish an electrically grounded shield as a continuous sheet, provided that the conductive material can achieve electromagnetic shielding. Examples of suitable materials include metals, degenerate semiconductors, conductive polymers, metal-organic frameworks, and coordination polymers. Metal-organic frameworks are defined as crystalline compounds composed of metal ions or clusters coordinated to typically rigid organic molecules to form porous one-dimensional, two-dimensional, or three-dimensional structures. Coordination polymers are inorganic or organometallic polymer structures containing metal cation centers linked by ligands.

[0023] In an embodiment of the photonic integrated circuit according to the present invention, the electrical grounding shield of the second stack is configured as a mesh grid of conductive material.

[0024] It should be noted that configuring the electrical grounding shield as a conductive mesh can overcome the aforementioned drawbacks of constructing the electrical grounding shield as a continuous sheet of conductive material. Furthermore, the conductive mesh provides improved manufacturing tolerances because continuous conductive sheets are easier to peel off during manufacturing than conductive mesh. Additionally, the conductive mesh can help mitigate the accumulation of additional stress or strain in the electrical grounding shield during reliability testing of photonic integrated circuits.

[0025] A mesh grid can be created by providing a continuous layer of conductive material with through-holes. The through-holes can be configured and arranged to provide a mesh grid with uniform, non-uniform, or simultaneously regions with uniform and non-uniform mesh sizes. A mesh grid can also be created by interconnecting extended traces of conductive material using a mesh pattern. These extended traces of conductive material can be arranged relative to each other to create uniform, non-uniform mesh sizes, or regions with both uniform and non-uniform mesh sizes.

[0026] It should be noted that any kind of conductive material with any suitable composition and size can be used to construct the mesh grid, as long as the conductive material can achieve electromagnetic shielding. Examples of suitable materials include metals, degenerate semiconductors, conductive polymers, metal-organic frameworks, and coordination polymers.

[0027] In an embodiment of the photonic integrated circuit according to the invention, the mesh grid of conductive material is configured to have a maximum grid size equal to one-tenth the wavelength of the radio frequency signal carried by the first set of extended traces of the conductive material when the photonic integrated circuit is used. Typically, the maximum grid size is on the order of a few millimeters. The minimum aperture size is typically determined by process constraints. A minimum grid size of zero would practically result in a continuous sheet of conductive material.

[0028] In an embodiment of the photonic integrated circuit according to the present invention, the electrically grounded shield of the second stack is configured as a second set of extended traces of conductive material, the second set of extended traces of conductive material being interconnected via a mesh grid of conductive material.

[0029] In this way, the electrical grounding shield is established in a hybrid manner, namely by using continuous traces of conductive material interconnected by a mesh grid of conductive material. It should be noted that any kind of conductive material with any suitable composition and size can be used to establish an extension of the second set of extended traces interconnected by the mesh grid, provided that the conductive material can achieve electromagnetic shielding. Examples of suitable materials include metals, degenerate semiconductors, conductive polymers, metal-organic frameworks, and coordination polymers.

[0030] In an embodiment of the photonic integrated circuit according to the present invention, the extension traces of the second set of extended traces of the conductive material are arranged below the extension traces of the first set of extended traces of the conductive material. It should be noted that the extension traces of the second set of extended traces of the conductive material can also be arranged to cover the optical waveguide intersection.

[0031] In an embodiment of the photonic integrated circuit according to the present invention, the corresponding extension traces of the second set of extension traces of the conductive material are arranged below the corresponding extension traces of the first set of extension traces of the conductive material and have a corresponding second width (W2) as seen in a direction parallel to the indium phosphide substrate, and the corresponding extension traces of the first set of extension traces of the conductive material have a first width (W1) as seen in a direction parallel to the indium phosphide substrate, wherein the second width (W2) is greater than the first width (W1).

[0032] The second width (W2) can be at least 75% larger than the first width (W1). The first width (W1) can be in the range of 5 μm to 15 μm, depending in particular on the specific requirements of the desired impedance of the extended traces of the first set of extended traces with respect to the conductive material.

[0033] In embodiments of the photonic integrated circuit according to the present invention, the conductive material includes a metal. It should be noted that any metal with high conductivity can be used, provided that the metal is compatible with indium phosphide (InP) processing and does not cause yield and / or reliability issues.

[0034] In embodiments of the photonic integrated circuit according to the present invention, the metal includes gold. It should be noted that the gold-containing metal alloy must be compatible with indium phosphide processes and should not cause yield and / or reliability issues.

[0035] In an embodiment of the photonic integrated circuit according to the invention, the conductive material is gold. Gold is advantageous due to its high conductivity and compatibility with indium phosphide processes.

[0036] In an embodiment of the photonic integrated circuit according to the present invention, the first stack includes an unintentionally doped epitaxial semiconductor layer arranged relative to the doped epitaxial semiconductor layer to provide an optical waveguide to the photonic integrated circuit.

[0037] In an embodiment of the photonic integrated circuit according to the present invention, the unintentionally doped epitaxial semiconductor layer is the In of the optical waveguide. x Ga 1-x A Sy P 1-y The core layer, and the doped epitaxial semiconductor layer is a p-type doped InP-based cladding layer for the optical waveguide.

[0038] In an embodiment of the photonic integrated circuit according to the present invention, the fourth surface of the first dielectric layer of the second stack is associated with the third surface of the first stack via a third dielectric layer, wherein the first dielectric layer and the third dielectric layer comprise different materials.

[0039] The first dielectric layer can be a polymer layer, such as benzocyclobutene (BCB). The fourth thickness (T4) of the first dielectric layer can be in the range of 500 nm to 3 μm, for example, 1.5 μm. The third dielectric layer can be an oxygen-containing compound material, such as silicon dioxide (SiO2) having a fifth thickness (T5) seen in a direction perpendicular to the indium phosphide substrate. The fifth thickness (T5) can be in the range of 20 nm to 300 nm, for example, 150 nm.

[0040] In an embodiment of the photonic integrated circuit according to the present invention, the eighth surface of the second dielectric layer of the second stack is associated with the seventh surface of the electrically grounded shield of the second stack via a fourth dielectric layer, wherein the second dielectric layer and the fourth dielectric layer comprise different materials.

[0041] The second dielectric layer can be a polymer layer, such as benzocyclobutene (BCB). The third thickness (T3) of the second dielectric layer can be in the range of 1 μm to 5 μm, for example, 3 μm. The fourth dielectric layer can be an oxygen-containing compound material, such as silicon dioxide (SiO2) having a sixth thickness (T6) seen in a direction perpendicular to the indium phosphide substrate. The sixth thickness (T6) can be in the range of 50 nm to 500 nm, for example, 300 nm.

[0042] According to another aspect of the invention, an optoelectronic system is provided, comprising a photonic integrated circuit according to the invention, wherein the optoelectronic system is one of a transmitter, a receiver, a transceiver, a coherent transmitter, a coherent receiver, and a coherent transceiver. The optoelectronic system can, for example but not exclusively, be used in telecommunications applications, LiDAR, or sensor applications. Based on the foregoing, those skilled in the art will understand that any of the aforementioned transmitters, receivers, and transceivers can benefit from the advantages provided by the photonic integrated circuit according to the invention. Attached Figure Description

[0043] Other features and advantages of the invention will become apparent from the description of exemplary and non-limiting embodiments of the photonic integrated circuits and optoelectronic systems according to the invention.

[0044] Those skilled in the art will understand that the described embodiments of photonic integrated circuits and optoelectronic systems are merely exemplary in nature and should not be construed as limiting the scope of protection in any way. Those skilled in the art will recognize that alternative and equivalent embodiments of photonic integrated circuits and optoelectronic systems can be conceived and practiced without departing from the scope of protection of this invention.

[0045] Please refer to the figures in the accompanying drawings. The drawings are schematic in nature and therefore not necessarily drawn to scale. Furthermore, the same reference numerals denote the same or similar parts. In the accompanying drawings, Figure 1A schematic cross-sectional view of a first exemplary, non-limiting embodiment of a photonic integrated circuit according to the present invention is shown; Figure 2 A schematic cross-sectional view of a second exemplary, non-limiting embodiment of a photonic integrated circuit according to the present invention is shown; Figure 3 A schematic cross-sectional view of a third exemplary, non-limiting embodiment of a photonic integrated circuit according to the present invention is shown; Figure 4 A schematic cross-sectional view of a fourth exemplary, non-limiting embodiment of a photonic integrated circuit according to the present invention is shown; Figure 5 A schematic top view of a portion of a photonic integrated circuit according to the present invention is shown, wherein two extension traces of a first set of conductive material extension traces are arranged relative to a first exemplary, non-limiting embodiment of an electrically grounded shield, wherein, for clarity, any dielectric layer disposed between the two extension traces and the electrically grounded shield is omitted. Figure 6 A schematic top view of a portion of a photonic integrated circuit according to the present invention is shown, wherein two extension traces of a first set of conductive material extension traces are arranged relative to a second exemplary, non-limiting embodiment of an electrically grounded shield, wherein, for clarity, any dielectric layer disposed between the two extension traces and the electrically grounded shield is omitted. Figure 7 A schematic top view of a portion of a photonic integrated circuit according to the present invention is shown, wherein two extended traces of a first set of conductive material are arranged relative to a third exemplary, non-limiting embodiment of an electrically grounded shield, wherein, for clarity, any dielectric layer disposed between the two extended traces and the electrically grounded shield is omitted; and Figure 8 A schematic top view of a first exemplary, non-limiting embodiment of an optoelectronic system according to the present invention is shown, including a photonic integrated circuit according to the present invention. Detailed Implementation

[0046] Figure 1 A schematic cross-sectional view of a first exemplary, non-limiting embodiment of a photonic integrated circuit 1 according to the present invention is shown. The photonic integrated circuit 1 includes an indium phosphide substrate 2 and a first stack 4, the indium phosphide substrate 2 having a first surface 3, and the first stack 4 including a doped epitaxial semiconductor layer 5. The first stack 4 is configured and arranged to provide optical functionality when the photonic integrated circuit 1 is in use. The first stack 4 has a second surface 6 and a third surface 7, the second surface 6 being associated with the first surface 3 of the indium phosphide substrate 2, and the third surface 7 being arranged opposite to the second surface 6.

[0047] The photonic integrated circuit 1 further includes a second stack 8 configured and arranged to provide electrical functionality when the photonic integrated circuit 1 is in use. The second stack 8 includes a first dielectric layer 9 having a fourth surface 10 and a fifth surface 11, the fourth surface 10 being associated with a third surface 7 of the first stack 4, and the fifth surface 11 being arranged opposite to the fourth surface 10. The second stack 8 also includes an electrically grounded shield 12 and a seventh surface 14, the electrically grounded shield 12 having a sixth surface 13 associated with the fifth surface 11 of the first dielectric layer 9, and the seventh surface 14 being arranged opposite to the sixth surface 13. The second stack 8 also includes a second dielectric layer 15 and a ninth surface 17, the second dielectric layer 15 having an eighth surface 16 associated with the seventh surface 14 of the electrically grounded shield 12, and the ninth surface 17 being arranged opposite to the eighth surface 16.

[0048] The photonic integrated circuit 1 also includes a first set of extended traces 18a, 18b of conductive material associated with a ninth surface 17 of the second dielectric layer 15 of the second stack 8. The first set of extended traces 18a, 18b of conductive material is configured and arranged to carry radio frequency signals when the photonic integrated circuit 1 is used. Those skilled in the art will understand that the first set of extended traces of conductive material may include any suitable number of extended traces. Figure 1 The two extended traces 18a and 18b shown are merely non-limiting examples.

[0049] The photonic integrated circuit 1 also includes at least one electrical bonding pad 19 and at least one radio frequency (RF) component 20 electrically associated with each other via a first set of extended traces 18a, 18b of conductive material. Those skilled in the art will understand that the photonic integrated circuit 1 may include any suitable number of electrical bonding pads 19 and RF components 20, which can be electrically associated using any suitable number of extended traces in the first set of conductive material. One electrical bonding pad 19, one RF component 20, and two extended traces 18a, 18b of conductive material configured and arranged to associate the electrical bonding pad 19 and the RF component 20 with each other are merely non-limiting examples.

[0050] It should be noted that Figure 1The first dielectric layer 9 of the second stack 8 of the photonic integrated circuit 1 shown is configured and arranged to provide DC isolation between the electrically grounded shield 12 and the first stack 4 when the photonic integrated circuit 1 is used. Additionally, the electrically grounded shield 12 is configured and arranged to minimize or prevent overlap between the electric field caused by the radio frequency signal and the doped epitaxial semiconductor layer 5 of the first stack 4 when the photonic integrated circuit 1 is used. In this way, the photonic integrated circuit 1 includes on-chip electrical interconnects or feeds 18a, 18b implemented using a shielded on-chip electrical interconnect or feed scheme. According to the first exemplary, non-limiting embodiment of the photonic integrated circuit 1 described above, it is clear that the extended traces 18a, 18b of the first set of extended traces of conductive material will be interpreted as on-chip electrical interconnects or feeds.

[0051] Shielded on-chip interconnects or feeder solutions are used in Figure 1 , Figure 2 , Figure 3 and Figure 4 All exemplary, non-limiting embodiments of the photonic integrated circuit 1 according to the present invention minimize or prevent overlap between the doped epitaxial semiconductor layer 5 of the photonic integrated circuit 1 and the electric field of the radio frequency signal carried by the on-chip electrical interconnects or feeds 18a, 18b when the photonic integrated circuit 1 is used, without the need for at least one of the aforementioned prior art isolation trenches, thick polymer layers that are difficult to implement, and fragile air bridges. The shielded on-chip electrical interconnect or feed scheme enables the realization of long (i.e., in the range of 0.5 mm to 5 mm), low-loss on-chip electrical interconnects or feeds 18a, 18b with desired impedance for use in photonic integrated circuits with increasingly complex layouts. Long shielded on-chip electrical interconnects or feeds can be routed on photonic components (such as on-chip optical waveguides) without any performance loss. It should be noted that the shielded on-chip electrical interconnects or feeders of the photonic integrated circuit according to the present invention are suitable for use with any kind of radio frequency components, such as Mach-Zehnder modulators (MZMs), electroabsorption modulators (EAMs), and radio frequency photodiodes (RF PDs).

[0052] The conductive material used for the extension traces 18a and 18b of the first set of extension traces can be any kind of conductive material with any suitable composition and size, as long as it can carry high-quality radio frequency signals between the bonding pads 19 and the radio frequency component 20 of the photonic integrated circuit 1 when used in the photonic integrated circuit 1. It should be noted that the composition and size of the extension traces 18a and 18b of the first set of extension traces of conductive material are determined by the desired impedance of the on-chip electrical interconnects or feeds and the manufacturing process tolerances.

[0053] A practical example is: using electroplated gold as the conductive material to fabricate the first set of extended traces 18a. The electroplated gold traces 18a of the first set of extended traces can have a first width (W1) of 10 μm as seen in the direction parallel to the indium phosphide substrate 2 (see...). Figures 5-7 ), and a first thickness (T1) of 3 μm as seen in the direction perpendicular to the indium phosphide substrate 2 (see Figures 1-4 This allows for on-chip electrical interconnects or feeders with a 55-ohm impedance. It should be noted that, depending on the specific technical requirements of the photonic integrated circuit 1, any other size and composition of the conductive material can be envisioned.

[0054] It should be noted that the shielding performance of the electrically grounding shield 12 is not affected by the size and / or composition of the extended traces 18a, 18b of the first set of extended traces of conductive material. The electrically grounding shield 12 may have a second thickness (T2) in the range of 50 nm to 4 μm. The disadvantage of an electrically grounding shield 12 with a second thickness (T2) greater than 4 μm is that topology and / or reliability problems may occur without any performance improvement. The disadvantage of an electrically grounding shield 12 with a second thickness (T2) less than 50 nm is that performance is compromised due to excessively high resistivity.

[0055] It should be noted that the degree of coupling between the electrically grounded shield 12 and the electric field associated with the radio frequency signal (carried by the first set of extended traces 18a, 18b of the first set of extended traces of conductive material when used in the photonic integrated circuit 1) may be affected by the composition and thickness of the second dielectric layer 15. For example, if the extended traces 18a, 18b of the first set of extended traces of conductive material have a first thickness (T1) of, for example, 3 μm, and the second dielectric layer 15 comprises benzocyclobutene (BCB) with a third thickness (T3) of, for example, 3 μm as seen in a direction perpendicular to the indium phosphide substrate 2, then the electric field associated with the radio frequency signal (carried by the first set of extended traces 18a, 18b of conductive material when used in the photonic integrated circuit 1) can be considered to be tightly coupled to the electrically grounded shield 12. Additionally, it should be noted that the composition and third thickness (T3) of the second dielectric layer 15 can affect the impedance of the on-chip electrical interconnects or feeds 18a, 18b. Therefore, the composition of the second dielectric layer 15 and the third thickness (T3) need to be carefully selected and / or controlled.

[0056] The above example of a second dielectric layer 15 containing benzocyclobutene (BCB) and having a third thickness (T3) of 3 μm can be used to implement on-chip electrical interconnects or feeds with a impedance of 55 ohms. It will be clear that the impedance values ​​of the on-chip electrical interconnects or feeds 18a, 18b, and therefore the composition and size of the second dielectric layer 15, depend on the actual use of the photonic integrated circuit 1.

[0057] As described above, when the photonic integrated circuit 1 is used, the first dielectric layer 9 provides DC electrical isolation between the electrically grounded shield 12 and the first stack 4 including the doped epitaxial semiconductor layer 5. Although it would be sufficient for the first dielectric layer 9 to have a fourth thickness (T4) of, for example, 20 nm as seen in a direction perpendicular to the indium phosphide substrate 2, it would be advantageous for the first dielectric layer 9 to have a fourth thickness (T4) of, for example, 3 μm, for planarization purposes. Therefore, the first dielectric layer 9 will also have a planarization function that can improve the yield and reliability of the photonic integrated circuit 1.

[0058] It should be noted that the conductive material used for extending traces 18a and 18b may include a metal, which may be any metal with high conductivity, compatible with indium phosphide processes, and that does not cause yield and / or reliability issues. The metal may be a pure metal or an alloy. A pure metal may be gold, or an alloy may contain gold due to its high conductivity and compatibility with indium phosphide processes.

[0059] Reference Figures 1-4 It should be noted that the first thickness (T1) of the first set of extended traces 18a and 18b of the conductive material can be in the range of 0.5 μm to 8 μm. Additionally, it should be noted that the second thickness (T2) of the electrically grounded shield 12 can also be in the range of 0.5 μm to 8 μm. Although according to Figures 1-4 In an exemplary non-limiting embodiment of the photonic integrated circuit 1 shown, the second thickness (T2) is selected to be equal to the first thickness (T1). However, it should be noted that the second thickness (T2) may also be different from the first thickness (T1) depending on the specific requirements of the photonic integrated circuit 1.

[0060] Figure 2 A schematic cross-sectional view of a second exemplary, non-limiting embodiment of the photonic integrated circuit 1 according to the present invention is shown, wherein the fourth surface 10 of the first dielectric layer 9 of the second stack 8 is associated with the third surface 7 of the first stack 4 via a third dielectric layer 26. It should be noted that the first dielectric layer 9 and the third dielectric layer 26 comprise different materials. The first dielectric layer 9 may be a polymer layer, such as benzocyclobutene (BCB). The fourth thickness (T4) of the first dielectric layer 9 may be in the range of 500 nm to 3 μm, for example, 1.5 μm. The third dielectric layer 26 may be an oxygen-containing compound material, such as silicon dioxide (SiO2) having a fifth thickness (T5) seen in a direction perpendicular to the indium phosphide substrate 2. The fifth thickness (T5) may be in the range of 20 nm to 300 nm, for example, 150 nm.

[0061] according to Figure 2In a second exemplary, non-limiting embodiment of the photonic integrated circuit 1 shown, the eighth surface 16 of the second dielectric layer 15 of the second stack 8 is associated with the seventh surface 14 of the electrically grounded shield 12 of the second stack 8 via a fourth dielectric layer 27. It should be noted that the second dielectric layer 15 and the fourth dielectric layer 27 comprise different materials. The second dielectric layer 15 may be a polymer layer, such as benzocyclobutene (BCB). The third thickness (T3) of the second dielectric layer 15 may be in the range of 1 μm to 5 μm, for example, 3 μm. The fourth dielectric layer 27 may be an oxygen-containing compound material, such as silicon dioxide (SiO2) having a sixth thickness (T6) seen in a direction perpendicular to the indium phosphide substrate 2. The sixth thickness (T6) may be in the range of 50 nm to 500 nm, for example, 300 nm. As a practical example, note that 55-ohm MZM feed lines 18a and 18b can be obtained by applying a second dielectric layer 15 (including a third dielectric layer (T3) of BCB with a thickness of 3 μm) and a fourth dielectric layer 27 (including a sixth dielectric layer (T6) of SiO2 with a thickness of 300 nm). Clearly, the third thickness (T3) of the second dielectric layer 15 and the sixth thickness (T6) of the fourth dielectric layer 27 will depend on the specific requirements of the photonic integrated circuit 1. However, for the yield and / or reliability of the photonic integrated circuit 1, a minimum sum of the third thickness (T3) and the sixth thickness (T6) of 50 nm is recommended.

[0062] Figure 3 A schematic cross-sectional view of a third exemplary, non-limiting embodiment of the photonic integrated circuit 1 according to the present invention is shown. Figure 1 Compared to the first exemplary, non-limiting embodiment of the photonic integrated circuit 1 shown, Figure 3 The first stack 4 of the photonic integrated circuit 1 shown includes an unintentionally doped epitaxial semiconductor layer 24, which is arranged relative to the doped epitaxial semiconductor layer 5 of the first stack 4 to provide an optical waveguide 25 to the photonic integrated circuit 1. The unintentionally doped epitaxial semiconductor layer 24 may be an In-type semiconductor layer of the optical waveguide 25. x Ga 1-x A Sy P 1-y The core layer, and the doped epitaxial semiconductor layer 5 can be a p-type doped indium phosphide-based cladding layer of the optical waveguide 25.

[0063] Figure 4 A schematic cross-sectional view of a fourth exemplary, non-limiting embodiment of the photonic integrated circuit 1 according to the present invention is shown. Figure 2 Compared to the second exemplary, non-limiting embodiment of the photonic integrated circuit 1 shown, Figure 4The first stack 4 of the photonic integrated circuit 1 shown includes an unintentionally doped epitaxial semiconductor layer 24, which is arranged relative to the doped epitaxial semiconductor layer 5 of the first stack 4 to provide an optical waveguide 25 to the photonic integrated circuit 1. The unintentionally doped epitaxial semiconductor layer 24 may be an In-type semiconductor layer of the optical waveguide 25. x Ga 1-x A Sy P 1-y The core layer, and the doped epitaxial semiconductor layer 5 can be a p-type doped indium phosphide-based cladding layer of the optical waveguide 25.

[0064] Based on all the above, it is clear that, according to Figures 1-4 The photonic integrated circuit 1 in any of the above exemplary non-limiting embodiments shown includes on-chip interconnects or feeds 18a, 18b implemented according to a shielded on-chip interconnect or feed scheme. This avoids the aforementioned problems associated with typical methods known from the prior art, which are used to reduce the aforementioned problems associated with implementing on-chip interconnects or feeds in photonic integrated circuits with increasingly complex layouts. In particular, it should be understood that the shielded on-chip interconnect or feed scheme allows for easier fabrication of the photonic integrated circuit 1 according to the invention. Furthermore, the shielded on-chip interconnect or feed scheme provides a general solution for the specific situations described above, such as on-chip interconnects disposed on a doped epitaxial semiconductor layer, and / or on-chip interconnects that must span an on-chip optical waveguide.

[0065] Figure 5 A schematic top view of a portion of a photonic integrated circuit 1 according to the present invention is shown, wherein two extension traces 18a, 18b of a first set of conductive material extension traces are arranged relative to a first exemplary, non-limiting embodiment of an electrically grounded shield 12. It should be noted that, for clarity, any dielectric layer arranged between the two extension traces 18a, 18b and the electrically grounded shield 12, as seen in a direction perpendicular to the indium phosphide substrate 2, has been omitted (see [reference needed]). Figure 1 , Figure 2 , Figure 3 and Figure 4 ).

[0066] like Figure 5 As shown, the electrical grounding shield 12 of the second stack 8 is configured as a continuous sheet of conductive material. The continuous sheet of conductive material is the simplest implementation of the electrical grounding shield 12, which provides the required electrical shielding for the two extended traces 18a, 18b (i.e., on-chip electrical interconnects or feeds) relative to the doped epitaxial semiconductor layer 5 of the first stack 4 of the photonic integrated circuit 1 (see [link to documentation]). Figure 1 , Figure 2 , Figure 3 and Figure 4However, the use of a continuous sheet as the conductive material constituting the electrical grounding shield 12 may introduce reliability issues. In particular, if the continuous sheet has an area covering most or all of the underlying layer, the venting material from the underlying layer beneath the continuous sheet may become trapped, potentially leading to a failure point that could impair the yield and reliability of the photonic integrated circuit 1.

[0067] It should be noted that any kind of conductive material with any suitable composition and size can be used to establish an electrically grounded shield as a continuous sheet, provided that the conductive material can achieve electromagnetic shielding. Examples of suitable materials include metals, degenerate semiconductors, conductive polymers, metal-organic frameworks, and coordination polymers. Metal-organic frameworks are defined as crystalline compounds composed of metal ions or clusters coordinated to typically rigid organic molecules to form porous one-dimensional, two-dimensional, or three-dimensional structures. Coordination polymers are inorganic or organometallic polymer structures containing metal cation centers linked by ligands.

[0068] Figure 6 A schematic top view of a portion of a photonic integrated circuit 1 according to the present invention is shown, wherein two extended traces 18a, 18b of a first set of extended traces of conductive material are arranged relative to a second exemplary, non-limiting embodiment of an electrically grounded shield 12. (See above regarding...) Figure 5 As mentioned, for clarity, any dielectric layer arranged between the two extended traces 18a, 18b and the electrical grounding shield 12, as seen in the direction perpendicular to the indium phosphide substrate 2, has been omitted (see [link to documentation]). Figure 1 , Figure 2 , Figure 3 and Figure 4 ).

[0069] like Figure 6 As shown, the electrical grounding shield 12 of the second stack 8 is configured as a mesh grid of conductive material. Configuring the electrical grounding shield 12 as a mesh grid of conductive material overcomes the aforementioned disadvantages of constructing the electrical grounding shield 12 as a continuous sheet of conductive material. Furthermore, the mesh grid of conductive material provides improved manufacturing tolerances because a continuous sheet of conductive material can be more easily peeled off during manufacturing than a mesh grid of conductive material. Additionally, the mesh grid of conductive material can help mitigate the accumulation of additional stress or strain in the electrical grounding shield 12 during reliability testing of the photonic integrated circuit 1.

[0070] A mesh grid can be created by providing a continuous layer of conductive material with through-holes. The through-holes can be configured and arranged to provide a uniform mesh size (i.e., as shown in the image). Figure 6As shown, the vias have equal widths (W) and lengths (L) and non-uniform grid sizes (not shown), or simultaneously provide areas with uniform grid sizes and areas with non-uniform grid sizes (not shown). Another way to create a mesh grid is to interconnect extended traces of conductive material using a mesh pattern. The extended traces of conductive material can be arranged relative to each other to create uniform grid sizes (i.e., vias with equal widths (W) and lengths (L)), non-uniform grid sizes (not shown), or areas with both uniform and non-uniform grid sizes (not shown).

[0071] The conductive material mesh can have a maximum mesh size equal to one-tenth the wavelength of the radio frequency signal carried by at least one of the two traces 18A and 18B when the photonic integrated circuit 1 is used. Typically, the maximum mesh size is on the order of a few millimeters. The minimum aperture size is usually determined by process limitations. A minimum mesh size of zero would practically result in a continuous sheet of conductive material.

[0072] As mentioned above, any kind of conductive material with any suitable composition and size can be used to construct a mesh grid, as long as the conductive material can achieve electromagnetic shielding. Examples of suitable materials include metals, degenerate semiconductors, conductive polymers, metal-organic frameworks, and coordination polymers.

[0073] Figure 7 A schematic top view of a portion of a photonic integrated circuit 1 according to the present invention is shown, wherein two extended traces 18a, 18b of a first set of extended traces of conductive material are arranged relative to a third exemplary, non-limiting embodiment of an electrically grounded shield 12. (See above regarding...) Figure 5 and Figure 6 As mentioned, for clarity, any dielectric layer arranged between the two extended traces 18a, 18b and the electrical grounding shield 12, as seen in the direction perpendicular to the indium phosphide substrate 2, has been omitted (see [link to documentation]). Figure 1 , Figure 2 , Figure 3 and Figure 4 ).

[0074] like Figure 7 As shown, the electrical grounding shield 12 of the second stack 8 is configured as a second set of extended traces 23a and 23b of conductive material, which are interconnected via a mesh grid of conductive material. In this way, the electrical grounding shield 12 is established in a hybrid manner, that is, by using continuous traces 23a and 23b of conductive material interconnected by a mesh grid of conductive material.

[0075] It should be noted that any kind of conductive material with any suitable composition and size can be used to establish the extension traces 23a, 23b of the second set of extension traces interconnected by a mesh grid of conductive material, provided that the conductive material can achieve electromagnetic shielding. Examples of suitable materials include metals, degenerate semiconductors, conductive polymers, metal-organic frameworks, and coordination polymers.

[0076] like Figure 7 As shown, the first extension trace 23a of the second group of conductive material extension traces is arranged below the first extension trace 18a of the first group of conductive material extension traces, and the second extension trace 23b of the second group of conductive material extension traces is arranged below the second extension trace 18b of the first group of conductive material extension traces. It should be noted that, as Figure 7 As shown, the arrangement of the first extension trace 23a and the second extension trace 23b of the second set of extended traces of the conductive material below the first extension trace 18a and the second extension trace 18b of the first set of extended traces of the conductive material is exemplary and non-limiting in nature. Figure 7 In a third exemplary, non-limiting embodiment of the electrically grounded shield 12 shown, the first extension trace 23a and the second extension trace 23b of the second set of conductive material extension traces are completely disposed below the first extension trace 18a and the second extension trace 18b of the first set of conductive material extension traces. As described above, the first extension trace 23a and the second extension trace 23b of the second set of conductive material extension traces have the advantage that they can be arranged such that the first extension trace 18a and the second extension trace 18b of the first set of conductive material extension traces can cross, for example, an optical waveguide.

[0077] Figure 7 A first extension trace 18a of a first set of conductive material extension traces is shown, having a first width (W1) as seen in a direction parallel to the indium phosphide substrate 2. A first extension trace 23a of a second set of conductive material extension traces is arranged below the first extension trace 18a of the first set of conductive material extension traces and has a second width (W2) as seen in a direction parallel to the indium phosphide substrate 2. The second width (W2) is greater than the first width (W1). It should be noted that the second width (W2) can be at least 75% larger than the first width (W1). The first width (W1) can be in the range of 5 μm to 15 μm, depending particularly on the specific requirements for the desired impedance of the first extension trace 18a of the first set of conductive material extension traces. Although not shown in Figure 7 As shown, but those skilled in the art will understand, this also applies to the second extension trace 18b of the first set of extension traces of conductive material and the second extension trace 23b of the second set of extension traces of conductive material.

[0078] Figure 8A schematic diagram of a first exemplary, non-limiting embodiment of an optoelectronic system 100 according to the present invention is shown, including a photonic integrated circuit 1 according to the present invention. The optoelectronic system 100 can be used, for example but not exclusively, in telecommunications applications, LIDAR, or sensor applications. The optoelectronic system 100 can be, for example, one of a transmitter, receiver, transceiver, coherent transmitter, coherent receiver, and coherent transceiver. Based on the foregoing, those skilled in the art will understand that the optoelectronic system 100 according to the present invention can benefit from the advantages provided by the photonic integrated circuit 1 according to the present invention.

[0079] This invention can be summarized as relating to a photonic integrated circuit 1, including bonding pads 19, radio frequency (RF) components 20, a first stack 4, a second stack 8, and a first set of extended traces 18a and 18b of conductive material. The first stack 4 has a doped epitaxial semiconductor layer 5. The second stack 8 is associated with the first stack 4, and the first set of extended traces 18a and 18b of conductive material are associated with the second stack 8. When the photonic integrated circuit 1 is used, the first set of extended traces 18a and 18b of conductive material can carry radio frequency (RF) signals between the bonding pads 19 and the RF components 20. The second stack 8 includes an electrically grounded shield 12 sandwiched between a first dielectric layer 9 and a second dielectric layer 15. When the photonic integrated circuit 1 is used, the electrically grounded shield 12 minimizes or prevents the overlap between the electric field caused by the RF signals and the doped epitaxial semiconductor layer 5. This invention also relates to an optoelectronic system 100, including the photonic integrated circuit 1.

[0080] Those skilled in the art will recognize that the scope of this invention is not limited to the examples discussed above, but that various modifications and alterations can be made therein without departing from the scope of the invention as defined by the appended claims. In particular, combinations of specific features of various aspects of the invention are possible. One aspect of the invention can be further advantageously enhanced by adding features described with respect to another aspect of the invention. While the invention has been detailed and described in the accompanying drawings and specification, such description and specification are to be considered illustrative or exemplary only, and not restrictive.

[0081] This invention is not limited to the disclosed embodiments. By studying the drawings, description, and appended claims, those skilled in the art can understand and implement variations of the disclosed embodiments in practicing the claimed invention. In the claims, the word "comprising" does not exclude other steps or elements, and the indefinite articles "a" or "an" do not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that combinations of these measures cannot be advantageously used. Any reference numerals in the claims should not be construed as limiting the scope of the invention.

Claims

1. A photonic integrated circuit, characterized in that, include: -Indium phosphide substrate (2), the indium phosphide substrate (2) having a first surface (3); - A first stack (4), the first stack (4) including a doped epitaxial semiconductor layer (5), the first stack (4) being configured and arranged to provide optical functionality when the photonic integrated circuit (1) is used, the first stack (4) having: • Second surface (6), which is associated with the first surface (3) of the indium phosphide substrate (2); as well as • A third surface (7), the third surface being arranged to face away from the second surface (6); as well as - A second stack (8), configured and arranged to provide electrical functionality when the photonic integrated circuit (1) is used, the second stack (8) comprising: • First dielectric layer (9), the first dielectric layer (9) has: ○ A fourth surface (10), which is associated with the third surface (7) of the first stack (4); and ○ Fifth surface (11), which is arranged to face away from the fourth surface (10); • Electrical grounding shield (12), the electrical grounding shield (12) having: ○ A sixth surface (13), which is associated with the fifth surface (11) of the first dielectric layer (9); and ○ Seventh surface (14), the seventh surface (14) is arranged to face away from the sixth surface (13); • Second dielectric layer (15), the second dielectric layer (15) having: ○ The eighth surface (16), which is associated with the seventh surface (14) of the electrically grounded shield (12); and ○ Ninth surface (17), which is arranged to face away from the eighth surface (16); - A first set of extended traces (18a, 18b) of conductive material, associated with the ninth surface (17) of the second dielectric layer (15) of the second stack (8), the first set of extended traces (18a, 18b) of conductive material being configured and arranged to carry radio frequency signals when used in the photonic integrated circuit (1); and - At least one electrical bonding pad (19) and at least one radio frequency component (20), wherein at least one of the electrical bonding pads (19) and at least one of the radio frequency components (20) are electrically connected to each other via the first set of extended traces (18a, 18b) of conductive material; The first dielectric layer (9) of the second stack (8) is configured and arranged to provide DC isolation between the electrically grounded shield (12) and the first stack (4) when the photonic integrated circuit (1) is used, and wherein the electrically grounded shield (12) is configured and arranged to minimize or prevent the overlap between the electric field caused by the radio frequency signal and the doped epitaxial semiconductor layer (5) of the first stack (4) when the photonic integrated circuit (1) is used.

2. The photonic integrated circuit according to claim 1, characterized in that, The electrical grounding shield (12) of the second stack (8) is configured as a continuous sheet of conductive material.

3. The photonic integrated circuit according to claim 1, characterized in that, The electrical grounding shield (12) of the second stack (8) is configured as a mesh grid of conductive material.

4. The photonic integrated circuit according to claim 3, characterized in that, The conductive material mesh grid is configured to have a maximum mesh size equal to one-tenth of the wavelength of the radio frequency signal carried by the first set of extended traces (18a, 18b) of the conductive material when the photonic integrated circuit (1) is used.

5. The photonic integrated circuit according to claim 1, characterized in that, The electrical grounding shield (12) of the second stack (8) is configured as a second set of extended traces (23a, 23b) of conductive material, which are interconnected via a mesh grid of conductive material.

6. The photonic integrated circuit according to claim 5, characterized in that, The extension traces of the second set of extension traces (23a, 23b) of the conductive material are arranged below the extension traces of the first set of extension traces (18a, 18b) of the conductive material.

7. The photonic integrated circuit according to claim 6, characterized in that, The corresponding extension traces of the second set of extension traces (23a, 23b) of the conductive material are arranged below the corresponding extension traces of the first set of extension traces (18a, 18b) of the conductive material and have a corresponding second width W2 as seen in a direction parallel to the indium phosphide substrate (2), and the corresponding extension traces of the first set of extension traces (18a, 18b) of the conductive material have a first width W1 as seen in the direction parallel to the indium phosphide substrate (2), wherein the second width W2 is greater than the first width W1.

8. The photonic integrated circuit according to claim 1, characterized in that, The conductive material includes metals.

9. The photonic integrated circuit according to claim 8, characterized in that, The metal includes gold.

10. The photonic integrated circuit according to claim 1, characterized in that, The conductive material is gold.

11. The photonic integrated circuit according to claim 1, characterized in that, The first stack (4) includes an unintentionally doped epitaxial semiconductor layer (24) arranged relative to the doped epitaxial semiconductor layer (5) to provide an optical waveguide (25) to the photonic integrated circuit (1).

12. The photonic integrated circuit according to claim 11, characterized in that, The unintentionally doped epitaxial semiconductor layer (24) is the In of the optical waveguide (25). x Ga 1-x A Sy P 1-y The core layer, and the doped epitaxial semiconductor layer (5) is a p-type doped indium phosphide cladding of the optical waveguide (25).

13. The photonic integrated circuit according to claim 1, characterized in that, The fourth surface (10) of the first dielectric layer (9) of the second stack (8) is associated with the third surface (7) of the first stack (4) via the third dielectric layer (26), wherein the first dielectric layer (9) and the third dielectric layer (26) comprise different materials.

14. The photonic integrated circuit according to claim 1, characterized in that, The eighth surface (16) of the second dielectric layer (15) of the second stack (8) is associated with the seventh surface (14) of the electrically grounded shield (12) of the second stack (8) via the fourth dielectric layer (27), wherein the second dielectric layer (15) and the fourth dielectric layer (27) comprise different materials.

15. A photoelectric system, characterized in that, Including the photonic integrated circuit (1) according to claim 1, the optoelectronic system (100) is one of a transmitter, a receiver, a transceiver, a coherent transmitter, a coherent receiver, and a coherent transceiver.

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