Integrated circuit device and method of forming same

Abstract

The invention relates to an integrated circuit device and a method of forming the same. The integrated circuit device includes a first lower mold layer and a second lower mold layer, each of the first lower mold layer and the second lower mold layer extending in a first direction and spaced apart from each other in a second direction perpendicular to the first direction; a lower metal line between the first lower mold layer and the second lower mold layer and extending in the first direction; an intermediate mold layer on the first lower mold layer and the second lower mold layer and separated from the lower metal line by an air gap; and a via contact on the lower metal line and extending through the opening in the intermediate mold layer, the via contact including a first portion adjacent to the lower metal line, the first portion having a first width in the first direction wider than a second width in the second direction.

Description

Technical Field

[0001] This disclosure generally relates to the field of integrated circuit devices, and more specifically to back-end process (BEOL) interconnect structures and methods for forming them. Background Technology

[0002] Back-end operation (BEOL) is a process in integrated circuit device manufacturing that involves depositing metal interconnect layers onto a wafer already patterned with devices. It is the second part of the integrated circuit device manufacturing process after the front-end operation (FEOL) process. In BEOL, individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected according to how metal wiring is deposited. However, parasitic capacitances can occur between BEOL interconnects on the same or different vertical levels, partly due to the high dielectric constant of the insulating layers separating the interconnects. Furthermore, leakage currents can occur between interconnects on the same or different vertical levels. Summary of the Invention

[0003] According to some embodiments, an integrated circuit device includes: a first lower mold layer and a second lower mold layer, each of the first lower mold layer and the second lower mold layer extending in a first direction and spaced apart from each other in a second direction perpendicular to the first direction; a lower metal line, between the first lower mold layer and the second lower mold layer and extending in the first direction; an intermediate mold layer, on the first lower mold layer and the second lower mold layer and separated from the lower metal line by an air gap; and a via contact, on the lower metal line and extending through an opening in the intermediate mold layer, the via contact including a first portion adjacent to the lower metal line, the first portion having a first width in the first direction that is wider than a second width in the second direction.

[0004] According to some embodiments, a method includes: forming a pattern including a first lower mold layer and a second lower mold layer, with a lower metal line between the first lower mold layer and the second lower mold layer; forming an intermediate mold layer on the first lower mold layer and the second lower mold layer, such that the intermediate mold layer is separated from the lower metal line by an air gap; etching the intermediate mold layer to form a passage opening therein; epitaxially growing a first portion of a passage contact on the lower metal line in the passage opening; and depositing a second portion of the passage contact on the first portion in the passage opening. Attached Figure Description

[0005] Figure 1A This is a cross-sectional view of an integrated circuit device including an air gap extending along the axis of a metal line, according to some embodiments of the present disclosure.

[0006] Figure 1B It is along Figure 1A The line A-A' intercepts Figure 1A A cross-sectional view of an integrated circuit device;

[0007] Figures 2A to 2FThis is a cross-sectional view illustrating a method of forming an integrated circuit device including an air gap extending along the axis of a metal line according to some embodiments of the present disclosure.

[0008] Figure 3 This illustrates some embodiments of the present disclosure. Figures 2A to 2F The flowchart of the operations associated with the sectional view; and

[0009] Figures 4A to 4K This is a cross-sectional view showing an example operation of the front-end process (FEOL) handling. Detailed Implementation

[0010] Some implementations stem from the understanding that parasitic capacitances may arise between BEOL interconnects, at least in part, due to the excessively high dielectric constant of the insulating layers separating the upper and lower interconnects. Furthermore, leakage currents may occur between interconnects on the same or different vertical levels. Some embodiments of this disclosure can provide an integrated circuit device in which an air gap is formed extending along the axis of a metal line. According to some embodiments of this disclosure, a first lower die layer and a second lower die layer extend in a first direction and are spaced apart from each other in a second direction. A lower metal line extends between the first and second lower die layers, and also in the first direction. An intermediate die layer is formed on the first and second lower die layers using, for example, a selective deposition process (such as atomic layer deposition) or an epitaxial growth process. When the intermediate die layer is formed, an air gap is formed over the lower metal line and separates the intermediate die layer from the lower metal line. The air gap extends along the axis of the metal line in the first direction. An upper die layer comprising a generally low dielectric constant material can be formed on the intermediate die layer. Path patterning can be performed on the resulting structure to open paths above the lower metal line. The via contacts are then formed on the lower metal line using a two-stage process: in the first stage, a first portion of the via contact is formed by epitaxial growth on the lower metal line; and in the second stage, a second portion of the via contact is formed on the first portion using atomic layer deposition. Due to the presence of an air gap, the first portion of the via contact can extend along the length of the lower metal line, such that the via contact has a wider width in a first direction along the length of the lower metal line than in a second direction corresponding to the spacing between the lower mold layer and the lower metal line. In some embodiments, the via contact comprises molybdenum. After forming the via contact, the upper surface of the upper mold layer and the upper surface of the via contact can be planarized using, for example, a chemical mechanical processing (CMP) process, such that the upper surface of the via contact and the upper surface of the upper mold layer are coplanar.

[0011] Advantageously, the air gap effectively reduces the dielectric constant between one or more lower metal lines and the upper metal contact, thereby reducing parasitic capacitance. Additionally, the air gap can reduce leakage current between one or more lower metal lines and the upper metal contact, as well as between lower metal lines on the same vertical level or horizontal plane. As mentioned above, the air gap allows the first portion of the via contact to extend along the length of the metal line. The increased contact surface area associated with this profile can reduce the resistance between the via contact and the lower metal line. When forming the via opening, the air gap can further improve etching efficiency because less material needs to be etched to ensure that no upper or intermediate mold layers are present on a portion of the lower metal line. Using molybdenum for the via contact typically provides low resistivity and also reduces diffusion, which eliminates the need for padding material in the via opening. By eliminating the need for padding in the via opening, the process for forming the via contact in the via opening is simplified. The two-stage process for forming via contacts can provide the benefit of accuracy in epitaxial growth to form a first portion of the via contact extending along the underlying metal line within the air gap, while further benefiting from the efficiency of using deposition processes such as atomic layer deposition to complete a second portion of the via contact on the first portion. Embodiments of this disclosure can provide a self-aligned air gap formation technique in which air gap tunnels are formed to reduce parasitic capacitance and leakage current, while improving the efficiency of etching via openings due to reduced material to be etched. The via contact formation process is improved by using a combination of selective growth and atomic layer deposition, benefiting from both the accuracy of selective growth operations and the efficiency of the atomic layer deposition process.

[0012] Front-end processing (FEOL) in semiconductor manufacturing is the stage in which active devices for integrated circuits are directly formed on a substrate or wafer (such as, but not limited to, gallium arsenide, silicon carbide, sapphire, germanium, and / or gallium nitride). For illustrative purposes, an example implementation will be described with respect to a silicon substrate or wafer. The process begins with a polished silicon wafer, typically lightly doped to form the base substrate. Isolation regions, typically formed using shallow trench isolation (STI), are etched and filled with oxide to electrically isolate the devices. Next, dopants are introduced by ion implantation to form n-wells and p-wells, which define the regions where NMOS and PMOS transistors will be built. Once the wells are in place, a gate stack is formed, starting with a thin gate oxide (typically SiO2 or a high-k dielectric for advanced nodes), followed by deposition and patterning of polysilicon or metal gate material. Source and drain regions are then implanted on either side of the gate to form active transistor channels, and sidewall spacers are added to control diffusion and define extended implantation regions. To reduce resistance, a silicide step can be performed, in which a metal such as nickel, cobalt, and / or titanium reacts with exposed silicon on the gate, source, and drain to form silicides. Finally, an interlayer dielectric is deposited to insulate the device and prepare the wafer for the back-to-office (BEOL) stage, in which multiple layers of metal interconnects are built to complete the integrated circuit.

[0013] Example operations processed by FEOL are in Figures 4A to 4K As shown in the sectional view. Reference Figure 4A For example, a single-crystal silicon wafer 402 is cleaned and polished to obtain a substrate with a surface as regular and flat as possible. Cleaning is performed to ensure good adhesion of the photoresist material. Contaminants such as airborne particles are controlled via a cleanroom, and most inorganic materials can be removed using chemicals or plasma stripping. In the case of water absorption, a process called dehydration baking is employed before proceeding to the next step. Then, as... Figure 4B As shown, the top of wafer 402 is prepared for photolithography by covering the top of wafer 402 with an insulating layer 404 (typically an oxide) as a mask.

[0014] This process involves exposing a silicon (or other substrate material) layer to an oxidizing atmosphere at elevated temperatures. A steam or oxygen atmosphere is typically used. In a steam atmosphere, the following reaction occurs, where silicon reacts with water to form silicon dioxide and hydrogen gas:

[0015] Si + 2H₂O -> SiO₂ + 2H₂

[0016] In an oxygen atmosphere, silicon reacts with oxygen to form silicon dioxide, as shown in the following reaction:

[0017] Si + O2 -> SiO2

[0018] The temperature during this process is typically between approximately 900°C and 1300°C. By controlling the set temperature and duration of this process, the thickness of the resulting oxide layer can be predicted. As can be seen from the reaction formula above, silicon is consumed during this process. To achieve a specific thickness of the oxide layer, a silicon layer approximately 0.44 times the thickness of the oxide layer can be used.

[0019] In other embodiments, chemical vapor deposition (CVD) is a process that adds thin films of silicon oxide, silicon nitride (Si3N4), and silicon to a substrate via chemical reactions or gas decomposition. To form silicon oxide on a non-silicon layer, silicon compounds (such as silanes (SiH4)) react with oxygen on a heated substrate (typically around 425°C), resulting in the following reaction:

[0020] SiH4 + O2 → SiO2 + 2H2

[0021] Generally, the resulting oxide films exhibit weaker bonding properties than those achieved through thermal oxidation. Therefore, CVD is typically used only when the substrate on which the film is to be formed is not made of silicon, or when the operating temperature of the thermal oxidation process exceeds permissible limits. Silicon nitrides are used as masking agents during the oxidation process because the resulting nitride layer has a lower oxidation rate compared to silicon. The CVD process for forming nitride films involves reacting silane and ammonia (NH3) at approximately 800°C to perform the following reaction:

[0022] 3-SiH4 + 4-NH3 -> Si4N4 + 12-H2

[0023] To help reduce the operating temperature of the process, plasma-enhanced CVD is used to lower the temperature to approximately 300°C. CVD can also be used to deposit polycrystalline silicon (PSS) layers onto wafers. Polycrystalline silicon is used as a conductive material for leads, gate electrodes in metal-oxide-semiconductor (MOS) devices, and contact materials in shallow junction devices. This process involves reducing silane at a high temperature of approximately 600°C, as shown in the following reaction:

[0024] SiH4-> Si +2H2

[0025] The process associated with CVD is called "epitaxy deposition." This involves growing an additional film on a substrate as an extension of the same material. Two methods used for epitaxial deposition are "vapor phase epitaxy" and molecular beam epitaxy. In vapor phase epitaxy, a process similar to CVD is used, where silicon tetrachloride (SiCl4) is reduced by hydrogen in a highly controlled reaction at temperatures reaching 1100°C, as shown in the following reaction:

[0026] SiCl4 + 2H2 → Si + 4HCl

[0027] In molecular beam epitaxy, silicon and its dopants are evaporated and transported to a substrate in a vacuum chamber. While it has the advantage of being performed at a low temperature of approximately 400°C, it has lower throughput and requires more expensive equipment than vapor phase epitaxy.

[0028] refer to Figure 4CAfter forming the insulating layer 404, a film of a photosensitive protective material called photoresist 406 is formed. In some embodiments, a uniform photoresist 406 coating is applied by supplying a measured amount of liquid photoresist to the center of the wafer and then rotating it at high speed on a turntable to produce uniform diffusion. This process is determined by a number of parameters, including when to dispense the liquid (static / dynamic), rotation speed, acceleration, volume, viscosity, and time. Optimal conditions are found through experimental procedures. After coating, the resulting photoresist 406 film can be dried to remove excess solvent, promote adhesion, and harden the photoresist 406. As a result, the photoresist 406 can become less susceptible to particulate contamination because it becomes less sticky.

[0029] Photomasks 408 and 410, having circuit patterns for a single layer of the chip, are mounted and aligned with the wafer, as shown. Figure 4D As shown. Photomasks 408 and 410 protect certain areas of the substrate from exposure, thereby exposing the unprotected areas of the photoresist 406. Photomasks 408 and 410 can be thin, flat, transparent glass with a thickness of approximately 2 mm, in which opaque material is deposited in the areas of photomasks 408 and 410 corresponding to the desired unexposed areas of the photoresist 406. The process of aligning photomasks 408 and 410 relative to the wafer before exposing the photoresist 406 to leave an image in the coated surface is typically a high-precision process. Subsequent exposure depends primarily on two parameters: light intensity and time.

[0030] like Figure 4E As shown, the process of exposing the wafer to strong UV light through photomasks 408 and 410 allows for the removal of the exposed photoresist 406 area. (Reference) Figure 4F The unprotected insulating layer 404 is then stripped using, for example, a chemical etching process, and the remaining photoresist 406 is removed using a developer solution. Generally, there are two types of photoresists: negative and positive. When exposed to UV light, negative photoresists polymerize and are more difficult to dissolve in the developer solution than positive photoresists. For negative photoresists, the developer solution only removes the unexposed areas. In this way, a pattern can be formed of unprotected silicon wafer areas surrounded by regions of non-conductive material. Modification of the electrical properties of the exposed areas then involves doping processes (such as ion implantation) used to form the source and drain 414 of one or more transistors, such as... Figure 4GAs shown. The doping process involves accelerating vaporized ions of a dopant through an electric field and directing them toward a substrate. These penetrate the substrate to a known average depth, which can be obtained from the voltage of the electric field. This ability to know the average density of the dopant, and the ability to perform the process at room temperature, are some of the main advantages over other techniques. However, ion collisions can damage the crystal structure of the substrate. This damage can be mitigated by annealing the wafer at a temperature of about 500°C to 900°C, allowing the structure to repair itself. In some embodiments, the dopant may include ions of boron (B), phosphorus (P), and / or arsenic (As).

[0031] Other conductive or insulating layers can also be added. New material layers are added, and the entire photolithography process, including imaging, deposition, etching, and doping, is repeated to form many different parts of the chip layer by layer.

[0032] Once all the active components of the IC are ready, a BEOL (Better-on-Order) process is performed to deposit metal wiring between the individual devices to interconnect them; this process is called metallization. Figure 4H As shown, after the FEOL process, one or more integrated circuit devices include three well regions corresponding to, for example, source / drain regions 414. Common metals used in metallization processes include, but are not limited to, copper and aluminum, but many other metals can be suitable for use as nanoscale metal interconnects. The BEOL stage of chip fabrication may also include the formation of contact and dielectric structures. The BEOL process typically begins when the first layer of conductive metal 416 is deposited on top of the wafer, as... Figure 4I As shown. Similar to the process described above regarding FEOL processing, a layer of UV-sensitive photoresist 418 is added on top of metal 416. Then, in a manner similar to component processing during FEOL processing, a UV light source exposes the photoresist 418 through photomasks 420, 422 defining the desired layout of the metal lines, as... Figure 4J As shown. Then, in the subsequent chemical etching step, the exposed portions of the positive photoresist are removed, as... Figure 4K As shown. The etching process removes unprotected metal to obtain a wire pattern defined by photomasks 420 and 422, which connects different components of the chip. Most IC devices use more than one layer of wires to form all the necessary connections. In some chips, multiple layers are added in the BEOL process. Typically, metal interconnects are isolated by a dielectric layer to prevent short circuits between the wires and other metal layers. The various metal layers are interconnected by etching holes (creating pathways) in the insulating material.

[0033] Following BEOL processing, post-manufacturing processes are performed, including wafer testing, die separation, die testing, IC packaging, and final device testing.

[0034] The following describes embodiments of the present disclosure that can reduce parasitic capacitance that may be generated between interconnects formed during BEOL processing, which may be at least in part due to the high dielectric constant of the insulating layers separating the upper and lower interconnects and leakage current that may be generated between interconnects on the same or different vertical levels.

[0035] Figure 1A This is a cross-sectional view of an integrated circuit device including an air gap extending along the axis of a metal line, according to some embodiments of the present disclosure. Figure 1B It is along Figure 1A The line A-A' intercepts Figure 1A A cross-sectional view of an integrated circuit device.

[0036] refer to Figure 1A and Figure 1B An integrated circuit device 100, including an air gap extending along the axis of a metal line, includes lower metal lines 110 spaced apart from each other in a second direction (X direction). According to some embodiments, the lower metal lines 110 may include aluminum, copper, cobalt, and / or ruthenium. The lower metal lines 110 have a lower mold layer 112a therebetween. An intermediate mold layer 112b is on the lower mold layer 112a and is separated from the lower metal lines 110 via a corresponding air gap 116. Figure 1B As shown, the air gap 116 extends along the axis of the lower metal line 110 in a first direction (Y direction), thereby providing separation between the lower metal line 110 and the intermediate mold layer 112b. The upper mold layer 118 is on the intermediate mold layer 112b. According to some embodiments, the intermediate mold layer 112b and the upper mold layer 118 may comprise silica, fluorinated silicate glass, organosilicon glass, and / or spin-coated polymers. Passage openings are formed in the intermediate mold layer 112b and the upper mold layer 118, and passage contacts are formed therein. The passage contacts include a first portion 114a formed in the passage opening by, for example, epitaxial growth. This allows for the formation of a wider contact area with the lower metal line 110, such as... Figure 1B As shown, because the first portion 114a of the via contact can extend into the air gap 116 with a skirt profile, the first portion 114a of the via contact has a width W2 in the first direction (Y direction), which is greater than the width W1 in the second direction (X direction). Once the first portion 114a of the via contact is formed, the second portion 114b of the via contact is formed using, for example, atomic layer deposition. Advantageously, atomic layer deposition can be more efficient than epitaxial growth, thereby allowing for increased efficiency in forming the via contact. In some embodiments, the via contact comprises molybdenum, which typically provides low resistivity and also inhibits diffusion.

[0037] Figures 2A to 2F This is a cross-sectional view illustrating a method for forming an integrated circuit device including an air gap extending along the axis of a metal line, according to some embodiments of the present disclosure.

[0038] Reference Figures 2A to 2F and Figure 3 Methods for forming an integrated circuit device 100 including an air gap extending along the axis of a metal line, according to some embodiments of the present disclosure, are described below. Reference is now made to... Figure 2A This forms a pattern including lower metal lines 110, wherein the lower mold layer 112a is located between adjacent lower metal lines 110 in the X direction. (Reference) Figure 2B An intermediate template layer 112b is formed on the lower template layer 112a and separated from the lower metal line 110 via a corresponding air gap 116. According to different embodiments of this disclosure, various selective deposition or growth techniques can be used to form the intermediate template layer 112b. In some embodiments, epitaxial growth can be used to form the intermediate template layer 112b, and in other embodiments, atomic layer deposition can be used to form the intermediate template layer 112b. (See reference...) Figure 2C An upper mold layer 118 comprising a material having a relatively low dielectric constant (such as silicon dioxide, fluorinated silicate glass, organosilicon glass, and / or spin-coated polymer) is deposited on the intermediate mold layer 112b. In some embodiments, chemical vapor deposition is used to deposit the upper mold layer 118. (See reference...) Figure 2D A via opening can be formed on the lower metal line 110 to form a via contact therein. The location of the via opening is shown by a dashed line, marking the area to be etched 120. (As in...) Figure 2D As can be seen, the presence of the air gap 116 above the lower metal line 110 reduces the amount of etching required to remove the intermediate mold layer 112b and the upper mold layer 118 to form the via opening. (Reference) Figure 2E ,masking Figure 2D The structure exposes region 120, and the upper mold layer 118 and the intermediate mold layer 112b are etched using, for example, a dry etching process to form the passage opening 122. (See reference...) Figure 2F A passage contact is formed in the passage opening 122. In some embodiments, the formation of the passage contact includes a two-stage process. In the first stage, a first portion 114a of the passage contact is formed in the passage opening by, for example, epitaxial growth. As described above regarding... Figure 1B This allows for the formation of a wider contact area with the lower metal line 110 because the first portion 114a of the via contact can extend into the air gap 116. After forming the first portion 114a of the via contact, a second portion 114b of the via contact is formed on the first portion 114a using, for example, atomic layer deposition. As mentioned above, atomic layer deposition can be more efficient than epitaxial growth, thereby allowing for increased efficiency in forming the via contact. In some embodiments, the via contact comprises molybdenum, which typically provides low resistivity and also inhibits diffusion. Figure 2FAs shown, after the path contact is formed, the upper surface of the second part 114b of the path contact and the upper surface of the upper mold layer can be planarized so that they are coplanar.

[0039] Figure 3 This illustrates some embodiments of the present disclosure. Figures 2A to 2F The flowchart of the operations associated with the sectional view. Now refer to Figure 3 The operation begins at frame 305, where a pattern is formed. This pattern includes a first lower mold layer 112a and a second lower mold layer 112a, and a lower metal line 110 is present between the first lower mold layer 112a and the second lower mold layer 112a. This implementation... Figure 2A As shown in the diagram. According to some embodiments, the lower metal wire 110 may include aluminum, copper, cobalt, and / or ruthenium. At frame 310, an intermediate mold layer 112b is formed on the first lower mold layer 112a and the second lower mold layer 112a, such that the intermediate mold layer 112b is separated from the lower metal wire 110 by an air gap 116. Such embodiments are shown in... Figure 2B As shown in the diagram. The intermediate mold layer 112b may comprise silicon dioxide, fluorinated silicate glass, organosilicon glass, and / or spin-coated polymer. The intermediate mold layer 112b can be formed using epitaxial growth, and in other embodiments, atomic layer deposition can be used to form the intermediate mold layer 112b. The intermediate mold layer 112b is etched at frame 315 to form a via opening 122 therein. Such embodiments are shown in the diagram. Figure 2D and Figure 2E As shown in the diagram, the presence of an air gap 116 above the lower metal line 110 reduces the amount of etching required to remove the intermediate mold layer 112b and the upper mold layer 118 to form the via opening. The etching process can be performed, for example, using a dry etching process. Figure 2F As shown, at frame 320, the first portion 114a of the epitaxially grown passage contact is formed on the lower metal line 110 within the passage opening 122. As... Figure 2F As shown, at frame 325, a second portion 114b of the via contact is deposited on a first portion 114a of the via contact within the via opening 122. In some embodiments, the formation of the first portion 114a and the second portion 114b of the via contact comprises a two-stage process. In the first stage, the first portion 114a of the via contact can be formed in the via opening by, for example, epitaxial growth. Epitaxial growth can provide improved accuracy when forming the first portion 114a of the via contact, which provides an interface with the lower metal line 110. As mentioned above regarding... Figure 1BAs described, the extended air gap allows for the formation of a wider contact area with the lower metal line 110. This wider contact area results from the first portion 114a of the via contact extending into the air gap 116. After forming the first portion 114a of the via contact, a second portion 114b of the via contact is formed on the first portion 114a using, for example, atomic layer deposition. Atomic layer deposition can be more efficient than epitaxial growth, thus allowing for increased efficiency in forming the via contact. Therefore, the two-stage process for forming the via contact utilizes both the accuracy of selective growth and the efficiency of atomic layer deposition. In some embodiments, the via contact comprises molybdenum, which typically provides low resistivity and also suppresses diffusion. As a result, no pad is required between the via contact and the lower metal line 110, which further improves the efficiency of the process for forming the via contact.

[0040] Some embodiments of this disclosure can provide an integrated circuit device and a method of forming the same, the integrated circuit device having an air gap extending along the axis of a metal line for improving interconnect performance characteristics as illustrated in the following examples: Example 1: An integrated circuit device comprising: a first lower die layer and a second lower die layer, each of the first lower die layer and the second lower die layer extending in a first direction and spaced apart from each other in a second direction perpendicular to the first direction; a lower metal line, between the first lower die layer and the second lower die layer and extending in the first direction; an intermediate die layer, on the first lower die layer and the second lower die layer and separated from the lower metal line by the air gap; and a via contact, on the lower metal line and extending through an opening in the intermediate die layer, the via contact including a first portion adjacent to the lower metal line, the first portion having a first width in the first direction that is wider than a second width in the second direction.

[0041] Example 2: The integrated circuit device of Example 1 further includes: an upper module layer on the intermediate module layer.

[0042] Example 3: An integrated circuit device of Example 2, wherein the upper mold layer comprises silicon dioxide, fluorinated silicate glass, organosilicon glass or spin-coated polymer.

[0043] Example 4: An integrated circuit device of any of Examples 2-3, wherein the upper surface of the upper module and the upper surface of the via contact are coplanar.

[0044] Example 5: An integrated circuit device of any of Examples 1-4, wherein the lower metal line comprises aluminum, copper, cobalt, or ruthenium.

[0045] Example 6: An integrated circuit device of any one of Examples 1-5, wherein the intermediate layer comprises silicon dioxide, fluorinated silicate glass, organosilicon glass or spin-coated polymer.

[0046] Example 7: An integrated circuit device of any of Examples 1-6, wherein the via contact includes molybdenum.

[0047] Example 8: A method comprising: forming a pattern including a first lower die layer and a second lower die layer having a lower metal line between the first lower die layer and the second lower die layer; forming an intermediate die layer on the first lower die layer and the second lower die layer such that the intermediate die layer is separated from the lower metal line by an air gap; etching the intermediate die layer to form a via opening therein; epitaxially growing a first portion of a via contact on the lower metal line in the via opening; and depositing a second portion of the via contact on the first portion in the via opening.

[0048] Example 9: The method of Example 8, wherein the second portion of the deposition pathway contact comprises: depositing the second portion of the pathway contact on the first portion in the pathway opening by atomic layer deposition.

[0049] Example 10: A method of any one of Examples 8-9, wherein forming an intermediate mold layer includes: forming an intermediate mold layer on a first lower mold layer and a second lower mold layer by epitaxial growth.

[0050] Example 11: A method of any of Examples 8-9, wherein forming an intermediate mold layer comprises: forming an intermediate mold layer on a first lower mold layer and a second lower mold layer by atomic layer deposition.

[0051] Example 12: A method of any one of Examples 8-11, wherein a first lower die layer and a second lower die layer extend in a first direction and are spaced apart from each other in a second direction perpendicular to the first direction, wherein a lower metal wire extends in the first direction, and wherein a first portion has a first width in the first direction, the first width being wider than a second width in the second direction.

[0052] Example 13: The method of any of Examples 8-12, depositing an upper mold layer on the intermediate mold layer before etching the intermediate mold layer.

[0053] Example 14: The method of any of Example 13, wherein etching the intermediate mold layer includes: etching the intermediate mold layer and the upper mold layer to form a passage opening therein.

[0054] Example 15: The method of any one of Examples 13-14 further includes: flattening the upper surface of the upper mold layer and the upper surface of the passage contact, such that the upper surface of the upper mold layer and the upper surface of the passage contact are coplanar.

[0055] Example 16: A method of any one of Examples 13-15, wherein depositing the upper modulus includes: using chemical vapor deposition to deposit the upper modulus.

[0056] Example 17: The method of any one of Examples 13-16, wherein the upper mold layer comprises silica, fluorinated silicate glass, organosilicon glass or spin-coated polymer.

[0057] Example 18: A method of any of Examples 8-17, wherein the pathway contact includes molybdenum.

[0058] Example 19: A method of any of Examples 8-18, wherein the lower metal wire comprises aluminum, copper, cobalt, or ruthenium.

[0059] Example 20: A method of any one of Examples 8-19, wherein the intermediate layer comprises silica, fluorinated silicate glass, organosilicon glass or spin-coated polymer.

[0060] This document describes exemplary embodiments with reference to the accompanying drawings. Many different forms and embodiments are possible without departing from the teachings of this disclosure, and therefore this disclosure should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. Throughout the description, the same reference numerals refer to the same elements. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Note that aspects described with respect to one embodiment may be incorporated into different embodiments, although not with respect to their specific description. That is, features of all and / or any embodiment may be combined in any manner and / or combination.

[0061] This document describes exemplary embodiments with reference to cross-sectional diagrams, which are schematic illustrations of idealized embodiments and intermediate structures of the exemplary embodiments. Therefore, variations relative to the illustrated shape are expected as a result of, for example, manufacturing techniques and / or tolerances. Consequently, the embodiments described herein should not be construed as limited to the specific shapes shown herein, but may include, for example, deviations in shape due to manufacturing processes.

[0062] It should also be noted that in some alternative implementations, the functions / actions indicated in the flowchart boxes herein may not occur in the order shown in the flowchart. For example, depending on the functions / actions involved, two boxes shown consecutively may actually be executed substantially simultaneously, or these boxes may sometimes be executed in reverse order. Furthermore, the function of a given box in a flowchart and / or block diagram may be divided into multiple boxes, and / or the functions of two or more boxes in a flowchart and / or block diagram may be at least partially integrated. Finally, without departing from the scope of the invention, other boxes may be added / inserted between the shown boxes, and / or boxes / operations may be omitted.

[0063] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant field and will not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0064] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprising,” “including,” “including,” and / or “comprising” indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0065] It will be understood that when a component is referred to as being "connected to" another component or "on" another component, it can be directly connected to or on another component, or there may be intermediate components. Conversely, when a component is referred to as being "directly connected to" another component or "directly on" another component, there are no intermediate components. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Furthermore, the symbol " / " (e.g., when used in the term "source / drain") will be understood to be equivalent to the term "and / or".

[0066] This document has disclosed many different embodiments in conjunction with the foregoing description and accompanying drawings. It will be understood that a literal description and illustration of each combination and sub-combination of these embodiments would be excessively repetitive and confusing. Therefore, this specification (including the accompanying drawings) should be construed as a complete written description of all combinations and sub-combinations of the embodiments described herein, as well as the ways and processes of making and using them, and should support the claims for any such combination or sub-combination.

[0067] The subject matter disclosed above is to be considered illustrative rather than restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments falling within the scope of the inventive concept. Therefore, to the fullest extent permitted by law, the scope will be determined by the broadest permissible interpretation of the appended claims and their equivalents, and should not be bound or limited by the foregoing detailed description.

[0068] This application claims the benefit of U.S. Provisional Patent Application Serial No. 63 / 721,109, filed November 15, 2024, entitled “Air Gap Structure on Metal Line of Interconnection,” the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An integrated circuit device, comprising: A first lower mold layer and a second lower mold layer, each of the first lower mold layer and the second lower mold layer extending in a first direction and spaced apart from each other in a second direction perpendicular to the first direction; The lower metal wire extends between the first lower die layer and the second lower die layer in the first direction; An intermediate mold layer is located on the first lower mold layer and the second lower mold layer and is separated from the lower metal wire by an air gap; as well as A passage contact is provided on the lower metal wire and extends through an opening in the intermediate mold layer. The passage contact includes a first portion adjacent to the lower metal wire, the first portion having a first width in the first direction that is wider than a second width in the second direction.

2. The integrated circuit device according to claim 1, further comprising: The upper mold layer on the intermediate mold layer.

3. The integrated circuit device according to claim 2, wherein the upper mold layer comprises silicon dioxide, fluorinated silicate glass, organosilicon glass, or spin-coated polymer.

4. The integrated circuit device according to claim 2, wherein the upper surface of the upper module and the upper surface of the path contact are coplanar.

5. The integrated circuit device according to claim 1, wherein the lower metal line comprises aluminum, copper, cobalt, or ruthenium.

6. The integrated circuit device according to claim 1, wherein the intermediate layer comprises silicon dioxide, fluorinated silicate glass, organosilicon glass, or spin-coated polymer.

7. The integrated circuit device of claim 1, wherein the via contact comprises molybdenum.

8. A method for forming an integrated circuit device, comprising: A pattern comprising a first lower mold layer and a second lower mold layer is formed, wherein a lower metal line is present between the first lower mold layer and the second lower mold layer; An intermediate mold layer is formed on the first lower mold layer and the second lower mold layer, such that the intermediate mold layer is separated from the lower metal wire through an air gap; Etch the intermediate mold layer to form a passage opening therein; The first portion of the epitaxial growth passage in the opening of the passage contacts the lower metal line; as well as A second portion of the passage contact is deposited on the first portion in the passage opening.

9. The method of forming an integrated circuit device according to claim 8, wherein depositing the second portion of the via contact comprises: The second portion of the pathway contact is deposited on the first portion in the pathway opening by atomic layer deposition.

10. The method of forming an integrated circuit device according to claim 8, wherein forming the intermediate module layer comprises: The intermediate mold layer is formed by epitaxial growth on the first lower mold layer and the second lower mold layer.

11. The method of forming an integrated circuit device according to claim 8, wherein forming the intermediate module layer comprises: The intermediate mold layer is formed on the first and second lower mold layers by atomic layer deposition.

12. The method of forming an integrated circuit device according to claim 8, wherein each of the first lower mold layer and the second lower mold layer extends in a first direction, and the first lower mold layer and the second lower mold layer are spaced apart from each other in a second direction perpendicular to the first direction. The lower metal wire extends in the first direction, and The first portion has a first width in the first direction, and the first width is wider than the second width in the second direction.

13. The method for forming an integrated circuit device according to claim 8, further comprising: Before etching the intermediate mold layer, an upper mold layer is deposited on the intermediate mold layer.

14. The method of forming an integrated circuit device according to claim 13, wherein etching the intermediate mold layer comprises: The intermediate mold layer and the upper mold layer are etched to form the passage opening therein.

15. The method for forming an integrated circuit device according to claim 14, further comprising: The upper surface of the upper mold layer and the upper surface in contact with the passage are flattened so that the upper surface of the upper mold layer and the upper surface in contact with the passage are coplanar.

16. The method of forming an integrated circuit device according to claim 13, wherein depositing the upper mold layer comprises: The upper mold layer is deposited using chemical vapor deposition.

17. The method of forming an integrated circuit device according to claim 13, wherein the upper mold layer comprises silicon dioxide, fluorinated silicate glass, organosilicon glass, or spin-coated polymer.

18. The method of forming an integrated circuit device according to claim 8, wherein the via contact comprises molybdenum.

19. The method of forming an integrated circuit device according to claim 8, wherein the lower metal line comprises aluminum, copper, cobalt or ruthenium.

20. The method for forming an integrated circuit device according to claim 8, wherein the intermediate layer comprises silicon dioxide, fluorinated silicate glass, organosilicon glass, or spin-coated polymer.

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