Chip packaging structure, preparation method thereof and electronic equipment

Abstract

The embodiment of the invention discloses a chip packaging structure, a preparation method thereof and electronic equipment, and relates to the technical field of semiconductors. The chip packaging structure comprises a first substrate, a first chip electrically connected to the first substrate, a plurality of second chips stacked on the first chip, switching structures located on the plurality of second chips, lead bonding areas connected with the second chips and first leads of the first substrate, the second lead is connected with the lead bonding area of the second chip and the switching structure; and the third lead is connected with the first substrate and the switching structure. And along the thickness direction of the first substrate, the lead bonding areas of the two adjacent second chips are arranged in a staggered manner. By arranging the switching structure, the second lead and the third lead and adopting the leads (such as the first lead, the second lead and the third lead) to realize interconnection between the first chip and the second chip, the setting area of I / O in the second chip can be increased, the number of I / O in the second chip can be increased, the interconnection density is effectively improved, and the bandwidth performance is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a chip packaging structure and its fabrication method, and electronic devices. Background Technology

[0002] Computing power refers to the processing capability of storage devices when performing various computing tasks, including computing speed, storage capacity, and power consumption. With the continuous development of science and technology, such as artificial intelligence (AI), big data, and cloud computing, there is a high demand for improving computing power.

[0003] High computing power places higher demands on storage bandwidth, and how to improve bandwidth performance has become a pressing technical problem to be solved. Summary of the Invention

[0004] This application provides a chip packaging structure and its fabrication method, as well as an electronic device, for improving the bandwidth performance of the chip packaging structure.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, a chip packaging structure is provided, comprising: a first substrate, a first chip, a chip stacking structure, a connector structure, a first lead, a second lead, and a third lead. The first chip is located on one side of the first substrate and is electrically connected to the first substrate. The first chip is, for example, a flip chip, soldered onto the first substrate using a surface mount method. The chip stacking structure is located on the side of the first chip away from the first substrate. The connector structure is located on the side of the chip stacking structure away from the first substrate. The chip stacking structure includes a plurality of second chips stacked along the thickness direction of the first substrate, with the wire bonding areas of adjacent second chips staggered. The first, second, and third leads are all located between the first substrate and the connector structure. The first lead connects the wire bonding area of ​​the second chip to the first substrate, the second lead connects the wire bonding area of ​​the second chip to the connector structure, and the third lead connects the first substrate to the connector structure. The first chip is, for example, a logic chip, and the second chip is, for example, a memory chip.

[0007] The chip packaging structure provided in some embodiments of this application includes a first chip electrically connected to a first substrate, a chip stack structure including multiple second chips on the first chip, a transition structure on the side of the chip stack structure away from the first substrate, and a first lead, a second lead, and a third lead between the first substrate and the transition structure. The first lead connects the wire bonding area of ​​the second chip to the first substrate, the second lead connects the wire bonding area of ​​the second chip to the transition structure, and the third lead connects the first substrate and the transition structure. This allows for interconnection and communication between the first chip and the second chip via the first lead and the first substrate, or via the second lead, the transition structure, the third lead, and the first substrate. This facilitates increasing the I / O (input / output) area in the second chip, allowing for an increase in the number of I / Os in the second chip, effectively improving interconnection density and bandwidth performance.

[0008] Moreover, the first, second, and third leads can be fabricated using wire bonding technology. Compared to using TSV stacking and interconnection, the embodiments of this application can omit the complex process caused by the setting of through silicon vias, effectively reducing costs.

[0009] Furthermore, by stacking multiple second chips on the first chip along the thickness direction of the first substrate in the chip stacking structure, and staggering the wire bonding areas of adjacent second chips, it is beneficial to increase the storage capacity of the chip package structure and reduce its area. On the other hand, the second chips can also be used to separate the wire bonding areas of the second chips located on the upper and lower sides of the first chip, which makes it easier to leave wiring space for the first leads electrically connected to the second chips, reducing the difficulty of the wire bonding process and improving the wire bonding yield. Moreover, it can avoid setting other structures (such as pads) to separate adjacent second chips, which is beneficial to reduce the size of the chip package structure in the thickness direction of the first substrate.

[0010] In one possible design approach, the wire bonding region of the second chip includes a first wire bonding region and a second wire bonding region; two adjacent second chips include a first sub-chip and a second sub-chip, with the first and second wire bonding regions of the first sub-chip located on opposite sides of the second sub-chip. The first wire is connected to the first wire bonding region of the second chip, and the second wire is connected to the second wire bonding region of the second chip. This allows for partitioned bonding of the first and second wires. Since the other ends of the first and second wires are electrically connected to the first substrate and the transition structure respectively, partitioned bonding of the first and second wires not only provides the second chip with dual-sided wire output capability but also improves the regularity of the arrangement of the first and second wires, increases the number of I / O outputs of the second chip, and thus improves the interconnection density and internal bandwidth of the second chip.

[0011] In one possible design approach, the second chip includes a plurality of first pads located in the first wire bonding region, with first leads electrically connected to the first pads; the plurality of first pads are arranged in at least one row. And / or, the second chip includes a plurality of second pads located in the second wire bonding region, with second leads electrically connected to the second pads; the plurality of second pads are arranged in at least one row. This is advantageous in improving the regularity of the arrangement of the plurality of first pads and / or the plurality of second pads, both increasing the number of first pads and / or second pads to improve interconnect density and bandwidth performance, and reducing the area of ​​the first wire bonding region and / or the second wire bonding region, thereby reducing the size of the chip package structure.

[0012] In one possible design approach, the aforementioned multiple first pads are arranged in multiple rows, with the first pads in adjacent rows being staggered. This multi-row routing arrangement helps to further increase the routing density of the second chip and further enhance bandwidth performance.

[0013] In one possible design approach, the aforementioned multiple second pads are arranged in multiple rows, with the second pads in adjacent rows being staggered. This multi-row routing arrangement helps to further increase the routing density of the second chip and further enhance bandwidth performance.

[0014] In one possible design approach, the first wire bonding regions of at least two second chips at least partially overlap along the thickness direction of the first substrate. This allows for the reduction of the area occupied by the first wire bonding regions of different second chips while achieving electrical connection between the first wire bonding regions of the second chips and the first leads, thereby facilitating a reduction in the size of the chip package structure.

[0015] In one possible design approach, the second lead bonding areas of at least two second chips are staggered along the thickness direction of the first substrate. This avoids obscuring the second lead bonding areas of the second chips, facilitates wiring of the second leads, and enables electrical connection between the second lead bonding areas and the second leads of different second chips.

[0016] In one possible design approach, three adjacent second chips include a first sub-chip, a second sub-chip, and a third sub-chip. The first wire bonding regions of the first and third sub-chips are located on the same side of the second sub-chip, and the second wire bonding regions of the first and third sub-chips are also located on the same side of the second sub-chip. By planning the positions of the first and second wire bonding regions of each second chip, wire bonding fabrication of the first and second leads can be facilitated, and the area occupied by the first and second leads can be reduced.

[0017] In the first possible design approach, there are multiple chip stack structures. The second lead connecting the first and third sub-chips is located between two adjacent chip stack structures. This helps to reduce the spacing between two adjacent chip stack structures, thereby helping to reduce the size of the chip package structure.

[0018] In one possible design approach, the first sub-chip is located between the third sub-chip and the first substrate. The dimension of the first sub-chip in the direction from its first wire bonding area to its second wire bonding area is larger than the dimension of the third sub-chip in the same direction. This facilitates the exposure of the second wire bonding areas of the second chips, which are relatively far from the first substrate, to the second wire bonding areas of the second chips, which are relatively close to the first substrate, thus enabling connections between the second wire bonding areas of each second chip and the second wires.

[0019] In one possible design approach, the third lead is located on the side of the first lead furthest from the first chip. And / or, the third lead is located on the side of the second lead furthest from the first chip. This facilitates the fabrication of the third lead, avoids short circuits caused by cross wiring, and improves the yield of the chip package structure.

[0020] In one possible design approach, two adjacent second chips are rotated out of alignment, and the angle of rotation between any two adjacent second chips is the same. For example, the angle of rotation out of alignment can be 60°, 90°, 120°, etc.

[0021] In one possible design approach, the second and third leads extend along the thickness direction of the first substrate. In this way, the size of the orthographic projection of the second lead on the first substrate is substantially the same as the linewidth of the second lead, and the orthographic projection of the second lead on the first substrate is within the orthographic projection range of the second chip it is connected to on the first substrate. Consequently, the second lead does not occupy any additional area, thus avoiding an increase in the size (or area) of the chip package structure. Furthermore, the size of the orthographic projection of the third lead on the first substrate is substantially the same as the linewidth of the third lead, and the orthographic projection area of ​​the third lead on the first substrate is small, which avoids a significant increase in the size (or area) of the chip package structure.

[0022] In one possible design approach, the chip package structure further includes a heat dissipation layer. This heat dissipation layer is disposed between the chip stack structure and the transition structure. By providing a heat dissipation layer, the upward (i.e., the direction from the first substrate to the transition structure) heat dissipation rate of the chip stack structure can be accelerated, thereby increasing the heat dissipation effect of the chip package structure.

[0023] In one possible design approach, the chip package structure further includes a first adhesive layer and a second adhesive layer. The first adhesive layer is bonded between the first chip and the chip stack structure, and the second adhesive layer is bonded between two adjacent second chips. The chip stack structure can be fixed to the first chip by the first adhesive layer, and two adjacent second chips can be fixed by the second adhesive layer.

[0024] In one possible design approach, the chip package structure further includes a filler portion and a packaging layer. The filler portion is located between the first substrate and the first chip. The packaging layer is located between the first substrate and the adapter structure, and surrounds the first chip, the chip stack structure, the first lead, the second lead, and the third lead. By providing the filler portion, the connection stability between the first substrate and the first chip can be enhanced, and insulation protection can be provided for the first connectors, preventing short circuits between adjacent first connectors. By providing the packaging layer, the connection stability between the first substrate and the adapter structure can be enhanced, as well as the connection stability between the first substrate, the first chip, the chip stack structure, the first lead, the second lead, and the third lead.

[0025] In one possible design approach, the adapter structure includes a second substrate or a third chip.

[0026] In a second aspect, a method for fabricating a chip package structure is provided, the method comprising: providing a first substrate; attaching a first chip to one side of the first substrate; forming a chip stack structure and forming a first lead on the side of the first chip away from the first substrate; the chip stack structure including a plurality of second chips stacked along the thickness direction of the first substrate, the lead bonding regions of adjacent second chips being staggered; the first lead connecting the lead bonding regions of the second chips and the first substrate; forming a second lead and a third lead, the second lead being connected to the lead bonding regions of the second chips, and the third lead being connected to the first substrate; and providing a transition structure on the side of the chip stack structure away from the first substrate, the transition structure being electrically connected to the second lead and the third lead.

[0027] In a possible design approach in the second aspect, the wire bonding region of the second chip includes a first wire bonding region and a second wire bonding region, and two adjacent second chips include a first sub-chip and a second sub-chip. A chip stack structure is formed on the side of the first chip away from the first substrate, and a first lead is formed, including: sequentially stacking a first sub-chip and a second sub-chip on the side of the first chip away from the first substrate, with the first wire bonding region and the second wire bonding region of the first sub-chip located on opposite sides of the second sub-chip. The first lead is formed and connected to the first wire bonding region of the first sub-chip and the first wire bonding region of the second sub-chip.

[0028] In a possible design approach in the second aspect, before setting the transition structure on the side of the chip stack structure away from the first substrate, the fabrication method further includes: forming an encapsulation layer that surrounds the first chip, the chip stack structure, the first lead, the second lead, and the third lead.

[0029] Thirdly, an electronic device is provided, comprising: a chip package structure and a circuit board. The chip package structure is as described in any embodiment of the first aspect, and the circuit board is electrically connected to the chip package structure.

[0030] The technical effects of any of the design methods in the second or third aspect can be found in the technical effects of different design methods in the first aspect, and will not be repeated here. Attached Figure Description

[0031] Figure 1 A structural diagram of an electronic device provided in an embodiment of this application;

[0032] Figure 2 for Figure 1 An exploded view of an electronic device is shown.

[0033] Figure 3 for Figure 1 A partial structural diagram of the electronic device shown;

[0034] Figure 4 A structural diagram of a high-bandwidth memory packaging structure provided in an embodiment of this application;

[0035] Figure 5a This is a cross-sectional view of a chip packaging structure provided in an embodiment of this application;

[0036] Figure 5b A cross-sectional view of another chip packaging structure provided in this application embodiment;

[0037] Figure 6 for Figure 5a The diagram shows a top view of the chip stacking structure in the chip packaging structure.

[0038] Figure 7 for Figure 5a Another top view of the chip stacking structure in the chip packaging structure shown;

[0039] Figure 8 This is a top view of a partial structure of a chip packaging structure provided in an embodiment of this application;

[0040] Figure 9 A cross-sectional view of another chip packaging structure provided in the embodiments of this application;

[0041] Figure 10 A cross-sectional view of another chip packaging structure provided in the embodiments of this application;

[0042] Figure 11 for Figure 9 or Figure 10 The diagram shows a top view of the chip stacking structure in the chip packaging structure.

[0043] Figure 12 for Figure 9 or Figure 10 Another top view of the chip stacking structure in the chip packaging structure shown;

[0044] Figure 13 A flowchart illustrating a method for fabricating a chip packaging structure provided in this application embodiment;

[0045] Figures 14a-14j The diagram shows the structural diagrams corresponding to each step in the fabrication method of a chip packaging structure provided in this application embodiment. Detailed Implementation

[0046] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0047] In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more. "At least one" or similar expressions refer to any combination of these items, including any combination of a single item or a plurality of items. For example, at least one of a, b, and c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple. "a and / or b" includes the following three combinations: only a, only b, and a combination of a and b. "Spacing" refers, for example, to the minimum distance between two adjacent structures.

[0048] Furthermore, to facilitate a clear description of the technical solutions in the embodiments of this application, the terms "first" and "second" are used in the embodiments of this application to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that "first" and "second" are not necessarily different. Meanwhile, in the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is being used as an example, illustration, or description. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of terms such as "exemplary" or "for example" is intended to present related concepts in a concrete manner for ease of understanding.

[0049] In describing some embodiments, the term "connection" and its derived expressions are used. The term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. Unless otherwise explicitly specified and limited, the term "electrical connection" should be interpreted broadly. For example, "electrical connection" can be a direct electrical connection, such as physical contact and electrical conduction between two components; it can also be understood as an electrical connection between different components in a circuit structure through physical lines that can transmit electrical signals, such as copper foil or wires on a printed circuit board (PCB), to transmit electrical signals; or, "electrical connection" can be an indirect electrical connection between two components through an intermediate medium; or, "electrical connection" can be an electrical connection between two components in a non-contact manner, such as an electrical connection between two components using capacitive coupling to transmit electrical signals.

[0050] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0051] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0052] In this application embodiment, the terms "upper," "lower," "left," and "right" are not limited to the orientation of the components schematically placed in the accompanying drawings. It should be understood that these directional terms can be relative concepts used for description and clarification, and can vary accordingly depending on the orientation of the components in the accompanying drawings. In the drawings, for clarity, the thickness of layers and regions is exaggerated, and the dimensional proportions between the parts in the illustrations do not reflect actual dimensional proportions. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, exemplary embodiments should not be construed as being limited to the shapes of the areas shown in this application, but rather include shape deviations due to, for example, manufacturing. For example, an etched area shown as rectangular would typically have a curved feature. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0053] Furthermore, the architecture and scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of architecture and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0054] This application provides an electronic device. This electronic device can be a mobile phone, tablet, smart screen, speaker, monitor, television, desktop computer, laptop computer, handheld computer, laptop, ultra-mobile personal computer (UMPC), netbook, as well as cellular phone, personal digital assistant (PDA), augmented reality (AR) device, virtual reality (VR) device, artificial intelligence (AI) device, smart wearable device (e.g., smartwatch, smart bracelet), in-vehicle device, smart home device, and / or smart city device, etc. This application does not impose any special limitations on the specific type of this electronic device.

[0055] For ease of explanation, we will use a mobile phone as an example to illustrate the following. This should not be considered a specific limitation on the structural form of electronic devices. Figure 1 This is a structural diagram of an electronic device in some embodiments. Figure 2 for Figure 1 The diagram shown is an exploded view of an electronic device. Figure 3 for Figure 1 The diagram shows a partial structural diagram of the electronic device.

[0056] like Figure 1 As shown, the electronic device 1000 includes a housing 100. For example, as... Figure 2 As shown, the housing 100 may include a front frame 101, a middle frame 102, and a rear housing 103. The middle frame 102 includes a side frame 1021 and a middle plate 1022. The middle plate 1022 is, for example, a flat plate structure, and the side frame 1021 is, for example, a ring structure, surrounding the middle plate 1022. The side frame 1021 can be connected to the middle plate 1022 by welding, bonding, or other methods. Alternatively, the side frame 1021 and the middle plate 1022 can be integrally formed to improve the reliability of the connection between them.

[0057] The front frame 101 is connected to one edge of the side frame 1021, and the rear shell 103 is connected to the side edge of the side frame 1021 away from the front frame 101. The front frame 101, side frame 1021, and rear shell 103 can enclose an accommodating space. The middle plate 1022 is located within this accommodating space, for example. The middle plate 1022 can serve as the skeleton of the electronic device 1000, providing support. The front frame 101 and rear shell 103 can be connected to the side frame 1021 by means of snap-fit ​​or adhesive bonding, for example. The connection methods between the front frame 101 and the side frame 1021 and between the rear shell 103 and the side frame 1021 can be the same or different.

[0058] See further examples. Figure 2 The aforementioned electronic device 1000 may also include a display screen 200.

[0059] The aforementioned display screen 200 is used to display image information. The image information displayed on the display screen 200 can be a static image (such as a picture or photograph) or a dynamic image (such as a video or game screen). The display screen 200 can be of various types. Optionally, it can be a liquid crystal display (LCD), an organic light-emitting diode (OLED) display, a quantum dot light-emitting diode (QLED) display, a mini light-emitting diode (Mini LED) display, or a micro light-emitting diode (Micro LED) display, etc. Of course, the display screen 200 can also be other types of display screens.

[0060] The aforementioned front frame 101 is open (not shown in the figure), and the open end extends through the front frame 101 along its thickness direction. The display screen 200 is located in the receiving space between the middle plate 1022 and the front frame 101, and is embedded in the open end and connected to the front frame 101 to prevent the front frame 101 from obstructing the image information displayed on the display screen 200.

[0061] See further examples. Figure 2 The aforementioned electronic device 1000 may further include a camera assembly 300. This camera assembly 300 has image acquisition capabilities. The camera assembly 300 is located within a receiving space between the middle plate 1022 and the rear cover 103. Figure 2 As shown, a first through hole is provided on the rear cover 103, which extends through the rear cover 103 along its thickness direction. The camera assembly 300 is embedded in the first through hole and connected to the rear cover 103 to prevent the rear cover 103 from obstructing the camera assembly 300.

[0062] The number of camera components 300 can be one or more. When there are multiple camera components 300, the number of first through holes can be one, in which case the multiple camera components 300 are embedded in the one first through hole; or, the number of first through holes can also be multiple, in which case at least one camera component 300 is embedded in one first through hole.

[0063] In some examples, combined Figure 2 and Figure 3 The electronic device 1000 also includes a circuit board 400, a battery 500, a chip packaging structure 600, and other structures.

[0064] The aforementioned circuit board 400, battery 500, chip packaging structure 600, and other structures are located within the accommodating space enclosed by the housing 100. This allows the housing 100 to protect the circuit board 400, battery 500, chip packaging structure 600, and other structures, reducing the risk of damage to these structures.

[0065] Optionally, the circuit board 400 and the chip package structure 600 may be located within the receiving space between the middle plate 1022 and the rear shell 103, or the circuit board 400 and the chip package structure 600 may also be located within the receiving space between the middle plate 1022 and the front frame 101. The battery 500 is located, for example, within the receiving space between the middle plate 1022 and the rear shell 103. This application embodiment does not further limit the positions of structures such as the circuit board 400, battery 500, and chip package structure 600 within the housing 100.

[0066] For example, the circuit board 400 is electrically connected to the display screen 200 to control the image information displayed on the display screen 200.

[0067] The aforementioned circuit board 400 can be a printed circuit board (PCB). Of course, the circuit board 400 can also be a flexible circuit board, a rigid-flex circuit board, etc. Optionally, the circuit board 400 can be fixed between the middle plate 1022 and the rear shell 103 by means of threaded connection, snap-fit, adhesive, etc.

[0068] Furthermore, a universal serial bus (USB) device can be integrated on the aforementioned circuit board 400. This USB device can be a USB Type-C interface device, a USB Type-A interface device, a USB Type-Micro-B interface device, or a USB Type-B interface device. A port is provided on the frame 1021 corresponding to the location of the USB device. Accessories such as chargers, headphones, and data cables can be electrically connected to the USB device via this port to achieve the transmission of power, signals, and data.

[0069] For example, such as Figure 3 As shown, the chip package structure 600 can be integrated onto the circuit board 400. The chip package structure 600 includes a chip that is electrically connected to the circuit board 400. The number of chips included in the chip package structure 600 can be, for example, one, two, three, or even more.

[0070] Optionally, the aforementioned chips include, but are not limited to, system on chip (SOC), charging management chip, power management unit (PMU), radio frequency (RF) chip, display chip, application processor (AP), dynamic random access memory (DRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), universal flash storage (UFS), etc.

[0071] Understandably, with the continuous development of science and technology, such as artificial intelligence (AI), big data, and cloud computing, there is a high demand for improved computing power, which in turn places higher demands on storage bandwidth.

[0072] In one possible implementation, Figure 4 This diagram illustrates a high bandwidth memory (HBM) package structure, which includes a logic die 610 and multiple memory chips (including but not limited to DRAM dies) 620. The memory chips 620 are stacked on top of the logic die 610 along its thickness. The logic die 610 and adjacent memory chips 620, as well as adjacent memory chips 620, are stacked using through-silicon via (TSV) technology, enabling interconnection and communication between each memory chip 620 and the logic die 610.

[0073] The HBM packaging structure described above has good broadband performance; however, it has low interconnect density and high cost.

[0074] Based on this, embodiments of this application provide a chip packaging structure that can be applied to the aforementioned electronic device 1000. Optionally, this chip packaging structure can be used as... Figure 3 The chip packaging structure 600 shown is illustrated. This application does not limit the application scenarios of the above-described chip packaging structure. Figure 5a , Figure 5b , Figure 9 and Figure 10 The diagrams illustrate cross-sectional views of a chip packaging structure provided in the embodiments of the application. Figure 5a and Figure 5b The sectional views shown are different; Figure 6 and Figure 7 They respectively indicated Figure 5a The diagram shown is a top view of the chip stacking structure in the chip packaging structure. Figure 8 The illustration shows a top view of a partial structure of a chip packaging structure provided in the application embodiment. Figure 11 and Figure 12 They respectively indicated Figure 9 or Figure 10 The diagram shows a top view of the chip stacking structure in the chip packaging structure.

[0075] In some embodiments, such as Figure 5a and Figure 5bAs shown, the chip packaging structure 600 includes a first substrate 1, a first chip 2, a chip stacking structure 3, a transition structure 4, a first lead 5, a second lead 6, and a third lead 7.

[0076] The first substrate 1 described above can be of various types. Optionally, the first substrate 1 may include, but is not limited to, a packaging substrate, a redistribution layer (RDL), etc. For example, the first substrate 1 is a packaging substrate. This packaging substrate may include, but is not limited to, organic substrates, ceramic substrates, silicon substrates, etc.

[0077] In some examples, such as Figure 5a and Figure 5b As shown, the first chip 2 is located on one side of the first substrate 1 and is electrically connected to the first substrate 1.

[0078] Optionally, the first chip 2 can be a flip chip (FC). The first chip 2 can be soldered to the first substrate 1 using flip-chip bonding to form an electrical connection with the first substrate 1. For example, the surface of the first chip 2 facing the first substrate 1 is an active surface, and multiple chip pads are provided on the active surface. The surface of the first substrate 1 facing the first chip 2 has multiple substrate pads. First connectors such as solder balls or controlled collapse chip connection bumps (C4 bumps) are provided between the chip pads and the substrate pads. The first chip 2 and the first substrate 1 are electrically connected through the first connectors.

[0079] The first chip 2 mentioned above is, for example, a logic chip. Optionally, the number of the first chips 2 can be one or more. Figure 5a and Figure 5b The illustrations are all based on the example of one first chip 2. When there are multiple first chips 2, these multiple first chips 2 are, for example, laid flat on one side surface of the first substrate 1.

[0080] Combination Figure 3 , Figure 5a and Figure 5b The chip package structure 600 may also include a second connector 8 disposed between the circuit board 400 and the first substrate 1, through which the circuit board 400 can be connected (or soldered) to the first substrate 1. The second connector 8 may be, for example, a solder ball (also known as a solder ball).

[0081] In this way, the first chip 2 and the circuit board 400 are respectively connected to the opposite sides of the first substrate 1, and the first chip 2 can be electrically connected and transmit signals to the circuit board 400 through the first connector, the first substrate 1, and the second connector 8 in sequence.

[0082] In some examples, such as Figure 5a and Figure 5b As shown, the chip stack structure 3 is located on the side of the first chip 2 away from the first substrate 1. Along the thickness direction of the first substrate 1, the first substrate 1, the first chip 2, and the chip stack structure 3 are sequentially stacked. For example, as... Figure 5a and Figure 5b As shown, the chip packaging structure 600 may further include a first adhesive layer 9, which is located between the first chip 2 and the chip stack structure 3. The first adhesive layer 9 is bonded to the surface of the first chip 2 away from the first substrate 1, and also bonded to the surface of the chip stack structure 3 close to the first substrate 1. The chip stack structure 3 is bonded and fixed to the first chip 2 by the first adhesive layer 9. This means that there is no direct electrical connection between the chip stack structure 3 and the first chip 2.

[0083] Optionally, the first adhesive layer 9 includes, but is not limited to, a die attach film (DAF).

[0084] Continue reading Figure 5a and Figure 5b The aforementioned chip stack structure 3 includes multiple second chips 31, such as memory chips. The different second chips 31 can be of the same or different types. For example, the multiple second chips 31 can be of the same type, and all can be DRAM. The number of second chips 31 can be selected according to actual needs, and this embodiment does not limit this. Figure 5a and Figure 5b The illustrations are all based on the example of eight second chips 31.

[0085] The aforementioned plurality of second chips 31 are stacked along the thickness direction of the first substrate 1. The multiple second chips 31 included in the chip stacking structure 3 are merely stacked and not directly electrically connected. Furthermore, the first chip 2 and adjacent second chips 31, as well as two adjacent second chips 31, are not stacked via TSVs, and direct communication is not possible between the first chip 2 and adjacent second chips 31, or between two adjacent second chips 31.

[0086] For example, such as Figure 5a and Figure 5bAs shown, the chip package structure 600 may further include a second adhesive layer 10, which is located between two adjacent second chips 31 and is bonded to each of the two adjacent second chips 31. Of the two adjacent second chips 31, the second chip 31 that is relatively far away from the first substrate 1 is bonded and fixed to the second chip 31 that is relatively close to the first substrate 1 by the second adhesive layer 10.

[0087] Optionally, the second adhesive layer 10 includes, but is not limited to, DAF.

[0088] Combination Figure 5a , Figure 5b and Figure 6 Each second chip 31 has a wire bonding region A, which is located, for example, on the surface of the second chip 31 that is away from the first substrate 1. The wire bonding region A is used to bond the first lead 5 and the second lead 6. For details about the first lead 5 and the second lead 6, please refer to the description below, which will not be repeated here.

[0089] In the aforementioned plurality of second chips 31, the wire bonding regions A of adjacent second chips 31 are staggered. That is, in the thickness direction of the first substrate 1 (or the thickness direction of the second chip 31), the wire bonding regions A of adjacent second chips 31 may partially overlap and partially not overlap. Alternatively, in the thickness direction of the first substrate 1 (or the thickness direction of the second chip 31), the wire bonding regions A of adjacent second chips 31 do not overlap.

[0090] For example, combining Figure 5a , Figure 5b and Figure 6 The two adjacent second chips 31 include a first sub-chip 31a and a second sub-chip 31b. Here, the first sub-chip 31a and the second sub-chip 31b may refer to the two adjacent second chips 31 closest to the first substrate 1, or the two adjacent second chips 31 furthest from the first substrate 1, or the two adjacent second chips 31 located in the middle region of the chip stack structure 3. Figure 5a , Figure 5b and Figure 6 The illustrations are all based on the example of the first sub-chip 31a and the second sub-chip 31b being located in the middle region of the chip stack structure 3.

[0091] Combination Figure 5a , Figure 5b and Figure 6 In the thickness direction of the second chip 31, the wire bonding regions A of the first sub-chip 31a and the second sub-chip 31b do not overlap. Optionally, the first sub-chip 31a is located between the first substrate 1 and the second sub-chip 31b, and the second sub-chip 31b does not cover the wire bonding region A of the first sub-chip 31a.

[0092] In this way, on the one hand, the wire bonding area A of each second chip 31 can be exposed, which facilitates the electrical connection of each second chip 31 with the first lead 5 and the second lead 6; on the other hand, the wire bonding areas A of the second chips 31 located on the upper and lower sides of the second chip 31 can be separated by the second chip 31, which facilitates the provision of wiring space for the first lead 5 to which the second chip 31 is electrically connected; furthermore, it can avoid the need to set other structures (such as pads) to separate adjacent second chips 31, which is beneficial to reduce the size of the chip package structure 600 in the thickness direction of the first substrate 1.

[0093] Furthermore, the wire bonding regions A of any two second chips 31 are staggered.

[0094] In some examples, such as Figure 5a and Figure 5b As shown, the aforementioned adapter structure 4 is located on the side of the chip stack structure 3 away from the first substrate 1. The orthographic projection of the chip stack structure 3 onto the first substrate 1 is, for example, within the orthographic projection range of the adapter structure 4 onto the first substrate 1. The orthographic projection of the first chip 2 onto the first substrate 1 is, for example, within the orthographic projection range of the adapter structure 4 onto the first substrate 1. The orthographic projection of the adapter structure 4 onto the first substrate 1 is, for example, within the range of the first substrate 1 (e.g., ...). Figure 10 As shown), or it can overlap with the first substrate 1 (as shown). Figure 5a (As shown).

[0095] The above-mentioned adapter structure 4 includes various types, which can be selected and set according to actual needs.

[0096] For example, such as Figure 5a As shown, the adapter structure 4 includes a second substrate 41. The second substrate 41 includes, but is not limited to, a packaging substrate, a redistribution layer, etc. The second substrate 41 and the first substrate 1 can be of the same type or different. For example, the second substrate 41 and the first substrate 1 are of the same type, and both are redistribution layers.

[0097] For example, such as Figure 10 As shown, the adapter structure 4 includes a third chip 42. The third chip 42 is, for example, a flip chip. The third chip 42 includes, but is not limited to, logic chips, memory chips, etc.

[0098] In some examples, such as Figure 5a and Figure 5bAs shown, there are multiple first leads 5. These multiple first leads 5 are all located between the first substrate 1 and the transition structure 4, and connect the wire bonding area A of the second chip 31 and the first substrate 1. Specifically, one end of each first lead 5 is electrically connected to a substrate pad of the first substrate 1, and the other end is electrically connected to a wire bonding area A of the second chip 31. The substrate pads of the first substrate 1 connected to different first leads 5 can be the same or different. Different first leads 5 can be electrically connected to the same wire bonding area A of the second chip 31, or they can be electrically connected to different wire bonding areas A of the second chip 31.

[0099] Optionally, the first lead 5 may include, but is not limited to, gold wire, copper wire, alloy wire, etc. The first lead 5 may be formed, for example, using a wire bonding (WB) process. Based on the positional relationship between the first substrate 1 and the second chip 31, the first lead 5 may be, for example, curved.

[0100] In this case, the first chip 2 and each of the second chips 31 can be interconnected and communicate with each other through the first substrate 1 and the first lead 5.

[0101] In some examples, such as Figure 5a and Figure 5b As shown, there are multiple second leads 6. These multiple second leads 6 are all located between the first substrate 1 and the adapter structure 4, and connect the wire bonding area A of the second chip 31 and the adapter structure 4. Specifically, one end of each second lead 6 is electrically connected to the wire bonding area A of one second chip 31, and the other end is electrically connected to the adapter structure 4. The pads of the adapter structure 4 connected to different second leads 6 can be the same or different. Different second leads 6 can be electrically connected to the same wire bonding area A of the second chip 31, or they can be electrically connected to different wire bonding areas A of the second chips 31.

[0102] Continue reading Figure 5a and Figure 5b The number of the aforementioned third leads 7 is, for example, multiple. These multiple third leads 7 are all located between the first substrate 1 and the adapter structure 4, and connect the first substrate 1 and the adapter structure 4. Specifically, one end of each third lead 7 is electrically connected to a substrate pad of the first substrate 1, and the other end is electrically connected to the adapter structure 4. The substrate pads of the first substrate 1 connected to different first leads 5 may be the same or different. The pads of the adapter structure 4 connected to different third leads 7 may be the same or different.

[0103] Optionally, the second lead 6 may include, but is not limited to, gold wire, copper wire, alloy wire, etc., and the third lead 7 may include, but is not limited to, gold wire, copper wire, alloy wire, etc. Both the second lead 6 and the third lead 7 may be formed using, for example, wire bonding technology. Figure 5a and Figure 5bAs shown, based on the positional relationship between the second chip 31 and the adapter structure 4, the second lead 6 is, for example, straight, and extends, for example, along the thickness direction of the first substrate 1. Based on the positional relationship between the first substrate 1 and the adapter structure 4, the third lead 7 is, for example, straight, and extends, for example, along the thickness direction of the first substrate 1. In this way, the size of the orthographic projection of the second lead 6 on the first substrate 1 is substantially the same as the linewidth of the second lead 6, and the orthographic projection of the second lead 6 on the first substrate 1 is located within the orthographic projection range of the second chip 31 connected to it on the first substrate 1. Accordingly, the arrangement of the second lead 6 does not occupy any additional area, thereby avoiding an increase in the size (or area) of the chip package structure 600. Moreover, the size of the orthographic projection of the third lead 7 on the first substrate 1 is substantially the same as the linewidth of the third lead 7, and the orthographic projection area of ​​the third lead 7 on the first substrate 1 is small, which can avoid a significant increase in the size (or area) of the chip package structure 600.

[0104] In this case, the first chip 2 and each of the second chips 31 can also be interconnected and communicate with each other through the first substrate 1, the third lead 7, the adapter structure 4, and the second lead 6. For example, if the adapter structure 4 includes a third chip 42, the third chip 42 can also be interconnected and communicate with the first chip 2 through the second lead 6, and the third chip 42 can also be interconnected and communicate with the first chip 2 through the third lead 7 and the first substrate 1.

[0105] Understandably, compared to using TSV stacking and interconnection, using the first lead 5 to interconnect and communicate between the first chip 2 and each of the second chips 31 can not only eliminate the complex process caused by the setting of through silicon vias and effectively reduce costs, but also effectively increase interconnection density and improve bandwidth performance.

[0106] Furthermore, by setting up the adapter structure 4 and the second lead 6 and the third lead 7, it is beneficial to increase the area of ​​I / O (input / output) in the second chip 31, which facilitates increasing the number of I / O in the second chip 31, and thus further increases the bandwidth performance of the chip package structure 600.

[0107] In some embodiments, such as Figure 6 and Figure 7 As shown, the wire bonding region A of the second chip 31 includes a first wire bonding region A1 and a second wire bonding region A2, which are independent of each other. The first wire bonding region A1 and the second wire bonding region A2 are both strip-shaped, and their extension directions are, for example, the same.

[0108] For adjacent first sub-chip 31a and second sub-chip 31b, combined Figure 5a and Figure 6The first wire bonding region A1 and the second wire bonding region A2 of the first sub-chip 31a are located on opposite sides of the second sub-chip 31b. Along the thickness direction of the first substrate 1, the second sub-chip 31b does not overlap with the first wire bonding regions A1 and A2 of the first sub-chip 31a. The second sub-chip 31b does not cover the first wire bonding regions A1 and A2 of the first sub-chip 31a. This facilitates the electrical connection of the first wire bonding regions A1 and A2 of the first sub-chip 31a to their respective leads.

[0109] Furthermore, combined Figure 5b and Figure 6 Along the thickness direction of the first substrate 1, the first wire bonding region A1 and the second wire bonding region A2 of the second sub-chip 31b do not overlap with the first sub-chip 31a at least partially.

[0110] For example, when another second chip 31 is disposed on the side of the second sub-chip 31b away from the first sub-chip 31a, the first wire bonding region A1 and the second wire bonding region A2 of the second sub-chip 31b are located on opposite sides of the first sub-chip 31a. Along the thickness direction of the first substrate 1, the first wire bonding regions A1 and A2 of the first sub-chip 31a and the second sub-chip 31b do not overlap.

[0111] For example, if no other second chip 31 is disposed on the side of the second sub-chip 31b away from the first sub-chip 31a, then the second sub-chip 31b is the one furthest from the first substrate 1 in the chip stack structure 3. The first wire bonding region A1 and the second wire bonding region A2 of the second sub-chip 31b can be located on opposite sides of the first sub-chip 31a, or partially on opposite sides of the first sub-chip 31a, or other arrangements can be used. For example, in Figure 6 In the top view shown, along the thickness direction of the second chip 31, the first wire bonding area A1 of the first sub-chip 31a and the second sub-chip 31b does not overlap, but partially overlaps with the second wire bonding area A2 of the second sub-chip 31b.

[0112] This facilitates the electrical connection of the first wire bonding region A1 and the second wire bonding region A2 of the second sub-chip 31b to the corresponding wires.

[0113] In some examples, combined Figure 5a , Figure 5b and Figure 6 The first lead 5 is connected to the first lead bonding area A1 of the second chip 31, and the second lead 6 is connected to the second lead bonding area A2 of the second chip 31. That is, the first lead bonding area A1 of each second chip 31 is used to connect the first lead 5, and the second lead bonding area A2 of each second chip 31 is used to connect the second lead 6.

[0114] This means that, in this embodiment, the wire bonding area A of the second chip 31 is divided into two independent wire bonding areas, a first wire bonding area A1 and a second wire bonding area A2, and the first wire bonding area A1 and the second wire bonding area A2 of the first sub-chip 31a are located on opposite sides of the second sub-chip 31b, thus enabling partitioned bonding of the first lead 5 and the second lead 6. Since the other end of the first lead 5 and the other end of the second lead 6 are electrically connected to the first substrate 1 and the transition structure 4, partitioned bonding of the first lead 5 and the second lead 6 not only provides the second chip 31 with dual-sided wire output capability, but also improves the regularity of the arrangement of the first lead 5 and the second lead 6, increases the number of I / O outputs of the second chip 31, and thus helps to increase the interconnection density and the internal bandwidth of the second chip 31.

[0115] In some examples, such as Figure 8 As shown, the second chip 31 may include a plurality of first pads P1 and / or a plurality of second pads P2. That is, the second chip 31 may include a plurality of first pads P1, or the second chip 31 may include a plurality of second pads P2, or the second chip 31 may include a plurality of first pads P1 and a plurality of second pads P2.

[0116] For example, in combination Figure 5a , Figure 5b and Figure 8 The aforementioned multiple first pads P1 are located within the first wire bonding area A1, and the first leads 5 are electrically connected to the first pads P1. For example, the multiple first leads 5 electrically connected to the same second chip 31 are configured in a one-to-one correspondence with the multiple first pads P1 they include.

[0117] Furthermore, the aforementioned plurality of first pads P1 are arranged in at least one row. Among them, the plurality of first pads P1 in the same row are arranged sequentially at intervals along the extension direction of the first lead bonding region A1.

[0118] This helps to improve the regularity of the arrangement of the multiple first pads P1, which is beneficial to increasing the number of first pads P1 to improve interconnection density and bandwidth performance, and also helps to reduce the area of ​​the first wire bonding region A1 and reduce the size of the chip package structure 600.

[0119] Optionally, such as Figure 8 As shown, the aforementioned multiple first pads P1 are arranged in multiple rows, with the first pads P1 in adjacent rows being staggered. That is, the orthographic projections of the multiple first pads P1 in adjacent rows on the reference plane are alternately arranged. This reference plane is parallel to the extension direction of the first wire bonding area A1 and parallel to the thickness direction of the second chip 31.

[0120] For example, in multiple rows of first pads P1, the orthographic projections of the first pads P1 in odd-numbered rows on the reference plane coincide, and the orthographic projections of the first pads P1 in even-numbered rows on the reference plane coincide.

[0121] This will help to further increase the output line density of the second chip 31 and further increase bandwidth performance.

[0122] For example, in combination Figure 5a , Figure 5b and Figure 8 The aforementioned multiple second pads P2 are located within the second wire bonding area A2, and the second leads 6 are electrically connected to the second pads P2. For example, the multiple second leads 6 electrically connected to the same second chip 31 are configured in a one-to-one correspondence with the multiple second pads P2 they include.

[0123] Furthermore, the aforementioned plurality of second pads P2 are arranged in at least one row. Within the same row of second pads P2, the second pads P2 are arranged sequentially at intervals along the extension direction of the second lead bonding region A2.

[0124] This helps to improve the regularity of the arrangement of the multiple second pads P2, which is beneficial to increasing the number of second pads P2 to improve interconnection density and bandwidth performance, and also helps to reduce the area of ​​the second wire bonding region A2 and reduce the size of the chip package structure 600.

[0125] Optionally, such as Figure 8 As shown, the aforementioned multiple second pads P2 are arranged in multiple rows, with the second pads P2 in adjacent rows being staggered. That is, the orthographic projections of the multiple second pads P2 in adjacent rows on the aforementioned reference plane are alternately arranged.

[0126] For example, in multiple rows of second pads P2, the orthographic projections of the odd-numbered rows of second pads P2 on the reference plane coincide, and the orthographic projections of the even-numbered rows of second pads P2 on the reference plane coincide.

[0127] This will help to further increase the output line density of the second chip 31 and further increase bandwidth performance.

[0128] The first wire bonding area A1 and the second wire bonding area A2 of the second chip 31 can be configured in various ways, which are illustrated below with reference to the accompanying drawings.

[0129] In some embodiments, such as Figure 5a and Figure 5bAs shown, along the thickness direction of the first substrate 1, the first wire bonding regions A1 of at least two second chips 31 at least partially overlap, and / or, the second wire bonding regions A2 of at least two second chips 31 are staggered. Here, "at least two second chips 31" can refer to two, three, or even more second chips 31. Further, "at least two second chips 31" can also refer to at least two of an odd number of second chips 31, or at least two of an even number of second chips 31, along the thickness direction of the first substrate 1 and away from the first substrate 1.

[0130] In some examples, the above-mentioned "at least two second chips 31 first lead bonding regions A1 at least partially overlap" means that the orthographic projections of the at least two second chips 31 first lead bonding regions A1 on the first substrate 1 partially overlap, or overlap.

[0131] Optionally, such as Figure 6 As shown, when the orthographic projections of the first wire bonding regions A1 of at least two second chips 31 on the first substrate 1 partially overlap, the orthographic projection of the first wire bonding region A1 of at least one of the at least two second chips 31 on the first substrate 1 is located within the orthographic projection range of the first wire bonding regions A1 of the remaining second chips 31 on the first substrate 1. For example, as... Figure 6 As shown, the dimensions of the at least two second chips 31 are different in the extension direction of the first wire bonding region A1.

[0132] Optionally, such as Figure 7 As shown, when the orthographic projections of the first wire bonding regions A1 of the at least two second chips 31 on the first substrate 1 coincide, the dimensions of the at least two second chips 31 in the extension direction of the first wire bonding regions A1 are, for example, equal or approximately equal.

[0133] This allows for the reduction of the area occupied by the first wire bonding region A1 of the second chip 31 while achieving electrical connection between the first wire bonding region A1 and the first wire 5, thereby helping to reduce the size of the chip package structure 600.

[0134] In some examples, such as Figure 6 and Figure 7 As shown, the phrase "the second lead bonding areas A2 of at least two second chips 31 are staggered" means that the orthographic projections of the second lead bonding areas A2 of the at least two second chips 31 on the first substrate 1 do not overlap. For example, along the thickness direction of the first substrate 1, the second lead bonding areas A2 of the at least two second chips 31 are arranged in a stepped manner.

[0135] This avoids obstructing the second lead bonding area A2 of the second chip 31, making it easier to route the second lead 6 and achieve electrical connection between the second lead bonding area A2 and the second lead 6 of different second chips 31.

[0136] In some embodiments, such as Figure 5a and Figure 5b As shown, the three adjacent second chips 31 include a first sub-chip 31a, a second sub-chip 31b, and a third sub-chip 31c. Here, the first sub-chip 31a, the second sub-chip 31b, and the third sub-chip 31c can refer to the three adjacent second chips 31 closest to the first substrate 1, the three adjacent second chips 31 furthest from the first substrate 1, or the three adjacent second chips 31 located in the middle region of the chip stack structure 3. Figure 5a and Figure 5b The illustrations are all based on the example of the first sub-chip 31a, the second sub-chip 31b, and the third sub-chip 31c being located in the middle region of the chip stacking structure 3.

[0137] For example, in combination Figure 6 and Figure 7 The first wire bonding region A1 of the first sub-chip 31a and the third sub-chip 31c is located on the same side of the second sub-chip 31b, and the second wire bonding region A2 of the first sub-chip 31a and the third sub-chip 31c is located on the same side of the second sub-chip 31b. That is, based on the fact that the first wire bonding region A1 and the second wire bonding region A2 of the first sub-chip 31a are located on opposite sides of the second sub-chip 31b, the first wire bonding region A1 and the second wire bonding region A2 of the third sub-chip 31c are also located on opposite sides of the second sub-chip 31b, and the first wire bonding region A1 of the first sub-chip 31a and the third sub-chip 31c are disposed on the same side, and the second wire bonding region A2 of the first sub-chip 31a and the third sub-chip 31c are disposed on the same side. For example, in Figure 6 In the first sub-chip 31a and the third sub-chip 31c, the first wire bonding region A1 is located to the left of the second sub-chip 31b, and the second wire bonding region A2 of the first sub-chip 31a and the third sub-chip 31c is located to the right of the second sub-chip 31b.

[0138] Furthermore, such as Figure 5a As shown, along the thickness direction of the first substrate 1 and away from the first substrate 1, the first wire bonding regions A1 of the odd number of second chips 31 are located, for example, on the same side of the even number of second chips 31, such as... Figure 5b As shown, the first wire bonding regions A1 of an even number of second chips 31 are located, for example, on the same side of an odd number of second chips 31. Correspondingly, along the thickness direction of the first substrate 1, the first wire bonding region A1 of each second chip 31 occupies both sides of the chip stack structure 3 (e.g., Figure 6The second wire bonding regions A2 of each second chip 31 occupy both sides of the chip stack structure 3 (e.g., the left and lower sides of the stack). Figure 6 (Right and top sides of the middle).

[0139] By planning the positions of the first wire bonding region A1 and the second wire bonding region A2 of each second chip 31, the wire bonding preparation of the first wire 5 and the second wire 6 can be facilitated, and the area occupied by the first wire 5 and the second wire 6 can be reduced.

[0140] In some examples, such as Figure 5a As shown, the first sub-chip 31a is located between the third sub-chip 31c and the first substrate 1. That is, along the thickness direction of the first substrate 1 and away from the first substrate 1, the first sub-chip 31a, the second sub-chip 31b, and the third sub-chip 31c are arranged in sequence.

[0141] Continue reading Figure 5a The dimension of the first sub-chip 31a in the direction from its first wire bonding region A1 to its second wire bonding region A2 is larger than the dimension of the third sub-chip 31c in the same direction. That is, in Figure 5a and Figure 6 In this context, the lateral dimension of the first sub-chip 31a is larger than the lateral dimension of the third sub-chip 31c. For example, in... Figure 6 In the process, the vertical dimension of the first sub-chip 31a is greater than the vertical dimension of the third sub-chip 31c, and the vertical dimension of the third sub-chip 31c is smaller than the vertical dimension of the second sub-chip 31b.

[0142] Furthermore, combined Figure 5a and Figure 6 Along the thickness direction of the first substrate 1 and away from the first substrate 1, the dimensions of each of the odd-numbered second chips 31 in the direction from the first wire bonding region A1 to the second wire bonding region A2 decrease sequentially, for example; combined with Figure 5b and Figure 6 The dimensions of each of the even-numbered second chips 31 in the direction from the first wire bonding region A1 to the second wire bonding region A2 decrease sequentially, for example. Similarly, the dimensions of each of the odd-numbered second chips 31 in the extension direction of the first wire bonding region A1 decrease sequentially, for example; and the dimensions of each of the even-numbered second chips 31 in the extension direction of the first wire bonding region A1 decrease sequentially, for example.

[0143] This facilitates the exposure of the second lead bonding region A2 of the second chip 31, which is relatively far away from the first substrate 1, and makes it easier to achieve the connection between the second lead bonding region A2 of each second chip 31 and the second lead 6.

[0144] The number of the aforementioned chip stacking structures 3 can be one or more. When there are multiple chip stacking structures 3, these multiple chip stacking structures 3 are arranged in a flat configuration. Specifically, one, two, three, or even more chip stacking structures 3 can be disposed on the side of the same first chip 2 away from the first substrate 1. For example, combined with... Figure 9 , Figure 10 and Figure 11 For example, two chip stack structures 3 can be disposed on the side of the same first chip 2 away from the first substrate 1, or, combined with Figure 9 , Figure 10 and Figure 12 For example, four chip stack structures 3 are set on the side of the same first chip 2 away from the first substrate 1.

[0145] In some embodiments, such as Figure 11 and Figure 12 As shown, the second wire bonding region A2 of the first sub-chip 31a and the third sub-chip 31c is located between two adjacent chip stack structures 3; correspondingly, combined with Figure 9 The second lead 6, which connects the first sub-chip 31a and the third sub-chip 31c, is located between two adjacent chip stack structures 3.

[0146] Taking the first sub-chip 31a and the third sub-chip 31c as an example where there is an odd number of second chips 31.

[0147] For example, combining Figure 9 and Figure 11 When there are two chip stack structures 3, along the thickness direction of the first substrate 1 and away from the first substrate 1, the second lead bonding area A2 of the odd number of second chips 31 in each chip stack structure 3 is located between the two chip stack structures 3. Correspondingly, the second lead 6 connected to the odd number of second chips 31 in each chip stack structure 3 is located between the two chip stack structures 3.

[0148] For example, combining Figure 9 and Figure 12When there are four chip stack structures 3, these four chip stack structures 3 are arranged, for example, in two rows and two columns. Along the thickness direction of the first substrate 1 and away from the first substrate 1, the second wire bonding regions A2 of the odd number of second chips 31 in chip stack structures 3a and 3b are located between the two chip stack structures 3; the second wire bonding regions A2 of the odd number of second chips 31 in chip stack structures 3c and 3d are located between the two chip stack structures 3; the second wire bonding regions A2 of the even number of second chips 31 in chip stack structures 3a and 3d are located between the two chip stack structures 3; and the second wire bonding regions A2 of the even number of second chips 31 in chip stack structures 3b and 3c are located between the two chip stack structures 3.

[0149] By placing the second lead 6 connecting the first sub-chip 31a and the third sub-chip 31c between two adjacent chip stack structures 3, it is beneficial to reduce the spacing between the two adjacent chip stack structures 3, thereby reducing the size of the chip package structure 600.

[0150] In some embodiments, such as Figure 5a , Figure 5b and Figure 9 As shown, the third lead 7 is located on the side of the first lead 5 away from the first chip 2. And / or, as... Figure 5a and Figure 5b As shown, the third lead 7 is located on the side of the second lead 6 away from the first chip 2. That is, the third lead 7 is located on the periphery of the area occupied by the chip stack structure 3, the first lead 5, and the second lead 6.

[0151] This facilitates the fabrication of the third lead 7, avoids short circuits caused by cross wiring, and improves the yield of the chip package structure 600.

[0152] In some embodiments, such as Figure 7 As shown, multiple second chips 31 in the same chip stack structure 3 are staggered, for example, by rotation, so that the wire bonding areas A are offset. The rotational offset angle between two adjacent second chips 31 can be selected and set according to actual needs.

[0153] Optionally, the rotational offset angles of any two adjacent second chips 31 can be the same or different. For example, the rotational offset angles of any two adjacent second chips 31 can be the same, and the rotational offset angles can be 60° or 90° (e.g., ...). Figure 7 (as shown), 120°, etc.

[0154] Here, "rotational offset angle" refers, for example, the angle between the center lines of two adjacent second chips 31. The direction of extension of the center line is, for example, parallel to the direction from the first wire bonding region A1 to the second wire bonding region A2.

[0155] It is understood that the chip packaging structure 600 described above may also include other structures, which will be illustrated below with reference to the accompanying drawings.

[0156] In some embodiments, such as Figure 5a , Figure 9 and Figure 10 As shown, the chip package structure 600 may further include a heat dissipation layer 11. The heat dissipation layer 11 is disposed between the chip stack structure 3 and the transition structure 4.

[0157] The aforementioned heat dissipation layer 11 has a high thermal conductivity, and the material of the heat dissipation layer 11 includes materials with high thermal conductivity. Optionally, the material of the heat dissipation layer 11 includes, but is not limited to, silicon (Si), metallic materials (e.g., copper Cu), diamond, ceramic materials, etc.

[0158] By setting the heat dissipation layer 11, the upward heat dissipation rate of the chip stack structure 3 (that is, the direction from the first substrate 1 to the transition structure 4) can be accelerated, which can increase the heat dissipation effect of the chip packaging structure 600.

[0159] In some examples, such as Figure 5a , Figure 9 and Figure 10 As shown, a second adhesive layer 10 is provided between the heat dissipation layer 11 and the chip stack structure 3, and the heat dissipation layer 11 is fixed to the chip stack structure 3 through the second adhesive layer 10. Furthermore, the orthographic projection of the wire bonding area A of the second chip 31 closest to the heat dissipation layer 11 on the first substrate 1 does not overlap with the orthographic projection of the heat dissipation layer 11 on the first substrate 1. That is, the heat dissipation layer 11 does not cover the wire bonding area A of the second chip 31 closest to the heat dissipation layer 11. This avoids affecting the electrical connection between the second chip 31 and the first lead 5 and the second lead 6.

[0160] For example, when the adapter structure 4 includes a second substrate 41, the heat dissipation layer 11 is also in contact with the side surface of the second substrate 41 that is close to the first substrate 1.

[0161] For example, when the adapter structure 4 includes a third chip 42, there is a certain gap between the surface of the heat dissipation layer 11 away from the first substrate 1 and the surface of the third chip 42 close to the first substrate 1.

[0162] In some embodiments, such as Figure 5a , Figure 9 and Figure 10As shown, the chip package structure 600 may further include an underfill portion 12. This underfill portion 12 fills the space between the first substrate 1 and the first chip 2, and is in direct contact with both the first substrate 1 and the first chip 2. The underfill portion 12 also surrounds each of the first connectors located between the first substrate 1 and the first chip 2, spacing adjacent first connectors apart.

[0163] Optionally, the material of the filler portion 12 may include, but is not limited to, epoxy resin.

[0164] By providing the filling portion 12, the connection stability between the first substrate 1 and the first chip 2 can be enhanced, and the first connector can be insulated and protected to avoid short circuits between adjacent first connectors.

[0165] In some embodiments, such as Figure 5a , Figure 9 and Figure 10 As shown, the chip package structure 600 may further include a package layer 13. The package layer 13 is located between the first substrate 1 and the transition structure 4, and surrounds the first chip 2, the chip stack structure 3, the first lead 5, the second lead 6 and the third lead 7.

[0166] For example, when the adapter structure 4 includes a second substrate 41, the encapsulation layer 13 is also in contact with the side surface of the second substrate 41 that is closer to the first substrate 1.

[0167] For example, when the adapter structure 4 includes a third chip 42, there is a certain gap between the surface of the encapsulation layer 13 away from the first substrate 1 and the surface of the third chip 42 close to the first substrate 1.

[0168] Optionally, the material of the encapsulation layer 13 includes, but is not limited to, encapsulation materials such as polyimide, silicone, and epoxy resin.

[0169] By setting the encapsulation layer 13, the connection stability between the first substrate 1 and the transition structure 4 can be enhanced, as can the connection stability between the first substrate 1, the first chip 2, the chip stack structure 3, the first lead 5, the second lead 6, and the third lead 7.

[0170] Some embodiments of this application also provide a method for fabricating a chip package structure, which is used, for example, to fabricate the chip package structure 600 in some of the above embodiments. Figure 13 A flowchart illustrating a method for fabricating a chip packaging structure is shown. Figures 14a-14j The diagram illustrates the structural steps involved in the fabrication of a chip packaging structure. It should be understood that... Figure 13 The steps shown are not exclusive; more steps can be taken at other times. Figure 13Other steps may be performed before, after, or between any of the steps shown. Furthermore, some of the steps may be performed simultaneously, or they may be performed in a sequence different from the steps described. Figure 13 The execution is performed in the order shown.

[0171] The fabrication method of the chip packaging structure is illustrated below with reference to the accompanying drawings. Figure 13 As shown, the preparation method includes: S100-S500.

[0172] S100, such as Figure 14a As shown, a first substrate 1 is provided.

[0173] Optionally, the first substrate 1 includes, but is not limited to, a packaging substrate, a redistribution layer, etc.

[0174] Taking a first substrate 1 as an example of a redistribution layer. For instance, the fabrication method of the first substrate 1 includes: providing a substrate, the material of which is, but not limited to, glass; and then, fabricating the first substrate 1 on the substrate. Optionally, subsequent fabrication steps are all based on... Figure 14a The structure shown is implemented, but not limited to it. For example, the fabrication of the first substrate 1 is independent of the fabrication of subsequent structures.

[0175] S200, combined with Figure 14a and Figure 14b The first chip 2 is connected to one side of the first substrate 1.

[0176] For example, the first chip 2 is a chip that has been ground and patterned. Before connecting the first substrate 1 and the first chip 2, a first connector can be provided on the first substrate 1; then the first chip 2 is mounted on the first substrate 1; and then a reflow soldering process can be used to connect the first substrate 1 and the first chip 2.

[0177] Continue reading Figure 14b After connecting the first chip 2, adhesive or other materials can be filled between the first substrate 1 and the first chip 2 to form a filling portion 12, so as to fix the first chip 2 onto the first substrate 1 using the filling portion 12. The filling portion 12 can also provide insulation protection for the first connector, preventing short circuits between adjacent first connectors.

[0178] S300, such as Figure 14c , Figure 14d and Figure 14e A chip stack structure 3 is formed on the side of the first chip 2 away from the first substrate 1, and a first lead 5 is formed therein. The chip stack structure 3 includes a plurality of second chips 31 stacked along the thickness direction of the first substrate 1, with the lead bonding regions A of adjacent second chips 31 staggered. The first lead 5 connects the lead bonding regions A of the second chips 31 and the first substrate 1.

[0179] For example, before forming the chip stack structure 3 and the first lead 5, a first adhesive layer 9 can be formed on the side of the first chip 2 away from the first substrate 1 to facilitate bonding and fixing the subsequently formed chip stack structure 3 to the first chip 2. Optionally, the first adhesive layer 9 includes, but is not limited to, DAF.

[0180] In some examples, such as Figure 14c As shown, the wire bonding region A of the second chip 31 includes a first wire bonding region A1 and a second wire bonding region A2, and two adjacent second chips 31 include a first sub-chip 31a and a second sub-chip 31b.

[0181] In the above S300, a chip stack structure 3 is formed on the side of the first chip 2 away from the first substrate 1, and a first lead 5 is formed, for example including: S310-S320.

[0182] S310, such as Figure 14c As shown, a first sub-chip 31a and a second sub-chip 31b are stacked sequentially on the side of the first chip 2 away from the first substrate 1. The first wire bonding region A1 and the second wire bonding region A2 of the first sub-chip 31a are located on opposite sides of the second sub-chip 31b.

[0183] For example, before stacking the second sub-chip 31b on the first sub-chip 31a, a second adhesive layer 10 can be formed on the side of the first sub-chip 31a away from the first substrate 1 to facilitate the subsequent bonding and fixing of the second sub-chip 31b onto the first sub-chip 31a. During the stacking of the second sub-chip 31b, for example, the second sub-chip 31b can be rotated 90° and then stacked on the first sub-chip 31a so that the wire bonding regions A of the first sub-chip 31a and the second sub-chip 31b are staggered.

[0184] S320, such as Figure 14d As shown, a first lead 5 is formed, and the first lead 5 is connected to the first lead bonding area A1 of the first sub-chip 31a and the first lead bonding area A1 of the second sub-chip 31b.

[0185] For example, a wire bonding process can be used to form a first lead 5, one end of which is connected to the first substrate 1, and the other end is connected to the first wire bonding area A1 of the first sub-chip 31a or the first wire bonding area A1 of the second sub-chip 31b.

[0186] Here, as Figure 14eAs shown, when the number of second chips 31 is greater than two, steps S310-S320 can be repeated until the stacking of multiple second chips 31 and the fabrication of the first lead 5 are completed. In step S310, the number of stacked second chips 31 is not limited to two.

[0187] S400, such as Figure 14f As shown, a second lead 6 and a third lead 7 are formed. The second lead 6 is connected to the lead bonding area A of the second chip 31, and the third lead 7 is connected to the first substrate 1.

[0188] For example, the second lead 6 and the third lead 7 can be formed using a wire bonding process. The second lead 6 and the third lead 7 both extend along the thickness direction of the first substrate 1, for example.

[0189] S500, such as Figure 14h As shown, a transition structure 4 is provided on the side of the chip stack structure 3 away from the first substrate 1, and the transition structure 4 is electrically connected to the second lead 6 and the third lead 7.

[0190] The chip packaging structure fabrication method provided in some embodiments of this application obtains a chip stack structure 3 by stacking multiple second chips 31 away from the first chip 2 and away from the first substrate 1, and staggering the wire bonding areas A of adjacent second chips 31. This method is beneficial in increasing the storage capacity of the fabricated chip packaging structure and reducing its area. Furthermore, it can also use the second chips 31 to space the wire bonding areas A of the second chips 31 located on the upper and lower sides of the second chips 31, which makes it easier to leave wiring space for the first leads 5 electrically connected to the second chips 31, reducing the difficulty of the wire bonding process and improving the wire bonding yield. Moreover, it can avoid setting other structures (such as pads) to separate adjacent second chips 31, which is beneficial in reducing the size of the fabricated chip packaging structure in the thickness direction of the first substrate 1.

[0191] Furthermore, by forming the second lead 6 and the third lead 7, and providing the transition structure 4 on the side of the chip stack structure 3 away from the first substrate 1, the second lead 6 connects the wire bonding area A of the second chip 31 to the transition structure 4, and the third lead 7 connects the first substrate 1 to the transition structure 4. This allows the first chip 2 and the second chip 31 to interconnect and communicate via the second lead 6, the transition structure 4, the third lead 7, and the first substrate 1. This facilitates increasing the I / O (input / output) area in the second chip 31, making it easier to increase the number of I / Os in the second chip 31, effectively improving interconnect density and bandwidth performance.

[0192] Moreover, the first lead 5, the second lead 6 and the third lead 7 mentioned above can be fabricated based on wire bonding technology. Compared with TSV stacking and interconnection, the embodiments of this application can omit the complex process caused by the setting of through silicon vias, effectively reducing costs.

[0193] In some embodiments, combined with Figure 14g and Figure 14h Before step S500, that is, before the transition structure 4 is provided on the side of the chip stack structure 3 away from the first substrate 1, the above-described fabrication method further includes forming an encapsulation layer 13. The encapsulation layer 13 surrounds the first chip 2, the chip stack structure 3, the first lead 5, the second lead 6, and the third lead 7.

[0194] For example, the above-mentioned encapsulation layer 13 can be formed by injection molding, grinding, or other processes in the embodiments of this application.

[0195] After setting up the above-mentioned transition structure 4, combined with Figure 14h and Figure 14i For example, the prepared structure can be flipped 180° and then the substrate removed. Further, such as... Figure 14j As shown, for example, surface mount technology (SMT) can be used to mount resistors and capacitors on the side of the first substrate 1 away from the first chip 2 to optimize SIPI performance. During the mounting process, balls can be placed on the surface of the first substrate 1 away from the first chip 2 to form a second connector 8; subsequently, the first substrate 1 can be cut to obtain a single-package.

[0196] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0197] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed herein should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip packaging structure, characterized in that, The chip packaging structure includes: First substrate; The first chip is located on one side of the first substrate and is electrically connected to the first substrate; A chip stacking structure is located on the side of the first chip away from the first substrate; the chip stacking structure includes a plurality of second chips stacked along the thickness direction of the first substrate, and the wire bonding areas of two adjacent second chips are staggered. The adapter structure is located on the side of the chip stack structure away from the first substrate; The first lead is located between the first substrate and the adapter structure, and connects the lead bonding area of ​​the second chip and the first substrate; The second lead is located between the first substrate and the adapter structure, and connects the wire bonding area of ​​the second chip and the adapter structure; The third lead is located between the first substrate and the adapter structure, and connects the first substrate and the adapter structure.

2. The chip packaging structure according to claim 1, characterized in that, The wire bonding area of ​​the second chip includes a first wire bonding area and a second wire bonding area; two adjacent second chips include a first sub-chip and a second sub-chip, and the first wire bonding area and the second wire bonding area of ​​the first sub-chip are located on opposite sides of the second sub-chip; The first lead is connected to the first lead bonding region of the second chip, and the second lead is connected to the second lead bonding region of the second chip.

3. The chip packaging structure according to claim 2, characterized in that, The second chip includes a plurality of first pads located in the first wire bonding region, wherein the first wires are electrically connected to the first pads; the plurality of first pads are arranged in at least one row; And / or, The second chip includes a plurality of second pads located in the second wire bonding region, the second wires being electrically connected to the second pads; the plurality of second pads are arranged in at least one row.

4. The chip packaging structure according to claim 3, characterized in that, The plurality of first pads are arranged in multiple rows, with the plurality of first pads in two adjacent rows being staggered.

5. The chip packaging structure according to claim 3 or 4, characterized in that, The plurality of second pads are arranged in multiple rows, with the plurality of second pads in two adjacent rows being staggered.

6. The chip packaging structure according to any one of claims 2-5, characterized in that, Along the thickness direction of the first substrate, the first wire bonding regions of at least two of the second chips at least partially overlap, and / or, the second wire bonding regions of at least two of the second chips are staggered.

7. The chip packaging structure according to any one of claims 2-6, characterized in that, The three adjacent second chips include a first sub-chip, a second sub-chip, and a third sub-chip; The first wire bonding regions of the first sub-chip and the third sub-chip are located on the same side of the second sub-chip, and the second wire bonding regions of the first sub-chip and the third sub-chip are located on the same side of the second sub-chip.

8. The chip packaging structure according to claim 7, characterized in that, The number of the chip stacking structures is multiple; The second lead connecting the first sub-chip and the third sub-chip is located between two adjacent chip stack structures.

9. The chip packaging structure according to claim 7 or 8, characterized in that, The first sub-chip is located between the third sub-chip and the first substrate; The dimension of the first sub-chip in the direction from its first wire bonding region to its second wire bonding region is greater than the dimension of the third sub-chip in the same direction.

10. The chip packaging structure according to any one of claims 2-9, characterized in that, The third lead is located on the side of the first lead away from the first chip; and / or, The third lead is located on the side of the second lead away from the first chip.

11. The chip packaging structure according to any one of claims 1-10, characterized in that, The two adjacent second chips are rotated out of alignment, and the angle of rotation between any two adjacent second chips is the same.

12. The chip packaging structure according to any one of claims 1-11, characterized in that, The second lead and the third lead extend along the thickness direction of the first substrate.

13. The chip packaging structure according to any one of claims 1-12, characterized in that, The chip packaging structure further includes a heat dissipation layer; the heat dissipation layer is disposed between the chip stack structure and the adapter structure.

14. The chip packaging structure according to any one of claims 1-13, characterized in that, The chip packaging structure further includes: a first adhesive layer and a second adhesive layer; The first adhesive layer is bonded between the first chip and the chip stack structure; The second adhesive layer is bonded between two adjacent second chips.

15. The chip packaging structure according to any one of claims 1-14, characterized in that, The chip packaging structure further includes: a filling portion and a packaging layer; The filling portion is filled between the first substrate and the first chip; The encapsulation layer is located between the first substrate and the adapter structure, and surrounds the first chip, the chip stack structure, the first lead, the second lead and the third lead.

16. The chip packaging structure according to any one of claims 1-15, characterized in that, The adapter structure includes a second substrate or a third chip.

17. A method for fabricating a chip packaging structure, characterized in that, The preparation method includes: Provide a first substrate; A first chip is connected to one side of the first substrate; A chip stack structure is formed on the side of the first chip away from the first substrate, and a first lead is formed thereon; the chip stack structure includes a plurality of second chips stacked along the thickness direction of the first substrate, and the lead bonding areas of two adjacent second chips are staggered; the first lead connects the lead bonding areas of the second chips and the first substrate. A second lead and a third lead are formed, the second lead being connected to the lead bonding area of ​​the second chip, and the third lead being connected to the first substrate; A transition structure is provided on the side of the chip stack structure away from the first substrate, and the transition structure is electrically connected to the second lead and the third lead.

18. The preparation method according to claim 17, characterized in that, The wire bonding area of ​​the second chip includes a first wire bonding area and a second wire bonding area, and two adjacent second chips include a first sub-chip and a second sub-chip; The step of forming a chip stack structure on the side of the first chip away from the first substrate and forming a first lead includes: The first sub-chip and the second sub-chip are stacked sequentially on the side of the first chip away from the first substrate, and the first wire bonding area and the second wire bonding area of ​​the first sub-chip are located on opposite sides of the second sub-chip. The first lead is formed, and the first lead is connected to the first lead bonding area of ​​the first sub-chip and the first lead bonding area of ​​the second sub-chip.

19. The preparation method according to claim 17 or 18, characterized in that, Before setting the transition structure on the side of the chip stack structure away from the first substrate, the fabrication method further includes: An encapsulation layer is formed, the encapsulation layer surrounding the first chip, the chip stack structure, the first lead, the second lead, and the third lead.

20. An electronic device, characterized in that, The electronic device includes: The chip packaging structure as described in any one of claims 1-16; The circuit board is electrically connected to the chip package structure.

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