Semiconductor structure and forming method thereof
By forming a chamfered trench structure in a semiconductor device and forming a bonding layer on its surface, the problem of void defects during molten bonding is solved, thereby improving the performance and reliability of the semiconductor structure.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NINGBO SEMICON INT CORP
- Filing Date
- 2024-11-13
- Publication Date
- 2026-05-15
AI Technical Summary
In the fusion bonding process of existing semiconductor devices, the protrusion at the edge of the trench structure causes a large area of void defects at the top of the cavity structure, which affects the device performance.
A trench structure is formed in the substrate of the device wafer. The top corner of the trench structure is chamfered. A bonding layer is formed on the top of the substrate, the bottom of the trench structure, and the sidewalls. The bonding layer enables fusion bonding between the device wafer and the bare die wafer, forming a cavity structure.
This reduces the probability of void defects at the top of the cavity structure, improving the performance and reliability of the semiconductor structure.
Smart Images
Figure CN122055034A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology
[0002] Fusion bonding technology enables 3D integration of wafer chips by permanently connecting dielectric layers on each wafer surface. Because of its unique ability to bond between similar materials, fusion bonding avoids the problem of significant thermal expansion stress caused by inconsistent thermal expansion coefficients between different materials when the device changes temperature.
[0003] Some semiconductor devices include a cavity structure, which is typically formed by growing thermal oxide on a wafer with a trench structure, followed by fusion bonding with another wafer, after which the trench structure is covered by the other wafer. However, growing thermal oxide on a wafer with a trench structure may cause slight bulges at the edges of the trench structure, resulting in large-area void defects at the top edge of the cavity structure after fusion bonding. This leads to bonding failure and affects the performance of the resulting semiconductor device. Summary of the Invention
[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which can improve the performance of the formed semiconductor structure.
[0005] To address the above problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising:
[0006] The provider offers device wafers and bare die wafers, wherein the device wafers include a substrate;
[0007] A trench structure is formed in the substrate of the device wafer, and the top corner of the trench structure is chamfered;
[0008] A second thermal oxidation process is performed on the top of the substrate of the device wafer and the bottom and sidewalls of the trench structure to form a bonding layer;
[0009] The bare die wafer is bonded to the device wafer using a fusion bonding process via the bonding layer; wherein, after the bare die wafer is bonded to the device wafer, the trench structure is covered by the bare die wafer, forming a cavity structure.
[0010] Optionally, the step of forming a trench structure in the substrate of the device wafer includes:
[0011] A patterned hard mask layer is formed on the substrate of the device wafer, and a bowl-shaped opening that is wider at the top and narrower at the bottom is formed in the hard mask layer, with the bottom of the bowl-shaped opening exposed on the top surface of the substrate of the device wafer.
[0012] Using the hard mask layer as a mask, a portion of the thickness of the substrate of the device wafer is etched away to form an initial trench structure;
[0013] After forming the initial trench structure, the remaining hard mask layer is removed;
[0014] After removing the remaining hard mask layer, a second thermal oxidation process is performed on the top of the substrate of the device wafer and the bottom and sidewalls of the initial trench structure to form a sacrificial oxide layer;
[0015] The sacrificial oxide layer is removed using a first wet etching process, thereby forming the trench structure from the initial trench structure.
[0016] Optionally, a patterned hard mask layer is formed on the substrate of the device wafer, the hard mask layer having a bowl-shaped opening that is wider at the top and narrower at the bottom, the bottom of the bowl-shaped opening exposing the top surface of the substrate of the device wafer, including:
[0017] A hard mask material layer and a patterned photoresist layer are formed on the substrate of the device wafer;
[0018] Using the photoresist layer as a mask, a first dry etching process is used to etch away part of the thickness of the hard mask material layer to form an initial opening;
[0019] After the initial opening is formed, the hard mask material layer exposed by the initial opening is removed by a second wet etching process using the photoresist layer as a mask until the top surface of the substrate of the device wafer is exposed, so that the initial opening forms the bowl-shaped opening that is wider at the top and narrower at the bottom, and the hard mask material layer forms the hard mask layer.
[0020] Optionally, during the process of etching away a portion of the thickness of the substrate of the device wafer using the hard mask layer as a mask to form the initial trench structure, the photoresist layer remains on the hard mask layer;
[0021] After the initial trench structure is formed, and before the remaining hard mask layer is removed, the process further includes the step of removing the remaining photoresist layer.
[0022] Optionally, the thickness of the hard mask material layer is 0.8 μm-1 μm.
[0023] Optionally, the etching solution used in the second wet etching process includes a BOE solution.
[0024] Optionally, the molar ratio of hydrofluoric acid to ammonium fluoride in the BOE solution is 1:3 to 1:12.
[0025] Optionally, the etching solution used in the first wet etching process includes a hydrofluoric acid solution.
[0026] Optionally, the thicknesses of the sacrificial oxide layer and the bonding layer are both less than 0.5 μm.
[0027] Optionally, the material of the hard mask layer includes silicon oxide.
[0028] Optionally, the bonding layer may be made of silicon oxide.
[0029] Accordingly, embodiments of the present invention also provide a semiconductor structure, comprising:
[0030] A device wafer, the device wafer including a substrate and a trench structure located in the substrate, the top corner of the trench structure being chamfered;
[0031] A bonding layer is located on the top of the substrate and on the bottom and sidewalls of the trench structure;
[0032] A bare die wafer is bonded to the top of the device wafer via the bonding layer;
[0033] The cavity structure is formed by the trench structure being covered and surrounded by the bare wafer.
[0034] Optionally, the semiconductor structure includes a MEMS device structure.
[0035] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:
[0036] The method for forming a semiconductor structure provided in this embodiment of the invention includes: providing a device wafer and a bare wafer; forming a trench structure in a substrate of the device wafer, wherein the top corner of the trench structure is chamfered; forming a bonding layer on the top of the substrate of the device wafer and the bottom and sidewalls of the trench structure; and achieving bonding between the device wafer and the bare wafer through the bonding layer; wherein, after the bonding between the device wafer and the bare wafer is achieved, the trench structure is covered by the bare wafer, forming a cavity structure.
[0037] In the semiconductor structure formation method provided by this invention, a trench structure is formed in the device wafer, and the top corner of the trench structure is chamfered. After forming bonding layers on the top of the device wafer and the bottom and sidewalls of the trench structure, the bonding layer located at the top corner of the trench structure is correspondingly chamfered. By bonding the bare wafer to the device wafer through the bonding layer, the probability of void defects occurring at the top of the cavity structure formed by the trench structure being covered by the bare wafer can be reduced. Therefore, the semiconductor structure formation method provided by this invention is beneficial to improving the performance of the formed semiconductor structure. Attached Figure Description
[0038] Figures 1 to 11 This is a schematic diagram of the intermediate structure formed in each step of an embodiment of the semiconductor structure formation method provided by the present invention. Detailed Implementation
[0039] As can be seen from the background technology, the performance of current semiconductor structures still needs to be improved.
[0040] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a device wafer and a bare wafer; forming a trench structure in a substrate of the device wafer, wherein the top corner of the trench structure is chamfered; forming a bonding layer on the top of the substrate of the device wafer and on the bottom and sidewalls of the trench structure; and achieving bonding between the device wafer and the bare wafer through the bonding layer; wherein, after the bonding between the device wafer and the bare wafer is achieved, the trench structure is covered by the bare wafer, forming a cavity structure.
[0041] In the semiconductor structure formation method provided by this invention, a trench structure is formed in the device wafer, and the top corner of the trench structure is chamfered. After forming bonding layers on the top of the device wafer and the bottom and sidewalls of the trench structure, the bonding layer located at the top corner of the trench structure is correspondingly chamfered. By bonding the bare wafer to the device wafer through the bonding layer, the probability of void defects occurring at the top of the cavity structure formed by the trench structure being covered by the bare wafer can be reduced. Therefore, the semiconductor structure formation method provided by this invention is beneficial to improving the performance of the formed semiconductor structure.
[0042] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0043] Figures 1 to 11The diagram shows an intermediate structure formed in each step of an embodiment of the semiconductor structure formation method provided by the present invention.
[0044] See Figure 1 The device wafer 100 and the bare wafer 200 are provided, wherein the device wafer 100 includes a substrate 101.
[0045] A device wafer 100 and a bare die wafer 200 are provided to provide a basis for subsequently bonding the bare die wafer 200 onto the device wafer 100.
[0046] In this embodiment, the device wafer 100 is a wafer on which the device fabrication is completed. Specifically, the device wafer 100 can be fabricated using integrated circuit manufacturing technology, such as forming N-type metal-oxide-semiconductor (NMOS) and P-type metal-oxide-semiconductor (PMOS) devices on a substrate through processes such as deposition and etching, and forming dielectric layers, metal interconnect structures, and pads electrically connected to the metal interconnect junctions on the devices.
[0047] In this embodiment, the substrate 101 of the device wafer 100 is a silicon substrate. In other embodiments, the substrate of the device wafer may also be made of other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate. The substrate of the device wafer may also be other types of substrates such as silicon-on-insulator (SiI) or germanium-on-insulator (CHI). The material of the substrate of the device wafer may be a material suitable for process requirements or easy to integrate.
[0048] In this embodiment, the substrate 101 of the device wafer 100 includes a first side (not shown) and a second side (not shown) opposite to the first side. Specifically, the first side is the front side of the substrate 101 of the device wafer 100, and the second side is the back side of the substrate 101 of the device wafer 100.
[0049] In this embodiment, the material of the bare wafer 200 is silicon.
[0050] In other embodiments, the material of the bare wafer may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ide, etc. The bare wafer may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates. The material of the bare wafer may also be a material suitable for process requirements or easy to integrate.
[0051] In this embodiment, the bare wafer 200 includes a third side (not shown) and a fourth side (not shown) that are opposite to each other. Specifically, the third side is the front side of the bare wafer 200, and the fourth side is the back side of the bare wafer 200.
[0052] See Figures 2 to 9 A trench structure 155 is formed in the substrate 101 of the device wafer 100, and the top corner of the trench structure 155 is chamfered.
[0053] In this embodiment, the step of forming the trench structure 155 in the substrate 101 of the device wafer 100 includes: as follows Figure 4 As shown, a patterned hard mask layer 110 is formed on the substrate 101 of the device wafer 100. A bowl-shaped opening 115, wider at the top and narrower at the bottom, is formed in the hard mask layer 110, with the bottom of the bowl-shaped opening 115 exposed above the top surface of the substrate 101 of the device wafer 100. Figure 5 As shown, the substrate 101 of the device wafer 100, with a portion of its thickness removed by etching using the hard mask layer 110 as a mask, forms an initial trench structure 150; as Figure 6 and Figure 7 As shown, after forming the initial trench structure 150, the remaining hard mask layer 110 is removed; as Figure 8 As shown, after removing the remaining hard mask layer 110, a second thermal oxidation process is performed on the top of the substrate 101 of the device wafer 100 and the bottom and sidewalls of the initial trench structure 150 to form a sacrificial oxide layer 170; as Figure 9 As shown, the sacrificial oxide layer 170 is removed by a first wet etching process, so that the initial trench structure 150 forms the trench structure 155.
[0054] In this embodiment, the step of forming a patterned hard mask layer 110 on the substrate 101 of the device wafer 100 includes: as follows Figure 2 As shown, a hard mask material layer 110' and a patterned photoresist layer 120' are formed on the substrate 101 of the device wafer 100; as Figure 3 As shown, using the photoresist layer 120' as a mask, a first dry etching process is employed to etch away a portion of the thickness of the hard mask material layer 110', forming an initial opening 115'; as Figure 4As shown, after the initial opening 115' is formed, the hard mask material layer 110' exposed by the initial opening 115' is removed by a second wet etching process using the photoresist layer 120' as a mask, until the top surface of the substrate 101 of the device wafer 100 is exposed, so that the initial opening 115' forms the bowl-shaped opening 115 which is wider at the top and narrower at the bottom, and the hard mask material layer 110' forms the hard mask layer 110.
[0055] Depending on the material used, the hard mask material layer 110' can be formed using chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes.
[0056] The chemical vapor deposition process can reduce the process cost of forming the hard mask material layer 110' and is conducive to forming a hard mask material layer 110' with a high top surface flatness, thereby providing a better platform for the subsequent formation of the patterned photoresist layer 120'.
[0057] Atomic layer deposition (ALD) enables the hard mask material layer 110' to be formed on the substrate 101 of the device wafer 100 in the form of an atomic layer. This improves the uniformity of the deposition rate, thickness, and structure of the hard mask material layer 110', and also gives the hard mask material layer 110' good coverage, which helps to improve the film quality of the formed hard mask material layer 110'. In addition, the process temperature of ALD is usually low, which also helps to reduce the thermal budget and reduce the probability of wafer distortion and device performance deviation.
[0058] In this embodiment, the hard mask material layer 110' is made of silicon oxide. Silicon oxide is a commonly used material in semiconductor manufacturing processes and has high process compatibility.
[0059] Accordingly, the hard mask material layer 110' is formed using a chemical vapor deposition process. The chemical vapor deposition process includes low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD), etc.
[0060] In other embodiments, the material of the hard mask material layer can also be other suitable materials, such as orthosilicate oxide, which can be selected by those skilled in the art according to actual needs, and no limitation is made here.
[0061] The thickness of the hard mask material layer 110' can be set according to the needs of subsequent etching of the substrate 101 of the device wafer 100. As an example, the thickness of the hard mask material layer 110' is 0.8 μm-1 μm.
[0062] In this embodiment, the step of forming the photoresist layer 120' includes steps such as coating, exposure and development of the photoresist layer.
[0063] The photoresist layer 120' is discretely disposed on the hard mask material layer 110' and is used as an etching mask for patterning the hard mask material layer 110'.
[0064] In this embodiment, the hard mask material layer 110', with the photoresist layer 120' as a mask, is etched using a first dry etching process to remove a portion of its thickness, forming an initial opening 115'. The dry etching process is an anisotropic process; the longitudinal etching rate of the hard mask material layer 110' is much greater than the transverse etching rate, resulting in accurate pattern transfer. Furthermore, the dry etching process is more directional, which helps improve the sidewall morphology quality and dimensional accuracy of the formed hard mask layer 110, thereby improving the sidewall morphology quality and dimensional accuracy of the subsequently formed initial opening 115'.
[0065] It is understood that the depth of the initial opening 115' should not be too large or too small. If the depth of the initial opening 115' is too large, the subsequent removal of the exposed hard mask material layer 110' using the hard mask material layer 110' of the photoresist layer 120 as a mask through a second wet etching process will result in an excessively small opening size for the formed bowl-shaped opening 115. Conversely, if the depth of the initial opening 115' is too small, the opening size of the bowl-shaped opening 115 will be excessively large. Therefore, the depth of the initial opening 115' can be set according to the required opening size of the subsequently formed bowl-shaped opening 115.
[0066] The etching gas and other process parameters used in the first dry etching process can be selected according to the needs of forming the initial opening 115', and are not restricted here.
[0067] After the initial opening 115' is formed, the hard mask material layer 110' exposed by the initial opening 115' is removed by a second wet etching process using the photoresist layer 120' as a mask, until the top surface of the substrate 101 of the device wafer 100 is exposed, so that the initial opening 115' forms the bowl-shaped opening 115 which is wider at the top and narrower at the bottom, and the hard mask material layer 110' forms the hard mask layer 110.
[0068] The second wet etching process is an isotropic etching process, which is relatively low in cost and simple in operation. It can perform isotropic etching on the hard mask material layer 110' exposed by the initial opening 115', thereby forming a bowl-shaped opening 115 that is wider at the top and narrower at the bottom. The bowl-shaped opening 115, which is wider at the top and narrower at the bottom, means that the opening size of the bowl-shaped opening 115 gradually decreases from top to bottom.
[0069] According to the etching requirements for forming the bowl-shaped opening 115, an etching solution with an etching selectivity ratio between the substrate 101 of the device wafer 100 and the hard mask material layer 110' is selected as the etching solution used to perform the second wet etching process.
[0070] In this embodiment, a buffered oxide etching (BOE) solution is used as the etching solution for performing the second wet etching process. Specifically, the BOE solution is a mixed solution of hydrofluoric acid and ammonium fluoride. The parameters of the BOE solution can be configured according to the required etching selectivity between the substrate 101 and the hard mask material layer 110' of the device wafer 100, and are not limited here.
[0071] As an example, the molar ratio of hydrofluoric acid to ammonium fluoride in the BOE solution used in the second wet etching process is 1:3 to 1:12. Setting the molar ratio of hydrofluoric acid to ammonium fluoride within this range allows the BOE solution to significantly improve the etching selectivity of the substrate 101 and the hard mask material layer 110' of the device wafer 100, thereby significantly improving the pattern accuracy and pattern quality of the bowl-shaped opening 115, which in turn helps to improve the pattern integrity of the subsequently formed trench structure 155.
[0072] In this embodiment, using the hard mask layer 110 as a mask, a second dry etching process is employed to etch the substrate 101 of the device wafer 100 to form the initial trench structure 150. Specifically, a deep silicon etching process is used to remove a portion of the substrate 101 of the device wafer 100 exposed by the hard mask layer 110 to form the initial trench structure 150.
[0073] It should be noted that the hard mask layer 110 has a bowl-shaped opening 115 that is wider at the top and narrower at the bottom. After the initial trench structure 150 is etched using the hard mask layer 110 as a mask, a protruding sharp corner (not shown) appears at the top corner of the initial trench structure 150.
[0074] The dimensions of the initial trench structure 150 can be set according to the dimensions of the cavity structure formed subsequently, and are not limited here.
[0075] In this embodiment, after the initial trench structure 150 is formed, the remaining hard mask layer 110 is removed using a first wet etching process. In other embodiments, either a wet etching process or a dry etching process can be used to remove the remaining hard mask layer. Those skilled in the art can choose according to actual needs, and no limitation is made here.
[0076] In this embodiment, during the etching of the substrate 101 of the device wafer 100 using the hard mask layer 110 as a mask and the second dry etching process to form the initial trench structure 150, the remaining photoresist layer 120' remains above the hard mask layer 110. Please refer to [reference needed] for details. Figure 6 .
[0077] The remaining photoresist layer 120' is left above the hard mask layer 110, which can protect the hard mask layer 110 during the second dry etching process, thereby improving the pattern integrity of the subsequently formed initial trench structure 150.
[0078] Accordingly, after forming the initial trench structure 150 and before removing the remaining hard mask layer 110, a step of removing the remaining photoresist layer 120' is also included, as detailed in the reference. Figure 7 Specifically, the remaining photoresist layer 120' can be removed using an ashing process or a wet stripping process.
[0079] In other embodiments, it is also possible to remove the remaining photoresist layer after the hard mask layer has been formed.
[0080] It should be noted that after the initial trench structure 150 is formed, there is a protruding sharp corner at the top corner of the initial trench structure 150. Correspondingly, during the second thermal oxidation process performed on the top of the substrate 101 of the device wafer 100 and the bottom and sidewalls of the initial trench structure 150, the material of the substrate 101 of the device wafer 100 is silicon. The growth rate of silicon and thermal oxidation is proportional to the contact area between them, resulting in a thicker sacrificial oxide layer 170 at the top corner of the initial trench structure 150 due to the presence of the sharp corner.
[0081] Therefore, after the sacrificial oxide layer 170 is removed by an isotropic etching process, and the initial trench structure 150 is formed into the trench structure 155, the sharp corner at the top corner of the initial trench 150 is also removed, making the top corner of the trench structure 155 smoother and chamfered.
[0082] According to the etching requirements for forming the sacrificial oxide layer 170, an etching solution with an etching selectivity ratio between the substrate 101 of the device wafer 100 and the sacrificial oxide layer 170 is selected as the etching solution used to remove the sacrificial oxide layer 170.
[0083] In this embodiment, hydrofluoric acid (HF) solution is used as the etching solution for removing the sacrificial oxide layer 170. The process parameters for the wet etching process to remove the sacrificial oxide layer 170, such as the temperature of the hydrofluoric acid solution and the volume concentration of hydrofluoric acid in the solution, can be configured according to the required etching selectivity between the substrate 101 of the device wafer 100 and the sacrificial oxide layer 170, and are not limited here.
[0084] Reference Figure 10 A first thermal oxidation process is performed on the top of the substrate 101 of the device wafer 100 and the bottom and sidewalls of the trench structure 155 to form a bonding layer 190.
[0085] A first thermal oxidation process is performed on the top of the substrate 101 of the device wafer 100 and the bottom and sidewalls of the trench structure 155 to form a bonding layer 190, which provides a basis for subsequently bonding the bare die wafer 200 to the device wafer 100 by means of the bonding layer 190 using a fusion bonding process.
[0086] In this embodiment, a first thermal oxidation process is performed on the top of the substrate 101 of the device wafer 100 and the bottom and sidewalls of the trench structure 155. That is, the device wafer 100 is placed in an oxidation furnace for thermal oxidation treatment, so that the top surface of the substrate 101 of the device wafer 100 and the bottom and sidewall surfaces of the trench structure 150 form a silicon oxide layer, which serves as the bonding layer 190.
[0087] By selecting silicon oxide as the material of the bonding layer 190, during the melt bonding process, the contact surfaces of the device wafer 100 and the bare wafer 200 can be bonded by Si-O-Si covalent bonds. Since the bond energy of silicon-oxygen bonds is relatively high, the bonding strength can be significantly improved. Furthermore, silicon oxide is a commonly used and low-cost material with high process compatibility. Therefore, selecting silicon oxide as the material for the bonding layer 190 helps reduce process difficulty and cost, and also helps minimize the impact on the performance of the formed semiconductor structure.
[0088] The top corner of the trench structure 155 is chamfered. After performing a second thermal oxidation process on the top of the substrate 101 of the device wafer 100 and the bottom and sidewalls of the trench structure 155, the bonding layer 190 located at the top corner of the trench structure 155 is chamfered accordingly.
[0089] The inventors of this application have discovered that the thickness of the sacrificial oxide layer 170 formed by the second thermal oxidation process and the thickness of the bonding layer 190 formed by the first thermal oxidation process have a significant impact on the bonding quality of the subsequent fusion bonding process. Specifically, by setting the thicknesses of the sacrificial oxide layer 170 and the bonding layer 190 to corresponding values, the height difference between the center anchor point and the bonding ring can be reduced when the device wafer 100 is bonded to the bare die wafer 200 using the subsequent fusion bonding process. This improves the bonding quality of the fusion bonding process, increases the bonding force, and consequently enhances the reliability of the formed semiconductor structure. Therefore, in this embodiment of the invention, the thicknesses of the sacrificial oxide layer 170 and the bonding layer 190 are both less than 0.5 μm.
[0090] See Figure 11 The bare die wafer 200 is bonded to the device wafer 100 by means of the bonding layer 190 using a fusion bonding process; wherein, after the bare die wafer 200 is bonded to the device wafer 100, the trench structure 155 is covered by the bare die wafer 200, forming a cavity structure 155'.
[0091] In this embodiment, the first side of the substrate 101 of the device wafer 100 is bonded to the third side of the bare wafer 200 by means of the bonding layer 190 using a fusion bonding process, thereby realizing the bonding of the bare wafer 200 to the device wafer 100.
[0092] Fusion bonding is a bonding process that mainly utilizes interfacial chemical forces. It helps improve the reliability of the bonding process, which in turn helps to improve the bonding strength between the device wafer 100 and the bare wafer 200. Furthermore, subsequent processes have little impact on the bonding strength, thereby increasing the yield of the formed semiconductor structure.
[0093] The bonding layer 190 at the top corner of the trench structure 155 is chamfered. By bonding the bare wafer 200 to the device wafer 100 through the bonding layer 190, the probability of void defects occurring at the top edge of the cavity structure 155' formed by the trench structure 155 being covered by the bare wafer 200 can be reduced. Therefore, the semiconductor structure formation method in this embodiment of the invention helps to improve the performance (such as reliability) of the formed semiconductor structure.
[0094] Accordingly, embodiments of the present invention also provide a semiconductor structure.
[0095] Please continue to refer to the reference. Figure 11 A semiconductor structure includes: a device wafer 100, including a substrate 101 and a trench structure 155 located in the substrate 101, the top corner of the trench structure 155 being chamfered; a bonding layer 190 located on the top of the substrate 101 of the device wafer 100 and on the bottom and sidewalls of the trench structure 155; a bare wafer 200 bonded to the top of the device wafer 100 by the bonding layer 190; and a cavity structure formed by the trench structure 155 located in the substrate 101 of the device wafer 100 being covered and surrounded by the bare wafer 200.
[0096] In this embodiment, the semiconductor structure is a microelectromechanical system (MEMS) device structure. In other embodiments, the semiconductor structure can also be other types of semiconductor device structures, which are not limited here.
[0097] The semiconductor structure in this embodiment of the invention can be formed by performing the aforementioned semiconductor structure formation method, or other semiconductor structure formation methods can be used to form the semiconductor structure in this embodiment of the invention. For details on the semiconductor structure formation method, please refer to the foregoing description, which will not be repeated here.
[0098] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is accorded the widest scope consistent with the principles and novel features disclosed herein.
[0099] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: The provider offers device wafers and bare die wafers, wherein the device wafers include a substrate; A trench structure is formed in the substrate of the device wafer, and the top corner of the trench structure is chamfered; A first thermal oxidation process is performed on the top of the substrate of the device wafer and the bottom and sidewalls of the trench structure to form a bonding layer; The bare die wafer is bonded to the device wafer using a fusion bonding process via the bonding layer; wherein, after the bare die wafer is bonded to the device wafer, the trench structure is covered by the bare die wafer, forming a cavity structure.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming a trench structure in the substrate of the device wafer includes: A patterned hard mask layer is formed on the substrate of the device wafer, and a bowl-shaped opening that is wider at the top and narrower at the bottom is formed in the hard mask layer, with the bottom of the bowl-shaped opening exposed on the top surface of the substrate of the device wafer. Using the hard mask layer as a mask, a portion of the thickness of the substrate of the device wafer is etched away to form an initial trench structure; After forming the initial trench structure, the remaining hard mask layer is removed; After removing the remaining hard mask layer, a second thermal oxidation process is performed on the top of the substrate of the device wafer and the bottom and sidewalls of the initial trench structure to form a sacrificial oxide layer; The sacrificial oxide layer is removed using a first wet etching process, thereby forming the trench structure from the initial trench structure.
3. The method for forming a semiconductor structure as described in claim 2, characterized in that, A patterned hard mask layer is formed on the substrate of the device wafer. The hard mask layer has a bowl-shaped opening that is wider at the top and narrower at the bottom, with the bottom of the bowl-shaped opening exposed above the top surface of the substrate of the device wafer. This includes: A hard mask material layer and a patterned photoresist layer are formed on the substrate of the device wafer; Using the photoresist layer as a mask, a first dry etching process is used to etch away part of the thickness of the hard mask material layer to form an initial opening; After the initial opening is formed, the hard mask material layer exposed by the initial opening is removed by a second wet etching process using the photoresist layer as a mask until the top surface of the substrate of the device wafer is exposed, so that the initial opening forms the bowl-shaped opening that is wider at the top and narrower at the bottom, and the hard mask material layer forms the hard mask layer.
4. The method for forming a semiconductor structure as described in claim 3, characterized in that, During the process of etching away a portion of the thickness of the substrate of the device wafer using the hard mask layer as a mask to form the initial trench structure, the photoresist layer remains on the hard mask layer; After the initial trench structure is formed, and before the remaining hard mask layer is removed, the process further includes the step of removing the remaining photoresist layer.
5. The method for forming a semiconductor structure as described in claim 3, characterized in that, The thickness of the hard mask material layer is 0.8μm-1μm.
6. The method for forming a semiconductor structure as described in claim 3, characterized in that, The etching solution used in the second wet etching process includes BOE solution.
7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The molar ratio of hydrofluoric acid and ammonium fluoride in the BOE solution is 1:3 to 1:
12.
8. The method for forming a semiconductor structure as described in claim 2, characterized in that, The etching solution used in the first wet etching process includes hydrofluoric acid solution.
9. The method for forming a semiconductor structure as described in claim 2, characterized in that, The thickness of the sacrificial oxide layer is less than 0.5 μm.
10. The method for forming a semiconductor structure as described in claim 2, characterized in that, The material of the sacrificial oxide layer includes silicon oxide.
11. The method for forming a semiconductor structure as described in claim 2, characterized in that, The material of the hard mask layer includes silicon oxide.
12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The bonding layer is made of silicon oxide.
13. A semiconductor structure, characterized in that, include: A device wafer, the device wafer including a substrate and a trench structure located in the substrate, the top corner of the trench structure being chamfered; A bonding layer is located on the top of the substrate and on the bottom and sidewalls of the trench structure; A bare die wafer is bonded to the top of the device wafer via the bonding layer; The cavity structure is formed by the trench structure being covered and surrounded by the bare wafer.
14. The semiconductor structure as described in claim 13, characterized in that, The semiconductor structure includes a MEMS device structure.