Reduction of gate switching instability for semiconductor power switch based on drive signal

Abstract

A circuit (21) can be used as part of an electric drive system having a direct current (DC) voltage source (18), a DC link capacitor (17) and an inverter circuit (11) for powering an electric machine (12). The circuit (21) comprises a driver circuit (15) connected to a gate terminal of a power switch (20), such as a silicon carbide power metal oxide semiconductor field effect transistor (SiC power MOSFET). The power switch (20) has a gate-to-source voltage responsive to the drive voltage (VDR), a degradation interval during which the gate-to-source voltage increases from a relatively low voltage level below the threshold voltage toward a relatively high voltage level above the threshold voltage. The drive circuit (15) is operable to shape a trajectory of the drive voltage (VDR) over a degradation interval such that the drive voltage (VDR) is non-linear over an entire duration of the degradation interval.

Description

Cross-reference to related applications

[0001] This application claims the benefit of priority to U.S. Provisional Application No. 63 / 555,563, filed February 20, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure generally relates to switching control of voltage-controlled semiconductor power switches, and more particularly to gate drive circuitry and associated methods for controlling the on-state of power switches. Background Technology

[0003] High-voltage electric drive systems typically include a direct current (DC) voltage bus connected to a DC power source (e.g., a lithium-ion battery pack or a nickel-metal hydride battery pack). One or more single-phase or multi-phase electric motors can be driven by inverter circuitry connected to the DC voltage bus. The resident semiconductor power switches in the inverter circuitry, as well as in other circuitry of the electric drive system (such as voltage rectifiers and DC-DC converters), employ voltage-controlled semiconductor switches to generate the desired voltage or current waveforms.

[0004] Voltage-controlled power switches can be used in a variety of configurations for a wide range of power electronics applications. For example, the switching circuitry of an electric drive system typically uses a metal-oxide-semiconductor field-effect transistor (MOSFET) as a high-frequency switching device with a drain terminal, a source terminal, and a gate terminal, where the gate terminal acts as the control terminal when the power switch is operated. That is, the gate-to-source voltage is determined by providing a drive voltage to the gate terminal via a drive circuit. This action changes the drain-to-source resistance level of the power switch and alters its on / off conduction state. Summary of the Invention

[0005] The solutions described in this article aim to reduce gate switching instability (GSI) of semiconductor power switches in circuits. (Based on JEDEC...) ® The Solid State Technology Association (SSTA) published a JEDEC report on February 1, 2023. ®Publication number JEP195, "Guideline for Evaluating Gate Switching Instability of Silicon Carbide Metal-Oxide-Semiconductor Devices for Power Electronic Conversion," defines GSI as the undesirable phenomenon of "threshold instability of MOS devices operating in gate-switching mode between voltages well above the threshold voltage and voltages below the flat-band voltage," and thus "describes the degradation of the conduction path of the device driven by switching events." This phenomenon is referred to in the art by various terms, including "AC gate bias stress" and "gate switching stress," with the term "GSI" used herein for consistency of illustration. GSI reduction is achieved in various ways using the solutions described below.

[0006] Specifically, this paper describes a circuit comprising a semiconductor power switch and an associated drive circuit. The power switch, which can optionally be configured as a metal-oxide-semiconductor field-effect transistor (MOSFET), such as a silicon carbide (SiC) power MOSFET, has a threshold voltage (V0). TH ), in response to driving voltage (V DR Gate-to-source voltage (V) GS ) and degradation interval (t deg During internal degradation, the gate-to-source voltage drops from a relatively low voltage level (V). GS_L As the drive voltage increases, this relatively low voltage level has a magnitude lower than / below the threshold voltage. In response to the drive voltage, the gate-to-source voltage moves towards a relatively high voltage level (V) having a magnitude exceeding the threshold voltage. GS_H The drive circuit connected to the gate terminal of the power switch is used to shape or generate a nonlinear trajectory of the drive voltage throughout the entire duration of the degradation interval.

[0007] The drive circuit can optionally be configured as a multi-level drive circuit, for example, a drive circuit with three or more drive circuits.

[0008] The nonlinear trajectory of the driving voltage over the entire duration of the degradation interval may include multiple ramp segments or stepped segments, or the trajectory may be constructed as a periodic oscillating trajectory. In one or more embodiments, the latter implementation may be accomplished using a resonant tank.

[0009] The circuit may also include a reduction circuit configured to reduce the rate of change of the gate-to-source voltage during the degradation interval. Possible implementations of this reduction circuit include: a bleed resistor (R). B The bleed resistor is coupled to the gate terminal of the N-type MOSFET; the diode is connected to the drain terminal of the N-type MOSFET; and the capacitor divider is connected to the bleed resistor and the N-type MOSFET.

[0010] This document also discloses an electric drive system. The electric drive system may include a direct current (DC) power supply connected in parallel with a DC link capacitor; an inverter circuit connected to the DC link capacitor; a multiphase motor connected to the inverter circuit; a rotary output member coupled to the multiphase motor; and a load coupled to the rotary output member.

[0011] In a possible implementation, the inverter circuit includes a plurality of silicon carbide (SiC) power MOSFETs. Each of the respective SiC power MOSFETs has a threshold voltage, a gate-to-source voltage responsive to a drive voltage, and a degradation interval during which the gate-to-source voltage increases from a relatively low voltage level to a relatively high voltage level, as outlined above. In this particular embodiment, a plurality of drive circuits are connected to the respective gate terminals of the different SiC power MOSFETs. The drive circuits are capable of operating together to shape or generate a nonlinear trajectory of the drive voltage throughout the entire duration of the degradation interval.

[0012] The foregoing summary is not intended to represent every embodiment or aspect of this disclosure. Rather, it exemplifies certain novel aspects and features as set forth herein. The foregoing and other features and advantages of this disclosure will become apparent from the following detailed description of representative embodiments and models for carrying out this disclosure, taken in conjunction with the accompanying drawings and appended claims. Attached Figure Description

[0013] The accompanying drawings described herein are for illustrative purposes only, are schematic in nature, and are intended to be exemplary rather than limiting the scope of this disclosure.

[0014] Figure 1 An exemplary inverter circuit for energizing a multiphase motor is illustrated, wherein the inverter circuit uses a voltage-controlled power switch controlled according to the present disclosure to reduce gate switching instability (GSI).

[0015] Figure 2It describes the gate-to-source voltage (V) of the degradation interval as used in this paper. GS ) and gate current (I G (Time graph)

[0016] Figure 3 The baseline drive voltage (V) is illustrated. R The gate-to-source voltage (GVV) may occur without the content of this teaching.

[0017] Figure 3A , Figure 3B and Figure 3C Exemplary drive signals, drive circuitry, and voltage pulses for reducing GSI are illustrated according to one aspect of this disclosure.

[0018] Figure 4A , Figure 4B and Figure 4C An exemplary drive signal, drive circuit, and voltage pulse for reducing GSI via one or more ramp segments, according to another aspect of this disclosure, are illustrated.

[0019] Figure 5A , Figure 5B and Figure 5C An exemplary drive signal, drive circuit, and voltage pulse for reducing GSI via a series of stepped segments, according to another aspect of this disclosure, are illustrated.

[0020] Figure 6 An exemplary drive signal and drive circuit are illustrated for reducing GSI via a periodic oscillation signal.

[0021] Figure 7A and Figure 7B It is a corresponding half-bridge circuit diagram and pulse train according to one aspect of this disclosure.

[0022] This disclosure may be modified or embodied in alternative forms, with representative embodiments shown in the accompanying drawings and described in detail below. The inventive aspects of this disclosure are not limited to the disclosed embodiments. Rather, this disclosure is intended to cover alternatives that fall within the scope of this disclosure as defined by the appended claims. Detailed Implementation

[0023] Referring to the accompanying drawings, the same reference numerals throughout the several views refer to the same or similar parts. Figure 1 The example shown is a multiphase rotating motor (M) E The electric drive system 10 of 12. The electric drive system 10 may include semiconductor power switches 20, each of which is derived from the gate-to-source voltage (V) of the corresponding drive circuit 15 as described herein. GSThe drive circuit (DR) 15 and the power switch 20 together form circuit 21 (e.g., Figure 3B For simplicity, power switch 20, labeled S3, is shown as being driven by drive circuit 15. In actual implementations, as understood in the art, each power switch in power switch 20 will be driven by a corresponding drive circuit 15. Furthermore, although power switch 20 is shown as... Figure 1 This is part of an exemplary AC-to-DC inverter circuit 11, but those skilled in the art will understand that other power electronics can benefit from the use of power switch 20, including, for example, voltage rectifiers, DC-DC converters, etc., and therefore the teachings are not limited to this. Figure 1 Representative uses illustrated in .

[0024] Power switch 20 can be implemented as any voltage-controlled switch that is susceptible to the undesirable effects of gate switching instability (GSI) without the present teachings. Power switch 20, as contemplated herein, can be implemented as a wide-bandgap (WBG) switch, such as a silicon carbide (SiC) power MOSFET. Other voltage-controlled power switches that can benefit from the present teachings include (by example and not limitation) gallium nitride (GaN) switches, insulated-gate bipolar transistors (IGBTs), and silicon controlled rectifiers (SCRs). For consistency of illustration, power switch 20 will be described below in representative embodiments as a SiC power MOSFET, and unless otherwise stated, power switch 20 is not limited to any particular construction.

[0025] In one or more embodiments, the rotating motor 12 can be implemented as an electric traction motor for powering a load in a stationary or mobile system, including phase leads 14, each of which is connectable to an inverter circuit 11. For example, a typical three-phase embodiment of the motor 12 includes three phase leads 14, which are individually labeled "a", "b", and "c" to indicate nominal phases a, b, and c. The electric drive system 10 also includes a positive voltage rail 16. + 16 negative voltage rails - (Electrical ground) and DC link capacitor 17. DC link capacitor 17 is connected to the corresponding positive and negative voltage rails (16). + , 16 - It is configured to receive a DC voltage waveform from a DC voltage source 18, such as a multi-cell electrochemical battery pack having suitable battery chemistry properties such as lithium-ion, lithium metal, nickel metal hydride, etc.

[0026] exist Figure 1Within the inverter circuit 11, multiple power switches 20, also individually labeled S1, S2, S3, S4, S5, and S6, are arranged into multiple switch pairs SP1, SP2, and SP3, namely power switches (S1, S2), (S3, S4), and (S5, S6). Each corresponding switch pair SP1, SP2, and SP3 is connected to the corresponding phase lead in the phase lead 14 of the DC link capacitor 17 and the motor 12. That is, switch pairs SP1, SP2, and SP3 are connected to the nominal a, b, and c phase leads 14 at nodes N1, N2, and N3, respectively. Each power switch 20 is voltage-controlled by a corresponding gate drive circuit. For simplicity, in Figure 1 One of the gate drive circuits is illustrated schematically in the diagram.

[0027] During normal switching operation, phase lead 14 is powered by the switching control operation of inverter circuit 11 to generate motor output torque (T) on rotating output member 120. O However, as a voltage-controlled device, power switch 20 may experience GSI during operation. This situation may be more prevalent in certain configurations of power switch 20, where trench-gate SiC MOSFETs are particularly susceptible to GSI. However, GSI is present at least to some extent in all voltage-controlled power switches, and therefore this teaching is not limited to SiC MOSFETs in general or, in particular, trench-gate SiC MOSFETs.

[0028] Brief reference Figure 2 The graph illustrates time in seconds (s) on the horizontal axis and voltage and current amplitudes in volts (V) and amperes (A) on the vertical axis. Gate switching instability (GSI) is a significant degradation mechanism for long-term operation of voltage-controlled power switches. As expected in this paper, GSI is a dynamic effect that occurs during normal gate drive, when the gate-to-source voltage (V... GS It has a rapid ramp time of less than about 200 nanoseconds (ns) and a voltage rating of about 0.1 volts / ns (V / ns) to 0.3 V / ns. and a peak gate current of approximately 1 ampere or greater (I0). PK Among other potential problems, GSI may cause a threshold voltage (V). TH ) and drain-source on-state resistance (R dson )(exist Figure 2 (Not depicted in the text) A permanent shift over operating time, where this shift can only be recovered at annealing temperatures above approximately 400 degrees Celsius (°C). However, in practice, a junction temperature of 400°C will never be reached during actual applications, and therefore the degradation is irreversible.

[0029] Degradation occurs during conduction and is caused by the interval (t) deg The gate-to-source voltage V is defined as follows: GS (Trace 24) from a relatively low voltage level (V GS_L Ramp up to threshold voltage V TH That is, as understood in the art, the V required to turn on the power switch 20 in both the linear and saturation operating regions. GS A specific value, and continues toward a relatively high voltage level (V). GS_H Threshold voltage (V) from approximately 3V to approximately 6V. TH This is typical. A relatively high voltage level V GS_H Between relatively low voltage levels (V) GS_L ) and threshold voltage (V TH Between ) . Within the degradation interval (t deg During V GS_L More negative values ​​and A larger value of I enhances the aforementioned degradation. G (Trace 25) is also in Figure 2 The diagram shows, and also illustrates, the peak gate current (I0). PK ) and minimum gate current (I 最小 ).reduce Previous solutions, such as increasing the gate resistance, tend to penalize transient power losses and are therefore suboptimal. In contrast, the solution of this invention incorporates a novel driving method to reduce... Without affecting switching losses, thereby reducing Figure 1 GSI in the illustrated controlled power switch 20.

[0030] Brief reference Figure 3 It illustrates the driving voltage (V) for trace 31. DR The signal and the gate-to-source voltage (V) at the gate and source terminals of the controlled power switch when not connected to a load. GS ) signal (trace 33), drive voltage (V DR ) is shown as a voltage level from a relatively low voltage level (V DR_L (e.g., from approximately -3V to approximately -8V) linearly toward relatively high voltage levels (V) DR_H (Typically, it rises from about 15V to about 20V). This rise occurs during the rising ramp interval (t). r Within. Drive voltage (V) DR Maintain a relatively high voltage level (V) during the calibration duration. DR_H Then it returns to a relatively low voltage level (V). DR_L ), where the trajectory occurs during the descending ramp interval (t f )Inside.

[0031] The corresponding gate-to-source voltage (V GS ) is exemplified as occurring during the aforementioned degradation interval (t). deg From a relatively low voltage level (V) GS_L The parabola rises through the defined threshold voltage (V) TH ), where V GS_L From approximately -3V to approximately -8V (as noted above) DR_L (same as above), continue in this manner until a relatively high voltage level (V) is reached. GS_H For example, approximately 15V to approximately 20V. When the power switch 20 is commanded to turn off, i.e., with the drive voltage signal (V... DR ) descending slope interval (t) f At the start of ), the gate-to-source voltage (V GS The voltage then quickly drops back to a relatively low level (V). GS_L ).

[0032] In comparison, Figure 3A The trace 30 indicates from Figure 1 The alternative drive voltage (V) from the drive circuit 15 to the gate contact of the corresponding power switch 20 DR ) signal. Drive voltage (V) DR ) during the aforementioned degradation interval (t deg (i.e., the switching interval of power switch 20) from a relatively low voltage level (V) DR_L The voltage level rises to a relatively high level (V). DR_H According to this disclosure, from V DR_L To V DR_H The slope in the degradation interval (t deg The timescale is nonlinear and therefore not constant. That is, while portions or segments of the generated trajectory may vary over the entire degradation interval (t...), the timescale is not constant. deg It increases linearly during the period, but during the degradation interval (t) deg The trajectory acquired over the entire duration of ) is generally nonlinear. Conversely, as shown, the degradation interval (t) deg It is divided into several intervals t r1 t 弛豫 and t r2 In this case r Indicates the rising trajectory. Then, a relatively high voltage level (V) DR_H Maintain for a predetermined duration until the drive voltage (V) indicated by trace 30 is reached. DR The slope drops back to a relatively low voltage level (V). DR_L This occurs during the duration of the descent. t f Inside, among whichf This represents the descent trajectory.

[0033] Figure 3A Trace 32 represents the gate-to-source voltage (V). GS Similarly, each has a representative low voltage V GS_L and high voltage V GS_H Threshold voltage (V) TH This is also illustrated as the minimum voltage required to turn on power switch 20 and thereby allow current to flow between the source and drain terminals. During the degradation interval (t... deg The nonlinear trajectory of the trace 30 over its entire duration may include a plateau segment 34, wherein a pair of ramp segments (R1, R2) are connected by the plateau segment 34. Therefore, relative to... Figure 3 The resulting trajectories of traces 33 and 32 provide a reduced GSI level.

[0034] Figure 3A The implementations of traces 30 and 32 can be achieved by using the relaxation time interval (t) 弛豫 Add to it V TH >V DR_R >V DR_L The solution is to use the driving voltage V. DR From V DR_L Inclined up to V DR_R Time (i.e., t) r1 ) plus V DR-R Platform time (t) 弛豫 ) than usually from V DR_L Directly ascend to V DR_H The time spent is long, that is, t r1 +t 弛豫 >t r The actual increase depends on the application and is customizable. The drive voltage (V) DR From V DR_R Inclined up to V DR_H The time, i.e., t r2 It is usually not longer than t r , i.e. t r2 t r In addition, V GS From V GS_L Inclined up to V TH The time, i.e., t deg In contrast Figure 3 The time is longer, thus reducing GSI. This increases the drive voltage (V) DR From V TH Inclined up to V GS_H The time is equal to or less than Figure 3 The baseline level, which ensures that when Figure 1 The switching losses of the power switch 20 do not increase when operating on a load. Generally speaking, t r t f and t r2 Roughly equal, ranging from about 1 ns to 20 ns, while t r1 With t 弛豫 They are roughly equal, ranging from approximately 10 ns to 200 ns.

[0035] exist Figure 3B The text shows what is suitable for providing Figure 3A A representative embodiment of the drive circuit 15 for the trajectory. Instead of a single driver, in this embodiment, the drive circuit 15 is configured as a corresponding first drive circuit 150 and a second drive circuit 250 (DR1 and D2). For a power switch 20 having a gate terminal (G), a source terminal (S), and a drain terminal (D), the corresponding first drive circuit 150 and the second drive circuit 250 are connected to the corresponding gate terminal (G) and source terminal (S), wherein the connection to the gate terminal (G) is through the gate resistor (R) of circuit 21. G 35 (see also) Figure 3B ), which may be part of the drive circuit 15.

[0036] The first driving circuit 150 and the second driving circuit 250 each have a corresponding local voltage source 180 or 280. For example, Figure 3A V DR_R It can be supplied by a local voltage source 280, where the low voltage (V) DR_L (This is supplied by another local voltage source 380. Voltage source 180 has V...) DR_H -V DR_R The corresponding voltage level. Input pulse (V IN1 and V IN2 ) are provided to the corresponding drive circuits 150 and 250 to generate Figure 3C Pulses 36A and 36B. Note that pulse 36A (i.e., V...) IN1 )Lapse pulse V IN2 Figure 3A The duration t shown and described above 弛豫 An optional resonant circuit 46 can be added to the drive circuit 15 to produce the following (see reference below). Figure 6 The described oscillation signal.

[0037] In other embodiments within the scope of this disclosure, modifications may be made. Figures 3A to 3C The method. For example, such as Figure 4A The trajectories of traces 300 and 320 in the image (respectively V) DR and V GS As shown, it can be implemented. Figure 3AThe method, where the interval t 弛豫 Approaching zero, making V DR and V GS The trajectory lacks a platform. In other words, the interval t r1 Formation of degradation interval t deg Most of the degradation intervals, while t deg The remaining part is the duration t r2 .

[0038] exist Figure 4B The text shows what is suitable for providing Figure 4A The representative drive circuit 15A of the trajectory. As shown, drive circuit 15A is configured as a first drive circuit 150. For a power switch 20 having a gate terminal (G), a source terminal (S), and a drain terminal (D), the first drive circuit 150 is driven by a gate resistor (R). G )35 is connected to the gate terminal (G). Voltage source 480 provides a relatively high voltage (V) to the first drive circuit 150. DR_H ), where a low voltage (V) is provided via voltage source 380. DR_L In this single-drive implementation, including... Reduce circuit 38 when V GS <V TH Time decrease .

[0039] like Figure 4C As shown, Figure 4B Used to reduce The reduction circuit 38 can be implemented as a reduction circuit 380 having various circuit components. For example, the reduction circuit 380 may include a MOSFET 200, such as a low-voltage N-type MOSFET, which is configured to interrupt the V of the power switch 20 for short intervals. GS Slope ratio, thus generating t 弛豫 Low-voltage diode 40 can be used to help prevent current from flowing to... Figure 4B The first drive circuit 150 includes a low-voltage diode 40 that acts as a parasitic element when the drive signal is negative. A capacitive voltage divider 42, shown as capacitors C1 and C2, is used to adjust the amplitude of the drive signal to activate the power switch 20. A bleed resistor (R) is also shown. B 44 can be connected to the gate (G) to ensure that the power switch 20 is in the on state only for short time intervals. This is contemplated within the scope of this disclosure. Figure 4B Other embodiments of the reduction circuit 38, and therefore Figure 4C The method described is exemplary and does not limit the content of this teaching.

[0040] Now for reference Figure 5ATraces 300A and 320A indicate the driving voltage used for shaping (V). DR ) and gate-to-source voltage (V GS Another alternative implementation of the trajectory of ). In this method, the driving voltage (V) DR The increase of ) in the degradation interval (t) deg Within this range, it occurs as a series of steps and ramps. That is, for trace 300A, i.e., from V... DR_L To V DR_H The low-to-high voltage transition can be completed within a duration of t. r1 The internal voltage reaches the intermediate voltage level V DR_R1 , where the interval t 弛豫 This is used to complete multiple step increases, which may correspond to different voltage levels and different time intervals, i.e., to level V. DR_R2 and V DR_R3 Then, trace 300A can be applied at interval t. r2 The voltage V rises to a relatively high level due to the inward slope. DR_H The driving voltage (V) DR After this, it reaches a plateau until the power switch 20 is in the descent interval t. f The internal circuit is turned off. This is due to the gate-to-source voltage (V...). GS From a relatively low voltage (V) GS_L Increase to the threshold voltage (V) TH ), in the degradation interval (t deg The corresponding effect of the trace 320A within the trace is a series of lobes or bending steps.

[0041] Any drive voltage level (V) used to perform this series of steps DR_Ri Condition V should be satisfied. TH >V DR_Ri >V DR_L The time required for a ramp between such steps is related to each V. DR_Ri The sum of platform time can be defined as follows:

[0042] exist Figure 5B The diagram shows what can be used to implement Figure 5A Possible hardware implementations of the traces 300A and 320A. Here, the drive circuit 15B can be configured as a plurality of drive circuits 150, 250, ..., 250n, i.e., DR1, DR2, ..., DRn. As explained above, the first drive circuit 150 is connected to the power switch 20 via the gate resistor 35. As shown, individual voltage sources 480 and 580 can be connected to the corresponding drive circuits 150, 250, ..., 250n, wherein voltage sources 480 and 580 have the indicated voltage value, i.e., V.DR_Ri (For voltage source 480) and V DR_H -……-V DR_Ri-1 -V DR_Ri For a non-limiting implementation using three drivers, using driver circuit 15B will produce... Figure 5C The pulses 36A, 36B, and 36n, i.e., V IN1 V INi-1 and V INi Pulses 36A, 36B, ..., 36n are activated at different times to provide... Figure 5A The desired trajectory, for example, where pulse 36A at t 弛豫 Then it begins, and pulse 36B starts earlier than pulse 36A, that is, the duration t after pulse 36n starts. 弛豫i Then it begins.

[0043] Now for reference Figure 6 The traces 300B and 320B, as taught herein, can be implemented as periodic oscillating signals, instead of... Figure 3A , Figure 4A and Figure 5A The aforementioned stepped and / or sloping distribution. That is, not within the degradation interval (t... deg The driving voltage (V) with a linear trajectory is used throughout the entire duration. DR ) and gate-to-source voltage (V GS Instead, it can generate a medium driving voltage (i.e., V). DR_R ( ) is a periodic oscillation signal.

[0044] This is intended as an example, not a limitation, and will be briefly referenced again. Figure 3B The drive circuit 15B can be used to generate by adding the resonant circuit 46 to its topology. Figure 6 The oscillation signal. In this embodiment, the output of the second drive circuit 250 can be connected to the resonant circuit 46, such that the resonant circuit 46 is connected to the second drive circuit 250 and to the source terminal (S) of the power switch 20. As understood in the art, the gain control of the resonant circuit 46 can be used to generate a sine wave by filtering out harmonics and outputting a sine wave. Figure 6 The oscillation signal.

[0045] As understood in the art, the resonant circuit 46 (also referred to in the art as a resonant circuit or tuning circuit) is an inductor-capacitor (LC) circuit that determines the oscillation frequency and sustains oscillation via positive feedback. The resonant circuit 46 can be constructed, for example, from a capacitor, a resonant inductor, a magnetizing inductor, and a transformer. In a possible implementation, the resonant inductor is arranged in series with the resonant capacitor and transformer, while the magnetizing inductor is connected in parallel with the resonant capacitor and transformer. The resonant circuit 46 has a resonant frequency... The resonant capability. At the resonant frequency, the inductive reactance and capacitive reactance are equal in amplitude and opposite in sign, thus canceling each other out. Therefore, the impedance of the resonant circuit 46 is purely resistive and is determined solely by the losses in the inductor and capacitor.

[0046] Now for reference Figure 7A A half-bridge 50 can replace Figure 1 The inverter circuit 11 is used to implement a DC-DC converter, wherein the half-bridge circuit 50 is controlled via any of the drive signal methods described above in the drive signal method of the present invention. The signal can be generated as a drive voltage (V) for each power switch in the power switches 20 used in the half-bridge 50. DR1 V DR2 In this case, power switches 20A and 20B are used. Drive circuits 15-1 and 15-2 can be used to provide drive voltages (V) to the corresponding power switches 20A and 20B. DR1 V DR2 Load resistance (R) L 135 represents the resistance of the coupled load. Other components of a typical half-bridge 50 include inductor (L) 37 and voltage source 18.

[0047] therefore, Figure 7A The half-bridge 50 can be used to generate Figure 7B The pulse trains 35D and 35E. Here, t r1 and t 弛豫 Embedded within the dead time (DT), that is, the period during which the power switches 20A and 20B of the half-bridge circuit 50 are not conducting. As noted above, t r1 and t 弛豫 The representative value is approximately 10 ns to approximately 200 ns. In contrast, the dead time (DT) can be on the order of approximately 300 ns to approximately 800 ns. Therefore, Figure 7B It was not drawn to scale, but exaggerated for clarity.

[0048] Therefore, the above solution can be used to reduce GSI in SiC power MOSFETs and other voltage-controlled power switches 20. By implementing... Figure 3A , Figure 4A , Figure 5A and Figure 6 Various driving methods, for example, in such Figure 7A In the half-bridge 50 shown, in Figure 1 In the electric drive system 10, or in other electrical systems, threshold voltage (V) can be avoided. TH ) and on-state resistance (R dson The permanent offset of ). This is achieved by reducing This is achieved without affecting switching losses. Those skilled in the art who benefit from this teaching will understand these and other accompanying benefits.

[0049] While several models for carrying out many aspects of this teaching have been described in detail, those skilled in the art to which this teaching pertains will recognize various alternative aspects for practicing this teaching within the scope of the appended claims. The above description and figures are illustrative and exemplary, covering the entire range of alternative embodiments implied by the included content, structurally and / or functionally equivalent to the included content, or otherwise apparent based on the included content, and are not limited to those embodiments explicitly depicted and / or described.

[0050] Furthermore, this concept explicitly includes combinations and sub-combinations of the described elements and features. The detailed description and accompanying drawings support and describe this teaching, the scope of which is defined only by the claims. For example, approximate terms such as “about,” “almost,” “substantially,” “roughly,” “approximately,” etc., may herein mean “at, near, or close to,” or “within the range of 0 to 5%,” or “within acceptable manufacturing tolerances,” or any logical combination thereof.

Claims

1. A circuit (21), the circuit comprising: Power switch (20), the power switch having a threshold voltage (V TH ), in response to the drive voltage (V) to the power switch (20) DR Gate-to-source voltage (V) GS ), degradation interval (t) deg During the degradation interval, the gate-to-source voltage (V GS From below the threshold voltage (V TH The relatively low voltage level (V) GS_L ) toward a voltage higher than the threshold voltage (V TH The relatively high voltage level (V) GS_H )Increase; and A drive circuit (15) is connected to the gate terminal of the power switch (20), wherein the drive circuit (15) is operable to operate during the degradation interval (t) deg The driving voltage (V) is generated throughout the entire duration of the process. DR The nonlinear trajectory of .

2. The circuit (21) according to claim 1, wherein the driving circuit (15) is configured as a multi-level driving circuit (15).

3. The circuit (21) according to claim 2, wherein the multilevel driving circuit (15) comprises three or more driving circuits (15).

4. The circuit (21) according to claim 1, wherein the power switch (20) comprises a metal-oxide-semiconductor field-effect transistor (MOSFET).

5. The circuit (21) according to claim 4, wherein the MOSFET is a silicon carbide (SiC) power MOSFET.

6. The circuit (21) according to claim 1, wherein in the degradation interval (t) deg The driving voltage (V) throughout the entire duration of the driving voltage (V) DR The trajectory of the ) includes multiple slope segments (R1, R2).

7. The circuit (21) according to claim 6, wherein a pair of ramp segments (R1, R2) of the plurality of ramp segments are connected by a platform segment (34).

8. The circuit (21) according to claim 1, wherein the driving voltage (V) DR ) in the degradation interval (t deg The trajectory over the entire duration of the event comprises multiple stepped segments.

9. The circuit (21) according to claim 1, wherein the driving circuit (15) includes a reduction circuit (38), the reduction circuit being configured to reduce the degradation interval (t) deg During the period of reducing the gate-to-source voltage (V) GS rate of change () ).

10. The circuit (21) according to claim 9, wherein the reduction circuit (38) comprises: N-type metal-oxide-semiconductor field-effect transistor (MOSFET) (200); bleed resistor (R) B (44), the bleed resistor is coupled to the gate terminal of the N-type MOSFET; diode (40), the diode is connected to the drain terminal of the N-type MOSFET; and capacitor divider (42), the capacitor divider is connected to the bleed resistor (44) and the N-type MOSFET.

11. The circuit (21) of claim 1, wherein the driving circuit (15) includes a resonant circuit (46) and is operable to control the driving voltage (V) via the resonant circuit (46). DR The trajectory of the driving voltage (V) is shaped to make the driving voltage (V) DR ) in the degradation interval (t deg The entire duration of the event has a periodic oscillating trajectory.

12. An electric drive system (10), the electric drive system comprising: DC voltage source (18); DC link capacitor (17), which is connected in parallel with the DC voltage source (18); Inverter circuit (11), the inverter circuit being connected to the DC link capacitor (17) and having: Multiple silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) (20), each of the SiC power MOSFETs (20) having a threshold voltage (V TH ), in response to driving voltage (V DR Gate-to-source voltage (V) GS ), degradation interval (t) deg During the degradation interval, the gate-to-source voltage (V GS From below the threshold voltage (V TH The relatively low voltage level (V) GS_L ) toward a voltage higher than the threshold voltage (V TH The relatively high voltage level (V) GS_L )Increase; and Multiple driving circuits (15), each of which is connected to a corresponding gate terminal of a different SiC power MOSFET in the SiC power MOSFET (20), wherein the driving circuits (15) are capable of cooperating to achieve the degradation interval (t deg The driving voltage (V) is generated throughout the entire duration of the process. DR The nonlinear trajectory of ) A multiphase motor (12) is connected to the inverter circuit (11). A rotary output component (120) is coupled to the multiphase motor (11). and The load is a load resistor (135) coupled to the rotating output member (120).

13. The electric drive system (10) according to claim 12, wherein the plurality of drive circuits (15) are coupled to the respective gate terminals via gate resistors.

14. The electric drive system according to claim 12, wherein the drive voltage (V) DR ) in the degradation interval (t deg The trajectory over the entire duration of the event includes multiple ramp segments.

15. The electric drive system according to claim 12, wherein the drive voltage (V) DR ) in the degradation interval (t deg The trajectory over the entire duration of the event comprises multiple stepped segments.

16. The electric drive system of claim 12, wherein the plurality of drive circuits (15) includes a reduction circuit (38), the reduction circuit being configured to, during the degradation interval (t) deg During the period of reducing the gate-to-source voltage (V) GS rate of change () ).

17. The electric drive system of claim 12, wherein at least one drive circuit in the drive circuit (15) includes a resonant circuit (46) operable to convert the drive voltage (V) DR ) in the degradation interval (t deg The trajectory over the entire duration is generated as a periodic oscillating trajectory.

18. A circuit (21) for use with a silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistor (MOSFET), the circuit comprising: Gate resistor (35); and Multiple drive circuits (15) coupled to the gate terminal of the SiC power MOSFET via the gate resistor (35), wherein the drive circuits (15) are capable of operating together to maintain a degradation interval (t deg The SiC power MOSFET generates a drive voltage (V) inside the MOSFET. DR During the degradation interval, the gate-to-source voltage (V GS From below the threshold voltage (V) of the SiC power MOSFET TH The relatively low voltage level (V) GS_L ) toward the threshold voltage (V) higher than that of the SiC power MOSFET TH The relatively high voltage level (V) GS_H The increase in the driving voltage (V) causes the driving voltage (V) to increase. DR The trajectory of ) in the degradation interval (t deg The entire duration is non-linear and includes multiple ramp sections or multiple stepped sections.

19. The circuit (21) of claim 18, wherein the circuit (21) includes a reduction circuit (38) configured to reduce the degradation interval (t) deg During the period of reducing the gate-to-source voltage (V) GS rate of change () ), and the reduction circuit (38) said therein includes: N-type MOSFET (200); Bleeding resistor (R) B (44), the bleed resistor is coupled to the gate terminal of the N-type MOSFET (200); the diode (40) is connected to the drain terminal of the N-type MOSFET (200); and the capacitor divider (42) is connected to the bleed resistor (44) and the N-type MOSFET (200).

20. The circuit (21) according to claim 18, further comprising: Resonant circuit (46), wherein the plurality of drive circuits (15) are operable via the resonant circuit (46) at the degradation interval (t deg The driving voltage (V) outputs a periodic oscillating trajectory throughout the entire duration of the specified duration. DR ).

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