On-chip game engine

Abstract

An electronic chip and a chip assembly are described. An electronic chip includes one or more processing cores and at least one hardware interface coupled to at least one of the one or more processing cores. At least one of the one or more processing cores implements an engine in hardware.

Description

[0001] This application is a divisional application of patent application filed on September 16, 2016, with application number 201680053259.X and invention title "Game Engine on a Chip".

[0002] Cross-reference to related applications This application claims the benefit of Provisional Application No. 62 / 220,167, filed September 17, 2015, and Provisional Application No. 62 / 219,593, filed September 16, 2015, the disclosures of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to an electronic chip or chip assembly. More specifically, this disclosure relates to a game engine implemented in hardware on an electronic chip or chip assembly. This disclosure may also relate to a system-on-a-chip or a system-in-package. Background Technology

[0004] Game engines play an increasingly important role in graphics applications. A primary task of software game engines is to deliver the most realistic and highest quality graphics possible with real-time performance. Software game engines are typically provided as computer-executable code that executes on a central processing unit (CPU). For example, game engines can often run on the processor or microprocessor of a computing device, such as the CPU of a personal computer, console, mobile phone, or tablet. Therefore, the performance of the CPU can determine the performance of the software game engine.

[0005] Software game engines can also access the graphics processing unit (GPU). For example, a GPU can render a list of individual objects to graphics memory or video memory at extremely high performance. A computer graphics scene can include a large number of objects with properties related to their position and orientation, behavior, material properties, and so on. To achieve highly realistic scenes, game engines need to consider panoramas, which may often contain millions of objects that will be rendered to the screen. For example, a game engine may consider the behavior and interactions between light and individual objects, as well as objects within the scene.

[0006] Furthermore, to address the increasing complexity of computer graphics scenarios, display resolutions are rapidly increasing. Standards include Full HD 1920×1080 pixels, Ultra HD 3840×2160 pixels, and others. This trend is expected to continue. For example, virtual reality headsets with horizontal resolutions exceeding 10,000 pixels are currently under development for the consumer market. The result is an explosive growth in performance requirements.

[0007] To achieve real-time target rendering and keep up with increasing demands, software game engines can balance imperceptible quality loss with improved performance. One way to do this is by dividing individual tasks into subtasks, particularly those that can be executed efficiently on GPUs. Graphics tasks can be parallelized across multiple CPUs. Currently, the typical number of CPUs per personal computer is only two, and the typical number of GPUs is only one; these numbers have not increased in recent years. Therefore, graphics software cannot rely on a sufficient number of CPUs and / or GPUs. Furthermore, even with a large number of CPUs available, multi-CPU subsystems are often too energy-efficient for specific tasks. Therefore, even parallel execution may be limited by currently available hardware.

[0008] However, parallel execution of tasks also requires a complete redefinition of the software layer between the graphics software application, which typically resides on one side, and the GPU driver, which typically resides on the other. Examples of such redefined interface layers include programming interfaces such as Mantle (available from Advanced Micro Devices (AMD), DirectX 12 (available from Microsoft), Metal (available from Apple), and Vulkan (available from Khronos Group). These interfaces share the common feature of interacting with the GPU at a much lower level for efficiency. However, there is a trade-off between the increased efficiency and the increased complexity of the programming interfaces. Therefore, it is expected that only a small number of experienced graphics programmers will actually use these new high-performance interfaces. For less demanding graphics software, the older, simpler interfaces are preferable.

[0009] Therefore, the purpose of this disclosure is to provide graphics processing that meets the requirements for complexity and efficiency. Summary of the Invention

[0010] This invention is provided to introduce some concepts in a simplified form, which are further described in the following detailed description. This invention is not intended to identify key features of the claimed subject matter, nor is it intended to be used to help determine the scope of the claimed subject matter.

[0011] As described in this article, this problem is addressed through embodiments of electronic chips and chip components.

[0012] A first aspect of this disclosure is an electronic chip comprising one or more processing cores and at least one hardware interface coupled to at least one of the one or more processing cores, wherein at least one of the one or more processing cores implements a game engine.

[0013] The verb "implement" used throughout this application refers to hardware implementation. Therefore, the processing core may include multiple electronic circuits configured to implement the functions of a game engine. The processing core of the chip implementing the game engine should not be interpreted as a central processing unit capable of executing instructions from a software game engine. More precisely, the processing core implementing the game engine is a dedicated electronic circuit that implements or performs the functions of a game engine in hardware. Therefore, the game engine can also be considered a hardware game engine, a hardwired game engine, or an on-chip game engine. Thus, the electronic chip can be referred to as an engine-on-chip (EOC). The processing core may implement the game engine as multiple hardwired electronic circuits that perform the functions, which can be arranged or assembled according to any suitable manufacturing process. Furthermore, a configured field-programmable gate array (FPGA) can be used to implement the game engine in hardware. The electronic chip can be provided as an integrated circuit that integrates all components and functions of the hardwired game engine into a single chip or multiple chips.

[0014] The processing core of an electronic chip can be considered a functional unit or module of its electronic circuitry. For example, at least one of the one or more processing cores can be implemented as an FPGA or any other form of integrator circuit that implements a specific function. Therefore, an electronic chip includes at least one integrated circuit that implements at least some of the one or more processing cores, wherein at least one of the processing cores implements a hard-wired game engine.

[0015] At least one hardware interface enables direct interaction with one or more processing cores, such as direct interaction with a hard-wired game engine. The hardware interface can be implemented as part of at least one integrated circuit of an electronic chip. However, the hardware interface can also be implemented as one or more further integrated circuits that provide connectivity to the processing cores, including the hard-wired game engine.

[0016] This disclosure provides support for efficient, real-time, and highly realistic rendering by implementing a game engine in hardware. While dedicated 3D graphics hardware allows electronic chips to be used to support the CPU of a host system, such as a console or mobile device, hardware control is simplified because the game engine's interface is readily available due to the hardware-based implementation. Therefore, general graphics programmers who need to write high-performance and highly realistic applications can use a hardwired game engine that maintains a simple interface while providing highly realistic real-time rendering options.

[0017] Preferably, the hardwired game engine may include a core that implements hardwired algorithms and code functionality applicable to datasets. This can also enable faster 2D, 3D, or 4D (3D plus time) graphics or simulation results, and even stereoscopic displays. The dataset processed by the game engine core can be fed to a graphics processing unit or a central processing unit for further processing, which may be located on the chip or provided through the main system.

[0018] In one embodiment, at least one of the processing cores implements a ray tracing engine (in hardware). A ray tracing engine can also be considered a hardwired ray tracing engine. Similar to a game engine, a ray tracing engine can be implemented in hardware by one or more dedicated electronic circuits, such as integrated circuits, one or more FPGAs, etc., to enable ray tracing functionality.

[0019] In a further embodiment, the game engine is coupled to a ray tracing engine, which is configured to extend the functionality of the game engine. The ray tracing engine can be a dedicated ray tracing engine for the game engine. Ray tracing tasks for the game engine can be offloaded to the ray tracing engine. However, multiple game engines implemented on a chip can also share a single or multiple ray tracing engines, where multiple game engines can offload their ray tracing tasks to a shared ray tracing engine. The game engine and the ray tracing engine can be directly coupled to each other, or coupled to each other using multiple caches, such as dedicated memory and / or dedicated command channels, where the game engine can write data to the dedicated memory and issue commands through the command channels to trigger processing by the ray tracing engine. By directly coupling the game engine and the ray tracing engine using dedicated components, data exchange speed and throughput can be significantly improved and optimized because data exchange can be performed via short data links and does not require the implementation of complex data exchange protocols.

[0020] In yet another embodiment, multiple processing cores implement multiple game engines and multiple ray tracing engines, wherein each of the multiple game engines is associated with one or at least one of the multiple ray tracing engines. Preferably, the associated ray tracing engine is a dedicated ray tracing engine for each game engine. Thus, each game engine can have a dedicated ray tracing engine to offload various ray tracing tasks to the ray tracing engine. The dedicated ray tracing engines used throughout this disclosure support a variety of algorithms not typically supported by ray tracing engines. For example, a dedicated ray tracing engine can enable voxel-space-based cone tracing for global illumination. Alternatively or as an alternative, a dedicated ray tracing engine can support G-buffer-based tracing algorithms, such as screen-space reflection mapping and parallax mapping. Thus, algorithms can be supported by a dedicated ray tracing engine rather than the game engine itself.

[0021] In another embodiment, at least one of the processing cores implements a central processing unit (CPU). Therefore, at least one processing core can be electronic circuitry that executes instructions of a computer program by performing basic arithmetic, logic, control, and input / output (I / O) operations. The CPU's functionality can be the same as or similar to that of an existing CPU. The CPU can allow software based on an instruction set architecture to execute directly on the electronic chip. The software can be specifically designed for game engine processing. However, it is understood that the CPU is not limited to game engine processing; more precisely, it can execute any kind of software that can expand the functionality of the electronic chip. The electronic circuitry can be included on a single electronic chip in any combination: at least one microcontroller, at least one microprocessor, or at least one digital signal processor (DSP). To enable the operation of the central processing unit (CPU), the electronic chip may further include, in any combination, a memory block selected from ROM, RAM, EEPROM, and / or flash memory; a timing source including an oscillator and a phase-locked loop; peripherals including a counting timer, a real-time timer, and a power-on reset generator; external interfaces such as USB, FireWire, Ethernet, SPI, etc.; analog interfaces including ADCs and DACs; voltage regulators; and power management circuitry. Some of these components may form part of the electronic circuitry implementing at least one processing core, while others may be separate and dedicated components of the electronic chip implemented by one or more electronic circuits that implement the required functions, wherein the at least one processing core implements the CPU. The game engine may be directly coupled to the CPU and / or may utilize cache or memory to exchange data between the CPU and the game engine. The CPU may also further include an interface for direct coupling to the hard-wired game engine. By using dedicated data links and / or caches to couple the game engine and the CPU, data exchange speed and throughput can be significantly improved and optimized because data exchange can be achieved through short data links and without the need to implement complex data exchange protocols.

[0022] In a further embodiment, multiple processing cores implement multiple central processing units, each configured to execute instructions of a different instruction set architecture. Therefore, the electronic chip can execute software on a separate central processing unit, which can be compiled for different systems, including but not limited to Intel's x86 architecture commonly used in personal computer systems, and ARM-based instruction set systems commonly used in mobile phones and tablets. Thus, the electronic chip can be used in heterogeneous environments that provide a unified access to a well-defined game engine interface for a wide range of software, without requiring software adaptation to a specific instruction set architecture.

[0023] According to one embodiment, the game engine is configured to transmit data to an external GPU via a hardware interface. The game engine can receive data from an external entity, such as a CPU or GPU, via the hardware interface. The game engine can also send processed data to the aforementioned external entity or another external entity via the hardware interface. Preferably, the hardware interface can be a bus interface or an external interface. The processed data can be provided to the external GPU for further processing and / or rendering on a target display.

[0024] In yet another embodiment, at least one of the processing cores implements a graphics processing unit (GPU). Therefore, the GPU can be considered a hard-wired GPU on an electronic chip. At least one hardware interface may include a media interface such as HDMI, which can provide data rendered by the on-chip GPU to a display or screen. However, it is understood that the GPU may also be connected via a hardware interface to the main system's bus or other interconnects to provide rendered data for display.

[0025] In another embodiment, the game engine is configured to generate data for the graphics processing unit (GPU). The game engine can preprocess input data suitable for processing on the GPU's dedicated hardware, such processing including SIMD processing or vector processing known in the art. The preprocessed data can be provided to the on-chip GPU, which can further process the data and / or generate a final rendering of the graphical scene based on the preprocessed data. The GPU can also provide results to the game engine for further processing. Therefore, the game engine can prepare data or datasets and offload specific tasks to the GPU to utilize GPU capabilities or the GPU's dedicated hardware.

[0026] According to one embodiment, the electronic chip may include memory, wherein the game engine is configured to provide data to the graphics processing unit (GPU) via the memory. For example, the game engine may store pre-processed data in the memory and may issue commands to the GPU to read and further process the data. The GPU may use the memory or different communication channels to transmit results to the hard-wired game engine. Registers or register sets may be used to control the properties of the memory, indicate the characteristics of the stored data, and / or control the operation of the GPU.

[0027] In another embodiment, the graphics processing unit (GPU) is connected to video memory, and the game engine is configured to provide data to the GPU via the video memory. The on-chip GPU can be connected to dedicated video memory used internally by the GPU to load, store, or cache data during GPU processing. The video memory can be located on the interposer as a stack of memory chips. The video memory can be further coupled, for example, via at least one hardware interface to at least one processing core implementing the game engine, thereby enabling the game engine to directly load and store data into the video memory. This can further improve the speed and throughput of data exchange between the hard-wired game engine and the on-chip GPU without deviating from the standard design of the GPU. This simplifies chip design and fabrication.

[0028] In yet another embodiment, the game engine is configured to perform one or more tasks, thereby generating commands and / or datasets. Preferably, the generated commands and / or datasets will be processed by a graphics processing unit, such as an on-chip graphics processing unit or an external GPU. The one or more tasks can be defined by the game engine and reflect the functionality of the game engine. An electronic chip can expose an interface for controlling the game engine according to its functionality. Preferably, the one or more tasks can be reflected in a programming interface exposed by the game engine through a hardware interface.

[0029] Preferably, the game engine and the ray tracing engine are interoperably coupled to perform one or more tasks. Therefore, the ray tracing engine of the game engine, or a dedicated ray tracing engine, can modify the functionality of the game engine so that a set of tasks or subtasks can be offloaded to the ray tracing engine and processed transparently by the ray tracing engine rather than the on-chip game engine. The game engine can interoperate with its associated ray tracing engine to generate commands and / or datasets that can be provided to, for example, an on-chip graphics processing unit or an external GPU, for further processing, such as final rendering, or for the generation of further auxiliary data that can be provided back to the game engine for further processing. This is advantageous because the functionality of the electronic chip can be controlled through the game engine interface without requiring any control from the underlying ray tracing engine or graphics processing unit. By utilizing the dedicated ray tracing engine on the electronic chip and the hardware capabilities of the graphics processing unit, the performance of the electronic chip is further improved.

[0030] In yet another embodiment, one or more tasks include one or more of the following: determining how an object casts shadows on other objects, how an object is reflected in other objects, or determining how light falling on an object illuminates other surrounding objects. One or more tasks can be initialized through the interface of the on-chip game engine and can be transparently offloaded in any combination to other components of the chip or external components, such as an on-chip central processing unit, an on-chip graphics processing unit, an on-chip ray tracing engine, an external CPU, and / or an external GPU. Furthermore or alternatively, the game engine can perform other and further tasks, including tasks related to the simulation and / or rendering of a graphical scene, such as simulating individual objects in the graphical scene, determining the characteristics of objects in the graphical scene, rendering one or more objects in the graphical scene, and so on. In addition, or as an alternative, the game engine may perform one or more of the following in any combination: viewport clipping and z-buffer clipping to determine the visibility of objects; voxelization of the scene as a preparatory step for global illumination calculations; cone tracing based on sparse voxels for global illumination; myofiber mechanics and myoskeletal skinning, finite element method for biomechanical muscle modeling; fluid dynamics using SPH (smooth particle fluid dynamics) for realistic effects involving water volume, volcanic lava volume, and astrophysical effects related to the surface of stars; real-time Euler water simulation; or realistic vegetation dynamics, etc.

[0031] In one embodiment, the chip is a system-on-a-chip (SOC). An SOC can be a game engine processor chip or a graphics processing unit (GPU) chip. Therefore, an electronic chip can be considered an integrated circuit that integrates all components of a game engine or even a graphics subsystem onto a single chip. An electronic chip can also be referred to as an on-chip engine. The integration of electronic chips on a single chip allows for low power consumption while providing high graphics performance.

[0032] According to a further aspect, a chip assembly comprising at least one chip according to an embodiment of the present disclosure is provided. The chip may preferably include one or more processing cores and at least one hardware interface coupled to at least one of the one or more processing cores, wherein at least one of the one or more processing cores implements a game engine. The chip assembly may include a silicon inserter or carrier, a board or substrate for mounting at least one chip and other components of the chip assembly.

[0033] As used throughout this disclosure, a chip can be considered a transistor layer, which may contain multiple metal interconnect layers above the transistor layer. Transistor layers can be difficult to manufacture, especially for very small transistors. Furthermore, the first layer of the metal interconnect layers, which may include very fine metal lines, is also difficult to manufacture. Those skilled in the art will understand that most failures occur during the manufacture of these layers. The upper layers can have thicker lines and are comparatively easier to manufacture and can cause fewer manufacturing failures. Therefore, they can be used to connect the main areas of the chip together.

[0034] The (silicon) interposers used throughout this disclosure can typically be very large chips, which may only use thicker lines on the upper interconnect layer. Therefore, (silicon) interposers can be designed and manufactured more cheaply using existing chip fabrication equipment. Although the lines can be relatively thick, (silicon) interposers can include tens of thousands of lines.

[0035] Throughout this disclosure, a chip assembly can refer to a combination of multiple (sub)chips on a single silicon inserter. Thus, a chip assembly can be functionally equivalent to a single chip that may be very large. This is particularly advantageous if, during production or fabrication, a single chip would become very large and the manufacturing cost would be prohibitively high, for example, due to a higher defect rate. Therefore, the design of a single chip can be subdivided into multiple individual (sub)chips, which can be smaller. Smaller chips can be tested first, and those that pass the test can then be connected together on the silicon inserter during chip assembly. Furthermore, by placing several equal small chips on medium, large, very large, and giant silicon inserters, the entire series of designs can consist of different sizes, such as medium, large, very large, and giant, at a small additional cost. Therefore, at least one chip of a chip assembly according to embodiments of this disclosure can be subdivided into multiple individual smaller (sub)chips connected together on the silicon inserter or carrier of the chip assembly.

[0036] Silicon interposers can be used to create tens of thousands of connections between multiple chips on a chip assembly. It is understood that silicon interposers can create significantly more interconnects than those provided by a carrier, board, or substrate to mount at least one chip. Silicon interposers can cover the entire area of ​​all (sub)chips interconnected via the silicon interposer.

[0037] In yet another embodiment, chip components can be interconnected using microbridges that include interconnect layers. The microbridges may cover only the edges of adjacent (sub)chips, providing interconnection between these adjacent (sub)chips.

[0038] In one embodiment, the chip assembly may further include at least one central processing unit (CPU), which is connected to the chip's hardware interface. The CPU may be connected to the hardware interface via a bus or any other suitable interface or interconnect of the chip assembly.

[0039] In yet another embodiment, the chip assembly may further include at least one graphics processing unit, wherein the at least one graphics processing unit is connected to the chip's hardware interface.

[0040] In yet another embodiment, the chip assembly further includes a memory controller configured to exchange data with the chip's game engine.

[0041] Therefore, a chip assembly can integrate electronic chips that implement a hard-wired game engine and further include one or more dedicated components, including a central processing unit, a graphics processing unit, and / or a memory controller. These dedicated components can be part of the chip assembly or off-chip relative to the chip implementing the hard-wired game engine. However, these components can differ from the components of the main system and the electronic chips implementing the hard-wired game engine, such as on-chip central processing units, on-chip graphics processing units, and / or on-chip memory controllers. By using off-chip implementation and integration of these components in the chip assembly, standard components for the central processing unit, graphics processing unit, and memory controller can be used, which simplifies the design, handling, and fabrication of the chip assembly and reduces various costs. The chip assembly and its components can be disposed on a carrier, board, or substrate, which may include interconnections for the individual components of the chip assembly.

[0042] In one embodiment, the chip assembly may include multiple stacked integrated circuits, wherein the integrated circuits are stacked on top of another integrated circuit or on an interposer chip. The (vertically) stacked integrated circuits can be connected via through-silicon vias (TSVs). TSVs are vertical electrical connections that pass through a silicon wafer or silicon die. Alternatively, the (vertically) stacked integrated circuits may be connected using inductive coupling technology to enable near-field wireless communication between the (vertically) stacked integrated circuits. The integrated circuits can be implemented in hardware as one or more electronic chips in any combination, including one or more processing cores implementing a hardwired game engine, a central processing unit, a graphics processing unit, a memory controller, and further components and interfaces of the chip assembly. The stacked design can be considered a variant of the interposer.

[0043] It should be noted that the use of the term silicon in "silicon inserter" or "through-silicon via" stems solely from the fact that silicon is the primary material used as a wafer substrate in chip manufacturing. However, it is understood that embodiments of this disclosure are not limited to specific materials. Other materials suitable for application to embodiments of this disclosure include, in any combination, germanium, gallium arsenide, indium arsenide, etc. Therefore, various inserters or vias can be used in the respective embodiments.

[0044] In one embodiment, the chip component may be included within a package. Preferably, the chip component may be included within a graphics processor package or a game engine processor package. Preferably, the chip component may be included within a system-in-package (SiP) or a stacked package. Packages including chip components can be easily integrated into a wide variety of target environments to enable high-performance and realistic rendering of computer graphics.

[0045] Within a System-in-Package (SiP), several integrated circuits can be housed within a single module (package). SiPs perform all or most of the functions of an electronic system and can be used in mobile phones, digital media players, and more. Dies containing integrated circuits can be stacked vertically on a substrate, carrier, or board. They can be internally connected via wires that can be bonded to the package. Alternatively, flip-chip technology can be applied, where bonding bumps are used to connect the stacked chips together. SiP dies can be stacked vertically or laid flat horizontally to create dense multi-chip packages. SiPs can connect dies to standard off-chip wire bonding or bonding bumps, or at least partially use techniques similar to those used for connecting stacked silicon dies to conductors passing through the dies in three-dimensional integrated circuits. SiPs can include one or more dedicated processors, DRAM, flash memory, and other active components that can be combined with passive components such as resistors and capacitors, which can all be mounted on the same board, carrier, or substrate. SiP represents a complete functional unit that can be embedded within a multi-chip package without further external components. This is advantageous in space-constrained environments such as mobile devices. The complexity of printed circuit boards and overall design can be significantly reduced.

[0046] According to yet another aspect, a computing device is provided, the computing device including at least one chip or chip assembly according to embodiments of the present disclosure and a display configured to display data based on data provided by the at least one chip or chip assembly.

[0047] In one embodiment, the computing device is a mobile device, a smartphone, or a virtual reality device.

[0048] According to another aspect, a method for providing an electronic chip for graphics processing is defined. The method includes providing at least one hardware interface comprising one or more processing cores and coupled to at least one of the one or more processing cores, and implementing a game engine in hardware through at least one of the one or more processing cores.

[0049] According to one embodiment, the method may further include providing an electronic chip on a chip assembly.

[0050] Therefore, according to the described embodiments, the electronic chip providing hard-wired functionality for high-performance and efficient computer graphics can be provided as a system-on-a-chip, including but not limited to a game engine processor chip or a graphics processor chip, or as a package, including but not limited to a graphics processor package or a game engine processor package.

[0051] According to yet another aspect, a computer-readable medium is provided, wherein instructions are stored thereon that, when installed and executed by a computing device, cause the computing device to perform a method according to an embodiment of the present disclosure. Preferably, the method may include the fabrication and / or operation of an electronic chip according to embodiments of the present disclosure. Attached Figure Description

[0052] The specific features, aspects, and advantages of this disclosure will be better understood with reference to the following description and accompanying drawings, wherein:

[0053] Figure 1 A schematic diagram illustrating an electronic chip including one or more hardwired game engines according to an embodiment of the present disclosure is provided.

[0054] Figure 2 A schematic diagram of an electronic chip including a plurality of hardwired game engines and a ray tracing engine according to an embodiment of the present disclosure is shown;

[0055] Figure 2a A schematic diagram of an electronic chip according to an embodiment of the present disclosure is shown, wherein each hardwired game engine includes its own dedicated ray tracing engine.

[0056] Figure 3 A schematic diagram of a game engine processor according to an embodiment of the present disclosure is shown;

[0057] Figure 4 A schematic diagram of a separate discrete graphics processor according to an embodiment of the present disclosure is shown;

[0058] Figure 4a Another schematic diagram of a separate discrete graphics processor according to an embodiment of the present disclosure is shown;

[0059] Figure 5 An implementation of a SoC with multiple CPUs according to an embodiment of the present disclosure is described;

[0060] Figure 5a Another schematic diagram of a SOC according to an embodiment of the present disclosure is shown;

[0061] Figure 5b Another schematic diagram of a SOC according to an embodiment of the present disclosure is shown;

[0062] Figure 6 An implementation of a chip as a coprocessor chip according to an embodiment of the present disclosure is shown;

[0063] Figure 6a A schematic diagram of a chip according to an embodiment of the present disclosure is shown;

[0064] Figure 7a , 7b Figures 7 and 7c show various examples of chip assemblies according to embodiments of the present disclosure. Detailed Implementation

[0065] In the following description, reference is made to the accompanying drawings, which illustrate various embodiments. Similarly, various embodiments will be described below with reference to several examples. It will be understood that embodiments may include changes in design and structure without departing from the scope of the claimed subject matter.

[0066] Figure 1 An electronic chip according to one embodiment of the present disclosure is shown. The electronic chip may include one or more hard-wired game engines that can be physically integrated onto the chip, which thus represents a system-on-a-chip (SoC).

[0067] Chip 100 may contain multiple processing cores, each implementing a game engine 102, a graphics processing unit (GPU) 104, and a central processing unit (CPU) 106 in hardware (hard-wired). Although each core is shown as a dedicated component implemented in hardware, it is understood that multiple processing cores can implement a single component, or a single processing core can implement multiple components in any combination, such as game engine 102, GPU 104, and CPU 106. Chip 100 may contain multiple game engines, multiple GPUs, and multiple CPUs in any number and any combination.

[0068] Chip 100 can be included as a System-on-Chip (SoC) in a main system (not shown). The hardwired game engine 102 can directly process specially constructed datasets located in the external main memory of the main system, accessible through one or more ports of the on-chip memory controller 108, and / or in a specially designated memory area (not shown) on the chip 100 itself.

[0069] The hardwired game engine 102 may be able to determine, for example, but not limited to, how an object casts shadows on other objects in a computer graphics scene, how an object is reflected in other objects, or how light falling on an object illuminates other surrounding objects. However, it is understood that the game engine 102 may be configured to perform other tasks and / or provide other functionalities, such as the management, simulation, and rendering of objects in a computer graphics scene.

[0070] The hard-wired game engine 102 can make the GPU 104 on chip 100 available to its control. The hard-wired game engine 102 is capable of generating datasets specifically designated for processing by the GPU 104 on chip 100. The hard-wired game engine 102 can place these datasets in external memory of chip 100 via one or more ports of on-chip memory controller 108, and / or place the datasets in a specially designated memory area on chip 100 itself. The hard-wired game engine 102 may have means of commanding the GPU 104 on chip 100 to process the datasets generated by the hard-wired game engine 102, such as one or more caches, command channels, and / or registers, or through a direct connection to the GPU 104, and / or indirectly through a connection to the CPU 106 on chip 100. In the latter case, the CPU 106 on chip 100 may be configured to instruct the GPU 104 to operate on the datasets generated by the hard-wired game engine 102.

[0071] like Figure 1 As shown, chip 100 may further include a video encoder and decoder 110, a display 112, and a hardware interface 114. The video encoder and decoder 110 may perform various dedicated functions for encoding and decoding video sequences. The display 112 may be a display configured to display at least some of the output of GPU 104, or it may be configured to display the status of chip 100 by, for example, using multiple status indicators. Furthermore, the display 112 may also be configured to provide an interface for providing data to an external display (not shown). The hardware interface 114 may include or represent one or more interfaces that may be configured to provide data to individual components of chip 100, such as game engine 102, GPU 104, CPU 106, video encoder and decoder 110, and / or output data generated by individual components, such as data generated by game engine 102, GPU 104, or CPU 106. The hardware interface may be configured to conform to one or more standards, such as USB, HDMI, etc.

[0072] Figure 2 This illustrates another embodiment of a chip according to the present disclosure. Chip 200 may be similar to... Figure 1 The chip 100. Therefore, with Figure 1 The same reference numerals used in the figures were used Figure 2 middle.

[0073] Chip 200 may include one or more game engines 102, GPUs 104, CPUs 106, memory controllers 108, video encoders and decoders 110, displays 112, and hardware interfaces 114. Chip 200 may also include, in any combination, multiple game engines 102, multiple GPUs 104, and multiple CPUs 106 implemented in hardware through at least one or more processing cores of chip 200.

[0074] One or more hardwired game engines 102 can be physically integrated onto chip 200 to form a System-on-a-Chip (SoC). One or more hardwired game engines 102 can be integrated onto the SoC along with one or more ray tracing engines 202. One or more ray tracing engines 202 can be implemented through at least one processing core of chip 200 and can be configured in such a way that the functionality of one or more game engines 102 can be extended. As those skilled in the art will recognize, typical functionalities of ray tracing engines are known. For example, functionalities can include, in any combination: viewport clipping and z-buffer clipping to determine the visibility of objects; voxelization of the scene as a preparatory step for global illumination calculations; sparse voxel-based cone tracing for global illumination; myofiber mechanics and myoskeletal skinning, finite element method for biomechanical muscle modeling; fluid dynamics (SPH) using SPH for realistic effects involving water volume, volcanic lava volume, and astrophysical effects related to, for example, the surface of stars; real-time Eulerian water simulation; and / or realistic vegetation dynamics.

[0075] One or more ray tracing engines 202 can be used to extend the functionality of the hardwired game engine 102. For example, the hardwired game engine 102 can transparently offload processing tasks to the ray tracing engine 202. It is understood that one or more ray tracing engines 202 can perform specific tasks better and / or faster due to their specialization for a given time constraint.

[0076] Ray tracing engine 202 can be allocated to a separate game engine 102 based on the workload of game engine 102 or according to a predetermined allocation. The allocation can be controlled by game engine 102 or by CPU 106, either according to internal conditions or in response to commands sent to chip 200 via hardware interface 114.

[0077] Figure 2aAnother embodiment of the chip according to this disclosure is shown, wherein each hardwired game engine can contain its own dedicated ray tracing engine. Chip 200' can include... Figure 1 and Figure 2 The same or similar parts are disclosed for chips 100 and 200. Therefore, the same reference numerals are used to denote similar parts. Chip 200' may include, in any combination, one or more GPUs 104, one or more CPUs 106, a memory controller 108, a video encoder and decoder 110, a display 112, and a hardware interface 114. Individual components may be implemented through at least one processing core of chip 200'.

[0078] Chip 200' further includes a combined game engine 202' with a merged professional version of the ray tracing engine. The professional version of the ray tracing engine can be specifically optimized for the functionalities required for hard-wiring the game engine 202'. The ray tracing engine can be hard-wired with the game engine, thereby optimizing data exchange between the game engine and the ray tracing engine in terms of bandwidth and latency using internal communication buffers or by sending data directly from the game engine to the integrated ray tracing engine.

[0079] Figure 3 A game engine processor including a chip is shown according to one embodiment of the present disclosure. The game engine processor 300 may include, for example, [missing information - likely related to a specific chip]. Figure 1 , Figure 2 as well as Figure 2a The components of chips 100, 200, and 200' shown are similar to those in the drawings. Therefore, the same reference numerals are used to denote the same or similar parts.

[0080] The game engine processor 300 may include one or more game engines 102, one or more ray tracing cores 202, a memory controller 108, a video encoder and decoder 110, a display 112, and a hardware interface 114. The processor 300 may be implemented in hardware as a game engine processor chip or a game engine processor package, wherein the package may contain one or more integrated circuits that implement the functionality of individual components in hardware. The hard-wired game engine 102 may be incorporated into hardware components such as the processor 300, which may be a standalone game engine processor chip or a game engine processor package. Game engine processors can be particularly useful in the context of high-end 3D graphics or gaming computers. These computer systems typically contain a separate main CPU and a separate 3D graphics card with one or more GPUs. For example, the standalone game engine processor 300 may be placed in a 3D graphics card along with one or more GPUs, but is not limited to this.

[0081] The game engine processor 300 may include additional means for transferring data related to the functionality of the hard-wired game engine 102 to or from an external GPU, such as by using a GPU on-chip DMA (direct memory access) facility that enables access to the GPU's video memory. These additional means may be implemented using hardware interface 114 or by using a separate communication controller (not shown).

[0082] Figure 4 A graphics processor including a chip or chip assembly is shown according to one embodiment of the present disclosure. The graphics processor 400 may include components compatible with... Figures 1 to 3 Similar components are discussed. Therefore, the same reference numerals are used to denote the same or similar components.

[0083] The graphics processor 400 may include, in any combination, at least one of the following: one or more game engines 102, one or more GPUs 104, a memory controller 108, a video encoder and decoder 110, a display 112, and a hardware interface 114. One or more hardwired game engines 102 may also be physically incorporated into the graphics processor 400 along with one or more ray tracing engines (not shown) configured to extend the functionality of the game engines. The graphics processor 400 may be embodied as a separate "discrete" graphics processor chip or a separate discrete graphics processor package, wherein the package may contain one or more integrated circuits.

[0084] Figure 4a Another embodiment of a graphics processor including a chip or chip assembly according to the present disclosure is shown. The graphics processor 400' may include... Figure 4 The graphics processor 400' may include components identical or similar to those in the graphics processor 400. Therefore, the same reference numerals are used to denote identical or similar components. The graphics processor 400' may include, in any combination, one or more GPUs 104, a memory controller 108, a video encoder and decoder 110, a display 112, and a hardware interface 114. Furthermore, the graphics processor 400' may include multiple hardwired game engines 402 that can be physically incorporated into the graphics processor 400', wherein each hardwired game engine 402 contains its own dedicated ray tracing engine optimized to extend the functionality of the game engine. The hardwired game engine 402 may be similar to... Figure 2a The game engine shown is 202'.

[0085] like Figure 4 and 4aAs shown, one or more hardware game engines 102, 402 can be incorporated into a separate discrete graphics processor chip or package, wherein the graphics processor chip or package may include one or more integrated circuits. Multiple integrated circuits within the package can be interconnected, for example, by means of an inserter and / or by stacking and / or by using a manufacturing process similar to that described in detail above.

[0086] Figure 5 , 5a And 5b discloses embodiments of a chip according to this disclosure. Chips 500, 500', and 500'' may include... Figures 1 to 4 The components shown are similar to those in the drawings. Therefore, the same reference numerals are used. Figure 5 , 5a And 5b.

[0087] Figure 5 The chip 500 can include, in any combination, one or more game engines 102, one or more GPUs 104, a memory controller 108, a video encoder and decoder 110, a display 112, and a hardware interface 114. (Similar to...) Figure 1 and 2 As discussed, individual components can be implemented using at least one processing core of chip 500. Chip 500 may further include multiple CPUs 106a, 106b, each configured to execute instructions according to a different instruction set architecture (ISA). The hard-wired game engine 102 and the various types of CPUs 106a, 106b can be integrated into a single hardware device, such as a System-on-a-Chip (SoC). Using multiple CPUs 106a, 106b, by directing individual instructions to CPUs 106a and / or 106b, chip 500 can be able to run software compiled for different platforms, systems, or architectures, such as, but not limited to, Intel-based x86 architecture systems commonly used in personal computers and ARM instruction set-based systems commonly used in mobile phones and tablets. Chip 500 may include logic for determining the architecture for each program code to be executed on chip 500 and logic for allocating the program code to each CPU, wherein the program code is compiled for that architecture. Although Figure 5 Only two types of CPUs, 106a and 106b, are shown, but it is understood that other types of CPUs, 106a and 106b, can be used for execution of instructions according to other ISAs without departing from the scope of this disclosure.

[0088] like Figure 5a As shown, chip 500' may include the same or similar components as those discussed above regarding chip 500. Figure 5a These parts are represented using the same reference numerals. Similar to... Figure 2 Chip 200 and chip 500' shown may further include one or more ray tracing engines 502. One or more hardwired game engines 102 may be physically integrated into the SoC along with the one or more ray tracing engines 202, and the one or more ray tracing engines 202 may be configured in a manner that expands the functionality of the hardwired game engines 102. Chip 500' may integrate multiple types of CPUs, each type of CPU being designed to execute a different ISA.

[0089] like Figure 5b The chip 500'' shown may include the above-mentioned components. Figure 5 and 5a The components discussed are the same or similar to chips 500 and 500'. Therefore, the same reference numerals are used. Figure 5b Chip 500'' may include the above for... Figure 2a The discussion of game engines 202' and above Figure 4a The game engine 402 discussed is similar to one or more game engines 502'. Chip 502' may include one or more hard-wired game engines 502' physically integrated onto the SOC, wherein each hard-wired game engine 502' may contain its own dedicated ray tracing engine optimized to extend the functionality of each game engine 502'. Chip 502' may contain multiple types of CPUs, each type of CPU being designed to execute instructions according to a different ISA.

[0090] Figure 6 A system according to an embodiment of the present disclosure is shown. System 600 may include CPU 602 and game engine coprocessor 604. Game engine coprocessor 604 may include one or more components for... Figures 1 to 5 The chip described. The game engine coprocessor 604 may include one or more hardwired game engines 606 and optionally one or more ray tracing engines 608. The optional ray tracing engine 608 may be configured in a way that expands the functionality of the game engine 606. The game engine coprocessor 604 may further include a memory controller 610 and a hardware interface 612 for communicating with a CPU 602. The CPU 602 may include one or more CPU cores 614, a memory controller 616, and a hardware interface 618.

[0091] The game engine coprocessor 604 can be understood as a separate chip, optionally with its own package, which can be connected to the CPU 602 via an interface bus such as a PCI express bus or any other bus interface or interconnect. The game engine coprocessor 604 may include its own memory controller 610, wherein the memory may be located external to the game engine coprocessor 604 or on the game engine coprocessor 604.

[0092] System 600 may further include one or more GPUs (not shown) and may include interfaces for connecting to one or more GPUs, such as a PCI express bus. However, it is understood that any other interconnect or bus technology may be used to interconnect CPU 602, game engine coprocessor 604, and one or more GPUs.

[0093] CPU 602 can issue commands to game engine coprocessor 604, which can then prepare datasets and commands that can be sent back to CPU 602 or transmitted to an external discrete GPU via interfaces 602 and 618. Higher performance can be achieved by offloading CPU tasks to game engine coprocessor 604, which may contain circuitry specifically designed for these tasks. One or more tasks may include one or more of the following: determining how an object casts shadows on other objects, determining how an object is reflected in other objects, or determining how light falling on an object illuminates other surrounding objects, etc. It is understood that this enumeration is not limiting and can be extended by one or more other tasks as defined above.

[0094] A dedicated memory controller 610 on the game engine coprocessor 604 enables the game engine coprocessor 604 to use its local memory to perform specific game engine tasks. This can advantageously improve performance by increasing I / O speed and bandwidth.

[0095] Figure 6a A chip 700 according to one embodiment of the present disclosure is shown. Chip 700 may include a CPU 702 having one or more CPU cores. Chip 700 may further include one or more hardwired game engines 704 and optionally one or more ray tracing engines 706, the one or more ray tracing engines 706 being configured to extend the functionality of game engine 704. Therefore, chip 700 can be considered as described above for... Figure 6The system 600 described is a variant. However, chip 700 can integrate the system on a single chip or within a chip assembly. Chip 700 may further include a memory controller 708 and an interface 710. Thus, chip 700 can be a single chip containing both a CPU 702 and a hardwired game engine 702, with an optional ray tracing core 706 on the single chip, wherein the memory controller 708 can be shared by the CPU 702 and the game engine 704 to connect to external components, such as an external GPU. For example, as discussed above for interfaces 612 and 618, interface 710 can be used to connect to one or more external discrete GPUs (not shown) via an interconnect or bus, such as via a PCI express bus or any other type of bus or interconnect.

[0096] Figure 7a , 7b Figures 7c and 7c show various examples of chip assemblies according to embodiments of the present disclosure. It is understood that a chip according to one embodiment of the present disclosure can be implemented in such a way that the chip assembly operates in the same manner as a single chip, but is divided into multiple sub-chips and has the necessary interconnections, such as thousands of interconnections, arranged between the sub-chips. Although embodiments of the present disclosure relate to on-chip game engines, chips can also be implemented as chip assemblies. Not only single chips, but also, for example... Figure 7a , 7b The implementation of the chip component shown in 7c will therefore be understood as a game engine on a chip according to embodiments of this disclosure.

[0097] Figure 7a , 7b Figures 7c and 7c illustrate exemplary chip assemblies according to one or more embodiments of the present disclosure. The chip assembly may include a package substrate 800, a plurality of sub-chips 802, and an interposer 804. The chip assembly can be configured on the package substrate 800 via the interposer 804. The plurality of sub-chips 802 may collectively form a game engine according to embodiments of the present disclosure, and the plurality of sub-chips 802 may be interconnected via the interposer 804. The interposer 804 itself may be a large silicon wafer with a metal interconnect layer manufactured using chip fabrication equipment. The metal interconnect layer on the interposer 804 may replace the interconnect layers that would otherwise interconnect the various regions of a single chip.

[0098] exist Figure 7a In one embodiment shown, using a through-silicon via 806, an inserter 804 can be connected to a package substrate 800.

[0099] Figure 7bThis illustration shows yet another embodiment of a chip assembly using a different method of interconnecting multiple sub-chips 802 into a single game engine. In this exemplary embodiment, individual sub-chips 802 can be integrated into the chip assembly using microbridges 808 that can be embedded in a packaging substrate 800. The microbridges 808 themselves can be silicon wafers with metal interconnect layers manufactured using chip fabrication equipment. The metal interconnect layers on the microbridges 808 can replace the interconnect layers that would otherwise interconnect the various regions of a single chip.

[0100] Figure 7c This illustrates yet another example embodiment of a chip assembly. In this example embodiment, multiple sub-chips 802 can be vertically interconnected as a chip assembly placed on a packaging substrate 800. This can also be considered as a 3D chip stack. The vertical interconnection of the sub-chips 802 can utilize, for example, through-silicon vias, such as... Figure 7a The 806 through-silicon via (TSV) or inductive coupling technology can enable near-field wireless communication between 3D stacked chips.

[0101] While some embodiments have been described in detail, it will be understood that aspects of this disclosure can take many forms. In particular, the claimed subject matter can be practiced or implemented by the described examples and features, and the features can be practiced or implemented in any combination. The embodiments shown herein are intended to be illustrative and not to limit the invention as defined in the claims.

Claims

1. An electronic chip (200, 300, 500, 600, 700), characterized in that, include: The first processing core implements the game engine in hardware (102, 606) through dedicated electronic circuits. as well as The second processing core implements the ray tracing engine (202, 502, 608) in hardware through dedicated electronic circuitry. Hardware interfaces (114, 612, 614, 710) couple the game engine (102, 606) implemented in the first processing core to the ray tracing engine (202, 502, 608) implemented in the second processing core. The hardware interfaces (114, 612, 614, 710) directly couple the game engine (102, 606) and the ray tracing engine (202, 502, 608), or use a buffer to couple the game engine (102, 606) and the ray tracing engine (202, 502, 608). The game engine (102, 606) is configured to offload a set of tasks or subtasks of the game engine (102, 606) to the ray tracing engine (202, 502, 608) via the hardware interface (114, 612, 614, 710).

2. The chip (200, 300, 500', 600, 700) according to claim 1, characterized in that, The chips (200, 300, 500', 600, 700) also include multiple processing cores, each of which implements a game engine (102, 606) or a ray tracing engine (202, 502, 608) in hardware via dedicated electronic circuitry, wherein each of the multiple game engines (102, 606) is associated with one of the multiple ray tracing engines (202, 502, 608).

3. The chip (200, 300, 500', 600, 700) according to claim 1 or 2, characterized in that, It also includes the processing cores that implement the central processing units (106, 106a, 106b, 602, 702).

4. The chip (200, 300, 500', 600, 700) according to claim 1 or 2, characterized in that, It also includes multiple processing cores that implement multiple central processing units (106, 106a, 106b, 602, 702), each central processing unit (106, 106a, 106b, 602, 702) being configured to execute instructions of different instruction set architectures.

5. The chip (200, 300, 500', 600, 700) according to any one of the preceding claims, characterized in that, The game engine (102, 606) is configured to communicate with the graphics processing unit (104) via the hardware interface (114, 612, 614, 710).

6. The chip (200, 300, 500', 600, 700) according to claim 5, characterized in that, The chips (200, 300, 500', 600, 700) include the graphics processing unit (104).

7. The chip (200, 300, 500', 600, 700) according to any one of claims 1 to 6, characterized in that, At least one of the processing cores implements a graphics processing unit (104), and the chips (200, 300, 500', 600, 700) further include a memory, wherein the game engine (102, 606) is configured to generate data for the graphics processing unit (104) and provide the data to the graphics processing unit (104) via the memory, or wherein the graphics processing unit (104) includes a video memory, and the game engine (102, 606) is configured to provide data to the graphics processing unit (104) via the video memory.

8. The chip (200, 300, 500', 600, 700) according to any one of claims 1 to 7, characterized in that, The game engine (102, 606) is configured to perform one or more tasks, thereby generating commands and / or datasets, wherein the game engine (102, 606) and the ray tracing engine (202, 502, 608) are interoperably coupled to perform the one or more tasks, and wherein the one or more tasks include one or more of the following: determining how an object casts shadows on other objects, determining how an object is reflected in other objects, and determining how light falling on an object illuminates other surrounding objects.

9. The chip (200, 300, 500', 600, 700) according to any one of claims 1 to 8, characterized in that, The chips (200, 300, 500', 600, 700) are system-on-a-chip (600).

10. A chip assembly, characterized in that, include: At least one chip (200, 300, 500', 600, 700) according to any one of claims 1 to 9.

11. The chip assembly according to claim 10, characterized in that, It also includes one or more of the following: at least one central processing unit (106, 106a, 106b, 602, 702), wherein the at least one central processing unit (106, 106a, 106b, 602, 702) is connected to at least one hardware interface (114, 612, 614, 710) of the chip (200, 300, 500', 600, 700); at least one graphics processing unit (104), wherein the at least one graphics processing unit (104) is connected to at least one hardware interface (114, 612, 614, 710) of the chip (200, 300, 500', 600, 700); and at least one graphics processing unit (104). A graphics processing unit (104) is connected to at least one hardware interface (114, 612, 614, 710) of the chips (200, 300, 500', 600, 700) and a memory controller (108, 610, 708) configured to exchange data with the game engine (102, 606) of the chips (200, 300, 500', 600, 700).

12. The chip assembly according to claim 10, characterized in that, It also includes multiple stacked integrated circuits, where one integrated circuit is stacked on top of another integrated circuit or on an inserter chip.

13. A package comprising a chip assembly according to any one of claims 10 to 12, characterized in that, The packaging is either a system-level package or a stacked package.

14. A computing device, characterized in that, include: At least one chip (200, 300, 500', 600, 700) according to any one of claims 1 to 9. as well as The display (112) is configured to display data based on data provided by the at least one chip (200, 300, 500', 600, 700).

15. The computing device according to claim 14, characterized in that, The computing device is a mobile device, smartphone, or virtual reality device.

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