Low power voltage regulator circuit with fast transient response and corresponding method of operation thereof

Abstract

The embodiment of the invention relates to a low-power voltage regulator circuit with fast transient response and a corresponding operating method thereof. A voltage regulator has an input differential stage. The circuit includes a bias current generator providing a bias current for a bias node, first and second input transistors coupled to the bias node, a first cascode transistor coupled to the first input transistor at a first node, and a second cascode transistor coupled to the second input transistor at a second node. The replica transistor is located between the power supply node and another node, has a gate terminal coupled to the gate terminal of the output transistor, and passes a scaled down replica current of the output current from the power supply node to the other node. A current mirror coupled to the replica transistor senses the scaled down replica current, draws a first additional bias current based on the replica current from the first node, and draws a second additional bias current based on the replica current from the second node.

Description

Cross-references to related applications

[0001] This application claims priority to Italian application No. 102024000025884, filed on 18 November 2024, which is incorporated herein by reference. Technical Field

[0002] This specification relates to low-power voltage regulator circuits that can be implemented in power management integrated circuits (PMICs) for applications such as automotive or other power applications. Background Technology

[0003] Voltage regulators with very low bias current typically have good power consumption (i.e., low power consumption) but poor dynamic response to load and line transient steps (i.e., slow response).

[0004] In fact, assuming a voltage regulator circuit is implemented using a metal-oxide-semiconductor (MOS) transistor of a certain size (e.g., defined according to the manufacturing technology), each node of the circuit is affected by a certain parasitic capacitance that must be charged and discharged during operation. If the available current in the circuit is low, the time required to achieve the desired voltage operating point can be very long.

[0005] Furthermore, a MOS transistor biased with a lower current may have a worse offset compared to a MOS transistor of the same size (e.g., the same area) but biased with a higher current. Therefore, a larger MOS transistor can be used to achieve the desired accuracy (in terms of offset) without having to excessively increase the bias current (which would result in higher parasitic capacitance).

[0006] Due to low bias current and high parasitic capacitance, the speed that can be achieved by known voltage regulator circuits is typically low.

[0007] Document US 2018 / 0173261 A1 is an example of prior art in the field of voltage regulators because it discloses a low-dropout (LDO) voltage regulator that can adapt the level of the bias current supplied to a differential amplifier based on the current drawn by the load. The LDO regulator includes a differential amplifier stage, a buffer stage, an adaptive bias stage, and an output stage. The differential amplifier stage includes a long-tailed pair arrangement comprising two n-channel MOS transistors. These transistors form a differential pair and are arranged to produce a differential output passed to the buffer stage. The tail transistors act as current sources and provide the differential amplifier stage with the minimum current required for its operation. Three current mirrors act as active loads that convert the output provided at the output of the differential amplifier stage into a single-ended voltage. The voltage present at this node depends on the difference between the voltages present at the gate terminals of the differential transistors. The buffer transistors are arranged as source followers, so that the voltage at their source terminals follows the voltage at their gate terminals, which provides a reduction in output impedance compared to the output impedance of the differential amplifier stage. The adaptive bias stage includes a PMOS replica transistor, which is a physically scaled-down version of the output transistor, and is coupled to an NMOS current mirror. A bias control transistor generates a current that is added to the minimum bias current drawn by the tail transistor to form the total bias current used to drive the differential amplifier within the error amplifier stage.

[0008] Document US 2022 / 0171417 A1 is also an example of prior art because it discloses a voltage regulator with improved overshoot suppression. The voltage regulator includes an output transistor for sensing the load current. A decaying copy of the load current is filtered and re-injected as an additional load to the output transistor by means of the copy transistor and filter circuitry. Therefore, the total load current is the sum of the load current caused by the normal load and the re-injected decaying copy. In the event of an overshoot event, the load current does not immediately drop to a low or zero load current level, but rather to a fraction of the initial load current before the overshoot event. Furthermore, due to the continuous re-injection of the decaying copy, the total load current stabilizes on a slower timescale.

[0009] Document US 2023 / 0283238 A1 is also an example of prior art because it discloses a bias circuit with high current drive capability for rapidly stabilizing the bias voltage of a stacked cascode amplifier. According to a first aspect, the bias circuit uses a transistor matched to the transistor of the cascode amplifier to generate a boost current during a transition phase that changes the bias voltage by charging or discharging a capacitor. The boost current is activated during the transition phase and deactivated when a steady-state condition is reached. According to a second aspect, the bias circuit uses an operational amplifier in a feedback loop that forces the source node of the cascode transistor in the reference circuit (i.e., a scaled-down replica of the cascode amplifier) ​​at the reference voltage. By isolating the high-frequency signal processed by the cascode amplifier from the reference circuit, the high gain and high current capability of the operational amplifier allow for rapid stabilization of the bias voltage.

[0010] Document US 2019 / 0258282 A1 is also an example of prior art, as it discloses an LDO voltage regulator with a frequency-dependent resistor device for pole-tracking compensation. Essentially, the feedback loop regulates the output voltage of the LDO regulator based on a reference voltage. Due to the feedback loop, changes in the load current cause changes in the control signal of the path device. This change in load current is mirrored and used to scale the frequency of the oscillator. The frequency change in the oscillator is used to change the value of the frequency-dependent resistor. The change in the resistor value is used to change the position of the zero frequency. The change in the zero frequency tracks the output pole and achieves LDO stability.

[0011] Document US 2021 / 0389790 A1 is also an example of prior art because it discloses an LDO regulator with a fast step response to sudden changes in load current. The LDO regulator has a transient detector circuit coupled to the output node and is configured to charge / discharge a corresponding capacitor coupled to the gate terminal of the output transistor based on the detected transient.

[0012] Document US 2019 / 0258283 A1 is also an example of prior art because it discloses an LDO regulator that operates with uniform output frequency characteristics over a wide range of load currents. A scaled copy of the output current is drawn from the tail node of the input differential pair.

[0013] Document US 2023 / 0367344 A1 is also an example of prior art because it discloses various architectures of LDO regulators (e.g., common-source cascode flip-flop voltage follower configuration or split-buffer stage configuration).

[0014] Despite advancements in this field, there remains a need for improved low-power voltage regulator circuits with very low power consumption (e.g., matching low quiescent current requirements), particularly during standby operation (if present), and with improved transient response and / or stability. Summary of the Invention

[0015] The purpose of one or more embodiments is to help provide such an improved low-power voltage regulator circuit and corresponding operating method.

[0016] According to one or more embodiments, such an object can be achieved by a voltage regulator circuit having the features described in the following claims.

[0017] One or more embodiments may involve corresponding operating methods.

[0018] The claims are an integral part of the technical teachings provided herein regarding the embodiments.

[0019] According to one aspect of this specification, a voltage regulator circuit includes an input differential stage. The input differential stage includes: a bias current generator configured to provide bias current to a bias node; an input differential transistor pair including a first input transistor and a second input transistor, both of which are coupled to the bias node; a cascode transistor pair including a first cascode transistor coupled to the first input transistor at a first node and a second cascode transistor coupled to the second input transistor at a second node; and an active load circuit coupled to the cascode transistor pair. The output node of the input differential stage is located between the first cascode transistor and the active load circuit (e.g., the output node of the input differential stage is a node between the first cascode transistor and the active load circuit). The voltage regulator circuit includes an output stage including an output transistor having a conductive channel disposed between a power supply node and an output node of the voltage regulator circuit. The output transistor has a gate terminal coupled to the output node of the input differential stage and is configured to deliver output current from the power supply node to the output node of the voltage regulator circuit. The voltage regulator circuit includes a replica transistor having a conductive channel disposed between a power node and another node. The replica transistor has a gate terminal coupled to the gate terminal of an output transistor and is configured to transfer a scaled-down replica current of the output current from the power node to the other node. The voltage regulator circuit includes a current mirror coupled to the replica transistor and configured to sense the scaled-down replica current, draw a first additional bias current from a first node based on the scaled-down replica current, and draw a second additional bias current from a second node based on the scaled-down replica current.

[0020] Therefore, one or more embodiments can provide a voltage regulator circuit that has good transient response, good stability, and low power consumption.

[0021] According to another aspect of this specification, a method of operating a voltage regulator circuit according to one or more embodiments includes: providing a bias current to a bias node via a bias current generator; passing an output current from a power node to an output node of the voltage regulator circuit via an output transistor; passing a scaled-down replica current of the output current from the power node to another node via a replica transistor; and sensing the scaled-down replica current via a current mirror, drawing a first additional bias current from a first node based on the scaled-down replica current, and drawing a second additional bias current from a second node based on the scaled-down replica current. Attached Figure Description

[0022] One or more embodiments will now be described by way of example only with reference to the accompanying drawings, in which:

[0023] Figure 1 This is an example circuit diagram of a low-power voltage regulator circuit that includes a loop for increasing the speed of the regulator; and

[0024] Figure 2 This is an example circuit diagram of a low-power voltage regulator circuit including a loop for increasing the speed of the regulator, according to one or more embodiments of this specification. Detailed Implementation

[0025] In the following description, one or more specific details are set forth to provide a thorough understanding of examples of embodiments of this specification. Embodiments may be obtained without one or more specific details, or may be obtained by other methods, components, materials, etc. In other instances, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of the embodiments are not obscured.

[0026] References to "embodiment" or "an embodiment" within the framework of this specification are intended to indicate that a particular configuration, structure, or feature described in connection with that embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment" that may appear in one or more locations within this specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, a particular configuration, structure, or feature may be combined in any suitable manner.

[0027] The headings / references used herein are provided for convenience only and therefore do not define the scope of protection or the scope of the embodiments.

[0028] In the accompanying drawings, unless the context otherwise indicates, the same component elements are represented by the same references / numbers, and for the sake of brevity, the corresponding descriptions will not be repeated.

[0029] By referring to the detailed description of exemplary embodiments, one can... Figure 1 , Figure 1 This is an example circuit diagram of a low-power voltage regulator circuit 10, which includes loops for improving the speed of the voltage regulator itself (e.g., response to transients).

[0030] like Figure 1 As shown, the voltage regulator 10 includes an input differential stage and an output power stage. The input differential stage includes an input differential pair of n-channel MOS transistors (M0 and M1). In the input differential stage, the input differential pair is loaded by a current mirror of a pair of cascode n-channel MOS transistors (M2 and M3) and p-channel MOS transistors (M4 and M5), the latter also referred to as "active loads". In the input differential stage, the input differential pair is biased by a tail current generator that draws a total bias current 2. I b For example, this includes the n-channel MOS transistor Mb.

[0031] Specifically, the input differential pair of the input differential stage may include an NMOS transistor M0 having a source terminal coupled to node 102 (e.g., referred to as the "tail node"), a drain terminal coupled to node 104 (e.g., also referred to as the "compensation node"), and configured to receive a reference voltage. Vref The gate terminal. The input differential pair may include an NMOS transistor M1 having a source terminal coupled to node 102, a drain terminal coupled to node 106, and configured to receive the output voltage of the indication voltage regulator 10. Vout Feedback voltage Vfb The gate terminal (e.g., the gate terminal of transistor M1 can be coupled to the intermediate node 108 of the voltage divider arranged between the output node 110 of regulator 10 and ground GND).

[0032] Specifically, the input differential cascode transistor pair may include an NMOS transistor M2 having a source terminal coupled to node 104 (e.g., coupled to the drain terminal of transistor M0), a drain terminal coupled to node 112 (e.g., referred to as the "output node of the input stage"), and configured to receive voltage. VC(For example, a voltage reference, a fixed voltage, or a constant voltage, which can be generated based on a bandgap reference) gate terminal. A cascode transistor pair may include an NMOS transistor M3 having a source terminal coupled to node 106 (e.g., coupled to the drain terminal of transistor M1), a drain terminal coupled to node 114, and configured to receive a voltage. VC (For example, the gate terminal coupled to the gate terminal of transistor M2). Therefore, transistor M2 has a conductive channel arranged in series with the conductive channel of transistor M0, and transistor M3 has a conductive channel arranged in series with the conductive channel of transistor M1.

[0033] A differential PMOS current mirror (or active load) can be configured to sense the current drawn from the drain terminal of transistor M3 and inject a current of the same magnitude into the drain terminal of transistor M2. Specifically, the PMOS current mirror may include a PMOS transistor M4 having a drain terminal coupled to node 112 (e.g., coupled to the drain terminal of transistor M2) and coupled to the supply voltage. VB The source terminal and gate terminal of node 116 (e.g., referred to as the "power rail"). The PMOS current mirror may include a diode-connected PMOS transistor M5 having a drain terminal coupled to node 114 (e.g., coupled to the drain terminal of transistor M3), a source terminal coupled to node 116, and a gate terminal coupled to the drain of the PMOS transistor at node 114 and to the gate terminal of transistor M4. Therefore, the node between transistor M2 and the active load circuit (e.g., transistor M4) may be an input-differential output node.

[0034] Specifically, the input differential tail current generator may include an NMOS transistor Mb having a source terminal coupled to ground GND, a drain terminal coupled to node 102, and configured to receive voltage. VA (For example, a voltage reference, a fixed voltage, or a constant voltage, which can be generated based on a bandgap reference) gate terminal. The NMOS transistor Mb can draw tail current 2 from node 102. I b Regarding the bias of voltage regulator 10, tail current 2 I b The bias current is evenly distributed between the two branches of the input differential pair, that is, the bias current is uniformly distributed between the two branches. I b The current flows through the series arrangement of transistors M0, M2, and M4, with equal currents. I b The transistors M1, M3, and M5 are arranged in series.

[0035] The output power stage of the voltage regulator 10 may include a PMOS transistor Mp, which has a conductive channel disposed between the power rail 116 and the output node 110 of the voltage regulator, and a voltage control terminal at node 112 (i.e., the output node of the input differential stage) to control the load current. I L The power supply is transferred from power rail 116 to output node 110. Specifically, transistor Mp may have a drain terminal coupled to node 110, a source terminal coupled to node 116, and a gate terminal coupled to node 112.

[0036] Furthermore, the voltage regulator 10 may include a feedback loop, which includes components configured to generate a feedback voltage. Vfb The voltage divider. Specifically, the feedback voltage divider may include a resistor R1 disposed between the output node 110 and the intermediate node 108, and a resistor R2 disposed between the intermediate node 108 and ground GND, such that the feedback voltage generated at node 108... Vfb Indicator regulator output voltage Vout (For example, with this voltage) Vout (proportional).

[0037] In addition, the voltage regulator 10 may include a compensation capacitor C disposed between the output node 110 and the input stage of the regulator 10. C (For example, for implementing Miller compensation architecture). Specifically, the compensation capacitor C C It may have a first terminal coupled to the output node 110 and a second terminal coupled to the node 104 between transistors M0 and M2.

[0038] Furthermore, the load can be coupled to the output node 110 of the voltage regulator 10, specifically, between node 110 and ground (GND). Figure 1 China-Israel load capacitor C L For example, the load capacitor C L It is connected in parallel with the current generator G between node 110 and ground GND. The load current generator draws load current from node 110. I L It should be understood that, despite... Figure 1 The diagram shows the load capacitor C. L The load generator G is not part of the voltage regulator 10, but is only used to illustrate the effect of coupling an external load to the output node 110 of the voltage regulator.

[0039] To improve the speed of voltage regulator 10 (i.e., improve its response to transients), one possible approach is to increase the bias current, for example, by increasing the tail current drawn from node 102 to ground GND. To this end, Figure 1 The voltage regulator 10 illustrated includes an additional circuit comprising a PMOS replica transistor and an NMOS current mirror, the PMOS replica transistor being configured to generate a load current. I L A scaled-down version of the NMOS current mirror, this NMOS current mirror is configured to sense the current supplied by the drain terminal of the replica transistor and draw a current of the same magnitude from the tail node 102 of the input differential pair. Specifically, the replica transistor may include a PMOS transistor Ms having a source terminal coupled to node 116, a drain terminal coupled to node 118, and a gate terminal coupled to node 112 (i.e., coupled to the gate terminal of the power transistor Mp to receive the same control voltage). The width-to-length ratio of the replica transistor Ms may be 1 / K of the width-to-length ratio of the power transistor Mp, and particularly, when the two transistors have the same length (i.e., transistors Mp and Ms are referred to as a K:1 ratio), the width of the replica transistor Ms may be 1 / K of the width of the power transistor Mp. Therefore, the current flowing through transistor Ms is 1 / K of the current flowing through transistor Mp. The total current flowing through transistor Ms is referred to as 2. I x Relation 2 I x = I L / K Applicable. The NMOS current mirror for the additional loop may include a diode-connected NMOS transistor M6, having a drain terminal coupled to node 118 (e.g., coupled to the drain terminal of the replica transistor Ms), a source terminal coupled to ground GND, and a gate terminal coupled to the drain terminal of the NMOS transistor at node 118. The NMOS current mirror may include an NMOS transistor M7, having a source terminal coupled to ground GND, a drain terminal coupled to the tail node 102 of the input differential pair, and a gate terminal coupled to the gate terminal of transistor M6. The width-to-length ratio of transistor M7 may be equal to that of transistor M6, and particularly, when both transistors have the same length (i.e., transistors Mp and Ms are referred to as a 1:1 ratio), the width of transistor M7 may be equal to the width of transistor M6, such that the same current 2 I x The current flows through transistors M6 and M7. By doing so, an additional tail current 2 is drawn from node 102. I xRegarding the bias of voltage regulator 10, the additional tail current 2 I x The additional bias current is evenly distributed between the two branches of the input differential pair, meaning it is uniformly distributed between the two branches. I x A series connection of transistors M0, M2, and M4 with equal additional bias current flows through them. I x The series arrangement of transistors M1, M3, and M5 ensures that the total bias current flowing through each branch is equal to... I b + I x .

[0040] Figure 1 The increased bias current achievable with the illustrated architecture is advantageous in terms of speed because a higher current is available for charging / discharging parasitic capacitances (compared to an architecture without the additional circuitry of transistors Ms, M6, and M7), and the transconductance (gm1 / gm2) of the first stage is also increased, resulting in a higher gain-bandwidth product (GBWP). However, the higher gain-bandwidth product may pose a risk of instability due to the presence of high-frequency parasitic poles in the transfer function.

[0041] It should be noted that Figure 1 The detailed transistor-level implementation of voltage regulator 10 is illustrated, but the same approach, which configures additional loops (Ms, M6, M7) to increase bias current, can also be applied to other voltage regulator architectures.

[0042] To achieve an increase in bias current without compromising stability performance, one or more embodiments may rely on Figure 2 The architecture of the voltage regulator 20 illustrated below will be mainly emphasized in conjunction with... Figure 1 Describing the differences in architecture.

[0043] The input differential stage (transistors M0, M1, M2, M3, M4, M5, Mb), output stage (transistor Mp), feedback loop (voltage divider R1, R2), and compensation capacitor (C) are considered. C In terms of voltage regulator 20, the architecture is basically the same as that of voltage regulator 10. Figure 2 In, with Figure 1 Similarly, the load capacitor C L The load generator G is illustrated to illustrate the effect of external loads coupled to node 110, but they are not part of the voltage regulator 20. Figure 2For ease of explanation, a parasitic capacitance Cp is arranged between the gate terminal of the power transistor Mp and the power rail 116. It should be understood that this capacitance does not correspond to a physical capacitor intentionally created in circuit 20, and similar parasitic capacitances can also be found in... Figure 1 The circuit diagram is shown below.

[0044] Now switch to voltage regulator 20 ( Figure 2 ) and voltage regulator 10 ( Figure 1 The differences and similarities between the circuit diagrams (with regard to additional loops) should be noted, and voltage regulator 20 includes components configured to generate load current. I L The smaller version 2 I x = I L / K is a replica of the same PMOS transistor Ms, but with a different NMOS current mirror. In fact, Figure 2 The NMOS current mirror architecture is configured to sense the current supplied by the drain terminal of the replicated transistor Ms.2. I x (Among them, transistor M6 and) Figure 1 The architecture is the same as in the previous one, but with two output branches, each configured to draw half a size (i.e., a size of) from the corresponding source terminals of the cascode transistors M2 and M3. I x The current flowing through transistor Ms is 1 / K of the current flowing through transistor Mp. Specifically, the replica transistor may include a PMOS transistor Ms having a source terminal coupled to node 116, a drain terminal coupled to node 118, and a gate terminal coupled to node 112 (i.e., coupled to the gate terminal of power transistor Mp to receive the same control voltage). The width-to-length ratio of the replica transistor Ms may be 1 / K of the width-to-length ratio of the power transistor Mp, and particularly, when both transistors have the same length (i.e., transistors Mp and Ms are referred to as a K:1 ratio), the width of the replica transistor Ms may be 1 / K of the width of the power transistor Mp. Therefore, the current flowing through transistor Ms is 1 / K of the current flowing through transistor Mp. The total current flowing through transistor Ms is referred to as 2. I x Relation 2 I x = I L / K Applicable. An NMOS current mirror may include a diode-connected NMOS transistor M6 having a drain terminal coupled to node 118 (e.g., coupled to the drain terminal of a replica transistor Ms), a source terminal coupled to ground GND, and a gate terminal coupled to the drain terminal of the NMOS transistor at node 118. Instead of a single NMOS output transistor M7 (such as... Figure 1 As shown), the NMOS current mirror may include two NMOS output transistors M8 and M9. NMOS transistor M8 may have a source terminal coupled to ground (GND), a drain terminal coupled to node 104 (e.g., coupled to the source terminal of cascode transistor M2, or in other words, coupled to the node between transistors M0 and M2), and a gate terminal coupled to the gate terminal of transistor M6. NMOS transistor M9 may have a source terminal coupled to ground (GND), a drain terminal coupled to node 106 (e.g., coupled to the source terminal of cascode transistor M3, or in other words, coupled to the node between transistors M1 and M3), and a gate terminal coupled to the gate terminal of transistor M6. The width-to-length ratio of transistors M8 and M9 may be half that of transistor M6, and specifically, when the three transistors have the same length (i.e., the ratio of transistors M8 and M9 to transistor M6 is 2:1), the width of transistors M8 and M9 may be half the width of transistor M6, therefore, if the current 2 I x When current flows through transistor M6, I x The current flows through transistors M8 and M9. In doing so, additional current is drawn from each of nodes 104 and 106. I x This causes the current to be biased relative to the voltage regulator 10. I b + I x The current flows through transistors M2 and M4, and transistors M3 and M5, and the current... I b The current flows through each of the transistors M0 and M1 in the input differential pair.

[0045] Additionally, it should be noted that in one or more embodiments, the aspect ratios of transistors M6, M8, and M9 may differ from the 2:1:1 relationship described above, as long as transistors M8 and M9 have the same aspect ratio and therefore draw the same amount of current from nodes 104 and 106, respectively. For example, the aspect ratio of transistors M8 and M9 may be one-quarter of the aspect ratio of transistor M6, such that if the current 2 I x When current flows through transistor M6,I x / 2 flows through transistors M8 and M9. In doing so, additional current is drawn from each of nodes 104 and 106. I x / 2, thus, with respect to the bias of voltage regulator 10, the current I b + I x / 2 flows through transistors M2 and M4, and transistors M3 and M5, and the current... I b The current flows through each of transistors M0 and M1 in the input differential pair. According to another example, the width-to-length ratio of transistors M8 and M9 can be equal to the width-to-length ratio of transistor M6, such that if the current 2... I x When current flows through transistor M6, the current is 2. I x The current flows through transistors M8 and M9. By doing so, an additional current of 2 is drawn from each of nodes 104 and 106. I x This causes the current to be biased relative to the voltage regulator 10. I b +2 I x The current flows through transistors M2 and M4, and transistors M3 and M5, and the current... I b The current flows through each of the transistors M0 and M1 in the input differential pair.

[0046] More generally, it should be understood that each of transistors M8 and M9 draws current (from nodes 104 and 106, respectively), and the magnitude of this current is based on the current 2 flowing through transistor M6. I x The size (e.g., is a function of that size, especially half of it).

[0047] for Figure 2 The architecture illustrated can be improved by adding load current at the source terminal of each transistor in the cascode transistors M2 and M3. I L Scaling copy I x To increase the bias current, thereby improving speed but avoiding instability. In the load current... I L During the step transition from low to high, the output voltage Vout It will exhibit a downward surge, but due to the compensation capacitor C... CThe additional current can be used to very quickly charge the gate (parasitic) capacitance Cp of the power transistor Mp, thereby increasing the gate-source voltage (Vgs) of transistor Mp and thus increasing its current capability to respond to undershoot. On the other hand, in the load current... I L During the high-to-low step transition, the output voltage Vout It will exhibit overshoot, but due to the compensation capacitor C C The cascode transistor M2 is switched off very quickly, and the gate capacitance Cp of the power transistor Mp is discharged through transistor M4, which provides current to the gate of transistor Mp. I b + I x (At node 112). The higher the current flowing through transistor M4, the faster the response.

[0048] exist Figure 2 In this architecture, since the bias current flowing through the input pair of transistors M0 and M1 remains constant (compared to the architecture without additional loops), the gain-bandwidth product also remains unchanged, avoiding the risk of instability while preserving the benefit of increased speed during transient response. Therefore, in other words, compared to the architecture without additional bias loops, Figure 2 The architecture is faster, with additional bias loops including the tail node 102 coupled to the input differential pair. Figure 1 The architecture is more stable compared to that.

[0049] Therefore, one or more embodiments can provide a fast (i.e., good response to transients) and stable voltage regulator circuit.

[0050] It should be noted that reference has been made. Figure 1 and Figure 2 One or more embodiments are described, including an NMOS transistor for a tail current generator, an input differential pair, a cascode transistor, and a current mirror in an additional bias loop, as well as a PMOS transistor for an active load, an output power transistor, and a replica transistor. It should be understood that, in different embodiments, a similar architecture of the additional bias loop can be applied to voltage regulators with complementary structures (e.g., input differential pairs with PMOS transistors).

[0051] Without prejudice to the fundamental principles, details and embodiments may be varied, even significantly, relative to what has been described by way of example only, without departing from the scope of protection.

[0052] The scope of protection is determined by the appended claims.

Claims

1. A voltage regulator circuit, comprising: Input difference levels, including: A bias current generator is configured to provide bias current for the bias node; An input differential transistor pair includes a first input transistor and a second input transistor, both of which are coupled to the bias node; A cascode transistor pair includes a first cascode transistor coupled to the first input transistor at a first node and a second cascode transistor coupled to the second input transistor at a second node; and An active load circuit is coupled to the cascode transistor pair, wherein the output node of the input differential is located between the first cascode transistor and the active load circuit. An output stage includes an output transistor having a conductive channel disposed between a power supply node and an output node of the voltage regulator circuit, the output transistor having a gate terminal coupled to the output node of the input differential stage, and being configured to deliver output current from the power supply node to the output node of the voltage regulator circuit. A replica transistor having a conductive channel between the power node and another node, the replica transistor having a gate terminal coupled to the gate terminal of the output transistor, and configured to transfer a scaled-down replica current of the output current from the power node to the other node; and A current mirror, coupled to the replica transistor, is configured to sense the scaled-down replica current, draw a first additional bias current from the first node based on the scaled-down replica current, and draw a second additional bias current from the second node based on the scaled-down replica current.

2. The voltage regulator circuit according to claim 1, wherein the current mirror comprises: A diode-connected transistor is coupled between the replicated transistor and ground; A first current-drawing transistor is coupled between the first node and ground, and has a gate terminal coupled to the gate terminal of the diode-connected transistor. as well as The second current-drawing transistor is coupled between the second node and ground, and has a gate terminal coupled to the gate terminal of the diode-connected transistor.

3. The voltage regulator circuit according to claim 2, wherein the aspect ratio of the first current-drawing transistor and the aspect ratio of the second current-drawing transistor are half the aspect ratio of the diode-connected transistor.

4. The voltage regulator circuit according to claim 1 further includes a compensation capacitor disposed between the output node and the first node of the voltage regulator circuit.

5. The voltage regulator circuit of claim 1, wherein the bias current generator includes a bias transistor having a gate terminal configured to receive a first fixed voltage.

6. The voltage regulator circuit of claim 1, wherein the first input transistor has a gate terminal configured to receive a reference voltage, and the second input transistor has a gate terminal configured to receive a feedback voltage indicating the output voltage of the voltage regulator circuit.

7. The voltage regulator circuit of claim 1, wherein the first input transistor has a source terminal coupled to the bias node and a drain terminal coupled to the first node, and the second input transistor has a source terminal coupled to the bias node and a drain terminal coupled to the second node.

8. The voltage regulator circuit according to claim 1, wherein: The first cascode transistor has a source terminal coupled to the first node, a drain terminal coupled to the output node of the input differential stage, and a gate terminal configured to receive a second fixed voltage; and The second cascode transistor has a source terminal coupled to the second node, a drain terminal coupled to the third node, and a gate terminal configured to receive the second fixed voltage.

9. The voltage regulator circuit according to claim 8, wherein the active load circuit comprises: The first active load transistor has a source terminal coupled to the power supply node, a drain terminal coupled to the output node of the input differential stage, and a gate terminal. as well as The second active load transistor connected to a diode has a source terminal coupled to the power supply node, a drain terminal coupled to the third node, and a gate terminal coupled to the drain terminal of the second active load transistor and the gate terminal of the first active load transistor.

10. A method of operating a voltage regulator circuit, the voltage regulator circuit including an input differential stage, the input differential stage having a bias current generator, an input differential transistor pair including a first input transistor and a second input transistor, and a cascode transistor pair, both the first input transistor and the second input transistor being coupled to a bias node of the bias current generator, the cascode transistor pair including a first cascode transistor coupled to the first input transistor at a first node and a second cascode transistor coupled to the second input transistor at a second node, the voltage regulator circuit further including an output stage, a replica transistor, and a current mirror, the output stage including an output transistor having a conductive channel disposed between a power supply node and an output node of the voltage regulator circuit, the replica transistor having a conductive channel between the power supply node and another node and a gate terminal coupled to a gate terminal of the output transistor, the current mirror being coupled to the replica transistor, the method comprising: The bias current is provided to the bias node through the bias current generator; The output current is transmitted from the power supply node to the output node of the voltage regulator circuit through the output transistor; A scaled-down replica of the output current is transmitted from the power node to the other node via the replica transistor. The scaled-down replica current is sensed by the current mirror; The first additional bias current is drawn from the first node by the current mirror based on the scaled-down replica current; as well as The second additional bias current is drawn from the second node by the current mirror based on the scaled-down replica current.

11. The method of claim 10, further comprising providing an active load for the cascode transistor pair via an active load circuit, wherein the output node of the input differential is located between the first cascode transistor and the active load circuit.

12. The method of claim 11, wherein the first cascode transistor has a source terminal coupled to the first node and a drain terminal coupled to the output node of the input differential stage, the second cascode transistor has a source terminal coupled to the second node and a drain terminal coupled to the third node, and the method further comprises: The second fixed voltage is received through the gate terminal of the first common-source cascode transistor; as well as The second fixed voltage is received through the gate terminal of the second common-source cascode transistor.

13. The method of claim 12, further comprising: The first active load transistor of the active load circuit provides a source terminal coupled to the power supply node, a drain terminal coupled to the output node of the input differential, and a gate terminal; as well as The second active load transistor, connected via a diode in the active load circuit, provides a source terminal coupled to the power node, a drain terminal coupled to the third node, and a gate terminal coupled to the drain terminal of the diode-connected second active load transistor and the gate terminal of the first active load transistor.

14. The method of claim 10, further comprising providing a gate terminal of the output node coupled to the input differential level via the output transistor.

15. The method of claim 10, further comprising: A transistor is provided that is coupled between the replicated transistor and ground via a diode connection; A first current-drawing transistor coupled between the first node and ground provides a gate terminal to the gate terminal of the diode-connected transistor; as well as A second current-drawing transistor coupled between the second node and ground provides a gate terminal to the gate terminal of the diode-connected transistor.

16. The method of claim 15, wherein the aspect ratio of the first current-drawing transistor and the aspect ratio of the second current-drawing transistor are half the aspect ratio of the diode-connected transistor.

17. The method of claim 10, further comprising providing a compensation capacitor between the output node of the voltage regulator circuit and the first node.

18. The method of claim 10, further comprising receiving a first fixed voltage through the gate terminal of the bias transistor of the bias current generator.

19. The method of claim 10, further comprising: The reference voltage is received through the gate terminal of the first input transistor; as well as The feedback voltage, which indicates the output voltage of the voltage regulator circuit, is received through the gate terminal of the second input transistor.

20. The method of claim 10, further comprising: The first input transistor provides a source terminal coupled to the bias node and a drain terminal coupled to the first node; as well as The second input transistor provides a source terminal coupled to the bias node and a drain terminal coupled to the second node.

Images