Storage device, storage system including the same, and operating method thereof

Abstract

A storage device includes a memory device and a storage controller. A memory device includes a memory cell array including a memory block having a plurality of pages to which memory cells are connected, and a control logic circuit. The memory controller obtains information on the memory block, determines a number of pages on which a program operation skipping the verification program is to be performed based on the obtained information, and transmits a program command for the program operation to the memory device. In response, the memory device receives a program command and performs a program operation by performing a single program loop without a verification program for at least one of the plurality of pages indicated by the program command.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0165186, filed with the Korean Intellectual Property Office on November 19, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to storage devices, storage systems including such storage devices, and methods of operating thereof. Background Technology

[0004] Semiconductor memories can be classified into volatile memory devices that lose stored data when power is cut off, such as static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM), and non-volatile memory devices that retain stored data even when power is cut off, such as read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable and programmable ROM (EEPROM), flash memory devices, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM).

[0005] Memory devices can be widely used as high-capacity storage media in computing systems. Memory devices can be designed to communicate with memory controllers based on various electrical signals.

[0006] The above information is intended to enhance understanding of the background of this disclosure and may include information not included in the related art. Summary of the Invention

[0007] This disclosure relates to a storage device for reducing the programming time of a memory device, a storage system including the storage device, and a method of operating the same.

[0008] The problems to be solved by this disclosure are not limited to those described above, and the following description of this disclosure will allow those skilled in the art to clearly understand other problems not mentioned above.

[0009] A storage device according to an embodiment of the present disclosure includes a memory device and a memory controller. The memory device includes a memory cell array and control logic circuitry. The memory cell array includes a memory block having multiple pages with memory cells connected to it. The memory controller obtains information about the memory block, determines, based on the obtained information about the memory block, the number of pages for which a first programming operation to skip a verification procedure is to be performed, and sends a first programming command for the first programming operation to the memory device. The memory device receives the first programming command from the memory controller and performs the first programming operation for the pages indicated by the first programming command among the multiple pages by executing a programming loop for skipping a verification procedure.

[0010] A storage device according to an embodiment of the present disclosure includes a memory device and a storage controller. The memory device includes a memory cell array and control logic circuitry. The memory cell array includes a memory block having multiple pages with memory cells connected to it. The storage controller sends programming commands to the memory device for programming operations on each of the multiple pages. The memory device obtains information about the memory block, determines, based on the information about the memory block, the number of pages on which programming operations for skipping a verification process are to be performed, receives programming commands from the storage controller, and performs programming operations on the pages corresponding to the number of pages and indicated by the programming commands by executing a programming loop for skipping a verification process.

[0011] An operation method of a storage system according to an embodiment of the present disclosure is performed by the storage system, which includes a memory device, a storage controller that exchanges data with the memory device, and a host device that exchanges data with the storage controller. The memory device includes a memory cell array and control logic circuitry. The memory cell array includes a memory block having a plurality of pages. The operation method of the storage system includes the storage system determining, based on obtained information about the memory block, the number of pages to which programming operations for skipping a verification procedure are to be performed; the storage controller sending programming commands for programming operations for each of the plurality of pages to the memory device; the memory device receiving the programming commands; and the memory device performing programming operations for the pages corresponding to the number of pages and indicated by the programming commands by executing a programming loop for skipping a verification procedure.

[0012] According to various embodiments of this disclosure, the time spent performing programming operations on memory blocks can be reduced.

[0013] According to various embodiments of this disclosure, failures in programming operations can be minimized by flexibly adjusting the count of fast programming based on a range of factors, while reducing the time spent performing programming on memory blocks. Therefore, the write speed of the memory device can be improved, and its throughput can be increased.

[0014] According to various embodiments of this disclosure, the power consumption required to perform programming operations can be reduced, and the stress applied to the memory cells can be reduced, thereby extending the lifespan of the memory device.

[0015] The effects of this disclosure are not limited to those described above. The following description of this disclosure will allow those skilled in the art to clearly understand other technical effects of this disclosure not mentioned above. Attached Figure Description

[0016] Figure 1 A storage system according to an embodiment of the present disclosure is shown.

[0017] Figure 2 This is a view used to illustrate a non-volatile memory according to an embodiment of the present disclosure.

[0018] Figure 3 This is a perspective view of a memory block according to an embodiment of the present disclosure.

[0019] Figure 4 This is a circuit diagram of a memory block according to an embodiment of the present disclosure.

[0020] Figure 5 A series of programming voltages for programming memory cells using multi-level data, according to an embodiment of the present disclosure, are shown.

[0021] Figure 6 This is a view used to illustrate the state of multiple memory cells according to some embodiments of this disclosure.

[0022] Figure 7 A method of operating a storage system according to an embodiment of the present disclosure is shown.

[0023] Figure 8A The execution was shown Figure 7 The storage system's operating methods and components.

[0024] Figures 8B to 8D It shows Figure 8A Various examples of the location of components on the storage system.

[0025] Figure 9 It is used to show in detail Figure 7 The flowchart of S710 in the document.

[0026] Figure 10A and Figure 10B It is used to show in detail Figure 9 The views of S712 and S713 in the image.

[0027] Figure 11 It is used to show in detail Figure 9 Views S714 to S717 in the diagram.

[0028] Figure 12 It is used to show in detail Figure 9 The view of S718 in the image.

[0029] Figure 13 It is used to show in detail Figure 7 The view of S720 in the image.

[0030] Figure 14 It is used to show in detail Figure 7 The flowchart of S720 in the document.

[0031] Figure 15 It is used to show in detail Figure 7 The flowchart of S730 in the document.

[0032] Figure 16 It is used to show in detail Figure 15 The view of S734 in the image.

[0033] Figure 17 It is used to show in detail Figure 7 The view of S740 in the image.

[0034] Figure 18 It is used to show in detail Figure 7 The flowchart of S740 in the document.

[0035] Figure 19 It is used to show in detail Figure 7 The view of the S750 in the image.

[0036] Figure 20 It is used to show in detail Figure 7 The flowchart of S750 in the document.

[0037] Figure 21 It is used to show in detail Figure 7 The view of S760 in the image. Detailed Implementation

[0038] In the following text, reference will be made to Figures 1 to 21 Various embodiments of this disclosure are described. Throughout this specification, the same reference numerals may refer to the same components.

[0039] In this disclosure, "fast programming" or "fast programming operation" can refer to a programming operation performed in a programming cycle on a single-level cell or a page or word line comprising a single-level cell. For example, a fast programming operation comprising a programming cycle can be performed on a page comprising a single-level cell to complete the programming operation for that page. A single programming cycle may include the operation of applying a programming voltage to the single-level cell or a page or word line comprising a single-level cell, and a verification procedure, such as the operation of applying a verification voltage to a memory cell, may be skipped for a single programming cycle.

[0040] In this disclosure, "normal programming" or "normal programming operation" can refer to a programming operation performed by one or more programming cycles, including operations of applying a programming voltage to a memory cell and operations of applying a verification voltage.

[0041] Figure 1 A storage system 10 according to an embodiment of the present disclosure is shown. Reference Figure 1 The storage system 10 may include a host device 20 and a storage device 100. The host device 20 and the storage device 100 may exchange data and / or signals with each other.

[0042] The host device 20 may be a device running an operating system (OS) such as Windows, iOS, and Android. In some embodiments, the host device 20 may include a host controller 21 and a host memory 22. The host memory 22 may be used as a buffer for temporarily storing data to be sent to or from the storage device 100.

[0043] According to one embodiment, the host controller 21 and host memory 22 can be implemented as separate semiconductor chips. In other embodiments, the host controller 21 and host memory 22 can be integrated into a single semiconductor chip. For example, the host controller 21 can be one of multiple modules of an application processor, and the application processor can be implemented as a system-on-chip (SoC). Furthermore, the host memory 22 can be embedded memory within the application processor, or volatile memory or a memory module located outside the application processor.

[0044] In one embodiment, the host controller 21 can manage the operation of storing data from the host memory 22 into non-volatile memory devices 300_1 to 300_3 via the storage controller 200, or storing data (e.g., information about memory blocks within non-volatile memory devices 300_1 to 300_3) from the non-volatile memory devices 300_1 to 300_3 into the host memory 22 via the storage controller 200.

[0045] Storage device 100 may include storage controller 200 and multiple nonvolatile memory devices (NVMs) 300_1 to 300_3. Each of the storage controller 200 and the multiple NVMs 300_1 to 300_3 can exchange data, signals, etc. with each other. Although Figure 1 Three non-volatile memory devices 300_1 to 300_3 have been shown, but this disclosure is not limited thereto, and memory device 100 may include any number of memory devices. For example, memory device 100 may include multiple memory devices arranged in an array and interconnected with each other.

[0046] Storage device 100 may include a storage medium for storing data upon request from host device 20. For example, storage device 100 may include at least one of a solid-state drive (SSD), embedded memory, and removable external memory. When storage device 100 is an SSD, it may be a device conforming to the non-volatile memory express (NVMe) standard. When storage device 100 is embedded memory or external memory, it may be a device conforming to the universal flash storage (UFS) or embedded multimedia card (eMMC) standard. Host device 20 and storage device 100 may each generate and send packets according to their respective standard protocols.

[0047] When the non-volatile memory devices 300_1 to 300_3 include flash memory, the flash memory may include a 2D NAND memory array or a 3D, vertical or bonded vertical NAND (VNAND) memory array. For another example, storage device 100 may include various other types of non-volatile and / or volatile memory. For instance, storage device 100 may include at least one of volatile or non-volatile memory, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable and programmable ROM (EEPROM), magnetic RAM (MRAM), spin-torque MRAM, conductive bridging RAM (CBRAM), ferroelectric RAM (FeRAM), phase RAM (PRAM), and resistive RAM.

[0048] The storage controller 200 may include a host interface 211, a controller interface circuit 212, and a central processing unit (CPU) 213. Furthermore, the storage controller 200 may also include an index read unit (IRU) 214, a flash translation layer (FTL) 215, a buffer memory 216, an error correction code (ECC) engine 217, and internal non-volatile memory 218. The storage controller 200 may also include working memory in which the flash translation layer 215 is loaded, and the operations of writing data to and reading data from the non-volatile memory can be controlled by the CPU 213 operating the flash translation layer 215.

[0049] Host interface 211 can exchange packets with host device 20. Packets sent from host device 20 to host interface 211 may include commands and / or data to be written to or sent to non-volatile memory devices 300_1 to 300_3, such as the number of quick programs, and packets sent from host interface 211 to host device 20 may include responses to commands, data read from non-volatile memory devices 300_1 to 300_3, or information about memory blocks, such as cell count values ​​within a specific threshold voltage range. The accompanying drawings show host interface 211 located inside memory controller 200, but this disclosure is not limited thereto. For example, host interface 211 may be located outside memory controller 200.

[0050] The controller interface circuit 212 can send data to be written to non-volatile memory devices 300_1 to 300_3, or receive data read from non-volatile memory devices 300_1 to 300_3. Such a controller interface circuit 212 can be designed to conform to standard protocols such as toggle or ONFI.

[0051] The flash translation layer 215 can perform various functions, such as address mapping, wear leveling, and garbage collection. Additionally, the buffer memory 216 can temporarily store data to be written to or read from the non-volatile memory devices 300_1 to 300_3. The buffer memory 216 can be a component located inside the memory controller 200, or it can be located outside the memory controller 200.

[0052] ECC engine 217 can be used to detect and correct errors in read data read from non-volatile memory devices 300_1 to 300_3. More specifically, ECC engine 217 can generate parity bits for write data to be written to non-volatile memory devices 300_1 to 300_3, and the parity bits generated in this way can be stored in non-volatile memory devices 300_1 to 300_3 along with the write data. When reading data from non-volatile memory devices 300_1 to 300_3, ECC engine 217 can use the parity bits read from non-volatile memory devices 300_1 to 300_3 and the read data to correct errors in the read data, and output the error-corrected read data.

[0053] Figure 2 This is a view used to illustrate a non-volatile memory according to an embodiment of the present disclosure. Reference Figure 2 , will describe Figure 1 The components of the non-volatile memory device 300_1 in the document, but it should be understood that, in reference to Figure 2 The described embodiments can be applied to connections to Figure 1 Any non-volatile memory device in the memory controller 200.

[0054] refer to Figure 2 The non-volatile memory device 300_1 may include a memory cell array 321, a voltage generator 322, a control logic circuit 323, a row decoder 340, and a page buffer circuit 350. In other embodiments, the non-volatile memory device 300_1 may also include data input / output circuitry or an input / output interface.

[0055] The memory cell array 321 may include multiple memory cells and is connected to word lines WL, serial select lines SSL, ground select lines GSL, and multiple bit lines BL. Specifically, the memory cell array 321 can be connected to the row decoder 340 via word lines WL, serial select lines SSL, and ground select lines GSL, and can be connected to the page buffer circuit 350 via multiple bit lines BL.

[0056] The memory cell array 321 may include multiple memory blocks BLK1 to BLKz. Each of the multiple memory blocks BLK1 to BLKz may include multiple pages to which memory cells are connected. One or more pages may be connected to each of the word lines WL.

[0057] Each of the multiple memory blocks BLK1 to BLKz can have a three-dimensional or vertical structure. Specifically, each memory block may include a structure extending upwards in a first direction to a third direction. For example, each memory block may include multiple NAND strings extending upwards in a third direction. Here, the multiple NAND strings may be spaced apart from each other by a specific distance in both the first and second directions.

[0058] The row decoder 340 can select one of a plurality of memory blocks BLK1 to BLKz. For example, the row decoder 340 can select a memory block corresponding to a block address from a plurality of memory blocks BLK1 to BLKz.

[0059] Each memory cell in the memory cell array 321 can store at least one bit. In one embodiment, the memory cell can be a single-level cell (SLC) that stores 1 bit of data. In another embodiment, the memory cell can be a multi-level cell (MLC) or a two-level cell that stores 2 bits of data, a triple-level cell (TLC) that stores 3 bits of data, a quadruple-level cell (QLC) that stores 4 bits of data, etc. That is, the memory cell can be an MLC that stores 2 or more bits of data, but this disclosure is not limited thereto.

[0060] The multiple memory blocks BLK1 to BLKz may include at least one of a single-level cell block containing SLC, a multi-level cell block containing MLC, a three-level cell block containing TLC, and a four-level cell block containing QLC. For example, some memory blocks in the multiple memory blocks BLK1 to BLKz of the memory cell array 321 may be single-level cell blocks, while other memory blocks therein may be multi-level cell blocks or three-level cell blocks.

[0061] When an erase voltage is applied to the memory cell array 321, multiple memory cells can be in an erase state, and when a programming voltage is applied to the memory cell array 321, multiple memory cells can be in a programming state. Here, each memory cell can be in an erase state or at least one programming state distinguished by a threshold voltage. That is, the state of a memory cell can include an erase state and at least one programming state, and the specific state of each memory cell can be one of an erase state and at least one programming state.

[0062] The control logic circuit 323 can control various operations performed in the non-volatile memory device 300_1. For example, the control logic circuit 323 can output various control signals for writing data to or reading data from the memory cell array 321 based on the command CMD, the address ADDR, and the control signal CTRL. The control logic circuit 323 can control multiple programming operations to be performed on multiple pages.

[0063] Various control signals output by the control logic circuit 323 can be sent to the voltage generator 322, the row decoder 340, and the page buffer circuit 350. For example, the control logic circuit 323 can provide the voltage control signal CTRL_vol to the voltage generator 322.

[0064] In some embodiments, the control logic circuitry 323 may further include a cell counter 324. The cell counter 324 may count the number of memory cells corresponding to a specific threshold voltage or a range of specific threshold voltages based on data sensed by the page buffer circuitry 350. The cell counter 324 may generate a cell count value indicating the number of memory cells. The number of memory cells corresponding to a specific threshold voltage range may be counted through two read operations or a single pre-charge double sensing (SPDS) operation, each corresponding to a threshold voltage corresponding to a boundary value of the threshold voltage range, but this disclosure is not limited thereto.

[0065] Voltage generator 322 can be connected to memory cell array 321 via multiple word lines WL. Voltage generator 322 can generate various types of voltages for performing programming, reading, and / or erasing operations on memory cell array 321 based on the voltage control signal CTRL_vol. Voltage generator 322 can generate word line voltages VWL, such as programming voltage, verification voltage, read voltage, and erase voltage.

[0066] Programming voltages, verification voltages, read voltages, erase voltages, etc., generated by voltage generator 322 can be provided to selected word lines in a multi-word line WL. The selected word line can be at least one word line selected via row address X-ADDR. Each of the multi-word lines WL can include multiple pages, and programming operations, verification operations, read operations, etc., performed by the voltage generated by voltage generator 322 can be executed page by page. For example, programming voltages (or pulses) and verification voltages (or pulses) can be applied to selected pages within a selected word line to perform programming and verification operations on the selected pages.

[0067] During an erase operation, voltage generator 322 may apply an erase voltage to the well and / or common source line of the memory block. Furthermore, based on the erase address, voltage generator 322 may apply an erase allowable voltage (e.g., ground voltage) to all word lines WL of the memory block or to some word lines corresponding to some sub-blocks. During an erase verification operation, voltage generator 322 may apply an erase verification voltage to all word lines WL of a memory block, or apply the erase verification voltage word-by-word.

[0068] During programming operations, voltage generator 322 can apply a programming voltage to selected word lines among multiple word lines WL, and apply a programming pass voltage to unselected word lines among multiple word lines WL. Furthermore, during programming verification operations, voltage generator 322 can apply a programming verification voltage to selected word lines, and apply a verification pass voltage to unselected word lines.

[0069] During normal read operations, voltage generator 322 can apply a read voltage to the selected word line and apply a read pass voltage to the unselected word line.

[0070] During a data recovery read operation, voltage generator 322 may apply a read voltage to the selected word line and apply the read voltage to at least one word line adjacent to the selected word line. Alternatively, voltage generator 322 may apply the read voltage to the selected word line and at least one word line adjacent to the selected word line.

[0071] The row decoder 340 can select a specific word line from the word lines WL in response to the row address X-ADDR received from the control logic circuit 323. Specifically, during programming operations, the row decoder 340 can provide a programming voltage to the selected word line. Furthermore, the row decoder 340 can select some of the serial select lines SSL or some of the ground select lines GSL in response to the row address X-ADDR received from the control logic circuit 323.

[0072] Page buffer circuit 350 can be connected to memory cell array 321 via multiple bit lines BL. Page buffer circuit 350 can select some of the multiple bit lines BL in response to a column address Y-ADDR received from control logic circuit 323. During verification operations (such as erase verification or program verification operations) or read operations, page buffer circuit 350 can operate as a sense amplifier to sense data stored in selected memory cells via the selected bit lines. Simultaneously, during programming operations, page buffer circuit 350 can operate as a write driver to input data to be stored in memory cell array 321. Page buffer circuit 350 may include multiple page buffers. In this case, each of the page buffers can be connected to at least one bit line.

[0073] Page buffer circuit 350 can store data read from memory cell array 321 or data to be stored in memory cell array 321.

[0074] Page buffer circuit 350 may include a plurality of page buffers connected to their respective bit lines BL. The plurality of page buffers may be arranged corresponding to their respective bit lines, and each page buffer may include a plurality of latches. Hereinafter, page buffer circuit 350 will be defined as a page buffer circuit including a plurality of page buffers connected to their respective bit lines. However, the terminology used to describe embodiments of the present disclosure may be defined differently, and for example, a page buffer may correspond to multiple bit line arrangements, and a unit corresponding to an assembly arranged on each bit line may be defined as a page buffer unit. Page buffer circuit 350 may temporarily store data to be programmed into a selected page during a programming operation and temporarily store data read from a selected page during a read operation.

[0075] The control logic circuit 323, voltage generator 322, row decoder 340, and page buffer circuit 350 can form the peripheral circuit.

[0076] Figure 3 This is a perspective view of a memory block according to an embodiment of the present disclosure, and Figure 4 This is a circuit diagram of a memory block according to an embodiment of the present disclosure.

[0077] refer to Figure 3 The memory block BLK may include a stack of STs extending in the vertical direction VD on the substrate SUB. For example, the memory block BLK may include a single stack of STs between the substrate SUB and bit lines BL1 to BL3. A common source line CSL may be disposed on the substrate SUB, and an insulating film IL extending in the second horizontal direction HD2 may be sequentially disposed in the vertical direction VD in the region between two adjacent common source lines CSL on the substrate SUB. The insulating films IL may be spaced apart from each other in the vertical direction VD. In the region between two adjacent common source lines CSL on the substrate SUB, pillars P penetrating the insulating film IL in the vertical direction VD may be disposed. The pillars may be referred to as channel vias. The pillars P may be cup-shaped or cylindrical with a closed bottom surface extending in the vertical direction VD. The surface layer S of each of the pillars P may contain a silicon material of the first type and may be used as a channel region. Meanwhile, the inner layer I of each of the pillars P may contain an insulating material such as silicon oxide or an air gap.

[0078] In the region between two adjacent common source lines CSL, a charge storage layer CS can be disposed along the exposed surfaces of the insulating film IL, pillars P, and substrate SUB. The charge storage layer CS may include a gate insulating layer, a charge trapping layer, and a barrier insulating layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. Furthermore, gate electrodes GE, such as select lines GSL and SSL, and word lines WL1 to WL8, can be disposed on the exposed surface of the charge storage layer CS in the region between the two adjacent common source lines CSL. A drain DR can be disposed on each of a plurality of pillars P. On the drain DR, bit lines BL1 to BL3 extending in a first horizontal direction HD1 and spaced apart from each other by a specific distance in a second horizontal direction HD2 can be disposed.

[0079] refer to Figure 4 The memory block BLK may include NAND strings NS11 to NS33, and each NAND string (e.g., NS11) may include a series-connected string select transistor SST, multiple memory cells MC, and ground select transistor GST. The transistors SST and GST of each NAND string and the memory cells MC may be stacked vertically on the substrate.

[0080] Bit lines BL1 to BL3 can extend in a first direction, and word lines WL1 to WL8 can extend in a second direction. NAND strings NS11, NS21, and NS31 can be located between the first bit line BL1 and the common source line CSL, NAND strings NS12, NS22, and NS32 can be located between the second bit line BL2 and the common source line CSL, and NAND strings NS13, NS23, and NS33 can be located between the third bit line BL3 and the common source line CSL.

[0081] The string select transistor SST can be connected to the corresponding string select lines SSL1 to SSL3. The memory cells MC can be connected to their respective word lines WL1 to WL8. The ground select transistor GST can be connected to the corresponding ground select lines GSL1 to GSL3. The string select transistor SST can be connected to the corresponding bit line, and the ground select transistor GST can be connected to the common source line CSL. Here, the number of NAND strings, word lines, bit lines, ground select lines, and string select lines can vary depending on the embodiment.

[0082] Figure 5 A series of programming voltages for programming memory cells using multi-level data, according to an embodiment of the present disclosure, are shown.

[0083] As for how to perform programming, such as Figure 5As shown, programming voltages can be applied as a series of programming voltages V1 to V9 to the control gate of a memory element, such as a memory cell. A memory device can program data into a memory cell by performing multiple programming cycles PL1 to PL9 on the memory cell. This is an example, and the number of programming voltages V1 to V9 can vary.

[0084] The programming voltages V1 through V9 can be increased by predetermined step sizes ΔV1 through ΔV8 for each subsequent voltage. Verification operations can be performed within the range of programming voltages V1 through V9.

[0085] For memory arrays comprising multi-level cells, verification operations can be performed for each programming state of a memory element to determine whether the element has reached its data-associated verification level. For example, a multi-level cell (e.g., a 4-level MLC) that can store data in four programming states may require verification operations associated with three comparison pointers or verification voltages VP1 through VP3. Similarly, a multi-level cell (e.g., an 8-level MLC) that can store data in eight programming states may require verification operations associated with seven comparison pointers or verification voltages VP1 through VP7.

[0086] The reference to Incremental Stepping Pulse Programming (ISPP) shows... Figure 5 The programming voltages V1 to V9 are specified, and the voltage application time (horizontal width of the graph) can be constant. Figure 5 The programming loop can increase the applied voltage value of each voltage by a predetermined step level, i.e., ΔV1 to ΔV8, to control the threshold voltage of the memory cell.

[0087] Figure 6 This is a view used to illustrate the state of multiple memory cells according to some embodiments of this disclosure.

[0088] Already Figure 6 The diagram shows the states of TLC E and P1 through P7, and... Figure 6 The embodiments shown are based on TLC, but the embodiments of this disclosure are not limited thereto. For example, the embodiments of this disclosure described below can be applied to SLCs that can have two states (e.g., E and P1), MLCs that can have four states (e.g., E and P1 to P3), QLCs that can have 16 states (e.g., E and P1 to P15), etc. The following embodiments will be described assuming that the memory cells are TLCs.

[0089] exist Figure 6In the diagram, the horizontal axis represents the threshold voltage (Vth) of the memory cell, and the vertical axis represents the number of memory cells (#OF CELLS) corresponding to the threshold voltage (Vth) or memory cell count value.

[0090] A TLC can have eight states, E and any one of P1 through P7. For example, an erased TLC can have the erase state E. As another example, a programmed TLC can have any one of the seven programmed states, P1 through P7.

[0091] By programming the TLC, the area of ​​the threshold voltage distribution corresponding to at least one state of the TLC can be different from the area of ​​the threshold voltage distribution corresponding to other states. For example, by programming the TLC, the areas of the threshold voltage distribution corresponding to some states E and P1 to P5 of the TLC can be the same as each other, the area of ​​the threshold voltage distribution corresponding to P6 can be larger than the area of ​​the threshold voltage distribution corresponding to states E and P1 to P5 of the TLC, and the area of ​​the threshold voltage distribution corresponding to P7 can be smaller than the area of ​​the threshold voltage distribution corresponding to states E and P1 to P5 of the TLC.

[0092] In the following text, the area of ​​a specific threshold voltage range within the threshold voltage distribution corresponding to a specific state and the number of memory cells within the threshold voltage range can refer to the same object, and therefore, the two expressions can be used interchangeably.

[0093] During a read operation, the TLC state (E and P1 to P7) can be determined by sequentially applying the first read voltage Vrd1 to the seventh read voltage Vrd7 to the unselected word line and the first verification voltage VP1 to the seventh verification voltage VP7 to the selected word line. However, because during a programming operation, in addition to the programming voltage Vpgm (e.g., Figure 5 In addition to one of V1 to V9 in the SLC, verification voltages VP1 to VP7 can also be applied to the selected word line, so performing the programming operation requires a significant amount of time. As in the case of the TLC described above, the verification operation to apply the verification voltage to the SLC takes time during the programming operation. Therefore, the following will refer to... Figures 7 to 21 Various embodiments are described in which the time required for programming operations is reduced by skipping at least a portion of the verification process for programming operations, while ensuring the reliability of programming operations.

[0094] Figure 7 An operation method 700 of a storage system according to an embodiment of the present disclosure is illustrated. The operation method 700 of the storage system can be provided by the storage system (e.g., Figure 1The operation method 700 of the memory system 10) is executed, and can be executed for a specific memory block within the memory cell array of the memory device. The operation method 700 of the memory system can be an operation method for reducing the time and resources required to perform programming operations in the memory block by performing fast programming operations on at least some of the multiple pages in the memory block. For example, a programming loop can be executed without a verification procedure for a page or word line containing a single-level cell, thereby reducing the time and resources required to apply a verification voltage to the memory cell.

[0095] In the S710, the control logic circuitry of the storage system or memory device can perform an erase operation on a memory block and obtain first information about the memory block based on the erase operation. (See reference...) Figures 9 to 12 Describe the specific process of S710 in detail.

[0096] In S720, the storage system can determine a first score based on the first information obtained in S710. (Refer to...) Figure 13 and Figure 14 Describe the specific process of S720 in detail.

[0097] In the S730, the control logic circuitry of the storage system or memory device can perform normal programming operations that run one or more programming cycles, and obtain second information about the memory block based on these normal programming operations. (See reference...) Figure 15 and Figure 16 Describe the specific process of S730 in detail.

[0098] In S740, the storage system can determine the second score based on the second information obtained in S730. (Refer to...) Figure 17 and Figure 18 Describe the specific process of S740 in detail.

[0099] In S750, the storage system can determine the number of word lines or pages to which a fast programming operation will be applied (fast programming count) based on the first and second fractions determined in S720 and S740, respectively. (See reference...) Figure 19 and Figure 20 Describe the specific process of S750 in detail.

[0100] In S760, the control logic circuitry of the storage system or memory device can perform fast programming operations based on a fast programming count already determined in S750. For example, the storage system can determine that the fast programming count is N (N is an integer equal to or greater than zero), and can perform fast programming operations on N pages (perform fast programming N times).

[0101] In one embodiment, the storage controller may send a command to the storage device to instruct a programming operation to skip a verification procedure for each of the pages corresponding to a determined fast programming count, and the storage device may perform a fast programming operation on the pages corresponding to the fast programming count in response to receiving the command. The command to instruct the programming operation to skip the verification procedure may include a single command, or may include a programming command for the programming operation and a command to skip verification.

[0102] In other embodiments, the storage controller may send programming commands to the storage device for programming operations, and the storage device may determine a fast programming count and perform a fast programming operation on the pages commanded by the programming commands and corresponding to the determined fast programming count. (See also...) Figure 21 Describe the specific process of S760 in detail.

[0103] In response to the number of times the fast programming operation is fully performed in S760 and corresponds to the fast programming count determined in S750, the storage system can perform a normal programming operation in S730 by applying a programming voltage and a verification voltage to the page to be programmed after the page to which a fast programming operation has already been performed, and can obtain second information. In S740, the storage system can determine or update the second score based on the obtained second information (e.g., information about the page to which a normal programming operation has already been performed), and in S750, can determine or update the fast programming count to be performed after the page to which a normal programming operation has already been performed based on the determined second score. Therefore, the fast programming count can be determined by considering information about adjacent pages or word lines.

[0104] In one embodiment, the storage system may update the fast programming count only when the fast programming count decreases.

[0105] In the S760, the storage system can perform fast programming by applying a programming voltage to each page corresponding to the updated fast programming count and skipping the verification procedure.

[0106] The storage system can repeat steps S730 to S760 until normal or fast programming operations have been completed for all pages within the memory block.

[0107] Figure 8A The execution was shown Figure 7 The storage system's operating methods and components.

[0108] The erase module 810 can perform erase operations on memory blocks, for example, Figure 7The erase operation in S710. The erase module 810 can obtain first information 812 about the memory block based on the result of the erase operation, for example, Figure 7 The first information in S710 is processed, and the obtained first information 812 is sent to the first score calculator 820. The erasure module 810 can send the obtained first information 812 to the information storage module 880.

[0109] The first fraction calculator 820 can determine the first fraction 822 based on the received first information 812, for example, Figure 7 The first score 822 is determined by the S720 and sent to the third score calculator 840. The first score calculator 820 can then send the determined first score 822 to the information storage module 880.

[0110] Normal programming module 870 can perform normal programming operations on specific pages (e.g., selected pages) within a memory block, for example, Figure 7 The normal programming operation of S730. The normal programming module 870 can obtain second information 872 about the selected page and / or the selected word line including the selected page based on the result of performing the normal programming operation, for example, Figure 7 The second information of S730 is obtained and sent to the second score calculator 830. The normal programming module 870 can send the obtained second information 872 to the information storage module 880.

[0111] The second fraction calculator 830 can determine the second fraction 832 based on the received second information 872, for example, Figure 7 The second score 832 is determined by the second score calculator 830 and sent to the third score calculator 840. The second score calculator 830 can then send the determined second score 832 to the information storage module 880.

[0112] The third score calculator 840 can determine the total score 842 based on the received first score 822 and second score 832, and send the determined total score 842 to the mode selector 850. Although not in Figure 8A As shown, however, the third score calculator 840 can send the determined total score 842 to the information storage module 880.

[0113] The mode selector 850 can receive the total score 842 and determine the quick programming count 852 and send it to the quick programming module 860. For example, when the quick programming count 852 is one or greater, the mode selector 850 can send the quick programming count 852 along with a command or signal to activate the quick programming module 860.

[0114] When the fast programming operation has been performed a number of times corresponding to the fast programming counter 852, or when the fast programming counter 852 is 0, the mode selector 850 can send a command or signal to the normal programming module 870 to activate the normal programming module 870. For example, whenever the mode selector 850 sends a command or signal to the fast programming module 860 to activate the fast programming module, the mode selector 850 can count the number of times the fast programming operation has been performed using a programming counter, etc., and when the number of times the fast programming operation has been performed equals the fast programming counter 852, the mode selector 850 can send a command or signal to the normal programming module 870 to activate the normal programming module 870.

[0115] refer to Figure 8A The third fraction calculator 840 and the mode selector 850 are separate components, but this disclosure is not limited thereto. For example, the third fraction calculator 840 and the mode selector 850 can be formed as a module, and a single module can receive a first fraction 822 and a second fraction 832 and output a fast programmable count 852.

[0116] exist Figure 8A In this disclosure, calculators 820, 830, and 840 are separate components, but this disclosure is not limited thereto. The first fraction calculator 820 and the second fraction calculator 830 may be configured as a single calculator, or the first fraction calculator 820, the second fraction calculator 830, and the third fraction calculator 840 may be configured as a single calculator.

[0117] The quick programming module 860 and the normal programming module 870 can be combined into a single programming module.

[0118] In one embodiment, the first score calculator 820, the second score calculator 830, the third score calculator 840, the mode selector 850, etc., may include or be connected to corresponding memories, such as registers. For example, after a first score 822 determined from the first score calculator 820 and a second score 832 determined from the second score calculator 832 have been stored in registers included in or connected to the third score calculator 840, the third score calculator 840 may begin to calculate the total score 842 by performing read operations on its corresponding registers.

[0119] The information stored in the information storage module 880 can store a predetermined time, a predetermined fast programming count, and a predetermined number of times the fast programming count is calculated. The description "information can be stored for a predetermined number of times the fast programming count is calculated" means that if the calculation operation of the fast programming count is determined to be repeated a specific number of times (e.g., 5 times), the information used in the earliest calculation can be sequentially deleted or updated. The information stored in the information storage module 880 can be used by calculators 820, 830, and 840. For example, for data collected immediately after a sudden power off (SPO) of the memory device, the total score 842 can be calculated by reflecting the data used in calculating the previous total score at a certain ratio.

[0120] Figures 8B to 8D It shows Figure 8A Various examples of the location of components in storage system 10.

[0121] refer to Figures 8B to 8D The erase module 810, the fast programming module 860, and the normal programming module 870 can be included in the memory device 300_1. For example, the erase module 810, the fast programming module 860, and the normal programming module 870 can be included in the control logic circuit of the memory device 300_1 (e.g., Figure 2 In the control logic circuit 323). It should be understood that, Figures 8B to 8D The components of memory device 300_1 can be applied to any memory device connected to memory controller 200.

[0122] refer to Figure 8B The first fraction calculator 820, the second fraction calculator 830, the third fraction calculator 840, and the mode selector 850 can be included in the storage controller 200.

[0123] according to Figure 8B In the illustrated embodiment, the memory device 300_1 or control logic circuitry can perform an erase operation on the memory block. The memory device 300_1 or control logic circuitry can obtain first information 812 about the memory block based on the result of the erase operation, and send the obtained first information 812 to the memory controller 200.

[0124] The memory device 300_1 or the control logic circuit can perform normal programming operations on a specific page within the memory block. The memory device 300_1 or the control logic circuit can obtain second information 872 about the selected page and / or the selected word line including the selected page based on the result of performing the normal programming operation, and send the obtained second information 872 to the memory controller 200.

[0125] The storage controller 200 can receive first information 812 and second information 872 about the memory block.

[0126] The storage controller 200 can determine a fast programming count based on information about the memory block and send it to the storage device 300_1. For example, the storage controller 200 can determine a first score 822 based on received first information 812 and a second score 832 based on received second information 872. The storage controller 200 can determine a total score 842 based on the first score 822 and the second score 832, and can determine a fast programming count 852 for performing fast programming operations based on the total score 842 and send it to the storage device 300_1.

[0127] When the fast programming count 852 is one or greater, the memory controller 200 can send the fast programming count 852 along with a command or signal to activate the fast programming module 860 or the control logic circuit. Conversely, when the fast programming count 852 is zero, the memory controller 200 can send a command or signal to activate the normal programming module 870 or the control logic circuit.

[0128] The memory device or control logic circuitry can receive information about the fast programming counter 852 from the memory controller 200 and perform a fast programming operation by applying a programming voltage to each page corresponding to the fast programming counter 852 and skipping the verification procedure for each page corresponding to the fast programming counter 852. The memory device or control logic circuitry can perform a normal programming operation by applying a programming voltage and a verification voltage to the page to be programmed after the page corresponding to the fast programming counter 852.

[0129] refer to Figure 8C The first fraction calculator 820, the second fraction calculator 830, the third fraction calculator 840, and the mode selector 850 can be included in the memory device 300_1.

[0130] and Figure 8B Unlike the examples in the examples, memory device 300_1 or control logic circuitry can determine the fast programming count 852 based on information about the memory block. For example, memory device 300_1 or control logic circuitry can determine a first score 822 based on first information 812 and a second score 832 based on second information 872. Memory device 300_1 or control logic circuitry can determine a total score 842 based on the first score 822 and the second score 832, and determine a fast programming count 852 for performing fast programming operations based on the total score 842.

[0131] When the fast programming counter 852 is one or greater, the fast programming module 860 can perform a fast programming operation by applying a programming voltage to each page corresponding to the fast programming counter 852 and skipping the verification procedure for each page corresponding to the fast programming counter 852. The normal programming module 870 can perform a normal programming operation by applying a programming voltage and a verification voltage to the page to be programmed after the page corresponding to the fast programming counter 852.

[0132] refer to Figure 8D The first fraction calculator 820, the second fraction calculator 830, the third fraction calculator 840, and the mode selector 850 can be included in the host device 20.

[0133] and Figure 8B Unlike the example in the example, the memory device 300_1 or the control logic circuit can send the first information 812 and the second information 872 that have been obtained to the host device 20 through the memory controller 200.

[0134] The host device 20 can receive first information 812 and second information 872 related to the memory block through the storage controller 200.

[0135] The host device 20 can determine a fast programming count based on information about the memory block and send it to the memory device 300_1 via the memory controller 200. For example, the host device 20 can determine a first score 822 based on received first information 812 and a second score 832 based on received second information 872. The host device 20 can determine a total score 842 based on the first score 822 and the second score 832, and determine a fast programming count 852 for performing fast programming operations based on the total score 842 and send it to the memory device 300_1 via the memory controller 200.

[0136] When the fast programming count 852 is one or greater, the host device 20 can send the fast programming count 852 along with a command or signal for activating the fast programming module 860 or the control logic circuit via the storage controller 200. Conversely, when the fast programming count 852 is zero, the host device 20 can send a command or signal for activating the normal programming module 870 or the control logic circuit via the storage controller 200.

[0137] The memory device or control logic circuitry can receive a fast programming count 852 from the host device 20 via the memory controller 200, and perform a fast programming operation by applying a programming voltage to each page corresponding to the fast programming count 852 and skipping the verification procedure for each page corresponding to the fast programming count 852. The memory device or control logic circuitry can perform a normal programming operation by applying a programming voltage and a verification voltage to the page to be programmed after the page corresponding to the fast programming count 852.

[0138] In one embodiment, Figure 8A The information storage module 880 can be included in the host device 20, the storage controller 200, or the memory device 300_1. In other embodiments, Figure 8A The information storage module 880 may include multiple modules, and each of the multiple modules may be included in the host device 20, the storage controller 200, or the memory device 300_1.

[0139] Figure 9 It is used to show in detail Figure 7 The flowchart of S710 in the diagram. S710 can be made by a memory device (e.g., Figure 2 In memory device 300_1), specifically, the control logic circuit of the memory device (e.g., Figure 2 The control logic circuit 323 in the middle is executed. Figure 9 The information obtained in S711, S713, S717 and S718 can be included Figure 7 The first information about the memory block in S710.

[0140] In S711, the memory device can obtain initial information. Initial information may include information that can be obtained without performing a separate erase or pre-programming operation. Initial information may be related to the current performance and / or period of use of the memory block.

[0141] In one embodiment, the initial information may include whether a memory block corresponds to a weak block. A weak block can be defined as a memory block in which the rate of increase of error bits during a program-erase cycle (PE cycle) exceeds a threshold rate of increase. When a memory block corresponds to a weak block, there is a high probability that programming pages within the memory block will fail within a single programming cycle; that is, fast programming operations will fail. Whether a specific memory block corresponds to a weak block can be determined by information pre-stored in the memory controller or memory device, or by looking up the address of the memory block, etc.

[0142] In one embodiment, initial information may include how many program-erase cycles (PE cycles) have been performed in the memory block.

[0143] In one embodiment, the initial information may include whether a memory cell within the memory block has been operated as a multilevel unit storing two or more bits of data. The initial information may also include how many times a memory cell within the memory block has been operated as a multilevel unit storing two or more bits of data.

[0144] In addition, initial information may include information about the date the memory device was powered off, information about the EPI time, information about the temperature, etc.

[0145] In S712, the memory device can perform a pre-programming operation to increase the threshold voltage of the over-erasing state of the memory cells. In S713, after performing the pre-programming operation, the memory device can obtain a cell count value by counting the number of memory cells programmed in the highest programming state (e.g., the SLC programming state) that have a threshold voltage less than or equal to the critical threshold voltage. (Refer to...) Figure 10A and Figure 10B S712 and S713 are described in detail.

[0146] In S714, the memory device can perform an erase operation. In S715, after performing the erase operation, the memory device can perform an erase verification operation to verify whether the erase operation was successful. In S716, the memory device can determine whether the erase operation was successful based on the erase verification operation. In response to determining that the erase operation failed based on the erase verification operation, in S714, the memory device can perform the erase operation again. Here, the erase voltage used for the re-execution of the erase operation can be a voltage at a higher level than the previous erase voltage. Conversely, in response to determining that the erase operation was successful based on the erase verification operation in S716, in S717, the memory device can obtain an erase cycle count. That is, based on the number of repetitions of S714 to S716, the erase operation performed on the memory block can include one or more erase cycles, and the memory device can obtain the count of these erase cycles as part of the first information. (Refer to...) Figure 11 Detailed description of S714 to S717.

[0147] In S718, the memory device can obtain a cell count value by counting the number of memory cells in the memory block that are in an erased state and have a threshold voltage lower than or equal to a critical threshold voltage. (Refer to...) Figure 12 This will be described in detail.

[0148] Figure 10A and Figure 10B It is used to show in detail Figure 9 Views of S712 and S713 in the diagram. (The diagram contains...) Figure 10A and Figure 10B The memory block with the threshold voltage distribution shown can be a single-cell memory block including single-level cells (SLC).

[0149] refer to Figure 10A Figure 1010 illustrates the threshold voltage distribution observed before pre-programming of a memory block. The critical threshold voltage Vtest can be a read level that causes the number of error bits in the programming state P of a memory cell for which pre-programming has not yet been performed to become a specific value (e.g., 100). The memory device or control logic circuitry can determine the critical threshold voltage Vtest by performing a read operation while gradually increasing the read level and checking for error bits.

[0150] The memory device can determine the first cell count value 1012 by counting the memory cells in the programming state P that have a threshold voltage lower than or equal to the critical threshold voltage Vtest.

[0151] refer to Figure 10B Figure 1020 shows the threshold voltage distribution observed after a pre-programming operation was performed on a memory block. Due to the increased property of the threshold voltage in the over-erased state of the memory cell caused by the pre-programming operation, the threshold voltage of the memory cell may generally increase. For example, compared to... Figure 10A Compared to Figure 1010, it can be seen that, Figure 10B The threshold voltage distribution curve in Figure 1020 has shifted to the right overall.

[0152] After the pre-programming operation has been performed, the memory device can determine the second cell count value 1022 by counting the memory cells in the memory block that are in a programmed state and have a threshold voltage lower than or equal to the critical threshold voltage Vtest.

[0153] Because memory cells are less responsive to preprogramming operations, it may be difficult to complete a programming operation by executing only one programming loop. In other words, because memory cells are less responsive to preprogramming operations, when programming a page within a memory block, it is likely that two or more programming loops will be executed, and fast programming operations will fail.

[0154] As the second cell count value of 1022 decreases, the memory cell may become more responsive to pre-programmed operations. Therefore, as the second cell count value of 1022 decreases, Figure 10A The first unit count value 1012 and Figure 10B If the difference between the second cell count value 1022 and the first cell count value increases, or if the ratio of the second cell count value to the first cell count value decreases, fast programming operations for pages within a memory block are less likely to fail.

[0155] Figure 11 It is used to show in detail Figure 9 Views S714 to S717 in the diagram.

[0156] refer to Figure 9 and Figure 11 The erase operation in S714 to S716 can be an erase operation by incremental step pulse erasing (ISPE).

[0157] An erase operation can include one or more erase cycles. For example, refer to... Figure 11 The memory device can sequentially execute multiple erase cycles (LOOP(1), LOOP(2), LOOP(3), ...) until the erase operation is completed. As the erase cycle repeats, the erase voltage (VERS1, VERS2, VERS3, ...) can be gradually increased.

[0158] Each erase cycle LOOP(i) can include an erase period ERASE and an erase verification period VERIFY.

[0159] refer to Figure 9 and Figure 11 In S714, the memory device can apply erase voltages (VERS1, VERS2, VERS3, ...) to the channel and apply erase allow voltages to the word lines during the ERASE period to perform an erase operation for erasing memory cells.

[0160] refer to Figure 9 and Figure 11 In the S715, the memory device can apply the erase verification voltage VVE to the word line during the erase verification period VERIFY to perform an erase verification operation to verify whether the erase has been successful.

[0161] refer to Figure 9 and Figure 11In S716, the memory device can determine whether the conditions for passing the erase verification operation have been met, thus determining whether the erase operation has been successfully passed. The memory device can repeat the erase operation and erase verification operation while gradually increasing the erase voltage (VERS1, VERS2, VERS3, ...) until the passing condition is met. Here, the passing condition can refer to the maximum allowable number of memory cells among the selected memory cells to be erased that have a threshold voltage higher than the data erase verification voltage VVE and have not yet been erased, and the erase cycle can be repeated until the number of memory cells that have not yet been erased is less than the maximum allowable number. The maximum allowable number can be determined based on the ECC level of the non-volatile memory device.

[0162] refer to Figure 9 and Figure 11 In S717, the memory device can obtain an erase cycle count. For example, when S714 to S716 are repeated three times and LOOP(1) to LOOP(3) are executed, the memory device can obtain "three" as an erase cycle count. The erase cycle count can indicate the degree of response of the memory cell to the erase voltage.

[0163] Because memory cells are not very responsive to erase operations, it may be difficult to complete an erase operation using only one erase cycle. In other words, because memory cells are not very responsive to erase operations, when performing an erase operation on a memory block, it is likely that two or more erase cycles will be executed, and fast programming operations will fail.

[0164] As the erase cycle count decreases, memory cells become more responsive to erase and program operations. Therefore, as the erase cycle count decreases, fast programming operations on pages within a memory block are less likely to fail.

[0165] Figure 12 It is used to show in detail Figure 9 The view of S718 in the image.

[0166] Figure 1210 shows the threshold voltage distribution observed after an erase operation is performed on a memory block. The memory device can obtain the cell count value 1212 by counting the memory cells in the erase state E and having a threshold voltage lower than or equal to the critical threshold voltage Vde.

[0167] The critical threshold voltage Vde refers to the threshold voltage in the erase state. In the erase state, it is difficult to reach the minimum threshold voltage required for the programming state through programming operations. Memory cells with a threshold voltage below the critical threshold voltage Vde can be called deep-erased memory cells, and fast programming operations on such memory cells are likely to fail.

[0168] Figure 13 It is used to show in detail Figure 7 The view of S720 in the image.

[0169] Storage systems (e.g., Figure 1 The storage system 10 in the middle can be based on the storage system 10 in the middle. Figure 7 The first information 812 collected in S710 determines the first score 822. Summarize the above references. Figures 9 to 12 In the described embodiment, the first information 812 may include initial information 812_1 about the memory block, a cell count value 812_2 of the memory block in a programmed state after a preprogramming operation, a count 812_3 of the erase cycles performed on the memory block, and a cell count value 812_4 of the memory block in an erased state below a critical threshold voltage after an erase operation.

[0170] The first score calculator 820 within the storage system can receive first information 812 and determine a first score 822. In one embodiment, the first score calculator 820 can determine the first score 822 based on at least a portion of the first information 812.

[0171] The first fraction calculator 820 can assign a higher first fraction 822 because it determines that the fast programming operation performed within the memory block is unlikely to fail; that is, the programming operation is likely to succeed using a single programming loop against a specific page or word line within the memory block. When the first fraction 822 determined by the first fraction calculator 820 is higher, fast programming can be performed more times.

[0172] In one embodiment, when the memory block is not a weak block, the first score calculator 820 may assign a higher first score 822 based on the initial information 812_1, compared to when the memory block is a weak block.

[0173] In one embodiment, when the count of the program-erase cycles of the initial information 812_1 corresponds to a second count greater than the first count, the first score calculator 820 may assign a lower first score 822 compared to when the count of the program-erase cycles corresponds to a first count. For example, the count of the program-erase cycles and the first score 822 may be inversely proportional under the same conditions. This is because fast programming operations are likely to fail, as the memory cell may become less responsive to the programming voltage due to frequent write and erase operations as the count of the program-erase cycles increases.

[0174] In one embodiment, when each memory cell within a memory block has not yet been used as a multi-level unit operation to store two or more bits of data, the first score calculator 820 may assign a higher first score 822 based on the initial information 812_1, compared to when each memory cell has a history of being used as a multi-level unit operation. This is because when a memory cell has a history of being used as a multi-level unit operation, fast programming operations are more likely to fail, as the memory cell may become less responsive to programming voltages due to frequent read operations, etc.

[0175] In one embodiment, since the memory cells within the memory block have been operated as multi-level units less frequently, the first score calculator 820 can assign a higher first score 822.

[0176] In one embodiment, when a cell count value 812_2 (e.g., after pre-programming, is in a programmed state and has a threshold voltage lower than or equal to a critical threshold voltage) is used... Figure 10B When the second cell count value 812_2 is high, the first fraction calculator 820 can assign a lower first fraction 822. This is because, since the memory cell is less responsive to the programming voltage, the cell count value 812_2 may be high, and a fast programming operation is likely to fail.

[0177] In other embodiments, when the cell count value 812_2 is in the programmed state after pre-programming and has a threshold voltage lower than or equal to the critical threshold voltage (e.g., Figure 10B The second cell count value 1022 in the code is compared with the cell count value 812_2 (e.g., in the programmed state before pre-programming, which has a threshold voltage lower than or equal to the critical threshold voltage) Figure 10A When the ratio of the first unit count value (1012) in the first fraction calculator decreases, the first fraction calculator 820 can assign a higher first fraction 822.

[0178] In one embodiment, when the erase cycle count 812_3 is high, the first score calculator 820 may assign a lower first score 822. This is because fast programming operations targeting pages or word lines within a memory block are likely to fail, as the memory cells may become less responsive to erase and programming voltages as the erase cycle count 812_3 increases.

[0179] In one embodiment, when the cell count value 812_4, which is below the critical threshold voltage and is in the erased state after an erase operation (e.g., ...), ... Figure 12 As the cell count value 812_4 increases, the first fraction calculator 820 can allocate a lower first fraction 822. This is because fast programming operations targeting pages or word lines within a memory block are likely to fail, as the number of memory cells within the memory block that are difficult to reach the minimum threshold voltage for programming may increase as the cell count value 812_4 increases.

[0180] Figure 14 It is used to show in detail Figure 7 The flowchart of S720 in the document. Figure 14 The flowchart in the diagram represents the use of Figure 13 The first fraction calculator 820 in the example demonstrates a specific process for determining the first fraction 822, but the process for determining the first fraction 822 is not limited to this.

[0181] In S721, the first fraction 822 can be set to an initial value, such as 100. In S722, the first fraction 822 can be the initial value and the cell count value (p_under_ref, e.g., a cell that is in a programmed state before pre-programming and has a threshold voltage lower than or equal to the critical threshold voltage) that is also present. Figure 10A The first cell count value (1012) and the cell count value (p_under_count, e.g., p_under_count) in the programmed state after pre-programming, having a threshold voltage lower than or equal to the critical threshold voltage. Figure 10B The smaller of the values ​​obtained by multiplying the ratio of the second cell count value 1022 in the memory cell by a coefficient (e.g., 0.05). That is, the first fraction 822 can be updated proportionally to the degree of responsiveness of the memory cell to the pre-programmed operation.

[0182] In S723, the first fraction calculator 820 can be based on the cell count value (E_STATE_COUNT) that is in the erased state after the erase operation and is below the critical threshold voltage (e.g., Figure 12 The first score 822 is determined by whether the unit count value (1212) in the middle exceeds the threshold.

[0183] In response to determining that the cell count value below the critical threshold voltage in the erase state after the erase operation exceeds a threshold, the first fraction calculator 820 can decrease the first fraction 822. For example, in S723_1, in response to determining that the cell count value below the critical threshold voltage in the erase state exceeds the threshold, the first fraction calculator 820 can set the first fraction 822 to zero. When the first fraction 822 is set to zero, Figure 14 The S720 in the middle can terminate and the process can proceed to... Figure 7 The S730 in the middle.

[0184] In response to a cell count value below the critical threshold voltage that is not determined to be in an erasure state exceeding the threshold, the first score calculator 820 may maintain the original value of the first score 822.

[0185] In S724, the first score calculator 820 can determine the first score 822 based on whether the memory block corresponds to a weak block.

[0186] The first fraction calculator 820 can decrease the first fraction 822 in response to a memory block corresponding to a weak block. For example, in S724_1, the first fraction calculator 820 can set the first fraction 822 to zero in response to a memory block corresponding to a weak block. When the first fraction 822 is set to zero, Figure 14 The S720 in the middle can terminate and the process can proceed to... Figure 7 The S730 in the middle.

[0187] In response to a memory block not corresponding to a weak block, the first score calculator 820 can maintain the original value of the first score 822.

[0188] The first fraction calculator 820 can decrease the first fraction 822 as the count of programming-erase cycles increases. For example, in S725, the first fraction calculator 820 can update the first fraction 822 by dividing the first fraction 822 by the count of programming-erase cycles (PE cycles) and multiplying the result by a specific coefficient (e.g., 100).

[0189] In S726, the first fraction calculator 820 can determine the first fraction 822 based on whether each memory cell in the memory block has ever been used as a multi-level unit operation to store two or more bits of data.

[0190] The first fraction calculator 820 can decrease the first fraction 822 in response to a memory cell in the memory block having been operated as a multi-level cell. For example, in S726_1, in response to determining that a memory cell in the memory block has been operated as a multi-level cell, the first fraction calculator 820 can divide the first fraction 822 by a specific value, such as 2.

[0191] In response to the fact that a memory cell in the memory block has not yet been operated as a multi-level unit, the first fraction calculator 820 can maintain the original value of the first fraction 822.

[0192] In S727, the first score calculator 820 can determine the first score 822 based on whether the count of the erase cycles included in the erase operation for the memory block exceeds a threshold number (e.g., 5).

[0193] In response to the count of erase cycles included in the erase operation for the memory block exceeding a threshold number, the first fraction calculator 820 can decrease the first fraction 822. For example, in S727_1, in response to the count of erase cycles included in the erase operation for the memory block exceeding the threshold number, the first fraction calculator 820 can set the first fraction 822 to zero. When the first fraction 822 has been set to zero, Figure 14 The S720 in the middle can terminate and the process can proceed to... Figure 7 The S730 in the middle.

[0194] In response to determining that the count of the erasure cycle has not exceeded the threshold number, the first score calculator 820 can maintain the original value of the first score 822.

[0195] In S728, the first fraction calculator 820 can determine the first fraction 822 based on whether the count of the erase cycle included in the erase operation for the memory block is "one".

[0196] The first fraction calculator 820 may decrease the first fraction 822 in response to the count of the erase cycle included in the erase operation for the memory block being not "one". For example, in S728_1, the first fraction calculator 820 may divide the first fraction 822 by a specific value, such as 2, in response to the count of the erase cycle included in the erase operation for the memory block being not "one".

[0197] The first fraction calculator 820 can maintain the original value of the first fraction 822 in response to the count of the erase cycle included in the erase operation for the memory block being "one".

[0198] Figure 14 The operation in S720 of dividing the first fraction 822 and setting it to a specific value such as "zero" can be replaced with other operations. For example, these operations can be replaced by any of the operations of decreasing the first fraction 822. For example, these operations can be any of the operations of dividing the first fraction 822 by a specific value, setting it to a specific value lower than the current value, and subtracting a specific value from the first fraction 822.

[0199] Figure 15 It is used to show in detail Figure 7The flowchart of S730 in the diagram. S730 can be made by a memory device (e.g., Figure 2 In the memory device 300_1), specifically, the control logic circuit of the memory device (e.g., Figure 2 The control logic circuit 323 in the middle is executed. Figure 15 The information obtained in S731, S733, and S734 can be included Figure 7 The second information about the memory block in S730.

[0200] In S731, the memory device can obtain weak word lines (weak WL) information within a memory block. Weak word lines may be susceptible to the influence of adjacent word lines or memory cells and have poor properties. The weak word line information within the memory block (e.g., the location of the weak word lines, etc.) can be experimental data that has been measured and recorded in advance.

[0201] In S732, a memory device can perform a normal programming operation by applying a programming voltage and a verification voltage to selected pages within a memory block. For example, the memory device can perform a normal programming operation in response to receiving a command from the memory controller instructing a normal programming operation. The memory device can perform a programming cycle by applying a programming voltage to the selected page and performing a verification operation by applying a verification voltage to the selected page to verify whether programming has been successful. Here, if programming fails, the memory device can re-execute the programming cycle by reapplying the programming voltage and verification voltage to the page. The memory device can perform a normal programming operation by executing one or more programming cycles.

[0202] In S733, a memory device can obtain a count of one or more programming cycles that have been executed for a selected page. For example, a memory device can obtain the count of programming cycles using the "GetNANDStatus" command.

[0203] In S734, a memory device can obtain a cell count value (P-state count) by counting memory cells in the memory cells connected to the selected page that are in a programmed state and have a threshold voltage lower than or equal to a critical threshold voltage. For example, the memory device can obtain the cell count value through the "GetFeature" command.

[0204] Figure 16 It is used to show in detail Figure 15 The view of S734 in the image.

[0205] Having such Figure 16 The memory block with the threshold voltage distribution shown can be a single-cell memory block including a single-level cell (SLC).

[0206] The memory device can obtain a cell count value 1612 by counting the memory cells connected to the selected page that are in a programmed state and have a threshold voltage lower than or equal to a critical threshold voltage Vth. The critical threshold voltage Vth can be a voltage corresponding to the level of the verification voltage for a verification operation, and the cell count value 1612 can indicate the number or proportion of memory cells that do not meet the criteria used to pass the verification operation. As the cell count value 1612 increases, it is likely that a fast programming operation will fail because the threshold voltage distribution may not shift to the desired location when the same voltage is applied to the selected page.

[0207] Figure 17 It is used to show in detail Figure 7 The view of S740 in the image.

[0208] Storage systems (e.g., Figure 1 The storage system 10 in the middle can be based on the storage system 10 in the middle. Figure 7 The second information 872 collected in S730 determines the second score 832. The second information 872 may include whether the word line of the selected page is a weak word line 872_1, the count of the programming cycle performed for the selected page 872_2, and the cell count value 872_3 of the cells in the programming state below the critical threshold voltage after the programming operation.

[0209] The second score calculator 830 within the storage system can receive the second information 872 and determine the second score 832. In one embodiment, the second score calculator 830 can determine the second score 832 based on at least a portion of the second information 872.

[0210] The second fraction calculator 830 can assign a higher second fraction 832 because it determines that the rapid programming operation is unlikely to fail; that is, the programming operation is likely to succeed using a programming loop. For example, as the second fraction 832 determined by the second fraction calculator 830 increases, rapid programming can be performed more times.

[0211] In one embodiment, when the word line including the selected page is a weak word line, the second score calculator 830 may assign a lower second score 832 compared to when the word line including the selected page is not a weak word line. This is because fast programming operations targeting the weak word line or its adjacent word lines are likely to fail due to the low responsiveness of the memory cells connected to the weak word line.

[0212] In one embodiment, the second fraction calculator 830 may assign a lower second fraction 832 as the count 872_2 of the programming cycle performed on the selected page increases. This is because the count 872_2 of the programming cycle may increase as the responsiveness to the programming voltage decreases, and the fast programming operation is more likely to fail.

[0213] In one embodiment, when the cell count value 872_3, which is below a critical threshold voltage and in a programmed state after a programming operation, increases, the second score calculator 830 may assign a lower second score 832. This is because the cell count value 872_3 may increase as the responsiveness to the programming voltage decreases, and the rapid programming operation is likely to fail.

[0214] Figure 18 It is used to show in detail Figure 7 The flowchart of S740 in the document. Figure 18 The flowchart in the diagram represents the use of Figure 17 The second fraction calculator 830 in the text provides a specific example of the process for determining the second fraction 832, but the process for determining the second fraction 832 is not limited to this.

[0215] In S741, the second fraction 832 can be set to an initial value, such as 100.

[0216] In S742, the second fraction calculator 830 can determine the second fraction 832 based on whether the word lines of the selected page, including the page to which normal programming operations have been performed, correspond to weak word lines.

[0217] In response to the fact that the word line of the selected page, which has already been properly programmed, corresponds to a weak word line, the second fraction calculator 830 can decrease the second fraction 832. For example, in S743, in response to the fact that the word line of the selected page, which has already been properly programmed, corresponds to a weak word line, the second fraction calculator 830 can set the second fraction 832 to zero. When the second fraction 832 is set to zero, Figure 18 The S740 in the middle can be terminated and the process can proceed to... Figure 7 The S750 in the middle.

[0218] In response to the fact that the word lines of the selected page, including those to which normal programming operations have been performed, do not correspond to weak word lines, the second fraction calculator 830 can maintain the original value of the second fraction 832.

[0219] In S744, the second fraction calculator 830 can determine the second fraction 832 based on whether the count of the programming loop performed on the selected page is equal to or greater than a threshold count.

[0220] In response to the fact that the count of the programming loop performed on the selected page is equal to or greater than a threshold count (e.g., 2 times), the second fraction calculator 830 can decrease the second fraction 832. For example, in S745, in response to the fact that the count of the programming loop performed on the selected page is equal to or greater than the threshold count, the second fraction calculator 830 can set the second fraction 832 to zero. When the second fraction 832 is set to zero, Figure 18The S740 in the middle can be terminated and the process can proceed to... Figure 7 The S750 in the middle.

[0221] In response to the fact that the count of the programming loop performed on the selected page is lower than the threshold count, the second fraction calculator 830 can maintain the original value of the second fraction 832.

[0222] In S746 and S748, the second fraction calculator 830 can determine the second fraction 832 based on the cell count value obtained by counting the memory cells connected to the selected page that are in a programmed state and have a threshold voltage lower than or equal to the critical threshold voltage.

[0223] For example, in S747, in response to the obtained cell count value being less than a first threshold (e.g., three percent of the total cell count value in the programming state), the second score calculator 830 can finally assign the second score 832 as the initial value.

[0224] In S748_1, in response to the obtained cell count value being equal to or greater than a first threshold and less than a second threshold greater than the first threshold (e.g., seven percent of the total cell count value in the programming state), the second fraction calculator 830 can ultimately assign the second fraction 832 to a value obtained by dividing the initial value by a specific value, such as 50.

[0225] In S748_2, in response to the obtained cell count value being equal to or greater than the second threshold, the second score calculator 830 can assign the second score 832 to a value lower than the value determined in S748_1, such as 0.

[0226] exist Figure 18 In this embodiment, the second score 832 is determined by classifying the cell count value into one of three ranges in S746 and S748, but this disclosure is not limited to this embodiment. For example, the cell count value can be classified into any number of multiple ranges, and the second score 832, as a score corresponding to that range, can be assigned.

[0227] Figure 18 The operation in S740 of dividing the second fraction 832 and setting it to a specific value such as "zero" can be replaced with other operations. For example, these operations can be replaced by any of the operations of decreasing the second fraction 832. For example, these operations can be any of the operations of dividing the second fraction 832 by a specific value, setting it to a specific value lower than the current value, and subtracting a specific value from the second fraction 832.

[0228] Figure 19 It is used to show in detail Figure 7 The view of the S750 in the image.

[0229] In one embodiment, the third score calculator 840 can determine that the sum of the first score 822 and the second score 832 is the total score 842. In another embodiment, the third score calculator 840 can determine that the weighted sum of the first score 822 and the second score 832 is the total score 842. For example, the weights applied to each of the first score 822 and the second score 832 can be any value in the range of zero to one. The sum of the weights applied to each of the first score 822 and the second score 832 can be one.

[0230] The mode selector 850 can determine the fast programmable count 852 based on the total score 842.

[0231] On the other hand, the third fraction calculator 840 and the mode selector 850 can be formed as a single module, and the single module can receive the first fraction 822 and the second fraction 832 and immediately determine and output the fast programmable count 852.

[0232] Figure 20 It is used to show in detail Figure 7 The flowchart of S750 is shown. S750 can be executed by the third fraction calculator 840 and the mode selector 850.

[0233] In S751, the third fraction calculator 840 can determine the total score 842.

[0234] In S752, S754, and S756, the mode selector 850 can determine which of a plurality of ranges the total score 842 falls into. In S753, S755, and S757, the mode selector 850 can determine, from a plurality of candidates for skipping counts corresponding to the plurality of ranges, a fast programmable count 852 corresponding to the range into which the total score 842 falls. The plurality of candidates for skipping counts may include a string selection line based on a memory cell array (e.g., ...). Figure 4 The number of skips (SSL1 to SSL3) is determined by the skip count.

[0235] For example, in S753, in response to the total score 842 being the maximum possible score, the mode selector 850 can determine the quick programming count 852 by subtracting one from a multiple (e.g., twice) of the number of string selection lines. This can be understood as follows: assuming that multiple pages corresponding to a multiple of the number of string selection lines (i.e., multiple pages in the word lines of the page that has been normally programmed to determine the second score) have similar properties, and that quick programming operations can be performed on such pages.

[0236] In S755, in response to the total score 842 being less than the maximum possible score and equal to or greater than the first threshold, the mode selector 850 can determine the quick programming count 852 by subtracting one from the number of string selection lines. This can be understood as follows: assuming that multiple pages corresponding to the number of string selection lines (i.e., multiple pages in the word lines including the pages that have already been normally programmed to determine the second score) have similar properties, and that quick programming operations can be performed on such pages.

[0237] In S757, in response to the total score 842 being less than a first threshold and equal to or greater than a second threshold, the mode selector 850 can determine the quick programming count 852 by subtracting one from half the number of string selection lines. This can be understood as follows: assuming that multiple pages corresponding to half the number of string selection lines (i.e., half of the word lines of multiple pages including the pages that have already been normally programmed to determine the second score) have similar properties, and that quick programming operations can be performed on such pages.

[0238] In S758, in response to the total score 842 being less than a possible second threshold, the mode selector 850 can determine that the fast programming count 852 is zero. That is, because there is a high probability that the fast programming operation will fail multiple times, it can be determined that normal programming operations will be performed on multiple pages within the corresponding memory block instead of fast programming operations.

[0239] The following text will summarize references. Figures 13 to 20 The embodiments described herein illustrate various embodiments of this disclosure.

[0240] In one embodiment, the control logic circuit (e.g., Figure 2 The control logic circuit 323 in the memory system can perform a pre-programming operation to increase the threshold voltage of the over-erased state of the memory cells, and can obtain a cell count value after the pre-programming operation by counting the memory cells programmed with a threshold voltage lower than or equal to the critical threshold voltage. The memory system (e.g., Figure 1 The storage system 10 in the middle can determine, in response to the obtained cell count value as a first value, that the fast programming count (e.g., the number of pages for which the verification process is skipped) corresponds to a specific value, and can determine, in response to the cell count value as a second value greater than the first value, that the fast programming count corresponds to a value less than the specific value.

[0241] In one embodiment, the control logic circuit (e.g., Figure 2The control logic circuit 323 in the memory system can obtain a cell count value by counting memory cells that are in an erased state and have a threshold voltage lower than or equal to the critical threshold voltage, and the memory system (e.g., Figure 1 The storage system 10 in the middle can determine that the fast programming count corresponds to a specific value in response to a first value of the cell count value, and determine that the fast programming count corresponds to a value less than the specific value in response to a second value of the cell count value greater than the first value.

[0242] In one embodiment, the control logic circuit (e.g., Figure 2 The control logic circuit 323 in the memory can perform an erase operation on the memory block, including one or more erase cycles, and the memory system (e.g., Figure 1 The storage system 10 in the middle can determine that the fast programming count corresponds to a specific value in response to a first value of one or more erase cycles, and determine that the fast programming count corresponds to a value less than the specific value in response to a second value of one or more erase cycles being greater than the first value.

[0243] In one embodiment, the storage system (e.g., Figure 1 The storage system 10 in the memory can determine that the fast programming count corresponds to a specific value in response to determining that the memory block is a weak block, and can determine that the fast programming count corresponds to a value greater than the specific value in response to determining that the memory block is not a weak block.

[0244] In one embodiment, the storage system (e.g., Figure 1 The storage system 10 in the middle can determine that the fast programming count corresponds to a specific value in response to the count of the program-erase cycle being a first value, and can determine that the fast programming count corresponds to a value less than the specific value in response to the count of the program-erase cycle being a second value greater than the first value.

[0245] In one embodiment, the storage system (e.g., Figure 1 The storage system 10) can determine that the fast programming count corresponds to a first value in response to determining that the memory cell has been operated as a multi-level cell, and can determine that the fast programming count corresponds to a second value greater than the first value in response to determining that the memory cell has never been operated as a multi-level cell.

[0246] In one embodiment, the control logic circuit (e.g., Figure 2 The control logic circuit 323 in the memory can execute one or more programming loops on selected pages from a plurality of pages, and the storage system (e.g., Figure 1The storage system 10 can determine that the fast programming count corresponds to a specific value in response to a first value being a count of one or more programming cycles, and determine that the fast programming count corresponds to a value less than the specific value in response to a second value being a count of one or more programming cycles being greater than the first value. The programming operation corresponding to the fast programming count can be a programming operation to be performed after a programming operation on the selected page.

[0247] In one embodiment, the control logic circuit (e.g., Figure 2 The control logic circuit 323 in the memory system can perform programming operations on selected pages among multiple pages, and can obtain a cell count value by counting memory cells connected to the selected page that are in a programmed state and have a threshold voltage lower than or equal to a critical threshold voltage. The memory system (e.g., Figure 1 The storage system 10 can determine that the fast programming count corresponds to a specific value in response to a first value obtained from the cell count value, and can determine that the fast programming count corresponds to a value less than the specific value in response to a second value obtained from the cell count value being greater than the first value. The programming operation corresponding to the fast programming count can be a programming operation to be performed after a programming operation for the selected page.

[0248] In one embodiment, the storage system (e.g., Figure 1 The storage system 10 in the memory can determine that the fast programming count is zero in the current programming-erase cycle in response to the fast programming count being zero based on a selected page among a plurality of pages in a programming-erase cycle performed before obtaining information about the memory block.

[0249] In one embodiment, the control logic circuit (e.g., Figure 2 The control logic circuit 323 in the memory can perform a programming operation in response to a programming operation performed in a programming-erase cycle before obtaining information about the memory block without performing a verification procedure for a selected page among multiple pages, by applying a programming voltage and a verification voltage to the selected page in the current programming-erase cycle.

[0250] In one embodiment, the storage system (e.g., Figure 1 The storage system 10) can determine that the fast programming count is below or equal to a predetermined threshold, such as 50 times. That is, the storage system can force the normal programming operation to be performed at regular intervals.

[0251] In one embodiment, the storage system (e.g., Figure 1 The storage system 10) can flexibly adjust the fast programming count based on the capacity of the single-level cell (SLC) cache and the capacity of the three-level cell (TLC) cache.

[0252] In one embodiment, the storage system (e.g., Figure 1 The storage system 10 can update the score by performing fast programming operations only on some of the fast programming counts and normal programming operations on the others. The storage system can recalculate the score based on the information obtained by performing normal programming operations and use the recalculated score to determine the fast programming count. In one example, the storage system can update the fast programming count only if the determined fast programming count is less than the existing fast programming count. In the example, assuming the storage system initially determines the fast programming count to be 10, the storage system first performs 4 fast programming operations (as part of the fast programming count). After the fourth fast programming operation, the storage system performs normal programming operations on the next page (the others). Through the normal programming operation, new, updated second information about the state of the memory cells is obtained. The storage system then recalculates the score based on this new information and uses the recalculated score to determine the fast programming count. This method allows the storage system to respond more quickly to changes in the state of memory cells during programming and minimizes the failure rate of fast programming operations, while still achieving the goal of "reducing the time spent performing programming operations".

[0253] Control logic circuits (e.g., Figure 2 The control logic circuit 323 in the above can receive information about the fast programming count determined according to the various embodiments described above, and can perform a programming operation by applying a programming voltage to each page corresponding to the fast programming count and skipping the verification procedure for each page corresponding to the fast programming count, and can perform a programming operation by applying the programming voltage and the verification voltage to the page after the page corresponding to the fast programming count to which programming operation is to be performed.

[0254] Figure 21 It is used to show in detail Figure 7 The view of S760 in the image.

[0255] Fast programming operations can be performed on pages corresponding to a determined fast programming count. For example, a fast programming count of two can be determined based on information obtained from a normal programming operation performed on PG1, allowing fast programming operations to be performed on PG2 and PG3.

[0256] Then, normal programming operations can be performed on PG4, which is the page to be programmed after the page corresponding to the fast programming count, and the fast programming count can be determined to be five based on the information obtained from the normal programming operations performed on PG4, so that fast programming operations can be performed on PG5 to PG9.

[0257] After that, normal programming operations can be performed on PG10, which is the page to be programmed after the page corresponding to the fast programming count, and the fast programming count can be determined to be zero based on the information obtained from the normal programming operations performed on PG10, so that normal programming operations can be performed on PG11.

[0258] Therefore, programming operation failures can be minimized by flexibly adjusting the fast programming count according to the various embodiments described above, while reducing the time required to perform programming on memory blocks. Consequently, the write speed of the memory device can be increased, and its throughput can be improved. Furthermore, the power consumption required to perform programming operations can be reduced, and the stress applied to the memory cells can be decreased, thereby extending the lifespan of the memory device.

[0259] One or more of the components disclosed herein may include or be implemented by processor circuitry, such as hardware including logic circuitry, hardware of a processor such as executing software, or combinations thereof. For example, processor circuitry may include a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-chip (SoC), a programmable logic device, a microprocessor, an application-specific integrated circuit (ASIC), etc., but this disclosure is not limited thereto.

[0260] This disclosure is not limited to the embodiments and drawings described above. Those skilled in the art can make various substitutions, modifications, and alterations to this disclosure within its technical scope, and these should be considered to fall within the scope of this disclosure. For example, one or more steps of each process described in the flowcharts in the accompanying drawings can be skipped, the order of the process steps can be changed, one or more steps can be performed simultaneously, or one or more steps can be repeated multiple times.

Claims

1. A storage device, comprising: A memory device, including control logic circuitry and a memory cell array, the memory cell array comprising a memory block having multiple pages to which memory cells are connected; and The storage controller is configured as follows: Obtain information about the memory block; Based on the obtained information about the memory block, determine the number of pages on which a first programming operation for skipping the verification procedure should be performed; and A first programming command for the first programming operation is sent to the memory device. in The memory device is configured to: Receive the first programming command from the storage controller; and The first programming operation is performed on the page indicated by the first programming command among the plurality of pages by executing a programming loop for skipping the verification process.

2. The storage device according to claim 1, wherein The storage controller is also configured to, in response to the completion of the first programming operation corresponding to the determined number of pages, send a second programming command to the storage device for a second programming operation on the next page to be programmed sequentially. The memory device is also configured to: Receive the second programming command from the storage controller; and The second programming operation is performed by executing one or more programming loops to apply programming and verification voltages to the next page to be programmed.

3. The storage device according to claim 2, wherein The storage controller is also configured to: Update the number of pages based on information about the pages to which the second programming operation has been performed; and Send a third programming command to the memory device for the first programming operation on pages corresponding to the updated number of pages, and The memory device is also configured to perform the first programming operation on the page indicated by the third programming command.

4. The storage device according to claim 3, wherein, The storage controller is also configured to update the number of pages only when a decrease in the number of pages is detected.

5. The storage device according to claim 1, wherein, The memory cell is a single-level cell, and the memory block is a single-level cell block.

6. The storage device according to claim 1, wherein The memory device is also configured to: Perform a pre-programming operation to increase the threshold voltage of the over-erased state of the memory cell; Following the pre-programming operation, a cell count value is obtained by counting the memory cells programmed with a threshold voltage lower than or equal to the critical threshold voltage; and The cell count value is sent to the storage controller. The information about the memory block includes the cell count value, and The storage controller is also configured to: In response to the cell count value being a first value, the number of pages is determined to be a first number; and In response to a second value where the cell count is greater than the first value, the number of pages is determined to be a second number less than the first number.

7. The storage device according to claim 1, wherein The memory device is also configured to: Perform an erase operation on the memory block; A cell count value is obtained by counting the memory cells in the erased state that have a threshold voltage lower than or equal to the critical threshold voltage; and The cell count value is sent to the storage controller. The information about the memory block includes the cell count value, and The storage controller is also configured to: In response to the cell count value being a first value, the number of pages is determined to be a first number; and In response to a second value where the cell count is greater than the first value, the number of pages is determined to be a second number less than the first number.

8. The storage device according to claim 1, wherein The memory device is also configured to: An erase operation is performed by executing one or more erase cycles on the memory block; and The count of the one or more erase cycles is sent to the storage controller. The information about the memory block includes the counts of the one or more erase cycles, and The storage controller is also configured to: In response to the count being a first value in the one or more erase cycles, the number of pages is determined to be a first quantity; and In response to the count of the one or more erase cycles being a second value greater than the first value, the number of pages is determined to be a second number less than the first number.

9. The storage device according to claim 1, wherein The information about the memory block includes whether the memory block is a weak block in which the rate of increase of error bits during the program-erase cycle of the memory block is greater than a threshold rate of increase, and The storage controller is also configured to: In response to determining that the memory block is the weak block, the number of pages is determined to be a first number; and In response to determining that the memory block is not the weak block, the number of pages is determined to be a second number greater than the first number.

10. The storage device according to claim 1, wherein The information about the memory block includes a count of the program-erase cycles performed for the memory block, and The storage controller is also configured to: In response to the count of the program-erase cycle being a first value, the number of pages is determined to be a first number; and In response to the count of the program-erase cycle being a second value greater than the first value, the number of pages is determined to be a second number less than the first number.

11. The storage device according to claim 1, wherein The information about the memory block includes whether each of the memory cells in the memory block has ever been operated as a multi-level unit storing two or more bits of data, and The storage controller is also configured to: In response to determining that the memory cell has been operated as the multilevel unit, the number of pages is determined to be a first number; and In response to determining that the memory cell has never been operated as the multilevel unit, the number of pages is determined to be a second number greater than the first number.

12. The storage device according to claim 1, wherein The storage controller is also configured to send a second programming command to the storage device for a second programming operation on a selected page of the plurality of pages. The memory device is also configured to: Receive the second programming command from the storage controller; and The second programming operation is performed by executing one or more programming loops to apply programming and verification voltages to the selected page. The information about the memory block includes the count of the one or more programming loops executed for the selected page. The storage controller is also configured to: In response to the count being a first value in the one or more programming loops, the number of pages is determined to be a first quantity; and In response to the count of the one or more programming loops being a second value greater than the first value, the number of pages is determined to be a second number less than the first number, and The first programming operation is the programming operation to be performed after the second programming operation on the selected page.

13. The storage device according to claim 1, wherein The storage controller is also configured to send a second programming command to the storage device for a second programming operation on a selected page of the plurality of pages. The memory device is also configured to: Receive the second programming command from the storage controller; The second programming operation is performed by executing one or more programming loops to apply programming voltage and verification voltage to the selected page; A cell count value is obtained by counting memory cells with a threshold voltage lower than or equal to the critical threshold voltage among the memory cells connected to the selected page to which the second programming operation has been performed; and The cell count value is sent to the storage controller. The information about the memory block includes the cell count value. The storage controller is also configured to: In response to the cell count value being a first value, the number of pages is determined to be a first number; and In response to a second value where the cell count is greater than the first value, the number of pages is determined to be a second number less than the first number, and The first programming operation is the programming operation to be performed after the second programming operation on the selected page.

14. The storage device according to claim 1, wherein In response to the determination, based on the first page of the plurality of pages, that the number of pages to which the first programming operation is to be performed is zero during a first program-erase cycle performed before obtaining the information about the memory block, the memory controller is further configured to send a second programming command to the memory device during a second program-erase cycle for a second programming operation on the first page, and The memory device is also configured to: Receive the second programming command from the storage controller; and The second programming operation is performed by executing one or more programming loops to apply programming and verification voltages to the first page.

15. The storage device according to claim 14, wherein The second page of the plurality of pages is the page to be programmed after the first page in the second program-erase cycle. The storage controller is also configured to: During the second program-erase cycle, a third programming command for the second programming operation on the second page is sent to the memory device; and In response to the determination, during the first program-erase cycle, that one or more pages are to be programmed with the first program operation based on the second page, the number of pages to be programmed with the first program operation during the second program-erase cycle is determined based on the obtained information about the memory block. The memory device is also configured to: Receive the third programming command from the storage controller; and Perform the second programming operation on the second page, and The first programming operation, corresponding to the number of pages determined based on the information about the memory block, is performed after the second programming operation for the second page.

16. The storage device according to claim 1, wherein In response to the first programming operation being performed on the selected page among the plurality of pages during a first program-erase cycle executed before obtaining the information about the memory block, the memory controller is further configured to send a second programming command to the memory device during a second program-erase cycle for a second programming operation on the selected page, and The memory device is also configured to: Receive the second programming command from the storage controller; and The second programming operation is performed by executing one or more programming loops to apply programming and verification voltages to the selected page.

17. The storage device according to claim 1, wherein, The storage controller is also configured to determine that the number of pages is less than or equal to a predetermined threshold.

18. The storage device according to claim 1, wherein, The number of pages is one of a plurality of candidates for skip counting, and the plurality of candidates for skip counting includes a skip count determined based on the number of string select lines of the memory cell array.

19. A storage device, comprising: A memory device, including a memory cell array and control logic circuitry, the memory cell array comprising a memory block having multiple pages to which memory cells are connected; and The storage controller sends programming commands to the storage device for programming operations on each of the plurality of pages. in The memory device is configured to: Obtain information about the memory block; Based on the information about the memory block, determine the number of pages on which to perform programming operations to skip the verification process; Receive the programming command from the storage controller; and The programming operation is performed by executing a programming loop to skip the verification process, targeting the pages corresponding to the number of pages and indicated by the programming commands.

20. A method of operating a storage system, the storage system comprising a memory device, a storage controller, and a host device, the memory device comprising a memory cell array and control logic circuitry, the memory cell array comprising a memory block having multiple pages, the storage controller exchanging data with the memory device, and the host device exchanging data with the storage controller, the method comprising: Information about the memory block is obtained from the storage system; The storage system determines, based on the information obtained about the memory block, the number of pages on which programming operations to be performed to skip the verification process should be executed; The storage controller sends programming commands for programming operations on each of the plurality of pages to the storage device; The programming command is received by the memory device; and The memory device performs the programming operation on pages corresponding to the number of pages and indicated by the programming command by executing a programming loop for skipping the verification process.

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