Mapping table construction method and device, flash memory decoding method and device and storage medium

Abstract

The invention provides a mapping table construction method, a flash memory decoding method, a flash memory decoding device and a computer storage medium. The mapping table construction method comprises the following steps: determining a plurality of logic pages of a target high-density flash memory unit; a high-reliability sequence and a low-reliability sequence of each logic page are determined, and the distance between the high-reliability sequence and the judgment threshold of the logic page is larger than the distance between the judgment threshold of the logic page of the low-reliability sequence; constructing a first mapping table for the low-reliability sequence, and constructing a second mapping table for the high-reliability sequence; wherein the absolute value in the first mapping table is smaller than the absolute value in the second mapping table; and combining the mapping tables of all the logic pages, and determining a target mapping table of the target high-density flash memory unit. Through the mapping table construction method, the error correction performance of the soft decoder is improved, and the reliability of the NAND system is enhanced.

Description

Technical Field

[0001] This application relates to the field of solid-state storage technology, and in particular to a mapping table construction method, a flash memory decoding method, a flash memory decoding device, and a computer storage medium. Background Technology

[0002] Solid-state storage, such as solid-state drives (SSDs) and USB cards, is currently in high demand. It stores data using non-volatile flash memory chips, preserving data even when power is lost. However, in SSDs, the optimal read voltage of the flash memory shifts with storage time and the number of erase / write cycles, leading to reduced data reliability.

[0003] As storage density increases, from SLC (Single-Level Cell) to MLC (Multi-Level Cell), TLC (Triple-Level Cell), and even QLC (Quad-Level Cell), the number of bits of data stored per flash memory cell increases, and data reliability gradually decreases. To maintain data reliability, LDPC (Low-Density Parity-Check Soft Decision Decoding) technology is typically used. Soft decoding requires performing multiple read operations (i.e., soft reading) on ​​both sides of the hard read voltage to obtain soft information, mapping it to an LLR (log-likelihood ratio) value, and then inputting it into the soft decoder for decoding.

[0004] Traditional LLR tables map a fixed LLR value to each LI pattern. While simple, this approach is not precise enough, leading to a decrease in the efficiency of the entire decoding process. Summary of the Invention

[0005] To address the aforementioned technical problems, this application proposes a mapping table construction method, a flash memory decoding method, a flash memory decoding device, and a computer storage medium.

[0006] To address the aforementioned technical problems, this application proposes a mapping table construction method, which includes: Identify several logical pages of the target high-density flash memory cell; Determine a high reliability sequence and a low reliability sequence for each logical page, wherein the distance between the high reliability sequence and the decision threshold of the logical page is greater than the distance between the low reliability sequence and the decision threshold of the logical page; A first mapping table is constructed for the low-reliability sequence, and a second mapping table is constructed for the high-reliability sequence; wherein the absolute value in the first mapping table is less than the absolute value in the second mapping table; Combine the mapping tables of all logical pages to determine the target mapping table for the target high-density flash memory cell.

[0007] The step of constructing a second mapping table for the high-reliability sequence includes: Determine the upper limit of the target decoder representation; The posterior probability value in the second mapping table is set according to the upper limit of the target decoder representation.

[0008] The number of bits in the sequence of the logical page is determined based on the type of the target high-density flash memory cell and the type of the logical page.

[0009] The mapping table construction method further includes: Determine the threshold voltage distribution information based on the type of the target high-density flash memory cell; Based on the threshold voltage distribution information, the level voltage number is determined; Determining the high-reliability sequence and low-reliability sequence for each logical page includes: Based on the type of the logic page and the level voltage number, the level indication information is divided into two categories; The voltage range located by the first type of level indication information is classified into the low reliability sequence; The voltage range located by the second type of level indication information is assigned to a high-reliability sequence; Wherein, the voltage range located by the first type of level indication information is adjacent to the target overlapping range, and the voltage range located by the second type of level indication information is far from the target overlapping range, and the target overlapping range is the voltage range where the decision threshold of the logic page is located.

[0010] To address the aforementioned technical problems, this application also proposes a flash memory decoding method, which includes: The target memory cell is read using a soft read level sequence to obtain the read sequence of the target memory cell; Extract the corresponding posterior probability value sequence from the pre-constructed mapping table according to the read sequence; The soft decoding process is performed using the posterior probability value sequence as initial posterior information until the decoding result of the target storage unit is determined. The mapping table is constructed using the mapping table construction method described above.

[0011] The step of extracting the corresponding posterior probability value sequence from the pre-constructed mapping table based on the read sequence includes: In response to the presence of a target sequence located in a high-reliability sequence within the read sequence, the target sequence is matched with the second mapping table to determine the posterior probability value of the target sequence.

[0012] After determining the posterior probability value of the target sequence, the flash decoding method further includes: Determine the upper limit of the decoder's representation; Determine whether the posterior probability value of the target sequence reaches the upper limit of representation; If not, update the posterior probability value of the target sequence to the representation upper bound.

[0013] Before extracting the corresponding posterior probability value sequence from the pre-constructed mapping table based on the read sequence, the flash decoding method further includes: The posterior probability values ​​in the pre-constructed second mapping table are updated according to the upper limit of the decoder's representation.

[0014] To address the aforementioned technical problems, this application also proposes a flash memory decoding apparatus, comprising a memory and a processor coupled to the memory; wherein the memory is used to store program data, and the processor is used to execute the program data to implement the mapping table construction method and / or the flash memory decoding method as described above.

[0015] To address the aforementioned technical problems, this application also proposes a computer storage medium for storing program data, which, when executed by a computer, is used to implement the aforementioned mapping table construction method and / or flash memory decoding method.

[0016] Compared with the prior art, the beneficial effects of this application are as follows: By designing enhanced LLR values ​​separately for high reliability intervals, this application can accurately identify the most reliable bits using LI information, assign these bits higher absolute LLR values, and increase their role in the decoding process; by leveraging the iterative characteristics of LDPC codes, reliable bits can efficiently correct unreliable bits, ultimately achieving the dual goals of accelerating decoding convergence speed and improving extreme error correction capability. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein: Figure 1 This is a schematic diagram of an embodiment of the threshold voltage distribution of a TLC provided in this application; Figure 2 This is a flowchart illustrating an embodiment of the mapping table construction method provided in this application; Figure 3This is a schematic diagram of the TLC Gray code mapping provided in this application; Figure 4 This is a flowchart illustrating an embodiment of the flash memory decoding method provided in this application; Figure 5 This is a schematic diagram of the structure of an embodiment of the flash memory decoding device provided in this application; Figure 6 This is a schematic diagram of the structure of an embodiment of the computer storage medium provided in this application. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0019] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0020] As flash memory density increases, the raw bit error rate (RBER) decreases. LDPC codes offer powerful soft decoding and error correction capabilities and are widely used in flash memory systems. To maintain data reliability, flash memory systems employ various measures for read recovery. Traditionally, when decoding failure occurs, a retry (hard read retry) process is first performed, adjusting the read voltage offset according to the retry table and rereading (hard read), followed by hard decoding. If retry still fails to correct errors, a soft reading process is used to obtain soft information, which is then mapped to an LLR value and input into the soft decoder (soft decoding).

[0021] To effectively manage and optimize data stored in X bit / cell (XLC) systems, manufacturers often subdivide NAND physical pages into multiple logical pages, with read, write, and erase operations independent for each logical page. Please refer to [link / reference] for details. Figure 1 Taking TLC as an example, a physical page is divided into a lower page (LP), a middle page (MP), and an upper page (UP). Three bits are written to the corresponding logical page using a Gray mapping. For example... Figure 1 The figure shows the threshold voltage distribution of TLC. The voltage range is divided into 8 states using 7 levels of voltage. Each state is represented by 3 bits and the states are separated by levels. Levels 1 and 5 are used to distinguish 0 and 1 on LP, levels 2, 4 and 6 are used to distinguish 0 and 1 on MP, and levels 3 and 7 are used to distinguish 0 and 1 on UP.

[0022] During the read recovery process, NAND generates cell pattern information based on multiple read results. This pattern information is composed of three parts: LI (level indicator) information, hard information, and soft information.

[0023] Through observation Figure 1 It can be seen that the closer to the target overlap region, the lower the reliability; the farther away, the higher the reliability. The target overlap region refers to the area in the flash memory cell threshold voltage distribution map where the distribution curves of two adjacent states intertwine and overlap.

[0024] During software decoding, the master controller maps the pattern information of each cell to LLR values ​​via a lookup table and inputs them into the software decoder. The pattern values ​​and the LLR lookup table determine the decoder input for each cell. The bit width of the page's LLR information is closely related to the number of levels. Figure 1 The bit widths of the LI information for LP, MP, and UP are 1, 2, and 1 (log2(number of page levels)) respectively. Based on the level number in the XLC, the LI information can be divided into two categories: (1) First type: The overlapping region of adjacent targets in the state located by LI, with Figure 1Taking MP as an example: When LI=10, that is, (UP, LP)=(1, 0), LI indicates that the overlapping interval is level 2, and two adjacent overlapping intervals level-2 located by the current LI data, state 110 and state 100. At this time, the pattern values ​​within state 110 and state 100 are relatively unreliable because they are adjacent to the overlapping intervals, so they are called low reliability intervals.

[0025] (1) Second type: The state located by LI is far from the target overlapping region, so as to Figure 1 Taking MP as an example: when LI=11, that is, (UP, LP)=(1,1), the states that LI information can locate are state111 and 101. These states are far from the target overlap interval, so the reliability of the corresponding MP data is very high. Therefore, this application refers to the pattern of this type of state interval as a high reliability interval.

[0026] Currently, when performing LLR mapping in NAND soft decoding, no special LLR mapping is performed separately for pattern data in the high reliability range.

[0027] In response, this application proposes an LLR mapping table design scheme for read data recovery in solid-state storage. By optimizing the LLR mapping values ​​of soft information, error correction performance is improved and latency and power consumption are reduced.

[0028] Please continue reading for details. Figure 2 , Figure 2 This is a flowchart illustrating an embodiment of the mapping table construction method provided in this application. Figure 2 In the mapping table construction method, the cell pattern values ​​are divided into two categories. A separate LLR mapping value is designed for the pattern values ​​in the high reliability range to improve the error correction performance of the soft decoder.

[0029] The flash memory decoding method of this application is applied to a flash memory decoding device, which can be a server, a terminal device, or a system in which the server and the terminal device cooperate with each other. Accordingly, the various parts of the flash memory decoding device, such as each unit, subunit, module, and submodule, can all be set in the server, all in the terminal device, or separately in the server and the terminal device.

[0030] Furthermore, the aforementioned server can be either hardware or software. When the server is hardware, it can be implemented as a distributed server cluster consisting of multiple servers, or as a single server. When the server is software, it can be implemented as multiple software programs or software modules, such as software or software modules used to provide distributed server functionality, or as a single software program or software module; no specific limitations are made here.

[0031] like Figure 2 As shown, the specific steps are as follows: Step S11: Determine several logical pages of the target high-density flash memory cell.

[0032] In the embodiments of this application, the same applies. Figure 1 For example, when the target high-density flash memory cell is TLC, a physical page is divided into a lower page (LP), a middle page (MP), and an upper page (UP).

[0033] In other embodiments, when the target high-density flash memory cell is QLC, a physical page is divided into least significant bit page, middle significant bit page, most significant bit page, and extra-high significant bit page. The mapping table construction logic is basically the same as that of the TLC mapping table in the example of this application, and will not be repeated here.

[0034] Step S12: Determine the high reliability sequence and low reliability sequence for each logical page, wherein the distance between the high reliability sequence and the decision threshold of the logical page is greater than the distance between the low reliability sequence and the decision threshold of the logical page.

[0035] In the embodiments of this application, please refer to Figure 1 Continue reading Figure 3 , Figure 3 This is a schematic diagram of the TLC Gray code mapping provided in this application.

[0036] by Figure 3 Taking the MP as an example, the MP level requires 2 bits of LI information to distinguish. The state and pattern in LI information 00, 01, and 10 are in the low reliability range, while the state and pattern in LI information 11 are in the high reliability range.

[0037] Step S13: Construct a first mapping table for the low-reliability sequence and a second mapping table for the high-reliability sequence; wherein the absolute value in the first mapping table is less than the absolute value in the second mapping table.

[0038] In this embodiment, if the soft information bit width is 1 bit and the decoder bit width is 6 bits (LLR_MAX = 1), then the MP pattern lookup table can be designed as follows: Figure 3 The mapping table shown.

[0039] In MP, LI is composed of bit information of (UP, LP), and hard and soft bits are generated by hard and soft read results of cell. The pattern is the decimal result of (LI + hard bit + soft bit).

[0040] For the first type of valid patterns, i.e. low reliability sequences, with LI=10, 00 and 01, the LLR mapping values ​​for the combination of hard bit and soft bit values ​​00-11 are set to 22, 11, -11 and -22 respectively.

[0041] For the second type of illegal pattern with LI=11, namely the high reliability sequence, the LLR value of the pattern with hard bit=1 is set to the minimum value of -31, and the LLR value of the pattern with hard bit=0 is uniformly set to the maximum value of 31.

[0042] In summary, for states located in the high reliability range, the threshold voltage distribution diagram shows that they are more than one state away from the page level voltage. Therefore, it is reasonable to believe that the soft information generated by these states is extremely reliable. When hard read bit=1, the LLR mapping value of the illegal pattern should be set to -LLR_MAX; when hard read bit=0, the LLR mapping value of the illegal pattern should be set to LLR_MAX.

[0043] Furthermore, the mapping table construction method of this application can set the LLR value of the high reliability range as the upper limit of the decoder representation, or it can be set to other values, but it is necessary to ensure that the LLR amplitude is large to reflect high reliability.

[0044] Step S14: Combine the mapping tables of all logical pages to determine the target mapping table of the target high-density flash memory cell.

[0045] In this embodiment, the flash memory decoding device locates the pattern value of the high reliability range based on the LI data, and sets its LLR mapping value to LLR_MAX and -LLR_MAX according to the hard read result, thereby optimizing the decoder input LLR value and improving the performance of the software decoder.

[0046] based on Figure 2In addition to the mapping table construction method shown, this application also provides a flash decoding method to combine... Figure 2 The resulting mapping table is constructed to optimize the flash decoding process.

[0047] Please continue reading for details. Figure 4 , Figure 4 This is a flowchart illustrating an embodiment of the flash memory decoding method provided in this application.

[0048] like Figure 4 As shown, the specific steps are as follows: Step S21: Use a soft read level sequence to read the target memory cell and obtain the read sequence of the target memory cell.

[0049] In this embodiment, the flash memory decoding device first performs a hard read of the execution voltage, and then executes a retry process if a decoding failure occurs. When all retry processes fail due to hard decoding, a soft decoding scheme is initiated.

[0050] Specifically, the flash memory decoder uses a denser, more precise sequence of soft read levels to probe cells. Multiple reads generate LI information, forming a pattern for each cell. The flash memory decoder automatically categorizes these patterns, identifying which cells are located in the target overlap region (low reliability region) and which are far from the target overlap region (high reliability region).

[0051] Step S22: Extract the corresponding posterior probability value sequence from the pre-constructed mapping table according to the read sequence.

[0052] In this embodiment of the application, the flash memory decoding device inputs the pattern read in step S21 into the LLR mapping table. The LLR mapping table is... Figure 2 The mapping table constructed by the method shown includes a first mapping table corresponding to the low reliability range and a second mapping table corresponding to the high reliability range.

[0053] according to Figure 2 As shown in the design concept, the low reliability pattern mapping in step S22 obtains an LLR close to 0, while the high reliability pattern mapping obtains an LLR with a large absolute value.

[0054] Step S23: Use the posterior probability value sequence as initial posterior information to perform a soft decoding process until the decoding result of the target storage unit is determined.

[0055] In this embodiment, the flash memory decoding device sends the LLR sequence obtained in step S22 to the LDPC soft decoder. The soft decoder utilizes the reliability information of the LLRs and, during iterative calculations, prioritizes trusting and propagating the opinions of high-reliability, strong LLR bits to correct low-reliability, weak LLR bits. Furthermore, strong LLR bits can quickly guide the decoding process towards convergence in the correct direction, avoiding oscillations between incorrect solutions, thereby improving decoding speed and success rate.

[0056] Furthermore, due to Figure 2 The constructed mapping table is pre-built and, to improve its applicability, can be applied to decoders with different representation upper limits. The flash memory decoding apparatus of this application can also update the absolute value of the posterior probability in the second mapping table corresponding to the high reliability interval, updating it to the representation upper limit of different decoders. The above process can occur at any stage of decoding, and its details are not elaborated here.

[0057] Those skilled in the art will understand that, in the above-described method of the specific implementation, the order in which each step is written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0058] To implement the above mapping table construction method and / or flash decoding method, this application also proposes a flash decoding apparatus, for details please refer to [link to details]. Figure 5 , Figure 5 This is a schematic diagram of an embodiment of the flash memory decoding device provided in this application.

[0059] The flash memory decoding device 500 of this embodiment includes a processor 51, a memory 52, an input / output device 53, and a bus 54.

[0060] The processor 51, memory 52, and input / output device 53 are respectively connected to the bus 54. The memory 52 stores program data, and the processor 51 is used to execute the program data to implement the mapping table construction method and / or flash memory decoding method described in the above embodiments.

[0061] In this embodiment, processor 51 can also be referred to as a CPU (Central Processing Unit). Processor 51 may be an integrated circuit chip with signal processing capabilities. Processor 51 can also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor can be a microprocessor, or processor 51 can be any conventional processor.

[0062] This application also provides a computer storage medium; please refer to the following: Figure 6 , Figure 6 This is a schematic diagram of a computer storage medium according to an embodiment of the present application. The computer storage medium 600 stores a computer program 61. When the computer program 61 is executed by the processor, it is used to implement the mapping table construction method and / or flash memory decoding method of the above embodiments.

[0063] When the embodiments of this application are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0064] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method for constructing a mapping table, characterized in that, The mapping table construction method includes: Identify several logical pages of the target high-density flash memory cell; Determine the high reliability sequence and low reliability sequence for each logical page, wherein the distance between the high reliability sequence and the decision threshold of the logical page is greater than the distance between the low reliability sequence and the decision threshold of the logical page; A first mapping table is constructed for the low-reliability sequence, and a second mapping table is constructed for the high-reliability sequence; wherein the absolute value in the first mapping table is less than the absolute value in the second mapping table; Combine the mapping tables of all logical pages to determine the target mapping table for the target high-density flash memory cell.

2. The mapping table construction method according to claim 1, characterized in that, The step of constructing a second mapping table for the high-reliability sequence includes: Determine the upper limit of the target decoder representation; The posterior probability value in the second mapping table is set according to the upper limit of the target decoder representation.

3. The mapping table construction method according to claim 1, characterized in that, The number of bits in the sequence of the logical page is determined based on the type of the target high-density flash memory cell and the type of the logical page.

4. The mapping table construction method according to claim 1 or 3, characterized in that, The mapping table construction method further includes: Determine the threshold voltage distribution information based on the type of the target high-density flash memory cell; Based on the threshold voltage distribution information, the level voltage number is determined; Determining the high-reliability sequence and low-reliability sequence for each logical page includes: Based on the type of the logic page and the level voltage number, the level indication information is divided into two categories; The voltage range located by the first type of level indication information is classified into the low reliability sequence; The voltage range located by the second type of level indication information is assigned to a high-reliability sequence; Wherein, the voltage range located by the first type of level indication information is adjacent to the target overlapping range, and the voltage range located by the second type of level indication information is far from the target overlapping range, and the target overlapping range is the voltage range where the decision threshold of the logic page is located.

5. A flash memory decoding method, characterized in that, The flash memory decoding method includes: The target memory cell is read using a soft read level sequence to obtain the read sequence of the target memory cell; Extract the corresponding posterior probability value sequence from the pre-constructed mapping table according to the read sequence; The soft decoding process is performed using the posterior probability value sequence as initial posterior information until the decoding result of the target storage unit is determined. The mapping table is constructed using the mapping table construction method described in any one of claims 1 to 4.

6. The flash memory decoding method according to claim 5, characterized in that, The step of extracting the corresponding posterior probability value sequence from the pre-constructed mapping table based on the read sequence includes: In response to the presence of a target sequence located in a high-reliability sequence within the read sequence, the target sequence is matched with the second mapping table to determine the posterior probability value of the target sequence.

7. The flash memory decoding method according to claim 6, characterized in that, After determining the posterior probability value of the target sequence, the flash decoding method further includes: Determine the upper limit of the decoder's representation; Determine whether the posterior probability value of the target sequence reaches the upper limit of representation; If not, update the posterior probability value of the target sequence to the representation upper bound.

8. The flash memory decoding method according to claim 5, characterized in that, Before extracting the corresponding posterior probability value sequence from the pre-constructed mapping table based on the read sequence, the flash decoding method further includes: The posterior probability values ​​in the pre-constructed second mapping table are updated according to the upper limit of the decoder's representation.

9. A flash memory decoding device, characterized in that, The flash memory decoding device includes a memory and a processor coupled to the memory; The memory is used to store program data, and the processor is used to execute the program data to implement the mapping table construction method as described in any one of claims 1 to 4, and / or the flash memory decoding method as described in any one of claims 5 to 8.

10. A computer storage medium, characterized in that, The computer storage medium is used to store program data, which, when executed by the computer, is used to implement the mapping table construction method as described in any one of claims 1 to 4, and / or the flash memory decoding method as described in any one of claims 5 to 8.

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