SiC parallel power board optimal configuration method and system based on joint simulation
By optimizing the PCB layout of SiC parallel power boards through co-simulation, the problems of parasitic parameter oscillation and uneven current were solved, achieving efficient and accurate SiC parallel power board configuration and improving current sharing and design efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CRRC ZHUZHOU ELECTRIC LOCOMOTIVE RESEARCH INSTITUTE CO LTD
- Filing Date
- 2024-11-18
- Publication Date
- 2026-05-19
AI Technical Summary
Existing technologies struggle to quickly and accurately determine the optimal layout of SiC parallel power boards, leading to parasitic parameter oscillations and uneven current distribution, and are complex and costly to implement.
By using a co-simulation method, the initial configuration of the PCB layout is first performed, followed by stray parameter simulation and circuit simulation. The PCB layout is then adjusted until the preset conditions are met, thus optimizing the configuration of the SiC parallel power board.
It enables efficient and accurate determination of the optimal configuration of SiC parallel power boards, reduces parasitic parameters, improves current sharing, and reduces complexity and cost.
Smart Images
Figure CN122065752A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of SiC (silicon carbide) power device board technology, and in particular to a method and system for optimizing the configuration of SiC parallel power boards based on co-simulation. Background Technology
[0002] Compared to silicon (Si) devices, SiC (silicon carbide) power devices have a higher dielectric breakdown field strength, allowing for the manufacture of power devices with higher withstand voltages while maintaining lower on-resistance. SiC parallel power boards connect multiple SiC power devices in parallel to improve current capacity and power module performance. However, due to SiC's relatively fast switching speed and high dv / dt (voltage change rate), the gate is more prone to coupling with parasitic parameters in the drive circuit of the power board, leading to oscillations. Differences in parasitic parameters between branches can also cause uneven current distribution. When oscillations are severe, they can significantly affect gate reliability and even damage the device. Therefore, controlling parasitic parameters on the power board is crucial.
[0003] To suppress turn-on oscillations in SiC devices, existing technologies typically employ methods such as slowing down the device's turn-on speed or reducing parasitic parameters in the gate circuit. However, slowing down the turn-on speed increases the device's turn-on losses, leading to higher junction temperatures. While reducing parasitic parameters in the gate circuit can effectively suppress oscillations without increasing switching losses, this approach requires prior PCB design and power board production before experimentally determining the actual parasitic parameters of the power board. Further optimization of the power board to reduce these parameters is then necessary. This method is extremely complex, time-consuming, costly, and inefficient. It is difficult to quickly and accurately determine the optimal power board layout with low parasitic parameters, and it is challenging to avoid oscillations in the SiC gate circuit caused by parasitic parameters. Furthermore, differences in parasitic parameters between branches can still lead to uneven current distribution. Summary of the Invention
[0004] The technical problem to be solved by this invention is: In view of the technical problems existing in the prior art, this invention provides a SiC parallel power board optimization configuration method and system based on co-simulation that is simple to implement, low in cost, efficient in execution and high in flow rate, and can efficiently determine the optimal configuration of SiC parallel power boards, effectively reduce and balance parasitic parameters, and improve flow rate.
[0005] To solve the above-mentioned technical problems, the technical solution proposed by this invention is as follows:
[0006] A method for optimizing the configuration of SiC parallel power boards based on co-simulation, comprising the following steps:
[0007] Step S01. PCB Initialization Configuration: Obtain the initial PCB layout configuration formed by arranging the SiC parallel power boards sequentially according to design requirements;
[0008] Step S02. Stray parameter simulation: Generate a PCB file for the current PCB layout configuration, perform stray parameter simulation on the generated PCB file to obtain the stray parameters under the current PCB file, and compare the stray parameters obtained by simulation with the stray parameter reference values to determine whether they meet the preset requirements. If they do not meet the preset requirements, adjust the current PCB layout configuration and re-perform stray parameter simulation until the stray parameters meet the preset requirements.
[0009] Step S03. Circuit Simulation: Based on the PCB layout configuration and corresponding stray parameters obtained from step S02, establish a SiC device circuit model and simulate the established SiC device circuit module. During the simulation, apply excitation to the SiC device circuit module and determine whether there is oscillation in the gate waveform of the gate switch. If so, adjust the PCB layout and return to step S02 until the gate waveform meets the preset requirements to obtain the final SiC parallel power board layout configuration.
[0010] Furthermore, step S01 also includes configuring the drive circuit as a symmetrical structure and setting the high-voltage side and the low-voltage side on both sides of the PCB board respectively.
[0011] Further, step S02 includes:
[0012] Step S201. Perform stray parameter simulation on the current PCB file to obtain the stray parameters under the current PCB file;
[0013] Step S202. Compare the spurious parameters obtained from the current simulation with the reference values of the spurious parameters, and determine whether the spurious parameters obtained from the previous simulation meet the preset requirements. If they do not meet the requirements, proceed to step S203; otherwise, proceed to step S204.
[0014] Step S203. Adjust the current PCB layout configuration, regenerate the PCB file from the adjusted PCB layout configuration, and return to step S201;
[0015] Step S204. Output the currently obtained PCB layout configuration and the corresponding stray parameters.
[0016] Further, in step S201, Ansys 3DL software is used to simulate stray parameters of the PCB file.
[0017] Further, in step S02, the formula for calculating the stray parameter reference value is:
[0018]
[0019] Where L0 is the reference value of the stray parameter, L net Let be the actual stray inductance of the current flowing through the loop, L be the self-inductance of the two conductors, M be the mutual inductance of the two conductors, u0 be the permeability of the material, l be the length of the conductor, and d be the distance between the two conductors.
[0020] In steps S01 and S02, the maximum allowable range of the noise parameter is:
[0021]
[0022] Where R is the external resistance including the gate current. ext and the internal resistance R of the device in The resistance value, L, includes the stray inductance L on the gate circuit. ext And the stray inductance L inside the SiC device in The parasitic inductance parameter value, C is the parasitic capacitance C on the gate circuit. s and the gate capacitance C within the SiC device gs With reverse transfer capacitor C gd .
[0023] Further, step S03 includes:
[0024] Step S301. Establish the SiC device circuit model based on the PCB layout configuration and corresponding stray parameters obtained from the simulation in step S02;
[0025] Step S302. Provide excitation to the SiC device circuit model;
[0026] Step S303. Determine whether the excitation applied to the SiC device circuit module meets the preset requirements. If not, proceed to step S304; otherwise, proceed to step S305.
[0027] Step S304. Adjust the coupling area of the gate circuit current signal, the thickness of the insulating layer between copper layers, or the distance from the gate signal to the SiC device, and return to step S02;
[0028] Step S305. Output the current SiC parallel power board layout configuration as the final SiC parallel power board layout configuration.
[0029] Further, in step S304, adjusting the coupling area of the gate circuit current signal, the thickness of the insulating layer between copper layers, or the distance from the gate signal to the SiC device includes any one or more of the following: increasing the coupling area of the gate circuit current signal, decreasing the thickness of the insulating layer between copper layers, and shortening the distance from the gate signal to the SiC device.
[0030] Furthermore, after step S03, a double-pulse test is performed on the obtained SiC parallel power board layout configuration. The test results are used to determine whether the preset conditions are met. If not, the PCB layout is adjusted according to the test results until the preset conditions are met.
[0031] A SiC parallel power board optimization configuration system based on co-simulation includes a processor and a memory, wherein the memory is used to store a computer program and the processor is used to execute the computer program to perform the method described above.
[0032] A computer-readable storage medium storing a computer program that, when executed by a processor, implements the method described above.
[0033] Compared with the prior art, the advantages of the present invention are as follows: The present invention first forms an initial PCB layout configuration by performing a preliminary PCB layout according to the design requirements, then simulates the stray parameters of the PCB file, and judges whether the preset requirements are met based on the stray parameters obtained from the simulation. If the requirements are not met, the PCB layout is continuously adjusted until the stray parameters meet the conditions. After obtaining a PCB layout configuration that initially meets the stray parameters, the state of the gate waveform is judged by combining circuit simulation. By readjusting the PCB layout until the optimal PCB layout configuration that meets the gate waveform conditions is obtained, the optimal power board layout configuration can be determined efficiently and accurately by combining stray parameter simulation and circuit simulation, which greatly reduces the implementation complexity, cost and time, improves the design implementation efficiency, and can effectively reduce and balance stray inductance parameters and parasitic parameters, thereby significantly improving current sharing. Attached Figure Description
[0034] Figure 1 This is a schematic diagram illustrating the principle of the magnetic flux direction of signals flowing in opposite directions in a gate circuit layout.
[0035] Figure 2 This is a schematic diagram illustrating the implementation process of the SiC parallel power board optimization configuration method based on co-simulation in this embodiment.
[0036] Figure 3 This is a schematic diagram illustrating the implementation process of stray parameter simulation in a specific application embodiment of the present invention.
[0037] Figure 4 This is a schematic diagram illustrating the implementation process of circuit simulation in a specific application embodiment of the present invention.
[0038] Figure 5 This is a detailed flowchart illustrating the optimized configuration of SiC parallel power boards in a specific application embodiment of the present invention.
[0039] Figure 6This is a schematic diagram of the simulation results of the flow equalization effect obtained in a specific application embodiment of the present invention.
[0040] Figure 7 This is a schematic diagram of the gate signal simulation results obtained in a specific application embodiment of the present invention. Detailed Implementation
[0041] The present invention will be further described below with reference to the accompanying drawings and specific preferred embodiments, but this does not limit the scope of protection of the present invention.
[0042] To facilitate understanding, the relevant technical background of the present invention will first be introduced by way of example.
[0043] If the SiC parallel power device is operated in an overdamped state, the gate can be prevented from oscillating, that is:
[0044]
[0045] Transforming the above equation yields:
[0046]
[0047] In equations (1) and (2), R includes the external resistance R of the gate current. ext and the internal resistance R of the device in L includes the stray inductance L on the gate circuit. ext and the internal inductance L of the device in C includes the parasitic capacitance C on the gate circuit. s and the gate capacitance C within the device gs With reverse transfer capacitor C gd .
[0048] Based on the relevant internal electrical parameters, parasitic parameters, external resistance, and gate capacitance of the device, L can be calculated using the above formula. ext The maximum allowable range provides a reference for the design of the gate circuit.
[0049] In the gate circuit layout, the gate signal flows in opposite directions at the gate and source. For signals flowing in opposite directions, the direction of their magnetic flux is as follows: Figure 1 As shown. It can be seen that the magnetic flux between conductors is in the same direction, while the magnetic flux outside the conductors is in the opposite direction. According to the general formula for calculating parasitic inductance:
[0050]
[0051]
[0052] In equation (3), L netLet L be the actual stray inductance of the current flowing through the loop, i.e., the equivalent parasitic low inductance. Let L be the self-inductance of the two conductors and M be the mutual inductance of the two conductors. From equation (3), it can be seen that when the self-inductance L of the two conductors is smaller and the mutual inductance M of the two conductors is larger, the actual stray inductance L... net The smaller the value, the greater the mutual inductance M. In equation (4), u0 is the permeability of the material, l is the length of the conductor, and d is the distance between the two conductors. It is easy to see from (4) that when the conductor length l is larger, the distance d between the two conductors is smaller, and the mutual inductance M is larger.
[0053] As can be seen from the above, the equivalent parasitic inductance L can be reduced by increasing the coupling area between signals (i.e., increasing the mutual inductance M by increasing l) and reducing the distance between signals (i.e., increasing the mutual inductance M by decreasing d). net However, the optimal signal coupling area and signal distance cannot be directly calculated by formula. Therefore, it is difficult to accurately minimize spurious parameters according to the traditional power board design method. Furthermore, there will be uneven current between different branches due to differences in spurious parameters.
[0054] This invention first establishes an initial PCB layout configuration based on design requirements. Then, it simulates the stray parameters of the PCB file and determines whether the simulated stray parameters meet the preset requirements. If not, the PCB layout is continuously adjusted until the stray parameters meet the conditions. After obtaining a PCB layout configuration that initially meets the stray parameters, circuit simulation is combined to establish a SiC device circuit model and determine whether there is oscillation in the gate waveform of the gate switch after applying excitation. If so, the PCB layout is readjusted until the optimal PCB layout configuration that meets the gate waveform conditions is obtained. This invention can efficiently and accurately determine the optimal power board layout configuration by combining stray parameter simulation and circuit simulation, greatly reducing implementation complexity, cost, and time, improving design implementation efficiency, and effectively reducing and balancing stray inductance parameters and parasitic parameters, thereby significantly improving current sharing.
[0055] The present invention will be further described below with reference to specific embodiments.
[0056] like Figure 2 As shown, the steps of the SiC parallel power board optimization configuration method based on co-simulation in this embodiment include:
[0057] Step S01. PCB Initialization Configuration: Obtain the initial PCB layout configuration formed by arranging the SiC parallel power boards sequentially according to design requirements.
[0058] Design requirements may include parameters of each module within the power board, performance parameters of the overall power board, or other available requirements information.
[0059] When designing a PCB, the necessary components are first added during the PCB schematic design process. These components are placed sequentially according to the SiC power board design requirements and the maximum allowable range of stray inductance parameters. The schematic netlist is then imported into Allegro PCB. Next, the components of the SiC power board are placed sequentially, and routing, vias, and copper pours are performed until the PCB layout is complete. When configuring the drive circuit, a symmetrical structure is used to ensure that stray parameters are similar in different locations and branches, improving the balance of stray parameters. Simultaneously, the high-voltage side and low-voltage side are located on opposite sides of the PCB to avoid interference.
[0060] In the initial PCB layout of specific application examples, the parallel SiC devices are horizontally mounted on the power board, and the parallel SiC devices are grouped together for easy routing. At the same time, the copper traces of the drive circuit maintain a symmetrical structure. In addition, based on the maximum allowable range of stray inductance parameters, the coupling area between different layers is maximized, and the interlayer spacing between different layers is reduced while meeting insulation requirements, thereby minimizing stray inductance. The high-voltage and low-voltage sides are placed on opposite sides of the PCB to avoid interference. The vias of the low-voltage section are treated as blind vias to fully isolate strong and weak electrical signals.
[0061] Step S02. Stray parameter simulation: Generate the corresponding PCB file based on the current PCB layout, perform stray parameter simulation on the current PCB file to obtain the stray parameters under the current PCB file, and compare the stray parameters obtained by simulation with the stray parameter reference values to determine whether they meet the preset requirements. If they do not meet the preset requirements, adjust the current PCB layout configuration and re-perform stray parameter simulation until the stray parameters meet the preset requirements.
[0062] The initial PCB layout configuration determined based on design requirements is often difficult to directly meet the requirements. In this embodiment, a PCB file suitable for stray parameter simulation is generated from the PCB layout configuration to perform stray parameter simulation. That is, the stray parameters of the corresponding PCB layout configuration are calculated by simulation, and then it is determined whether the stray parameters obtained by simulation meet the preset requirements. For example, if the deviation between the stray parameters and the stray parameter reference value is less than the preset value, it indicates that the stray parameters are close to the stray parameter reference value. Thus, the PCB layout configuration under the optimal stray parameter conditions can be quickly and accurately determined by using stray parameter simulation.
[0063] In this embodiment, the theoretical maximum allowable range of the stray inductance parameter can be calculated first according to formulas (1) and (2), that is... The irritation parameter L is calculated according to equations (3) and (4). net The noise parameter L net L0 is used as a reference value for stray parameters, i.e. During the stray parameter simulation, the stray inductance parameter is adjusted within the maximum allowable range of the stray inductance parameter determined above until the difference between it and the stray parameter reference value L0 is less than the preset value.
[0064] Understandably, the maximum allowable range of the noise parameter can also be determined in other ways according to actual needs. For example, a larger range can be determined based on experience, or a certain margin can be added to the theoretical maximum allowable range of the noise parameter to further ensure reliability.
[0065] In this embodiment, the detailed steps for implementing stray parameter simulation are as follows:
[0066] Step S201. Perform stray parameter simulation on the current PCB file to obtain the stray parameters under the current PCB file.
[0067] Step S202. Compare the spurious parameters obtained from the current simulation with the reference values of the spurious parameters, and determine whether the spurious parameters obtained from the previous simulation meet the preset requirements. If they do not meet the requirements, proceed to step S203; otherwise, proceed to step S204.
[0068] Step S203. Adjust the current PCB layout configuration, regenerate the PCB file from the adjusted PCB layout configuration, and return to step S201;
[0069] Step S204. Output the currently obtained PCB layout configuration and the corresponding stray parameters.
[0070] As an alternative implementation, Ansys 3DL software can be used to simulate stray parameters of the PCB file. Ansys 3DL is a software tool for three-dimensional electromagnetic field simulation, capable of performing quasi-static electromagnetic field analysis based on the three-dimensional boundary element method, and can effectively simulate stray parameters of power devices.
[0071] As an optional implementation, when adjusting the PCB layout configuration in step S203, the spacing between each parallel SiC and the position of the drive circuit can be adjusted.
[0072] In specific application embodiments, such as Figure 3As shown, after generating the PCB file, it is imported into Ansys 3DL and converted into an ODB model that matches SIwave. Then, the model is preprocessed in SIwave, including settings for materials, board thickness, via types, etc., and then exported to Ansys Q3D for stray parameter simulation. After setting the excitation and solving the parallel network to be simulated, the simulated stray parameters are obtained. Then, the simulation results are compared with the reference value L0. If the requirements are not met, the PCB layout is readjusted, such as adjusting the spacing between each parallel SiC and the position of the drive circuit, until a PCB with stray parameters that meet the requirements is designed.
[0073] Step S03. Circuit Simulation: Based on the PCB layout configuration and corresponding stray parameters obtained from step S02, establish the SiC device circuit model and simulate the established SiC device circuit module. During the simulation, apply excitation to the SiC device circuit module and determine whether there is oscillation in the gate waveform of the gate switch. If so, adjust the PCB layout and re-establish the SiC device circuit model and simulation until the gate waveform meets the preset requirements to obtain the final SiC parallel power board layout configuration.
[0074] Even after determining a PCB layout configuration that meets the required parasitic parameters through stray parameter simulation, this layout may still cause gate waveform oscillations in the gate switch. This embodiment first uses stray parameter simulation to initially determine a PCB layout configuration that meets the reference values for stray parameters, and then combines this with circuit simulation. By establishing a SiC device circuit model, circuit simulation is performed to determine the state of the gate waveform. When oscillations are observed in the gate waveform, the PCB layout is readjusted to ultimately obtain the optimal PCB layout configuration with the best stray inductance parameters. This effectively avoids oscillation problems caused by parasitic parameters, while also improving current sharing and resolving current imbalances caused by differences in parasitic parameters between different branches.
[0075] In this embodiment, the steps for performing circuit simulation include:
[0076] Step S301. Establish the SiC device circuit model based on the PCB layout configuration and corresponding stray parameters obtained from the simulation in step S02;
[0077] Step S302. Provide excitation to the SiC device circuit model;
[0078] Step S303. Determine whether the excitation applied to the SiC device circuit module meets the preset requirements and whether the gate waveform of the gate switch meets the preset requirements. If not, proceed to step S304; otherwise, proceed to step S305.
[0079] Step S304. Adjust the coupling area of the gate loop current signal, the thickness of the insulating layer between copper layers, or the distance from the gate signal to the SiC device, and return to step S02 to re-perform the simulation;
[0080] Step S305. Output the current SiC parallel power board layout configuration as the final SiC parallel power board layout configuration.
[0081] As an alternative implementation, the above circuit simulation can be performed using PSpice circuit simulation software, so as to efficiently obtain the PCB layout configuration under the optimal state of non-influence parameters by combining Ansys Q3D and PSpice simulation.
[0082] In this embodiment, adjusting the coupling area of the gate circuit current signal, the thickness of the insulating layer between copper layers, or the distance from the gate signal to the SiC device can be achieved by increasing the coupling area of the gate circuit current signal, decreasing the thickness of the insulating layer between copper layers, or shortening the distance from the gate signal to the SiC device.
[0083] like Figure 4 As shown, a SiC device model and circuit model can be established in PSpice software based on the design parameters of the SiC device and the stray parameters obtained from simulation. Excitation can be set, and the presence of oscillations during the gate switching process can be observed. If oscillations occur, the stray inductance L of the gate circuit can be reduced by increasing the coupling area of the gate circuit current signal, reducing the thickness of the insulating layer between copper layers, or shortening the distance from the gate signal to the SiC device (i.e., increasing the mutual inductance M). net The optimal PCB layout configuration is obtained until the required gate waveform appears.
[0084] Optionally, after step S03, a double-pulse test is performed on the obtained SiC parallel power board layout configuration. The test results are used to determine if the preset conditions are met. If not, the PCB layout is adjusted based on the test results until the preset conditions are met. The PCB is then manufactured, and a double-pulse test platform is built. An oscilloscope and probe are used to perform double-pulse testing. When the measured results do not meet expectations, the PCB and simulation model should be optimized based on the measured results until the simulation results are close to the measured results.
[0085] In specific application embodiments, when using the above method to optimize the configuration of SiC parallel power boards, such as... Figure 5As shown, first, the maximum allowable range of spurious parameters is determined. Then, the schematic and PCB are drawn according to the initial PCB layout to form an initial PCB file, which is imported into Q3D software for spurious parameter simulation. The simulation results are used to determine whether the design requirements are met. If not, the PCB layout is adjusted, and the PCB file is regenerated for simulation. If the conditions are met, further circuit simulation is performed in Simplier modeling and simulation software. The gate waveform is observed for oscillation. If oscillation is present, the PCB layout is readjusted until the expected gate waveform is obtained, resulting in the final PCB layout configuration. After PCB production, tests such as double pulse are conducted to determine whether fine-tuning of the layout is necessary.
[0086] The current sharing curves of different parallel SiC devices obtained by the above method are as follows: Figure 6 As shown, and the obtained gate signal curve is as follows. Figure 7 As shown, from Figure 6 It can be seen that the current sharing coefficient of each parallel SiC device is as high as 97%. Figure 7 As can be seen, the gate signal did not oscillate during the turn-on process. This verifies that the present invention can significantly accelerate the iteration speed of SiC power PCB design and significantly improve the current sharing coefficient of parallel power boards.
[0087] This embodiment further provides a SiC parallel power board optimization configuration system based on co-simulation, including a processor and a memory. The memory is used to store computer programs, and the processor is used to execute the computer programs to perform the methods described above.
[0088] It is understood that the method described in this embodiment can be executed by a single device, such as a computer or server, or it can be applied to a distributed scenario where multiple devices cooperate to complete the task. In a distributed scenario, one of the multiple devices may execute only one or more steps of the method described in this embodiment, and the multiple devices interact to complete the method. The processor can be implemented using a general-purpose CPU, microprocessor, application-specific integrated circuit, or one or more integrated circuits, and is used to execute relevant programs to implement the method described in this embodiment. The memory can be implemented using read-only memory (ROM), random access memory (RAM), static storage devices, and dynamic storage devices. The memory can store the operating system and other applications. When the method described in this embodiment is implemented through software or firmware, the relevant program code is stored in the memory and called and executed by the processor.
[0089] This embodiment further provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method described above.
[0090] Those skilled in the art will understand that the above embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create an implementation for the process. Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0091] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Therefore, any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention should fall within the protection scope of the present invention.
Claims
1. A method for optimizing the configuration of SiC parallel power boards based on co-simulation, characterized in that the steps include... include: Step S01. PCB Initialization Configuration: Obtain the initial PCB layout configuration formed by arranging the SiC parallel power boards sequentially according to design requirements; Step S02. Stray parameter simulation: Generate a PCB file for the current PCB layout configuration, perform stray parameter simulation on the generated PCB file to obtain the stray parameters under the current PCB file, and compare the stray parameters obtained by simulation with the stray parameter reference values to determine whether they meet the preset requirements. If they do not meet the preset requirements, adjust the current PCB layout configuration and re-perform stray parameter simulation until the stray parameters meet the preset requirements. Step S03. Circuit Simulation: Based on the PCB layout configuration and corresponding stray parameters obtained from step S02, establish a SiC device circuit model and simulate the established SiC device circuit module. During the simulation, apply excitation to the SiC device circuit module and determine whether there is oscillation in the gate waveform of the gate switch. If so, adjust the PCB layout and return to step S02 until the gate waveform meets the preset requirements to obtain the final SiC parallel power board layout configuration.
2. The SiC parallel power board optimization configuration method based on co-simulation according to claim 1, characterized in that, Step S01 further includes configuring the drive circuit as a symmetrical structure and setting the high-voltage side and the low-voltage side on both sides of the PCB board respectively.
3. The SiC parallel power board optimization configuration method based on co-simulation according to claim 1, characterized in that, Step S02 includes: Step S201. Perform stray parameter simulation on the current PCB file to obtain the stray parameters under the current PCB file; Step S202. Compare the spurious parameters obtained from the current simulation with the reference values of the spurious parameters, and determine whether the spurious parameters obtained from the previous simulation meet the preset requirements. If they do not meet the requirements, proceed to step S203; otherwise, proceed to step S204. Step S203. Adjust the current PCB layout configuration, regenerate the PCB file from the adjusted PCB layout configuration, and return to step S201; Step S204. Output the currently obtained PCB layout configuration and the corresponding stray parameters.
4. The SiC parallel power board optimization configuration method based on co-simulation according to claim 3, characterized in that, Step S201 uses Ansys 3DL software to perform stray parameter simulation on the PCB file.
5. The SiC parallel power board optimization configuration method based on co-simulation according to claim 1, characterized in that, In step S02, the formula for calculating the stray parameter reference value is: Where L0 is the reference value of the stray parameter, L net Let be the actual stray inductance of the current flowing through the loop, L be the self-inductance of the two conductors, M be the mutual inductance of the two conductors, u0 be the permeability of the material, l be the length of the conductor, and d be the distance between the two conductors. In steps S01 and S02, the maximum allowable range of the noise parameter is: Where R is the external resistance including the gate current. ext and the internal resistance R of the device in The resistance value, L, includes the stray inductance L on the gate circuit. ext And the stray inductance L inside the SiC device in The parasitic inductance parameter value, C is the parasitic capacitance C on the gate circuit. s and the gate capacitance C within the SiC device gs With reverse transfer capacitor C gd .
6. The SiC parallel power board optimization configuration method based on co-simulation according to any one of claims 1 to 5, characterized in that, Step S03 includes: Step S301. Establish the SiC device circuit model based on the PCB layout configuration and corresponding stray parameters obtained from the simulation in step S02; Step S302. Provide excitation to the SiC device circuit model; Step S303. Determine whether the excitation applied to the SiC device circuit module meets the preset requirements. If not, proceed to step S304; otherwise, proceed to step S305. Step S304. Adjust the coupling area of the gate circuit current signal, the thickness of the insulating layer between copper layers, or the distance from the gate signal to the SiC device, and return to step S02; Step S305. Output the current SiC parallel power board layout configuration as the final SiC parallel power board layout configuration.
7. The SiC parallel power board optimization configuration method based on co-simulation according to claim 6, characterized in that, In step S304, adjusting the coupling area of the gate circuit current signal, the thickness of the insulating layer between copper layers, or the distance from the gate signal to the SiC device includes any one or more of the following: increasing the coupling area of the gate circuit current signal, decreasing the thickness of the insulating layer between copper layers, and shortening the distance from the gate signal to the SiC device.
8. The SiC parallel power board optimization configuration method based on co-simulation according to claim 6, characterized in that, Step S03 includes performing a double-pulse test on the obtained SiC parallel power board layout configuration, determining whether the preset conditions are met based on the test results, and adjusting the PCB layout according to the test results until the preset conditions are met.
9. A SiC parallel power board optimization configuration system based on co-simulation, comprising a processor and a memory, wherein the memory is used to store computer programs, characterized in that, The processor is used to execute the computer program to perform the method as described in any one of claims 1 to 8.
10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1 to 8.