Design method and system for PCB integrated with BDU

Abstract

The invention relates to the technical field of printed circuit board design, and provides a BDU-integrated PCB design method and system, and the method comprises the steps: carrying out the region division of a PCB according to the electrical characteristics and signal types, and presetting the physical and electrical isolation strategies of all regions; based on the structural constraint of the PCB and the position of the connector terminal, the connector pin definition and the layout of the corresponding function module are adjusted; through collaborative design of a key channel and EMI, noise coupling suppression and high-low voltage junction isolation are carried out; functionally associated components are overlapped on the front and back surfaces of a PCB, decoupling and filtering elements are configured nearby, and three-dimensional integration is carried out. Through optimization of PCB layout, arrangement of a 1mm CAN via hole avoidance area, high-low voltage partition isolation and lamination design of a digital isolation chip and a transformer, EMC performance, signal integrity and high-voltage safety are remarkably improved, and high-density and low-noise integration of the BDU is realized.

Description

Technical Field

[0001] This invention relates to the field of printed circuit board design technology, and in particular to a PCB design method and system for integrating a BDU. Background Technology

[0002] With the acceleration of the global energy transition, new energy vehicles, energy storage systems, and industrial power electronic equipment are rapidly developing towards higher efficiency, higher power density, and lighter weight. Under this trend, the performance of the Battery Management System (BMS), as the core control unit, is crucial. The Battery Disconnect Unit (BDU) is the execution and protection component of the BMS, responsible for energy distribution, circuit switching, and overcurrent protection of the battery pack. Its integration and reliability directly affect the performance and safety of the entire system.

[0003] Traditional BDUs employ a discrete design, with large components such as fuses, contactors, and current sensors connected via copper busbars and wiring harnesses. This approach is space-consuming, heavy, and complex to assemble, and the numerous connection points introduce potential failure risks, failing to meet the compact space and high reliability requirements of modern platforms. Therefore, highly integrated solutions using printed circuit boards (PCBs) have become a key technological direction for industry development. By optimizing layout and wiring, integrated BDUs can significantly reduce system size, lower wiring harness costs and weight, increase production automation, and ultimately improve overall system reliability. However, integrating numerous modules with diverse functions and significantly different electrical characteristics onto a limited PCB presents unprecedented design and engineering challenges. Existing technologies mainly suffer from the following shortcomings and drawbacks: First, the difficulty of layout and routing increases dramatically. The significant reduction in PCB area makes component placement space extremely tight. Multiple signals, such as power circuits, low-voltage control, and high-speed communication, coexist in a small space, placing extremely high demands on the rationality of layout planning. An unreasonable layout will result in long and intersecting traces, which not only occupy valuable space but also introduce signal integrity problems.

[0004] Secondly, electromagnetic interference (EMI) is an exceptionally prominent issue. Integrated BDUs simultaneously contain switching noise from high-current power circuits (such as the KL30 main power supply) and highly sensitive weak-signal circuits (such as CAN bus communication and ADC sampling). In traditional designs, if these signal paths are too close together or the reference ground is improperly handled, high-frequency noise from the power circuits can easily couple to sensitive signals through crosstalk or "ground bounce" noise, leading to communication errors, sampling distortion, and consequently, system malfunctions or performance degradation, making it difficult to pass electromagnetic compatibility (EMC) tests.

[0005] Third, high-voltage insulation and safety risks are exacerbated. To improve charging efficiency and driving range, new energy vehicle platforms are evolving from 400V to 800V and above high-voltage platforms. Under this high-voltage environment, if the insulation design between high-voltage areas (such as the main positive circuit) and low-voltage areas (such as the MCU control unit) on the PCB is insufficient, the spacing cannot withstand the high electric field strength, making it extremely easy for serious faults such as breakdown and arc discharge to occur, endangering personal and vehicle safety. Traditional low-voltage PCB safety spacing standards can no longer meet the safety requirements of the 800V platform.

[0006] Fourth, traditional design methods lack targeted optimization techniques. For example, in CAN bus design, conventional wiring rules (such as setting 8mil via clearance areas) are usually followed, which is insufficient when facing the complex electromagnetic environment of the vehicle, and EMI tests are prone to failure due to special interference sources. Furthermore, when space is limited, digital isolation chips and transformers are often laid out separately, failing to fully utilize three-dimensional space and easily neglecting the correct configuration of Y capacitors, thus creating potential EMI problems.

[0007] Chinese patent CN111615254A discloses a printed circuit board and a power supply design method for the printed circuit board. By creating a physical isolation zone (Anti-Etch) in the ground plane, the high-voltage power module (such as 48V / 54V) and the high-voltage part of the voltage converter are enclosed in an area completely free from contact with the external copper surface. This prevents high-voltage noise from propagating through the copper plane to the digital signal area, thereby reducing interference and saving wiring space. However, in practical applications, this solution has the following drawbacks: 1. The isolation dimension is singular, focusing only on "copper surface segmentation" within a plane. The protection method is limited to creating an isolation zone by cutting ground copper on a two-dimensional plane, lacking comprehensive consideration of three-dimensional spatial layout, protection of critical signal channels, and high-frequency noise coupling paths. For example, it does not address protection against via crosstalk of high-speed differential signals (such as CAN bus), nor does it handle the suppression of spatial radiated noise.

[0008] 2. It fails to address insulation safety issues under high-voltage platforms. The highest voltage it targets is 54V, and its isolation zone design is solely for noise interference mitigation purposes, failing to consider safety regulations such as clearances and creepage distances necessary for high-voltage platforms of 800V and above. Its simple copper surface segmentation cannot prevent the risk of breakdown or arcing caused by high electric field strength.

[0009] 3. It fails to address the core layout challenges in high-density integration, merely centralizing and isolating high-voltage components, representing a relatively crude area division strategy. It does not solve the unique layout and routing difficulties inherent in high-density integration, such as optimizing connector definitions, shortening critical signal paths, and 3D stacking of functionally related devices (e.g., isolation chips and transformers) within extremely limited space.

[0010] 3. EMC optimization methods are insufficient and passive, relying solely on "isolation" to passively prevent noise propagation, which is a defensive strategy. It lacks proactive and refined EMI suppression measures, such as setting expanded via clearance areas for sensitive signals, configuring filtering components such as ferrite beads or common-mode inductors for power supply channels, and placing decoupling capacitors near isolation devices. Therefore, its adaptability to complex electromagnetic environments is limited.

[0011] Therefore, there is an urgent need in the field for a PCB design method for high-density integrated BDUs that can systematically solve the above-mentioned layout, EMI, insulation and space utilization problems, and achieve high reliability and high security integration within a limited area to meet the stringent requirements of next-generation high-voltage platforms for BDU products. Summary of the Invention

[0012] In view of this, in order to overcome the shortcomings of the prior art, the present invention aims to provide a PCB design method and system for integrating BDU.

[0013] According to a first aspect of the present invention, a PCB design method for integrating a BDU is provided, the method comprising: Step S1: Divide the PCB board into regions according to electrical characteristics and signal types, and preset the physical and electrical isolation strategies between each region; Step S2: Based on the structural constraints of the PCB and the position of the connector terminals, adjust the pin definitions of the connectors and the layout of the corresponding functional modules; Step S3: Through key channel and EMI co-design, noise coupling suppression and high-low voltage boundary isolation are achieved; Step S4: Overlap functionally related components on both sides of the PCB, place decoupling and filtering components nearby, and perform three-dimensional integration.

[0014] Optionally, in the PCB design method of the integrated BDU of the present invention, in step S1, the PCB board is divided into a high voltage area, a low voltage area, a power circuit area and a sensitive signal area, the high current power supply path is arranged in a separately divided power ground area, the secondary power supply is introduced into the digital chip power supply area after being filtered and isolated by a ferrite bead, and the communication sensitive signal is arranged in a quiet area away from the power area.

[0015] Optionally, the PCB design method for the integrated BDU of the present invention, step S1, further includes: routing the CAN differential signal using impedance-matched differential linewidth and spacing; and for the ADC sampling circuit, using analog ground to surround and perform star-point grounding.

[0016] Optionally, in the PCB design method for the integrated BDU of the present invention, step S2 includes: analyzing the fixed position of the high-voltage connector terminals, adjusting the layout position of the daisy-chain AFE chip to the central area between the two high-voltage terminals, and correspondingly adjusting the pin definition of the connector so that the sampling signal line is preferentially connected to the AFE chip.

[0017] Optionally, in the PCB design method for the integrated BDU of the present invention, step S3 includes: setting an enlarged via-free zone for sensitive differential signals to suppress noise coupling.

[0018] Optionally, in the PCB design method for the integrated BDU of the present invention, step S3 includes setting an enlarged via-restricted area for sensitive differential signals, including setting a circular restricted routing area with a diameter of not less than 1 mm around the differential line layer-change via.

[0019] Optionally, in the PCB design method for the integrated BDU of the present invention, step S3 further includes: using an isolation device to achieve electrical isolation between the high-voltage area and the low-voltage area, and ensuring that the electrical clearance between the high-voltage line and the low-voltage line or device is not less than a preset safety distance.

[0020] Optionally, in the PCB design method for the integrated BDU of the present invention, step S4 involves overlapping the functionally related components on the front and back sides of the PCB, including: placing the digital isolation chip and the matching push-pull transformer in the corresponding projection areas of the top and bottom layers of the PCB, so that the two overlap in vertical space.

[0021] Optionally, in the PCB design method for the integrated BDU of the present invention, step S4, configuring decoupling and filtering components nearby, includes: arranging a shared Y capacitor near the overlapping layout area of ​​the digital isolation chip and the push-pull transformer.

[0022] According to a second aspect of the present invention, a PCB design system integrating a BDU is provided, the PCB design system integrating a BDU comprising: The system partitioning and isolation module is used to divide the PCB board into regions based on electrical characteristics and signal types, and to preset physical and electrical isolation strategies between each region. The structure-driven layout optimization module is used to adjust the pin definitions and layout of corresponding functional modules based on the PCB's structural constraints and connector terminal positions. The collaborative design module is used to collaborate with EMI design through critical channels to suppress noise coupling and isolate high and low voltage boundaries; The three-dimensional integrated module is used to overlap functionally related components on the front and back of the PCB, and to place decoupling and filtering components nearby for three-dimensional integration.

[0023] The PCB design method and system for integrated BDU of the present invention have the following beneficial technical effects: 1. Significantly improves electromagnetic compatibility (EMC) and reduces system noise. Significantly reduces CAN communication interference: By setting a 1mm keepout zone for CAN differential signal vias (approximately 5 times that of conventional designs), high-frequency switching noise and power loop signals are effectively prevented from coupling to sensitive communication channels via parasitic capacitance. This measure forms a highly efficient noise isolation barrier, and field measurements show that it can optimize EMI radiation performance by up to 17dB, significantly improving communication reliability and making the system more likely to meet stringent automotive electronic electromagnetic compatibility standards such as CISPR 25, while reducing the cost and time required for subsequent shielding and rectification.

[0024] Optimized power supply and ground noise isolation: Through strict zoning, the KL30 high-current power supply is placed in a separate reference ground, and the KL15 power supply is introduced after isolation with ferrite beads. This effectively suppresses the propagation of power supply noise between different functional modules, especially preventing the interference of "ground bounce" noise to low-voltage sensitive circuits, and providing a clean working environment for MCU, ADC sampling and communication circuits.

[0025] 2. Optimize space utilization to achieve extremely high integration. Reduced horizontal layout area: By overlapping the digital isolation chip and push-pull transformer on both sides of the PCB, components that would otherwise need to be placed side-by-side are integrated vertically, saving approximately 30% of the isolation circuit plane area. This directly supports the design goals of product miniaturization and weight reduction.

[0026] Innovative layout shortens the critical path: By redefining the connector pins and centrally placing the daisy-chain AFE chip between the two high-voltage terminals, the daisy-chain sampling signal achieves symmetrical and shortest trace length. This optimization not only saves approximately 10mm of valuable layout space in the Y direction but also shortens the signal path length by about 30%, reducing signal attenuation and loop area.

[0027] 3. Enhance high-voltage safety and system reliability Ensuring high-voltage insulation safety: It is clearly stipulated that a clearance and creepage distance of not less than 5mm should be maintained between the high-voltage area (800V platform) and the low-voltage area, which fundamentally eliminates the fatal safety hazards such as breakdown and arcing that may occur under high electric field due to insufficient spacing, and meets the ultimate requirements of high-voltage applications for long-term reliability and safety.

[0028] Improving the performance and reliability of isolation circuits: The overlapping layout of the digital isolation chip and the transformer naturally allows the shared Y capacitor to serve both simultaneously with the shortest path, providing an efficient low-impedance discharge path for common-mode noise. This design not only saves the cost of a single capacitor but also fundamentally solves the EMI test failure problem caused by the Y capacitor being placed too far away or omitted, enhancing the long-term stability of the isolation interface.

[0029] 4. Improve signal integrity and enhance system performance Ensuring communication quality: The expanded CAN ban zone and optimized layout together ensure the impedance continuity of differential signals, reduce signal reflection and jitter, making CAN bus communication more stable and significantly reducing the bit error rate.

[0030] Improved sampling accuracy: The shortening and symmetry of the daisy-chain signal path reduces transmission delay and the possibility of interference, ensuring the accuracy and synchronization of battery voltage sampling data, thereby improving the core control accuracy of the battery management system.

[0031] In summary, through the synergistic application of the above-mentioned technical measures, this invention successfully achieves an integrated BDU solution that excels in high density, low noise, high safety, and high reliability. It is directly applicable to new energy vehicles and energy storage systems of 800V and above, significantly enhancing the market competitiveness of these products. Attached Figure Description

[0032] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is an example architecture diagram of a PCB design system integrating a BDU according to an embodiment of the present invention; Figure 2 This is a flowchart illustrating the steps of a PCB design method integrating a BDU according to an embodiment of the present invention. Figure 3 This is an example diagram of a CAN communication design based on the scenario described in this embodiment; Figure 4 This is an example diagram of a CAN communication PCB board design based on the scenario described in this embodiment; Figure 5 This is an example diagram of avoidance zone test data in existing technology; Figure 6 This is an example diagram of test data for a 6x avoidance zone set according to the method of this embodiment; Figure 7This is an example diagram of the structural terminal area space in an embodiment of the present invention; Figure 8 Example diagrams are provided for the digital isolation chip and push-pull transformer in this embodiment scenario; Figure 9 This is an example diagram showing the front and back stacking configuration of the digital isolation chip and push-pull transformer PCB in this embodiment.

[0034] Figure 10 This is an example diagram of the KL30 and CAN signal areas in this embodiment. Figure 11 This is an example diagram illustrating isolation using magnetic beads in this embodiment. Figure 12 This is an example diagram illustrating the setting of the safety distance between high voltage and low voltage in the scenario of this embodiment. Detailed Implementation

[0035] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0036] It should be noted that, in the absence of conflict, the following embodiments and features can be combined with each other; and, based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0037] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this disclosure, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0038] Figure 1 This is an example architecture diagram of a PCB design system integrating a BDU according to an embodiment of the present invention, as shown below. Figure 1 As shown, the PCB design system with integrated BDU in this embodiment includes: The system partitioning and isolation module is used to divide the PCB board into regions based on electrical characteristics and signal types, and to preset physical and electrical isolation strategies between each region. The structure-driven layout optimization module is used to adjust the pin definitions and layout of corresponding functional modules based on the PCB's structural constraints and connector terminal positions. The collaborative design module is used to collaborate with EMI design through critical channels to suppress noise coupling and isolate high and low voltage boundaries; The three-dimensional integrated module is used to overlap functionally related components on the front and back of the PCB, and to place decoupling and filtering components nearby for three-dimensional integration.

[0039] Based on the above system, this invention provides a PCB design method for integrating BDU, which will be described below through the following embodiments.

[0040] Figure 2 This is a flowchart illustrating the steps of a PCB design method integrating a Battery Disconnect Unit (BDU) according to an embodiment of the present invention. In this embodiment, the BDU is a battery disconnect unit or distribution box, a core power distribution and safety protection component in high-voltage power systems such as new energy vehicles and energy storage systems. It is equivalent to the "master switch" and "fuse box" of a high-voltage battery pack, responsible for power distribution, on / off control, and safety protection. The PCB (Printed Circuit Board) is the core skeleton and nervous system of modern electronic devices. It is a key component that uses electronic printing technology to process conductive patterns (lines, pads, vias, etc.) on an insulating substrate for connecting and supporting electronic components. In this embodiment, the role of the PCB is upgraded from a simple connection carrier to a core platform for achieving high-density integration and ensuring system functionality and reliability.

[0041] like Figure 2 As shown, the PCB design method for integrating a BDU in this embodiment includes the following steps: Step S1: Divide the PCB board into regions according to electrical characteristics and signal types, and preset the physical and electrical isolation strategies between each region.

[0042] As an optional example, in this embodiment, the high-current power supply path of KL30 is arranged in a separately divided power ground area so that its noise does not affect other areas; the power supply of KL15 is introduced into the digital chip power supply area after being filtered and isolated by a ferrite bead; sensitive signals such as CAN communication are arranged in a quiet area far away from the power area, and their reference ground is set as a unified static ground and isolated at the front and rear ends of the common-mode inductor. Thus, noise isolation between circuits of different natures is achieved in the layout, preventing common-mode interference and ground bounce noise from affecting the system stability.

[0043] A complete power path is constructed by using large-area copper cladding or copper foil traces. The line width is determined based on the current capacity calculation to ensure current carrying capacity and reduce parasitic inductance. At the same time, power devices are placed close to each other to minimize the power loop area, thereby reducing switching noise and conduction losses.

[0044] For CAN differential, impedance-matched differential line widths and spacings are used for wiring, with ground shielding throughout. CAN differential is the differential signal transmission mechanism used by the Controller Area Network (CAN) bus. It uses two signal lines (CAN_H and CAN_L) to transmit the same signal, but the voltage levels on these two lines are opposite.

[0045] For the ADC sampling circuit, an analog ground is used to surround it and a star-point ground is applied to keep it away from all power devices and high-frequency switching sources to ensure the accuracy of signal acquisition and anti-interference. The ADC sampling circuit is a complete electronic circuit system that realizes the function of analog-to-digital conversion. Its core task is to continuously acquire (sample) real analog voltage signals and convert them into digital values ​​that can be read and processed by a microprocessor (MCU) or digital signal processor (DSP).

[0046] Step S2: Based on the structural constraints of the PCB and the position of the connector terminals, adjust the pin definitions of the connectors and the layout of the corresponding functional modules.

[0047] As an optional example, in this embodiment, the fixed position of the high-voltage connector terminals is analyzed, and the layout position of the daisy-chain AFE chip is adjusted to the central area between the two high-voltage terminals. The pin definition of the connector is adjusted accordingly so that the sampling signal line is preferentially connected to the AFE chip, so that the daisy-chain sampling signal path achieves a symmetrical and shortest layout, effectively reducing signal transmission delay and loop area, and improving sampling accuracy and anti-interference capability.

[0048] Step S3: Through key channels and EMI co-design, noise coupling suppression and high / low voltage boundary isolation are achieved.

[0049] In this embodiment, an expanded via-free zone is set for sensitive differential signals to suppress noise coupling. For example, a circular no-route zone with a diameter of not less than 1mm is set around the differential line via, prohibiting all other network traces, power copper traces, and ground plane dividers from entering this area, forming a noise-free "clean" channel. This reduces the coupling of high-frequency switching noise to the differential signal through via parasitic capacitance, thereby significantly reducing EMI (Electromagnetic Interference) radiation and improving communication reliability. In this embodiment, EMI refers to the interference caused by noise sources such as power circuits on the PCB to sensitive signals such as CAN communication, which is a key issue that needs to be addressed during the design process.

[0050] In this embodiment, isolation devices are used to isolate the high- and low-voltage boundary area, achieving electrical isolation and insulation protection. For example, digital isolation chips and push-pull transformers are used in parallel between the high-voltage and low-voltage areas to achieve bidirectional isolated transmission of signals and energy; at the same time, it is ensured that the creepage distance and clearance between the high-voltage line and any low-voltage line or device are not less than 5mm to meet the insulation and safety regulatory requirements of 800V and above high-voltage platforms.

[0051] Step S4: Overlap functionally related components on both sides of the PCB, place decoupling and filtering components nearby, and perform three-dimensional integration.

[0052] In this embodiment, the digital isolation chip is placed on the top layer of the PCB, and the corresponding push-pull transformer is placed in the corresponding projection area on the bottom layer of the PCB, so that the two overlap in vertical space. This layout compresses the plane area occupied by the originally dispersed isolation circuit to a minimum, realizing high-density integration.

[0053] In this embodiment, a shared Y capacitor is placed near the center of the overlapping layout area of ​​the digital isolation chip and the push-pull transformer. The high-voltage end of the Y capacitor is connected to the primary ground of the push-pull transformer, and the low-voltage end is connected to the secondary ground of the digital isolation chip. This provides a very short and effective discharge path for common-mode noise, thereby solving the demand for Y capacitors for both types of isolation devices and effectively suppressing the propagation of common-mode noise.

[0054] The following section further explains the PCB design method for integrating BDU in a specific scenario.

[0055] This application scenario is in the automotive industry, where numerous electronic devices can interfere with CAN communication. In traditional CAN bus PCB design, the CAN bus uses CAN_H and CAN_L differential signals, with vias placed within an 8mil clearance zone. If encountering specific interfering devices, this can cause EMI testing to fail. To ensure high reliability of CAN communication, this embodiment uses a clearance zone five times the standard size (1mm) in the PCB design. By setting a 1mm clearance zone, crosstalk between CAN signal vias and power circuits or high-frequency switching lines is avoided, reducing common-mode noise radiation and effectively improving communication performance while reducing high-frequency noise coupling. Figure 3 This is a design example diagram of CAN communication based on the scenario described in this embodiment. Figure 4 This is an example diagram of a CAN communication PCB board design based on the scenario described in this embodiment. Figure 5 This is an example diagram of avoidance zone test data in existing technology. Figure 6 This is an example diagram of test data for a 6x avoidance zone set according to the method of this embodiment.

[0056] In the schematic design phase of this scenario, the traditional connector interface definition format is used, and the pin positions of the daisy chain definition are set below the CAN communication. Figure 7 This is an example diagram of the structural terminal area space in an embodiment of the present invention. Figure 7 As shown, due to the limited space of the structural terminals in this scenario, the only usable space is the area between the two terminals. This area is too small to accommodate the placement of CAN communication components. Therefore, this embodiment swaps the pin definitions of CAN communication and daisy-chain, placing the daisy-chain AFE chip in the middle of the terminals. This effectively utilizes PCB space, saving 10mm in the Y direction. Simultaneously, the distance from the connector to the daisy chain is shortened, improving EMC (Electromagnetic Compatibility) performance, reducing signal attenuation, and enhancing anti-interference capabilities, signal stability, and robustness. It should be noted that placing the daisy-chain chip between the two connector terminals in this embodiment symmetricalizes the sampling line length, reduces transmission delay, and shortens the critical signal path, typically by 30%. Furthermore, it saves PCB area; the optimized layout can reduce trace space by 10%-20%, making it suitable for compact BDU designs.

[0057] This scenario involves both high-voltage and low-voltage sections, using digital isolation chips and push-pull transformers for electrical isolation. Both the digital isolation chip and the push-pull transformer require the placement of Y capacitors. In existing designs, no Y capacitor is placed next to the digital isolation chip, leading to EMI failure. In this scenario, due to limited space in the Y direction, the digital isolation chip and push-pull transformer are placed back-to-back. This not only effectively saves space, but also ensures that the distance between the stacked digital isolation chip and the push-pull transformer and the Y capacitor is very close, thus avoiding test failures caused by the absence of a Y capacitor next to the digital isolation chip. Figure 8 Example diagrams are provided for the digital isolation chip and push-pull transformer in this embodiment scenario; Figure 9 This diagram illustrates the front-back stacking arrangement of the digital isolation chip and push-pull transformer PCB in this embodiment. In this embodiment, the overlapping front-back layout saves space occupied by the isolation circuitry and supports higher-density integration; the digital isolation chip and transformer are stacked, sharing a single Y capacitor, thus saving the cost of one Y capacitor. The optimized structure meets isolation standards such as UL 1577 and IEC 60747.

[0058] In this scenario, communication methods including CAN, KL30, KL15, and daisy chain are used. CAN communication and KL30 signals are placed separately. KL30 is referenced separately to KL31. KL15 is isolated by a ferrite bead. CAN signals are referenced to ground normally and isolated at the front and back ends by a common-mode inductor. Figure 10 This is an example diagram of the KL30 and CAN signal areas in this embodiment. Figure 11This is an example diagram illustrating isolation using magnetic beads in this embodiment.

[0059] In this embodiment, high voltage and low voltage coexist. The high voltage is designed for 800V. To avoid breakdown and leakage under high voltage conditions that could affect long-term reliability, the physical insulation distance between the high voltage and low voltage is 5mm. Figure 12 This is an example diagram illustrating the setting of the safety distance between high voltage and low voltage in the scenario of this embodiment.

[0060] In practical applications, the PCB design method and system with integrated BDU in this embodiment have the following beneficial technical effects: 1. Significantly improves electromagnetic compatibility (EMC) and reduces system noise. Significantly reduces CAN communication interference: By setting a 1mm keepout zone for CAN differential signal vias (approximately 5 times that of conventional designs), high-frequency switching noise and power loop signals are effectively prevented from coupling to sensitive communication channels via parasitic capacitance. This measure forms a highly efficient noise isolation barrier, and field measurements show that it can optimize EMI radiation performance by up to 17dB, significantly improving communication reliability and making the system more likely to meet stringent automotive electronic electromagnetic compatibility standards such as CISPR 25, while reducing the cost and time required for subsequent shielding and rectification.

[0061] Optimized power supply and ground noise isolation: Through strict zoning, the KL30 high-current power supply is placed in a separate reference ground, and the KL15 power supply is introduced after isolation with ferrite beads. This effectively suppresses the propagation of power supply noise between different functional modules, especially preventing the interference of "ground bounce" noise to low-voltage sensitive circuits, and providing a clean working environment for MCU, ADC sampling and communication circuits.

[0062] 2. Optimize space utilization to achieve extremely high integration. Reduced horizontal layout area: By overlapping the digital isolation chip and push-pull transformer on both sides of the PCB, components that would otherwise need to be placed side-by-side are integrated vertically, saving approximately 30% of the isolation circuit plane area. This directly supports the design goals of product miniaturization and weight reduction.

[0063] Innovative layout shortens the critical path: By redefining the connector pins and centrally placing the daisy-chain AFE chip between the two high-voltage terminals, the daisy-chain sampling signal achieves symmetrical and shortest trace length. This optimization not only saves approximately 10mm of valuable layout space in the Y direction but also shortens the signal path length by about 30%, reducing signal attenuation and loop area.

[0064] 3. Enhance high-voltage safety and system reliability Ensuring high-voltage insulation safety: It is clearly stipulated that a clearance and creepage distance of not less than 5mm should be maintained between the high-voltage area (800V platform) and the low-voltage area, which fundamentally eliminates the fatal safety hazards such as breakdown and arcing that may occur under high electric field due to insufficient spacing, and meets the ultimate requirements of high-voltage applications for long-term reliability and safety.

[0065] Improving the performance and reliability of isolation circuits: The overlapping layout of the digital isolation chip and the transformer naturally allows the shared Y capacitor to serve both simultaneously with the shortest path, providing an efficient low-impedance discharge path for common-mode noise. This design not only saves the cost of a single capacitor but also fundamentally solves the EMI test failure problem caused by the Y capacitor being placed too far away or omitted, enhancing the long-term stability of the isolation interface.

[0066] 4. Improve signal integrity and enhance system performance Ensuring communication quality: The expanded CAN ban zone and optimized layout together ensure the impedance continuity of differential signals, reduce signal reflection and jitter, making CAN bus communication more stable and significantly reducing the bit error rate.

[0067] Improved sampling accuracy: The shortening and symmetry of the daisy-chain signal path reduces transmission delay and the possibility of interference, ensuring the accuracy and synchronization of battery voltage sampling data, thereby improving the core control accuracy of the battery management system.

[0068] In summary, through the synergistic application of the above-mentioned technical measures, this invention successfully achieves an integrated BDU solution that excels in high density, low noise, high safety, and high reliability. It enables synergistic optimization of EMI, thermal distribution, and signal integrity, extends product lifespan, and is suitable for new energy vehicles and energy storage systems of 800V and above, significantly enhancing their market competitiveness.

[0069] The system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected based on actual needs to achieve the purpose of this embodiment. Those skilled in the art can understand and implement this without any creative effort.

[0070] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods of various embodiments or some parts of embodiments.

[0071] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A PCB design method for integrating a BDU, characterized in that, The method includes: Step S1: Divide the PCB board into regions according to electrical characteristics and signal types, and preset the physical and electrical isolation strategies between each region; Step S2: Based on the PCB structural constraints and connector terminal positions, adjust the connector pin definitions and the layout of corresponding functional modules; Step S3: Through key channel and EMI co-design, noise coupling suppression and high-low voltage boundary isolation are achieved; Step S4: Overlap functionally related components on the front and back of the PCB, place decoupling and filtering components nearby, and perform three-dimensional integration.

2. The PCB design method for integrated BDU according to claim 1, characterized in that, In step S1, the PCB board is divided into a high-voltage area, a low-voltage area, a power circuit area, and a sensitive signal area. The high-current power supply path is arranged in a separately divided power ground area. The secondary power supply is introduced into the digital chip power supply area after being filtered and isolated by a ferrite bead. The communication sensitive signal is arranged in a quiet area away from the power area.

3. The PCB design method for integrated BDU according to claim 1, characterized in that, Its features are, Step S1 further includes: routing the CAN differential signal using impedance-matched differential line width and spacing; and for the ADC sampling circuit, surrounding it with analog ground and performing star-point grounding.

4. The PCB design method for integrated BDU according to claim 1, characterized in that, Step S2 includes: analyzing the fixed position of the high-voltage connector terminals, adjusting the layout position of the daisy-chain AFE chip to the central area between the two high-voltage terminals, and adjusting the pin definition of the connector accordingly so that the sampling signal line is preferentially connected to the AFE chip.

5. The PCB design method for integrating BDU according to claim 1, characterized in that, Step S3 includes: setting an expanded via miss area for the sensitive differential signal to suppress noise coupling.

6. The PCB design method for integrating BDU according to claim 5, characterized in that, Step S3 involves setting an expanded via no-wiring zone for sensitive differential signals, including setting a circular no-wiring zone with a diameter of not less than 1 mm around the differential line layer-changing via.

7. The PCB design method for integrating BDU according to claim 1, characterized in that, Step S3 also includes: using isolation devices to achieve electrical isolation between the high-voltage area and the low-voltage area, and ensuring that the electrical clearance between the high-voltage line and the low-voltage line or device is not less than the preset safety distance.

8. The PCB design method for integrated BDU according to claim 1, characterized in that, In step S4, the functionally related components are laid out in an overlapping manner on the front and back of the PCB, including: placing the digital isolation chip and the matching push-pull transformer in the corresponding projection areas of the top and bottom layers of the PCB, so that the two overlap in vertical space.

9. The PCB design method for integrating BDU according to claim 8, characterized in that, In step S4, decoupling and filtering components are configured nearby, including: placing a shared Y capacitor near the overlapping layout area of ​​the digital isolation chip and the push-pull transformer.

10. A PCB design system integrating a BDU, characterized in that, The PCB design system integrating BDU includes: The system partitioning and isolation module is used to divide the PCB board into regions based on electrical characteristics and signal types, and to preset physical and electrical isolation strategies between each region. The structure-driven layout optimization module is used to adjust the pin definitions and layout of corresponding functional modules based on the PCB's structural constraints and connector terminal positions. The collaborative design module is used to collaborate with EMI design through critical channels to suppress noise coupling and isolate high and low voltage boundaries; The three-dimensional integrated module is used to overlap functionally related components on the front and back of the PCB, and to place decoupling and filtering components nearby for three-dimensional integration.

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