Method, device and equipment for automatically generating EMIR test case and medium
By automating the generation of EMIR test cases, the problem of insufficient testing resources in domestic EDA tools has been solved, and an efficient test case construction and verification process has been achieved, thereby enhancing the competitiveness of domestic EDA tools.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HANGZHOU YIFANG DIGITAL INNOVATION TECHNOLOGY CO LTD
- Filing Date
- 2026-02-05
- Publication Date
- 2026-05-19
AI Technical Summary
The lack of sufficient, diverse and practical testing resources for domestically produced EMIR-approved EDA tools leads to inefficient verification processes and makes it difficult to support the verification needs of tools under extreme working conditions and high-precision calculations.
The method for automatically generating EMIR test cases includes obtaining process information from parameter configuration files, performing geometric abstraction and coordinate calculations, and generating EMIR test cases.
It improves the efficiency of test case construction, saves manpower costs, enhances the competitiveness of domestic EDA tools, and promotes the efficient implementation of EMIR tool testing and verification processes.
Smart Images
Figure CN122065765A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit design, and specifically relates to a method, apparatus, device and medium for automatically generating EMIR test cases. Background Technology
[0002] In the current context of fierce competition and rapid technological iteration in the global integrated circuit industry, Electronic Design Automation (EDA) tools, as the core support for chip design, are directly related to the security of the industrial chain and the initiative in technological innovation in terms of their level of self-control.
[0003] EMIR (Electromigration and IR Drop) is a crucial aspect of chip physical verification, directly impacting power efficiency, heat dissipation, and long-term reliability. The corresponding signature-level EDA tool testing and verification places extremely high demands on the professionalism, diversity, and scenario coverage of test cases. Test cases must accurately simulate the physical effects of the chip under extreme operating conditions and complex layouts and routing scenarios to effectively expose potential defects in the tool's functional logic and computational accuracy. However, the core bottleneck currently facing the industry is that the physical layout and netlist data of real chip designs are core intellectual property of enterprises and are rarely disclosed to the public. This results in a lack of sufficient, diverse, and practically applicable test resources for domestically produced EMIR signature-level EDA tools.
[0004] Existing methods for obtaining test cases have significant limitations: On the one hand, relying on open-source circuit design resources cannot meet the verification requirements of approval-level tools. Open-source data often lacks targeted design for complex physical scenarios and has incomplete coverage of functional modules, making it difficult to support the verification of core capabilities such as extreme working conditions and high-precision calculations. On the other hand, the traditional manual test case construction model is limited by the experience and effort of designers, resulting in long cycles, high costs, and difficulty in generating customized test cases with precise coordinate control and extreme physical scenario simulation in batches. This leads to low efficiency in the verification process and seriously restricts the R&D and iteration speed of domestic EDA tools.
[0005] Against this backdrop, developing a technical solution capable of automatically generating high-fidelity, customized EMIR test cases has become crucial for overcoming the verification bottleneck of domestic EDA tools. This solution must be able to accurately reproduce various complex physical scenarios and circuit topologies, providing comprehensive and multi-layered testing support for EMIR approval-level tools. This will help domestic EDA tools reach international advanced levels in functional integrity, computational accuracy, and stability, accelerate the industrialization of independent EDA tools, and lay a solid foundation for the independent and controllable development of my country's integrated circuit industry. Summary of the Invention
[0006] To address the aforementioned problems in the prior art, this invention provides a method, apparatus, device, and medium for automatically generating EMIR test cases.
[0007] The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides a method for automatically generating EMIR test cases, the method comprising: Based on the pre-set parameter configuration file, the process information required for the layout is obtained; Based on the parameter configuration file, the geometric shapes of each component of the layout are obtained by geometrically abstracting each component of the layout. The coordinates of each component in the layout are obtained based on the geometry of each component, the parameter configuration file, and the process information. A script for drawing the layout is generated based on the coordinates of each component of the layout and executed to obtain a recorded layout file; The log file for this layout drawing is obtained from the layout file to generate EMIR test cases.
[0008] Optionally, obtaining the process information required for the layout based on a pre-set parameter configuration file includes: Based on the site in the parameter configuration file, obtain the height information from the preset physical library file; Based on the circuit units in the parameter configuration file, obtain the process information of the circuit units in the physical library file; Based on the bumps in the parameter configuration file, obtain the process information of the bumps in the physical library file; The required process information for the layout is obtained based on the height information, the process information of the circuit unit, and the process information of the bump.
[0009] Optionally, the step of geometrically abstracting each component of the layout according to the parameter configuration file to obtain the geometric shape of each component of the layout includes: Based on the site in the parameter configuration file, the layout geometry is abstracted into multiple rectangular regions of the same shape to obtain the first geometric shape; The ports, wires, and bumps in the parameter configuration file are geometrically abstracted into rectangles to obtain the second geometric shape; The circuit units in the parameter configuration file are geometrically abstracted into a combination of multiple rectangles to obtain a third geometric shape; The geometry of each component of the layout is obtained based on the first geometry, the second geometry, and the third geometry.
[0010] Optionally, obtaining the coordinates of each component in the layout based on the geometry of each component, the parameter configuration file, and the process information includes: The layout height is calculated based on the first geometric shape and the height information; The coordinates of the circuit unit are obtained based on the third geometry, the height information, and the process information of the circuit unit; The coordinates of the conductor are obtained based on the process information of the circuit unit and the second geometry; The coordinates of the bump are obtained based on the process information of the circuit unit and the second geometry; The coordinates of the port are obtained based on the first geometry and the second geometry; The coordinates of each component in the layout are obtained based on the layout height, the coordinates of the circuit unit, the coordinates of the wire, the coordinates of the bump, and the coordinates of the port.
[0011] Optionally, obtaining the log file for this layout drawing based on the layout file includes: Based on the layout file, obtain the design rule check results and connectivity results of the layout drawn this time; The log file is obtained based on the results of the design rules check and the connectivity results.
[0012] Secondly, the present invention provides an apparatus for automatically generating EMIR test cases, the apparatus comprising: The information acquisition module is used to obtain the process information required for the layout based on a pre-set parameter configuration file; The shape acquisition module is used to perform geometric abstraction on each component of the layout according to the parameter configuration file to obtain the geometric shape of each component of the layout; The coordinate acquisition module is used to obtain the coordinates of each component of the layout based on the geometry of each component, the parameter configuration file, and the process information. The layout file acquisition module is used to generate and execute a script for drawing the layout based on the coordinates of each component of the layout, thereby obtaining a recorded layout file; The test case generation module is used to obtain the log file of the current layout drawing based on the layout file, so as to generate EMIR test cases.
[0013] Thirdly, the present invention provides an electronic device, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, used to store computer programs; When a processor executes a program stored in memory, it implements any step of the automated EMIR test case generation method described in the first aspect above.
[0014] Fourthly, the present invention provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements any step of the automated EMIR test case generation method described in the first aspect.
[0015] The technical solutions provided by the embodiments of the present invention may include the following beneficial effects: In the above technical solution, the present invention parameterizes the geometric abstraction of each component of the EMIR test case layout, and automates the EMIR test case construction, which can greatly improve the efficiency of test case construction, save manpower costs, promote the EMIR tool testing and verification process, and enhance the competitiveness of domestic EDA tools in the current situation.
[0016] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description
[0017] Figure 1 This is a flowchart of an automated method for generating EMIR test cases provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the geometry of a wire and a port provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the geometric shape of a circuit unit and a through hole provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of a layout file style provided in an embodiment of the present invention; Figure 5 This is a block diagram of an automated EMIR test case generation device provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of an electronic device for automatically generating EMIR test cases, provided by an embodiment of the present invention. Detailed Implementation
[0018] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.
[0019] First, the correspondence between the full English names and their Chinese meanings involved in this invention is shown in Table 1: Table 1
[0020] Figure 1This is a flowchart of an automated method for generating EMIR test cases provided in an embodiment of the present invention, such as... Figure 1 As shown, the method may include the following steps: S101. Obtain the process information required for the layout based on the pre-set parameter configuration file.
[0021] Optionally, S101 may include: Based on the site in the parameter configuration file, obtain the height information from the preset physical library file; Based on the circuit units in the parameter configuration file, obtain the process information of the circuit units from the physical library file; Based on the bumps in the parameter configuration file, obtain the process information of the bumps in the physical library file; The required process information for the layout is obtained based on the height information, the process information of the circuit unit, and the process information of the bump.
[0022] Understandably, based on the site name in the parameter configuration file, its specific height information is obtained from the preset LEF file. This part of the process information will be used for the subsequent calculation of the actual height of the layout. Based on the instance name in the parameter configuration file, the process shape information of all instances is obtained from the preset LEF file. This part of the process information will be used for the subsequent calculation of the grid coordinates of the pinshape of each instance. Based on the bump name in the parameter configuration file, the bump process shape information is obtained from the preset LEF file. This part of the process information will be used for the subsequent calculation of the bump coordinates.
[0023] S102. Based on the parameter configuration file, perform geometric abstraction on each component of the layout to obtain the geometric shape of each component of the layout.
[0024] Optionally, S102 may include: Based on the site parameter configuration file, the layout geometry is abstracted into multiple rectangular regions of the same shape to obtain the first geometric shape; The ports, wires, and bumps in the parameter configuration file are geometrically abstracted into rectangles to obtain the second geometric shape; The circuit unit geometry in the parameter configuration file is geometrically abstracted into a combination of multiple rectangles to obtain the third geometric shape; The geometry of each component of the layout is obtained based on the first geometry, the second geometry, and the third geometry.
[0025] Understandably, geometric abstraction is performed on each component of the layout so that subsequent steps can perform coordinate calculations based on the abstracted component geometry and parameter configuration files. This geometric abstraction of the layout components includes: dividing the layout area into several rows, with row heights in the form of "site"; therefore, the layout can be viewed as a larger rectangle composed of multiple stacked rectangles of the same shape; and abstracting the port and net geometry as rectangles, such as... Figure 2 As shown. The geometric properties of a rectangle dictate that only the coordinates of its lower left corner, length, and width are needed to uniquely identify a rectangle. Subsequent calculation modules will calculate the precise coordinates of each net; the geometry of instances and vias will be abstracted as combinations of multiple rectangles, such as... Figure 3 As shown. For an instance, a combination of three rectangles is abstracted. The coordinate and shape relationships of these three rectangles are contained in the process information of the instance extracted by S101. For a via, the coordinate and shape relationships between its rectangles are all specified by the parameter configuration file. S101 will pass the via data parsed from the parameter configuration file to the subsequent calculation module. Although the shape of a bump is not fixed, its size is defined in the process file, so it can be regarded as a rectangle.
[0026] S103. Obtain the coordinates of each component in the layout based on the geometry, parameter configuration file, and process information of each component.
[0027] It is understandable that S103 may include: The map height is calculated based on the first geometric shape and height information; The coordinates of the circuit unit are obtained based on the third geometry, height information, and process information of the circuit unit; The coordinates of the wires are obtained based on the process information and second geometry of the circuit unit; The coordinates of the bump are obtained based on the process information and second geometry of the circuit unit; The coordinates of the port are obtained based on the first and second geometric shapes; The coordinates of each component in the layout are obtained based on the layout height, the coordinates of the circuit unit, the coordinates of the wire, the coordinates of the bump, and the coordinates of the port.
[0028] It is understood that the coordinate calculation method for each component of the layout proposed in this invention combines the parameter configuration file and process information extracted in S101, as well as the geometry of each component in the layout in S102, to calculate precise absolute coordinates. After obtaining the coordinates of each component, they are all passed to S103 without the need for secondary modification of the parameter configuration file.
[0029] Specifically, the layout height is calculated as follows: H = n_rows * h_site, where H is the layout height, n_rows is the number of rows specified in the S101 parameter configuration file, and h_site is the height information obtained by S101 based on the site specified in the parameter configuration file; the instance's ordinate is calculated as follows: Y = row * h_site, where Y is the instance's ordinate, and row is the row number of the instance to be placed specified in the S101 parameter configuration file; the instance's pinshape grid coordinates are calculated as follows: the instance's ordinate Y has been calculated and determined, and the abscissa is provided by the S101 parameter configuration file and denoted as X. The instance's process information is obtained from S101. Based on the relative distance between the pinshape grid points of VDD and VSS in the circuit cell's process information and the instance's coordinates (X, Y), VDD and VSS can be obtained. The specific coordinates of the four grid points of each pinshape of S; the coordinates of net are represented by the pinshape grid coordinates of the VDD and VSS of the instance in the parameter configuration file. Therefore, the specific coordinates of the lower left corner of each net are calculated by substituting the pinshape grid coordinates of the instance; the coordinates of bump are determined by the bump process information; first, the four edges of the layout area are numbered, with the upper left and lower right edges numbered 0, 1, 2, and 3 respectively. The port number specified in the parameter configuration file is obtained, and then they are placed on the edge in batches with a certain offset and equal interval.
[0030] S104. Generate a script for drawing the layout based on the coordinates of each component of the layout and execute it to obtain a recorded layout file.
[0031] S105. Obtain the log file of the layout drawn this time based on the layout file, so as to generate EMIR test cases.
[0032] Optionally, S105 may include: Based on the layout file, obtain the design rule check results and connectivity results for this layout; Log files are obtained based on the results of the design rules check and connectivity checks.
[0033] In one implementation, components such as bump, ALPA (Aluminum Pad Layer) layer to M1 layer cross-layer metal traces, and vias basically cover all test scenarios for EMIR test case construction. The entire implementation process is roughly as follows: first, set the parameter configuration file for this embodiment; then, extract the relevant parameters and find all the required process information in the specified process file; then, calculate the coordinates of all components based on the process information and the parameter configuration file; then, generate and execute the layout-related scripts based on the component coordinates; finally, check for DRC and connectivity issues and record the statistics in the log file so that users can understand which test cases encountered DRC issues during the automated construction process.
[0034] Specifically, the pre-set parameter configuration file is read to obtain the required process information. In this embodiment, the site height h_site obtained from the process file is 0.574. In the process shape information of the instance, the relative distances between the lower left corner grid point of the VDD's pinshape and the horizontal and vertical coordinates of the instance are -0.048 and 0.531, respectively, and the relative distances between the upper right corner grid point and the horizontal and vertical coordinates of the instance are 3.108 and 0.621, respectively; the relative distances between the lower left corner grid point of the VSS's pinshape and the horizontal and vertical coordinates of the instance are -0.048 and -0.045, respectively, and the relative distances between the upper right corner grid point and the horizontal and vertical coordinates of the instance are 3.108 and 0.045, respectively. In the process shape information of the bump, its horizontal length and vertical length are both 6.0.
[0035] Layout shape calculation: The total number of rows n_rows specified in the parameter configuration file is 100, the layout width is 55, and the distance between the placement and routing area and the four edges of the layout shape is 0. Layout height H = n_rows * h_site = 100 * 0.574 = 57.4. Therefore, the layout shape is a rectangle with a height of 57.4 and a width of 55, and the distance between the placement and routing area and the four edges of the layout shape is 0, meaning they completely overlap.
[0036] Instance coordinate calculation: Taking instance1 as an example, its x-coordinate is specified as 5 and its y-coordinate is specified as line 50 in the parameter configuration file. Therefore, the y-coordinate of instance1 = 50 * h_site = 28.7. Hence, the precise coordinates of instance1 are (50, 28.7). Calculation of pinshape grid coordinates for the VDD and VSS of the instance: Taking VDD as an example, we previously obtained the relative distances between the lower left and upper right corners of the VDD pinshape with respect to the instance coordinates. In the instance coordinate calculation section, we obtained the specific coordinates of instance1 as (50, 28.7). Therefore, the grid coordinates of the lower left corner of the VDD pinshape of instance1 are (x=50-0.048, y=28.7+0.531). We label the x and y coordinates of this grid point as (u1_vdd_ll_x, u1_vdd_ll_y), where u1_vdd represents the pinshape of the VDD of instance1, ll represents the lower left corner, and x represents the x-coordinate. Similarly, we can obtain the coordinates of the upper right corner of the VDD pinshape of instance1 as (u1_vdd_ru_x, u1_vdd_ru_y), where ru represents the right upper corner.
[0037] In the parameter configuration text proposed in this invention, the coordinates of a net are represented by the relative distance between the pinshape grid coordinates of the VDD and VSS of the instance. Therefore, after calculating the precise pinshape grid coordinates, it is necessary to combine the relative coordinates of the net and the pinshape grid in the parameter configuration file to calculate the actual precise coordinates. For example, in this embodiment, there is a net of VDD whose coordinates are represented as (u1_vdd_ll_x-2, u1_vdd_ll_y+1.91). Then, by combining the specific values of u1_vdd_ll_x and u1_vdd_ll_y obtained earlier, the actual absolute coordinates of the net can be calculated as (47.952, 31.141). Therefore, by calculating the actual absolute coordinates of each net in this way and passing them to subsequent steps, it is not necessary to manually calculate and modify the parameter configuration file a second time.
[0038] The precise coordinate calculation of a via is similar to that of a net. Its lower left corner coordinates are also represented in the parameter configuration file as the relative distance of pinshape grid points with respect to instance VDD and VSS. Therefore, based on the pinshape grid point coordinates obtained in the previous steps, the precise absolute position of each via is calculated iteratively and passed to the subsequent steps.
[0039] Bump coordinate calculation: Although the process shape of the bump is not fixed—it could be hexagonal, octagonal, or elliptical—its size is fixed. The process information describes its size as "SIZE 6.0 BY 6.0." From this size description, the bump can be considered equivalent to a rectangle. For the bump used in this example, the relative distance of its center coordinates with respect to the lower left corner of the bump rectangle is 3. Therefore, when placing the bump, the relative distance of the center coordinates needs to be considered to obtain the relative distance of the lower left corner of the bump with respect to the grid coordinates of the pinshape of the instance VDD. Following the coordinate calculation method for nets and vias mentioned earlier, the actual absolute coordinates of the bump are calculated and passed to subsequent steps without requiring secondary modification of the parameter configuration file.
[0040] Port allocation: The four edges of the layout area are numbered as follows: the top left, bottom right, and left edges are numbered 0, 1, 2, and 3 respectively. The port numbers specified in the parameter configuration file are retrieved, and then these ports are placed on the edge in batches with a certain offset and equal intervals. In this embodiment, the parameter configuration file specifies that ports A1, A2, A3, and A4 are placed on edge number 0, with an offset of 30 and an interval of 1. The data_out port is specified to be placed on edge number 3, with an offset of 25 and an interval of 1.
[0041] After calculating the coordinates of each component of the layout, a script for drawing the layout is generated and executed, resulting in a layout file in this embodiment with the following style: Figure 4 As shown, DRC and connectivity checks are performed on the layout file, and the results are compiled into a unified log file to filter out test cases with DRC or other issues.
[0042] In the above technical solution, the present invention parameterizes the geometric abstraction of each component of the EMIR test case layout, and automates the EMIR test case construction, which can greatly improve the efficiency of test case construction, save manpower costs, promote the EMIR tool testing and verification process, and enhance the competitiveness of domestic EDA tools in the current situation.
[0043] Figure 5 This is a block diagram of an automated EMIR test case generation device provided in an embodiment of the present invention, such as... Figure 5 As shown, the device 500 may include: The information acquisition module 501 is used to obtain the process information required for the layout based on a pre-set parameter configuration file; The shape acquisition module 502 is used to perform geometric abstraction on each component of the layout according to the parameter configuration file to obtain the geometric shape of each component of the layout; The coordinate acquisition module 503 is used to obtain the coordinates of each component in the layout based on the geometry, parameter configuration file and process information of each component in the layout. The layout file acquisition module 504 is used to generate and execute a script for drawing the layout based on the coordinates of each component of the layout, and obtain a recorded layout file. The test case generation module 505 is used to obtain the log file of the current layout drawing based on the layout file, so as to generate EMIR test cases.
[0044] The method provided in this invention can be applied to electronic devices. Specifically, the electronic device can be a desktop computer, a portable computer, a smart mobile terminal, a server, etc. No limitation is made herein; any electronic device that can implement this invention falls within the protection scope of this invention.
[0045] This invention also provides an electronic device, such as... Figure 6 As shown, it includes a processor 601, a communication interface 602, a memory 603, and a communication bus 604, wherein the processor 601, the communication interface 602, and the memory 603 communicate with each other through the communication bus 604. Memory 603 is used to store computer programs; When the processor 601 executes the program stored in the memory 603, it implements any step of the above-described method for automatically generating EMIR test cases.
[0046] The communication bus mentioned in the above electronic devices can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of representation, only one thick line is used in the diagram, but this does not indicate that there is only one bus or one type of bus.
[0047] The communication interface is used for communication between the aforementioned electronic devices and other devices.
[0048] The memory may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.
[0049] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.
[0050] The present invention also provides a computer-readable storage medium. A computer program is stored in the computer-readable storage medium, and when executed by a processor, the computer program implements any step of the above-described method for automatically generating EMIR test cases.
[0051] It should be noted that the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention.
[0052] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.
[0053] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings and the disclosure in carrying out the claimed invention. In the description of the invention, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.
[0054] The method provided in this invention can be applied to electronic devices. Specifically, the electronic device can be a desktop computer, a portable computer, a smart mobile terminal, a server, etc. No limitation is made herein; any electronic device that can implement this invention falls within the protection scope of this invention.
[0055] For the embodiments of the device / electronic device / storage medium, since they are basically similar to the method embodiments, the description is relatively simple, and relevant parts can be referred to in the description of the method embodiments.
[0056] It should be noted that the device, electronic device, and storage medium in the embodiments of the present invention are respectively devices, electronic devices, and storage media that apply the above-described automated EMIR test case generation method. Therefore, all embodiments of the above-described automated EMIR test case generation method are applicable to the device, electronic device, and storage medium, and can achieve the same or similar beneficial effects.
[0057] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus (devices), or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects, all of which are collectively referred to herein as "modules" or "systems." Furthermore, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program code. The computer program may be stored / distributed in a suitable medium, provided with or as part of other hardware, or may take other forms of distribution, such as via the Internet or other wired or wireless telecommunications systems.
[0058] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (devices), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0059] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0060] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0061] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.
Claims
1. A method for automatically generating EMIR test cases, characterized in that, The method includes: Based on the pre-set parameter configuration file, the process information required for the layout is obtained; Based on the parameter configuration file, the geometric shapes of each component of the layout are obtained by geometrically abstracting each component of the layout. The coordinates of each component in the layout are obtained based on the geometry of each component, the parameter configuration file, and the process information. A script for drawing the layout is generated based on the coordinates of each component of the layout and executed to obtain a recorded layout file; The log file for this layout drawing is obtained from the layout file to generate EMIR test cases.
2. The method for automatically generating EMIR test cases according to claim 1, characterized in that, The process of obtaining the required process information for the layout based on a pre-set parameter configuration file includes: Based on the site in the parameter configuration file, obtain the height information from the preset physical library file; Based on the circuit units in the parameter configuration file, obtain the process information of the circuit units in the physical library file; Based on the bumps in the parameter configuration file, obtain the process information of the bumps in the physical library file; The required process information for the layout is obtained based on the height information, the process information of the circuit unit, and the process information of the bump.
3. The method for automatically generating EMIR test cases according to claim 2, characterized in that, The step of geometrically abstracting each component of the layout according to the parameter configuration file to obtain the geometric shape of each component of the layout includes: Based on the site in the parameter configuration file, the layout geometry is abstracted into multiple rectangular regions of the same shape to obtain the first geometric shape; The ports, wires, and bumps in the parameter configuration file are geometrically abstracted into rectangles to obtain the second geometric shape; The circuit units in the parameter configuration file are geometrically abstracted into a combination of multiple rectangles to obtain a third geometric shape; The geometry of each component of the layout is obtained based on the first geometry, the second geometry, and the third geometry.
4. The method for automatically generating EMIR test cases according to claim 3, characterized in that, The step of obtaining the coordinates of each component in the layout based on the geometry of each component, the parameter configuration file, and the process information includes: The layout height is calculated based on the first geometric shape and the height information; The coordinates of the circuit unit are obtained based on the third geometry, the height information, and the process information of the circuit unit; The coordinates of the conductor are obtained based on the process information of the circuit unit and the second geometry; The coordinates of the bump are obtained based on the process information of the circuit unit and the second geometry; The coordinates of the port are obtained based on the first geometry and the second geometry; The coordinates of each component in the layout are obtained based on the layout height, the coordinates of the circuit unit, the coordinates of the wire, the coordinates of the bump, and the coordinates of the port.
5. The method for automatically generating EMIR test cases according to claim 3, characterized in that, The step of obtaining the log file for this layout drawing based on the layout file includes: Based on the layout file, obtain the design rule check results and connectivity results of the layout drawn this time; The log file is obtained based on the results of the design rules check and the connectivity results.
6. An automated device for generating EMIR test cases, characterized in that, The device includes: The information acquisition module is used to obtain the process information required for the layout based on a pre-set parameter configuration file; The shape acquisition module is used to perform geometric abstraction on each component of the layout according to the parameter configuration file to obtain the geometric shape of each component of the layout; The coordinate acquisition module is used to obtain the coordinates of each component of the layout based on the geometry of each component, the parameter configuration file, and the process information. The layout file acquisition module is used to generate and execute a script for drawing the layout based on the coordinates of each component of the layout, thereby obtaining a recorded layout file; The test case generation module is used to obtain the log file of the current layout drawing based on the layout file, so as to generate EMIR test cases.
7. An electronic device, characterized in that, include: processor; Memory used to store processor-executable instructions; The processor is configured to execute the executable instructions to implement the method for automatically generating EMIR test cases as described in any one of claims 1 to 7.
8. A computer-readable storage medium having computer program instructions stored thereon, characterized in that, When the program instructions are executed by the processor, they implement the steps of the automated EMIR test case generation method as described in any one of claims 1 to 6.