Chip local layout comparison method, device, equipment and medium

Abstract

The invention relates to the technical field of chips, and discloses a chip local layout comparison method and device, equipment and a medium, and the method comprises the steps: determining that a reference circuit diagram is a specified circuit diagram matched with the local layout for comparison under the condition that the local layout is successfully matched with a port of the reference circuit diagram; determining a circuit segment matched with the local layout to be compared from the specified circuit diagram; performing netlist extraction on the local layout and the circuit segment to obtain a local netlist matched with the local layout and a reference netlist matched with the circuit segment; and comparing the local netlist with the reference netlist to obtain a comparison result for the local layout. According to the technical scheme, real-time verification in the chip design process can be achieved, potential errors in design can be found and corrected as early as possible, the design period is shortened, and cost is reduced.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a method, apparatus, device and medium for comparing partial layouts of chips. Background Technology

[0002] In today's semiconductor industry, chip design is becoming increasingly complex, and the traditional Layout Versus Schematic (LVS) process faces serious challenges because engineers can only perform conformance verification after the entire design is completed. This creates time bottlenecks and potential errors are discovered at the last stage, leading to extended design cycles and increased correction costs.

[0003] Therefore, how to achieve real-time verification in the chip design process, so as to discover and correct potential errors in the design as early as possible, thereby shortening the design cycle and reducing costs, is a technical problem that urgently needs to be solved. Summary of the Invention

[0004] This application provides a method, apparatus, device, and medium for comparing partial layouts of a chip, which achieves the technical effect of real-time verification in the chip design process.

[0005] To achieve the above objectives, the main technical solutions adopted in this application include: In a first aspect, embodiments of this application provide a chip partial layout comparison method, the method comprising: If the ports of the local layout and the reference circuit diagram are successfully matched, the reference circuit diagram is determined to be the designated circuit diagram that is adapted to the local layout for comparison. From the specified circuit diagram, determine the circuit segment that matches the local layout to be compared; Netlist extraction is performed on the local layout and the circuit segment respectively to obtain a local netlist that matches the local layout and a reference netlist that matches the circuit segment; The local netlist is compared with the reference netlist to obtain the comparison result for the local layout.

[0006] In one implementation, determining the circuit segment from the specified circuit diagram that matches the local layout to be compared includes: Based on the cell name mapping relationship between the partial layout and the specified circuit diagram, the layout cells of the partial layout and the circuit cells in the specified circuit diagram are matched to obtain matching pairs; Based on the pin mapping relationship between the local layout and the specified circuit diagram, each pin of the layout unit in the matching pair is verified against each pin of the corresponding circuit unit in order to determine the circuit segment that matches the local layout to be compared from the specified circuit diagram.

[0007] In one implementation, before matching the layout cells of the local layout with the circuit cells in the designated circuit diagram according to the cell name mapping relationship between the local layout and the designated circuit diagram to obtain a matching pair, the method further includes: Determine the target level corresponding to the local layout in the specified circuit diagram; Select the cell name mapping relationship in the specified circuit diagram that is at the same level as the target level; wherein, the same level indicates that the physical level of the local layout is consistent with the logical level of the specified circuit diagram.

[0008] In one implementation, the step of verifying each pin of the matched layout unit with each pin of the corresponding circuit unit to determine the circuit segment that matches the local layout to be compared from the specified circuit diagram includes: Identify the link where the matching map unit is located within the local map; Identify the associated units on the link; Each pin of any associated unit is verified against each pin of the corresponding circuit unit in the circuit segment to determine that the link verification is correct, and from the specified circuit diagram, a circuit segment that matches the local layout to be compared is determined.

[0009] In one implementation, verifying each pin of any associated unit with each pin of the corresponding circuit unit in the circuit segment to determine that the link verification is correct includes: If each pin of any associated unit successfully matches each pin of the corresponding circuit unit, then the link verification is confirmed to be correct. If the pins of all associated units fail to match the pins of the corresponding circuit units, a prompt message is generated to supplement the pin mapping relationship.

[0010] In one implementation, comparing the local netlist with the reference netlist to obtain a comparison result for the local layout includes: If a circuit element that is not present in the local netlist but is defined in the reference netlist is identified, the comparison result of the circuit element is confirmed as correct.

[0011] In one implementation, the comparison result of the local layout includes: the link comparison result of any link in the local layout; the link comparison result is: open circuit, short circuit, or correct; wherein, The open circuit indicates that there is a physical connection breakpoint in the corresponding link in the local layout, which causes the connected path corresponding to the link in the circuit segment to be unconducted. The short circuit indicates that there is an additional physical connection in the corresponding link of the local layout that is not defined by the circuit segment, resulting in unexpected signal conduction in the link. The correct representation indicates that the connection relationship and physical conduction state of the corresponding link in the local layout are completely consistent with those of the link in the circuit segment.

[0012] Secondly, embodiments of this application provide a chip partial layout comparison device, the device comprising: The circuit diagram determination unit is used to determine the reference circuit diagram as the designated circuit diagram for comparison when the ports of the local layout and the reference circuit diagram are successfully matched. A circuit segment determination unit is used to determine, from the specified circuit diagram, a circuit segment that is compatible with the local layout to be compared. The netlist extraction unit is used to extract netlists from the local layout and the circuit segment respectively, to obtain a local netlist that matches the local layout and a reference netlist that matches the circuit segment. The netlist comparison unit is used to compare the local netlist with the reference netlist to obtain the comparison result for the local layout.

[0013] Thirdly, embodiments of this application provide a computer device, including: The system includes a memory and a processor, which are interconnected. The memory stores computer instructions, and the processor executes these computer instructions to perform the chip partial layout comparison method described above.

[0014] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer instructions, which are used to cause a computer to execute the chip partial layout comparison method described above.

[0015] The technical solutions provided by one or more embodiments of this application, by quickly locking the circuit segments corresponding to a local layout before the overall layout is completed, break the limitation of traditional LVS full circuit completion verification, allowing verification to start in real time with the design progress; extracting netlists only for the implemented local layout and corresponding circuit segments avoids the waste of resources in full layout computation and establishes an accurate logical benchmark for comparison; by using the rule of defaulting to correct for unimplemented parts and strictly comparing for implemented parts, invalid interference is filtered out, allowing real defects such as open circuits and short circuits to be exposed through comparison results in the early stages of design. This process realizes design-and-verify, allowing engineers to correct errors as early as possible and avoid large-scale rework later, and directly shortening the overall chip design cycle by compressing verification waiting time, ultimately achieving the core goal of cost reduction and efficiency improvement. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 A flowchart illustrating a chip partial layout comparison method provided in this application embodiment; Figure 2 These are comparison example diagrams for different scenarios provided in the embodiments of this application; Figure 3 A flowchart of step S3 provided in the embodiments of this application; Figure 4 A flowchart of step S33 provided in an embodiment of this application; Figure 5 A block diagram of a chip partial layout comparison device provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] In today's semiconductor industry, chip design complexity is increasing daily, and traditional verification processes are facing unprecedented challenges. Layout Versus Schematic (LVS) requires engineers to perform conformance checks only after the entire design flow is complete. While this "completed understanding" ensures design consistency, it also creates a significant time bottleneck. During this process, any potential errors may be discovered in the final stages, leading not only to extended design cycles but also increased costs associated with correcting these errors.

[0020] As manufacturing processes evolve towards more advanced stages (such as 3nm and 2nm), chip complexity increases dramatically. The integration of hundreds of millions or even tens of billions of transistors means a significantly longer physical implementation cycle. At this scale, if deep-seated errors are discovered during LVS verification, the backtracking and modification work will involve multiple stages from placement and routing to logic synthesis. The cost of such rework increases exponentially, directly impacting the overall project schedule and budget control. Therefore, relying on verification only after the entire process is completed not only increases the concentrated exposure of design risks but may also lead the project into an uncontrollable situation.

[0021] More importantly, current verification processes often postpone all risks to the later stages of design. At this point, whether it's correcting component connection errors or adapting to parameter adjustments caused by process variations, a significant investment of manpower and time is required. As a result, design teams not only face technical challenges but also have to deal with decision-making errors caused by time pressure.

[0022] Therefore, how to achieve real-time verification in the chip design process, so as to discover and correct potential errors in the design as early as possible, thereby shortening the design cycle and reducing costs, is a technical problem that urgently needs to be solved.

[0023] According to an embodiment of this application, a chip partial layout comparison method embodiment is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0024] This embodiment provides a method for comparing partial chip layouts. Figure 1 A flowchart of a chip partial layout comparison method provided in this application embodiment is shown below. Figure 1 As shown, the process includes the following steps: Step S1: If the ports of the local layout and the reference circuit diagram are successfully matched, the reference circuit diagram is determined to be the designated circuit diagram that is adapted to the local layout for comparison.

[0025] Specifically, in the chip partial layout comparison process, port matching is the core prerequisite for establishing an adaptation relationship between the specified circuit diagram and the partial layout. In essence, it involves verifying the compatibility of the ports of the two to select a reference circuit diagram that can be used as a comparison benchmark, and finally determining the adapted reference circuit diagram as the specified circuit diagram for this comparison.

[0026] As the core interface for signal interaction between the local layout and the circuit diagram, the port's matching directly determines the validity of subsequent comparisons. Only when the ports match successfully is the reference circuit diagram confirmed as the designated circuit diagram adapted to the local layout, ensuring the logical consistency between the comparison benchmark and the verification object. Ports include type, signal transmission direction, etc. For example, if the local layout contains three ports: VDD, DIN, and DOUT, the reference circuit diagram must also contain three corresponding ports with the same function; the types of each port (such as power port, data input port, clock port, ground port, etc.) must correspond one-to-one; and the signal transmission direction (input, output, bidirectional) of each port must be consistent (e.g., if DIN is an input port in the local layout, the signal direction of the corresponding port in the reference circuit diagram must also be input).

[0027] If all the above port dimensions are successfully matched, it means that the signal interaction interface of the reference circuit diagram is fully compatible with the local layout, and its logic design benchmark can accurately reflect the physical connection relationship that the local layout should achieve. At this time, the reference circuit diagram is officially determined as the designated circuit diagram and serves as the sole benchmark for subsequent cell matching, pin verification, and netlist comparison. If any port dimension fails to match (e.g., inconsistent port types, opposite signal directions), the reference circuit diagram is determined to be incompatible with the local layout and will not be identified as the designated circuit diagram. At the same time, a prompt message is generated, requiring the supplementation of port matching conditions (e.g., improving the port mapping table, adjusting the port definition of the local layout, or replacing the appropriate reference circuit diagram).

[0028] Step S3: From the specified circuit diagram, determine the circuit segment that matches the local layout to be compared.

[0029] A partial layout represents a portion of the chip's physical implementation where the overall design is not yet complete. This is the object of verification in this embodiment and can correspond to any level of the chip circuit (such as the layout of a functional module or several key links). A circuit diagram is the chip's logic design schematic, containing the circuit's hierarchical structure, unit connection relationships, device characteristics, and pin definitions. It serves as the benchmark for verification.

[0030] It is understood that the specified circuit diagram in this application represents a circuit diagram of the complete circuit structure of the chip. A circuit segment refers to a part of the logic circuit corresponding to a local layout in the specified circuit diagram. It is not a complete chip circuit, but a logical subset that matches the physical function and connection relationship of the local layout one by one, and is used as a logical reference object for local verification.

[0031] Specifically, based on the pre-defined mapping relationship, first find the circuit diagram units corresponding to all layout units in the local layout; then verify the pin connection relationship of these layout units and lock the signal links corresponding to these layout units in the circuit diagram; extract these matching layout units and logic connection relationships from the overall circuit diagram to form an independent logical subset, that is, obtain the circuit segment corresponding to the local layout.

[0032] Step S5: Extract netlists from the local layout and circuit segments respectively to obtain a local netlist that matches the local layout and a reference netlist that matches the circuit segments.

[0033] Specifically, in order to perform verification, it is necessary to extract netlists from local layouts and circuit segments. The extraction method is the same as that of LVS, to obtain the corresponding netlists for subsequent comparison.

[0034] Step S7: Compare the local netlist with the reference netlist to obtain the comparison result for the local layout.

[0035] Specifically, comparing the local netlist with the reference netlist will output the comparison results of the local layout. The comparison results of the local layout include the link comparison results of any link in the local layout. The link comparison results can be categorized as: open circuit, short circuit, or correct.

[0036] Preferably, the comparison results of the local layout can be output in a user-preset data format. For example, a comparison report characterizing the comparison results of the local layout can be generated. That is, the comparison report combines the comparison results with physical information (such as metal layers and device locations) and logical information (connection relationships in the reference netlist) to output a standardized verification document, which serves as the input for subsequent parasitic extraction (RC Extraction). If the comparison results are correct, parasitic extraction can be performed on the implemented local layout to extract local parasitic parameters. If open / short circuit errors exist, the local layout must be corrected before parasitic extraction is performed to avoid generating invalid parasitic parameters based on an incorrect layout and to ensure the reliability of chip performance verification.

[0037] In an optional implementation, the local netlist is compared with a reference netlist to obtain a comparison result for the local layout, including: If a circuit element that is not found in the local netlist but is defined in the reference netlist is identified, the comparison result of the circuit element is confirmed as correct.

[0038] Specifically, due to traditional LVS rules, unimplemented circuit elements are judged as missing errors, causing the verification process to be interrupted and preventing early verification. However, the technical solution of this application supports verification of partial layouts, allowing skipping of incomplete parts and focusing on real problems in implemented partial layouts (such as open circuits, short circuits, and pin connection errors), thus improving verification efficiency. Specifically, the local netlist and reference netlist are traversed synchronously. First, the types, attributes, and connection relationships of common circuit elements (cells, devices) are compared to see if they are consistent. Circuit elements that exist only in the reference netlist but have no corresponding entries in the local netlist are identified; the layouts corresponding to these circuit elements are not yet completed. For these missing circuit elements, they are not judged as missing errors, but their comparison results are automatically marked as correct, and the comparison report indicates that the circuit element is not yet implemented in the local layout, defaulting to correct.

[0039] In an optional implementation, the comparison result of the local layout includes: the link comparison result of any link in the local layout; the link comparison result is: open circuit, short circuit, or correct; wherein, An open circuit indicates that there is a physical connection break in the corresponding link in the local layout, which causes the connected path corresponding to that link in the circuit segment to be unconducted; A short circuit indicates that there is an undefined additional physical connection in the corresponding link in the local layout, which causes the link to have unexpected signal conduction; The correct representation of the corresponding link in the local layout is completely consistent with the connection relationship and physical conduction state of the link in the circuit segment.

[0040] Specifically, the comparison results of a partial layout use links as the core verification unit. Essentially, it's a collection of verification results for all independent links within the partial layout, rather than a single judgment of the entire partial layout. In the physical implementation of chip design, a partial layout consists of several independent links. Each link is physically connected through metal layers to form a closed connected domain (e.g., device A is connected to device B through metal layer M1, and device B is connected to device C through metal layer M2; then A, B, and C constitute an independent link; if device B is not physically implemented, then A and C are two independent links respectively). Since the partial layout represents an incomplete physical implementation, the links it contains may be in different connection states (some links are physically implemented and correctly connected, some links have connection anomalies, and some links may only have partially implemented devices). Therefore, the comparison results must accurately reflect the true state of each link to provide engineers with a practical basis for debugging.

[0041] Based on this, the comparison results of the local layout explicitly include the link comparison results of each link in the local layout. That is, by verifying the consistency between the physical connection status of each link and the logical design baseline, a specific result is finally formed for each link. Designers can use this result to quickly locate abnormal links (such as "link 2 has an open circuit" or "link 5 has a short circuit"), rather than relying on the vague conclusion of "the local layout is correct / abnormal as a whole".

[0042] To better understand the comparison results, an explanation is provided below, in conjunction with a practical application scenario. Please refer to [link / reference needed]. Figure 2 Examples of comparison diagrams for different scenarios provided in the embodiments of this application. Figure 2 (a) in the diagram is the logical connection baseline of the reference netlist, representing the ideal connection relationship of the circuit (the red path in the diagram is the logically valid connection, and the two blue devices form a complete link through the red line). Figure 2 (b) to Figure 2 (f) in the middle are all in Figure 2 (a) is used as a reference to compare the consistency between the local netlist and the reference netlist. The comparison results are as follows: Figure 2 The comparison result of (b) is "correct". The unrealized connection (red path) belongs to the part of the local layout that is not yet completed, and is judged as correct by default. At the same time, each device has completed the anchor point matching with the corresponding element in the reference netlist (cell / pin / instance association successful). Therefore, the connection relationship of the realized part (no connection) is consistent with the logical assumption of the unrealized connection.

[0043] Figure 2 The comparison result of (c) is "open". In the partial layout, a pin of a device leads out a part of the red metal line segment. That is, the implemented metal line segment belongs to the "complete part" and needs to be compared with the connection relationship of the reference netlist. In the reference netlist, the line segment should completely connect the two devices, but in fact only a part of the line segment is led out and not closed. Therefore, it is judged as "open" (the connection of the implemented part is incomplete).

[0044] Figure 2 The comparison result of (d) is "open". The lead segments of both devices belong to the "implemented part", but the segments are not closed to form a complete path, which is inconsistent with the logic of "the segments connect the two devices" in the reference netlist. Therefore, it is determined to be "open".

[0045] Figure 2 The comparison result (e) is "correct". The implemented red connection only covers a single device. The part that is not connected to another device belongs to the "part not yet completed" and is judged as correct by default. At the same time, both devices are successfully associated with the reference netlist and there are no connection errors in the implemented part.

[0046] Figure 2 The comparison result of (f) is "short". The extra ring connection in the local layout belongs to "unexpected implemented part". There is no such connection in the reference netlist, so it is judged as "short" (the extra physical connection causes logically unexpected conduction).

[0047] This embodiment provides a chip partial layout comparison method that can quickly locate the circuit segment corresponding to the partial layout even before the overall layout is completed. This breaks the limitation of traditional LVS verification after the entire circuit is completed, allowing verification to start in real time along with the design progress. Only the implemented partial layout and corresponding circuit segment are extracted from the netlist, avoiding the waste of resources in full-layout computation and establishing a precise logical benchmark for comparison. By using the rule of assuming the unimplemented parts are correct and strictly comparing the implemented parts, invalid interference is filtered out, allowing real defects such as open circuits and short circuits to be exposed through reports in the early stages of design. This process achieves design-and-verify, enabling engineers to correct errors as early as possible and avoid large-scale rework later. It also directly shortens the overall chip design cycle by reducing verification waiting time, ultimately achieving the core goal of cost reduction and efficiency improvement.

[0048] Figure 3 The flowchart for step S3 provided in the embodiments of this application may include the following steps: Step S31: Based on the cell name mapping relationship between the local layout and the specified circuit diagram, match the layout cells of the local layout with the circuit cells in the specified circuit diagram to obtain matching pairs.

[0049] Specifically, the cell name mapping record records the correspondence between layout cell names and schematic cell names. Based on the cell name mapping, a matching operation is performed on the layout cells of the local layout and the schematic cells of the schematic. Cell combinations that satisfy the condition that the cell names of the schematic and the local layout are consistent, or that provide a clear description of the cell name correspondence, and that also satisfy the condition that the instance names are consistent, or that provide a clear description of the instance name correspondence, are formed into matching pairs.

[0050] For example, the unit name includes the functional unit name and the instance name. If the layout unit name and the circuit diagram unit name are exactly the same (e.g., both are AND_GATE), they can be matched automatically without additional configuration. If the two names are different (e.g., the layout unit is called AND_LAY and the circuit diagram unit is called AND_SCH), the corresponding relationship must be explicitly written in the unit name mapping table (AND_LAY→AND_SCH), and the matching is completed by querying the unit name mapping relationship. If there is neither a match with the same name nor a corresponding unit name mapping relationship, the matching will fail directly, the unit cannot form a matching pair, and subsequent verification cannot be carried out.

[0051] Instance names represent the specific location of the same functional unit in the design and are crucial for avoiding confusion between units of the same type. For example, if there are two AND gate units (both of type AND_GATE) in the circuit diagram, with instance names AND1 and AND2 respectively, used for different signal paths, the corresponding two AND gate physical units in the layout must also have instance names AND1 and AND2, or the correspondence must be clearly defined through a mapping table. If the instance name of the unit in the layout is exactly the same as the instance name of the corresponding unit in the circuit diagram, it can be accurately bound to the specific circuit location; if the instance names are inconsistent, the instance name mapping relationship needs to be supplemented to clarify the correspondence between different instance names; if the instance names do not match and there is no mapping relationship, an invalid match will occur where the functional type is correct but the specific location is wrong, such as matching the physical unit of AND1 in the layout diagram to AND2 in the circuit diagram, subsequent verification cannot be carried out.

[0052] Therefore, the final selected matching pairs are layout cell-diagram cell combinations that simultaneously meet the requirements of cell name and instance name matching. Cells that do not meet either matching requirement will be marked as "unmatched cells," and a prompt message will be generated to help engineers complete the mapping relationship.

[0053] In an optional implementation, before matching the layout cells of the local layout with the circuit cells in the specified circuit diagram according to the cell name mapping relationship between the local layout and the specified circuit diagram to obtain a matching pair, the method further includes: Determine the target level of the local layout in the specified circuit diagram; Select the cell name mapping relationship in the specified circuit diagram that is at the same level as the target level; where the same level indicates that the physical level of the local layout is consistent with the logical level of the specified circuit diagram.

[0054] Specifically, due to the hierarchical architecture of chip circuit design, the functions and naming rules of units at different levels may differ. Therefore, it is necessary to first anchor the logic level of the local layout, and then achieve accurate matching through the unit name mapping relationship of the corresponding level to avoid verification errors caused by cross-level matching. In view of this, this embodiment first needs to determine the target level corresponding to the local layout in the specified circuit diagram, that is, first clarify which target level of the overall circuit diagram the local layout to be verified belongs to (such as the power module level under the top layer); then, according to the determined target level, retrieve the unit name mapping relationship specific to the target level, and use the unit name mapping relationship to match the names of the local layout units and the corresponding circuit diagram units of the target level. The successfully matched layout unit-circuit diagram unit pair is the matching pair.

[0055] Step S33: Based on the pin mapping relationship between the local layout and the specified circuit diagram, verify each pin of the matched layout unit and each pin of the corresponding circuit unit to determine the circuit segment that matches the local layout to be compared from the specified circuit diagram.

[0056] The pin mapping record records the correspondence between layout pins and corresponding schematic pins. Pins are physical ports used for signal interaction with other units; they are the access points for physical connections and have specific names and locations in the layout design or schematic diagram.

[0057] Specifically, the process involves determining whether the layout unit has explicitly defined pin names in the design; further, it determines whether these defined layout unit pins have established physical connections with the instance pins of the devices belonging to this unit within the layout; only when both conditions are met—that pins have defined names and that pins are physically connected to instance pins—are the pins of the layout unit valid, and the process proceeds to the next step of comparing them with the pins of the circuit unit; if either condition is not met, the process is directly marked as "invalid pin definition," the process is paused, and the engineer is prompted to correct the layout. If the names of all pins in the layout unit are exactly the same as those of the pins in the corresponding circuit unit (e.g., both are VDD, DIN), then the pin matching verification is successful. If the names are different, the specific device instance under this unit in the layout is verified with the device instance under the corresponding unit in the circuit diagram, based on the name of the device instance pin. If the two instance names are the same, or there is an instance name mapping relationship to support it, then the device instance can be determined to be successfully associated, and the association of this unit is considered valid, and the process can continue. If there are device instances that cannot be associated, then the mapping relationship (pin / instance name mapping) must be supplemented or the pin / instance name definition of the layout must be corrected.

[0058] This embodiment utilizes cell name mapping relationships to match layout cells in a local layout with circuit cells in a circuit diagram, enabling rapid determination of the correspondence between design elements. Pin mapping relationships are then used to accurately verify the pins in the matched pairs. Combining these two steps allows for the rapid matching of corresponding circuit segments for subsequent verification.

[0059] Figure 4 The flowchart for step S33 provided in the embodiments of this application may include the following steps: Step S331: Identify the link where the matching centering map unit is located within the local map.

[0060] A link is a physical set of connections consisting of devices and metal layer interconnections within a layout. It comprises devices and wiring that are interconnected via metal layers. Devices within a link can transmit signals through physical connections. Simply put, any two devices / units connected by a metal wire (including those connected via other devices) belong to the same link; devices / units without physical connections belong to different links.

[0061] Specifically, for target layout cells with generated matching pairs, their physical location and metal layer connection ports within the local layout are determined. Starting from the metal layer port of the target layout cell, the physical connections of the local layout are traversed in all directions, including other cells / devices directly connected to the metal port of the target layout cell, as well as cells / devices connected via metal lines or pins of other devices. To avoid duplicate link identification due to overly fine port splitting, if there is any physical metal layer connection path between two links, they are merged into one link; if there is no physical connection path between two links, they remain independent.

[0062] Step S333: Determine the associated units on the link.

[0063] Associated units represent all layout units within the same link. These layout units are physically connected via metal layers and belong to the same physical connectivity domain. The determination of associated units is to extend the verification scope from a single target layout unit to the entire signal link.

[0064] It should be noted that if there is only one independent unit in the link (without other connected units), the set of associated units is empty, and the link verification will be performed directly on the target layout unit in the future.

[0065] Step S335: Verify each pin of any associated unit against each pin of the corresponding circuit unit in the circuit segment to ensure that the link verification is correct, and determine the circuit segment that matches the local layout to be compared from the specified circuit diagram.

[0066] Specifically, the method for verifying each pin of any associated unit against each pin of the corresponding circuit unit is the same as described in steps S31 to S33. If the pin name of the associated unit is exactly the same as the pin name of the corresponding unit in the circuit diagram, then the pin verification of the associated unit is successful, indicating that the link is verified correctly. When the link is determined to be verified correctly, based on all validly bound units (target unit + associated unit) within the link, the corresponding logic units and their logical connections are extracted from the overall circuit diagram. This extracted logical subset is the circuit segment adapted to the current local layout.

[0067] In an optional implementation, each pin of any associated unit is checked against each pin of the corresponding circuit unit in the circuit segment to determine that the link check is correct, including: If each pin of any associated unit successfully matches each pin of the corresponding circuit unit, then the link verification is confirmed to be correct. If the pins of all associated units fail to match the pins of the corresponding circuit units, a prompt message is generated to supplement the pin mapping relationship.

[0068] Specifically, for each associated unit within the link, a pin verification process is executed sequentially. This checks whether the associated unit explicitly defines a pin name and whether the pin has physical connectivity with the pins of its internal device instances. Invalid pins are skipped, and the verification proceeds to the next associated unit. For valid pins, the name is compared with the corresponding circuit unit pin name. If the names match, the pin verification for that associated unit is successful, and the verification of other associated units in the current link is immediately terminated, determining the entire link to be verified correctly. If the names do not match, the pin verification for that associated unit fails, and the verification proceeds to the next associated unit, or a second-level judgment is triggered. All specific device instances (such as MOSFETs, resistors, capacitors, etc.) belonging to all associated units within the link are extracted. For each device instance, its name is compared with the name of the corresponding device instance in the circuit diagram. If the instance name matches, the device is successfully associated, and the entire link is immediately determined to be verified correctly. If all device instances within the link fail to associate, the entire link is determined to be mismatched, and supplementary mapping information is generated.

[0069] In other words, traditional LVS requires successful matching of all units and pins in the entire link before the netlist can be extracted, while this rule only requires success at any one node to allow passage. This means that in the early stages of chip design, even if most units in the link have not completed logical binding, as long as one unit / device is successfully matched, the entire link can be verified, and physical connection problems such as open circuits and short circuits can be detected in advance.

[0070] This embodiment accurately identifies multiple independent links containing layout units, focuses on related units within the link, and uses the successful verification of any related unit's pin as a criterion to determine if the link verification is correct. This breaks the limitation of traditional LVS requiring verification only after the entire process is completed, realizing real-time local verification at the link level during chip design. This process significantly lowers the early verification threshold, supporting a mode where verification of the entire link can be initiated once some units are completed. This allows design defects such as open circuits, short circuits, and incorrect pin connections to be detected and corrected in a timely manner during the early stages of development. At the same time, it improves verification effectiveness by accurately anchoring circuit segments, reduces the cost of ineffective troubleshooting, effectively shortens the overall chip design cycle, and reduces development costs.

[0071] Accordingly, please refer to Figure 5This is a block diagram of a chip partial layout comparison device provided in an embodiment of this application. The device includes: The circuit diagram determination unit 101 is used to determine the reference circuit diagram as the specified circuit diagram for comparison when the ports of the local layout and the reference circuit diagram are successfully matched. The circuit segment determination unit 103 is used to determine, from the specified circuit diagram, a circuit segment that is compatible with the local layout to be compared. The netlist extraction unit 105 is used to extract netlists from local layouts and circuit segments respectively, to obtain local netlists that match local layouts and reference netlists that match circuit segments. The netlist comparison unit 107 is used to compare the local netlist with the reference netlist to obtain the comparison result for the local layout.

[0072] In some alternative implementations, the circuit segment determination unit 103 includes: Based on the cell name mapping relationship between the local layout and the specified circuit diagram, the layout cells of the local layout and the circuit cells in the specified circuit diagram are matched to obtain matching pairs; Based on the pin mapping relationship between the local layout and the specified circuit diagram, the pins of each layout unit in the matching pair are verified against the pins of the corresponding circuit unit in order to determine the circuit segment that matches the local layout to be compared from the specified circuit diagram.

[0073] In some alternative implementations, the circuit segment determination unit 103 includes: Determine the target level of the local layout in the specified circuit diagram; Select the cell name mapping relationship in the specified circuit diagram that is at the same level as the target level; where the same level indicates that the physical level of the local layout is consistent with the logical level of the specified circuit diagram.

[0074] In some alternative implementations, the circuit segment determination unit 103 includes: Identify the links where the matched centering map units are located within a local map; Identify the associated units on the link; Verify each pin of any associated unit against each pin of the corresponding circuit unit in the circuit segment to ensure that the link verification is correct, and determine the circuit segment that matches the local layout to be compared from the specified circuit diagram.

[0075] In some alternative implementations, the circuit segment determination unit 103 includes: If each pin of any associated unit successfully matches each pin of the corresponding circuit unit, then the link verification is confirmed to be correct. If the pins of all associated units fail to match the pins of the corresponding circuit units, a prompt message is generated to supplement the pin mapping relationship.

[0076] In some optional implementations, the netlist comparison unit 107 includes: If a circuit element that is not found in the local netlist but is defined in the reference netlist is identified, the comparison result of the circuit element is confirmed as correct.

[0077] In some optional implementations, the comparison results of the local layout include: the link comparison result of any link in the local layout; the link comparison result is: open circuit, short circuit, or correct; wherein, An open circuit indicates that there is a physical connection break in the corresponding link in the local layout, which causes the connected path corresponding to that link in the circuit segment to be unconducted; A short circuit indicates that there is an undefined additional physical connection in the corresponding link in the local layout, which causes the link to have unexpected signal conduction; The correct representation of the corresponding link in the local layout is completely consistent with the connection relationship and physical conduction state of the link in the circuit segment.

[0078] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0079] In this embodiment, a chip partial layout comparison device is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0080] Please see Figure 6 , Figure 6 This application provides a schematic diagram of the structure of a computer device, as shown in the embodiment of the present application. Figure 6As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 6 Take a processor 10 as an example.

[0081] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0082] The memory 20 stores instructions executable by at least one processor 10 to cause the at least one processor 10 to perform the method shown in the above embodiments.

[0083] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0084] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0085] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0086] This application also provides a computer-readable storage medium. The methods described in this application can be implemented in hardware or firmware, or implemented as recordable on a storage medium, or implemented as computer code downloaded over a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and subsequently stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the methods shown in the above embodiments are implemented.

[0087] The apparatus and units described in the above embodiments can be implemented by a computer chip or physical entity, or by a product with a certain function. A typical implementation device is a computer. Specifically, a computer can be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smartphone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or any combination of these devices.

[0088] For ease of description, the above devices are described separately by function as various units. Of course, in implementing this application, the functions of each unit can be implemented in one or more software and / or hardware.

[0089] Those skilled in the art will understand that the embodiments of this application can be provided as methods or apparatus. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0090] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatuses, and devices according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0091] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0092] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0093] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0094] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the apparatus embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0095] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

[0096] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method for comparing partial layouts of a chip, characterized in that, The method includes: If the ports of the local layout and the reference circuit diagram are successfully matched, the reference circuit diagram is determined to be the designated circuit diagram that is adapted to the local layout for comparison. From the specified circuit diagram, determine the circuit segment that matches the local layout to be compared; Netlist extraction is performed on the local layout and the circuit segment respectively to obtain a local netlist that matches the local layout and a reference netlist that matches the circuit segment; The local netlist is compared with the reference netlist to obtain the comparison result for the local layout.

2. The method according to claim 1, characterized in that, The step of determining the circuit segment that matches the local layout to be compared from the specified circuit diagram includes: Based on the cell name mapping relationship between the partial layout and the specified circuit diagram, the layout cells of the partial layout and the circuit cells in the specified circuit diagram are matched to obtain matching pairs; Based on the pin mapping relationship between the local layout and the specified circuit diagram, each pin of the layout unit in the matching pair is verified against each pin of the corresponding circuit unit in order to determine the circuit segment that matches the local layout to be compared from the specified circuit diagram.

3. The method according to claim 2, characterized in that, Before matching the layout cells of the local layout with the circuit cells in the specified circuit diagram according to the cell name mapping relationship between the local layout and the specified circuit diagram to obtain matching pairs, the method further includes: Determine the target level corresponding to the local layout in the specified circuit diagram; Select the cell name mapping relationship in the specified circuit diagram that is at the same level as the target level; wherein, the same level indicates that the physical level of the local layout is consistent with the logical level of the specified circuit diagram.

4. The method according to claim 2, characterized in that, The step of verifying each pin of the matched layout unit with each pin of the corresponding circuit unit to determine the circuit segment that matches the local layout to be compared from the specified circuit diagram includes: Identify the link where the matching map unit is located within the local map; Identify the associated units on the link; Each pin of any associated unit is verified against each pin of the corresponding circuit unit in the circuit segment to determine that the link verification is correct, and from the specified circuit diagram, a circuit segment that matches the local layout to be compared is determined.

5. The method according to claim 4, characterized in that, The step of verifying each pin of any associated unit with each pin of the corresponding circuit unit in the circuit segment to determine that the link verification is correct includes: If each pin of any associated unit successfully matches each pin of the corresponding circuit unit, then the link verification is confirmed to be correct. If the pins of all associated units fail to match the pins of the corresponding circuit units, a prompt message is generated to supplement the pin mapping relationship.

6. The method according to claim 1, characterized in that, The step of comparing the local netlist with the reference netlist to obtain the comparison result for the local layout includes: If a circuit element that is not present in the local netlist but is defined in the reference netlist is identified, the comparison result of the circuit element is confirmed as correct.

7. The method according to claim 1, characterized in that, The comparison results of the local layout include: the link comparison result of any link in the local layout; the link comparison result is: open circuit, short circuit, or correct; wherein, The open circuit indicates that there is a physical connection breakpoint in the corresponding link in the local layout, which causes the connected path corresponding to the link in the circuit segment to be unconducted. The short circuit indicates that there is an additional physical connection in the corresponding link of the local layout that is not defined by the circuit segment, resulting in unexpected signal conduction in the link. The correct representation indicates that the connection relationship and physical conduction state of the corresponding link in the local layout are completely consistent with those of the link in the circuit segment.

8. A chip partial layout comparison device, characterized in that, The device includes: The circuit diagram determination unit is used to determine the reference circuit diagram as the designated circuit diagram for comparison when the ports of the local layout and the reference circuit diagram are successfully matched. A circuit segment determination unit is used to determine, from the specified circuit diagram, a circuit segment that is compatible with the local layout to be compared. The netlist extraction unit is used to extract netlists from the local layout and the circuit segment respectively, to obtain a local netlist that matches the local layout and a reference netlist that matches the circuit segment. The netlist comparison unit is used to compare the local netlist with the reference netlist to obtain the comparison result for the local layout.

9. A computer device, characterized in that, include: A memory and a processor are interconnected, the memory stores computer instructions, and the processor executes the chip partial layout comparison method according to any one of claims 1 to 7 by executing the computer instructions.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to execute the chip partial layout comparison method according to any one of claims 1 to 7.

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