Memory device including block selection circuit

Abstract

A memory device includes: a first semiconductor layer including an elongated region, a first cell region, and a second cell region, the first cell region and the second cell region being disposed on both sides of the elongated region, respectively, in a first horizontal direction; and a second semiconductor layer vertically overlapping the first semiconductor layer and including a pass transistor circuit connected to the first cell region and the second cell region through a word line, a block selection circuit for providing a block selection signal to the pass transistor circuit, and a voltage switching circuit for switching the block selection signal to the pass transistor circuit. And a voltage switching circuit for transmitting an operating voltage to the through transistor circuit, where the voltage switching circuit may include a voltage switching region disposed in an elongated lower region of the second semiconductor layer, where the elongated lower region vertically overlaps the elongated region, and at least a portion of the block selection circuit may be disposed in the elongated lower region.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0164029, filed with the Korean Intellectual Property Office on November 18, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of this disclosure relate to a memory device including block select circuitry. Background Technology

[0004] A three-dimensional memory device with memory cells arranged in a three-dimensional manner has been proposed for use. The advantage of a three-dimensional memory device is that, by vertically stacking memory cells, a larger capacity can be achieved in the same area, thus providing high performance and excellent power efficiency. The memory device may include multiple memory blocks and a block selection circuit for selecting one of the multiple memory blocks. Summary of the Invention

[0005] Embodiments of this disclosure may provide a memory device capable of reducing size.

[0006] The purposes of the embodiments disclosed herein are not limited to those described herein, but rather other purposes not mentioned will be clearly understood by those skilled in the art from the following description.

[0007] Embodiments of this disclosure may provide a memory device, comprising: a first semiconductor layer including a slim area, a first cell area, and a second cell area, the first cell area and the second cell area being respectively disposed on both sides of the slim area along a first horizontal direction; and a second semiconductor layer vertically overlapping the first semiconductor layer, and comprising: a pass transistor circuit, a block select circuit, and a voltage switching circuit, the pass transistor circuit being connected to the first cell area and the second cell area via word lines, the block select circuit being used to provide a block select signal to the pass transistor circuit, and the voltage switching circuit being used to send an operating voltage to the pass transistor circuit, wherein the voltage switching circuit includes a voltage switching region disposed in an under-slim region of the second semiconductor layer, wherein the under-slim region vertically overlaps the slim area, and wherein at least a portion of the block select circuit is disposed in the under-slim region.

[0008] Embodiments of this disclosure may provide a memory device, comprising: a first semiconductor layer including a cell region and an elongated region arranged along a first horizontal direction; and a second semiconductor layer vertically overlapping the first semiconductor layer, and comprising: a transistor circuit, a block select circuit, and a voltage switching circuit, wherein the transistor circuit is connected to the cell region via word lines, the block select circuit is configured to provide a block select signal to the transistor circuit, and the voltage switching circuit sends an operating voltage to the transistor circuit, wherein the voltage switching circuit includes a voltage switching region disposed in the elongated lower region of the second semiconductor layer, wherein the elongated lower region vertically overlaps with the elongated region, and wherein at least a portion of the block select circuit is disposed in the elongated lower region.

[0009] According to embodiments of this disclosure, a memory device capable of improving layout utilization efficiency and reducing size can be provided.

[0010] The effects of the embodiments disclosed herein are not limited to those described above, but rather other effects not mentioned will be clearly understood by those skilled in the art based on the description of the claims. Attached Figure Description

[0011] This disclosure will be more fully understood from the detailed description and accompanying drawings provided below, which are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0012] Figure 1 This is a schematic block diagram of a memory device according to an embodiment of the present disclosure.

[0013] Figure 2 It is shown Figure 1 A block diagram of the line decoder.

[0014] Figure 3 This is a perspective view of a memory device according to an embodiment of the present disclosure.

[0015] Figure 4 and Figure 5 This is a schematic plan view illustrating the first under-cell region, the second under-cell region, and the elongated under-cell region of the first semiconductor layer according to an embodiment of the present disclosure. Detailed Implementation

[0016] In the following description, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description of examples or embodiments of the present disclosure, reference will be made to the accompanying drawings, in which specific examples or embodiments that may be implemented are illustrated by way of illustration, and in which reference numerals and symbols may be used to denote the same or similar components even if the same reference numerals and symbols are shown in different drawings. Further, in the following description of examples or embodiments of the invention, a detailed description of well-known functions and components incorporated herein will be omitted when it is determined that such a detailed description might obscure the subject matter of some embodiments of the invention. Terms such as “comprising,” “having,” “including,” “forming,” “consisting of,” “made of,” and “formed by” as used herein are generally intended to allow for the addition of additional components, unless explicitly indicated by the context. As used herein, the singular forms are intended to include the plural forms unless the context clearly indicates otherwise.

[0017] Terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be used herein to describe elements of the invention. Each of these terms is not used to define the nature, order, sequence, or number of elements, but only to distinguish the corresponding element from other elements.

[0018] When referring to the first element and the second element as "connected or joined," "in contact or overlapping," etc., it should be interpreted as meaning that not only can the first element be "directly connected or joined" or "directly in contact or overlapping" with the second element, but a third element can also be "inserted" between the first element and the second element, or the first element and the second element can be "connected or joined," "in contact or overlapping," etc., via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or joined," "in contact or overlapping," etc., and that are mutually connected or joined, "in contact or overlapping," etc.

[0019] When time-relative terms such as “after,” “following,” “next,” or “before” are used to describe a process or operation of an element or configuration, or to describe a flow or step in an operation, process, or manufacturing method, these terms may be used to describe a discontinuous or non-sequential process or operation unless used with the terms “directly” or “immediately after.”

[0020] Furthermore, when referring to any size, relative dimensions, etc., even without a specific description, the numerical values ​​or corresponding information of the component or feature (e.g., grade, range, etc.) should be taken into account, including tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). In addition, the term "can" fully encompasses all the meanings of the term "able to".

[0021] In the following, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0022] Figure 1 This is a schematic block diagram of a memory device according to an embodiment of the present disclosure.

[0023] Reference Figure 1 According to an embodiment of the present disclosure, the memory device 10 includes a memory cell array 100, a row decoder (e.g., X-DEC) 210, a page buffer circuit (e.g., PB circuit) 220, and peripheral circuits (e.g., PERI circuit) 230.

[0024] The memory cell array 100 may include a plurality of memory blocks BLK1 to BLKn. Each of the memory blocks BLK1 to BLKn may include a plurality of memory cells. The memory cells may be, for example, flash memory cells. Hereinafter, memory cells are described as NAND flash memory cells, but this disclosure is not limited thereto. Memory cells may also be resistive memory cells such as ReRAM, PRAM, or MRAM.

[0025] Storage blocks BLK1 to BLKn can be connected to the line decoder 210 via word lines WL. Storage blocks BLK1 to BLKn can be connected to the page buffer circuit 220 via multiple bit lines BL.

[0026] The row decoder 210 can select one of the multiple memory blocks BLK1-BLKn included in the memory cell array 100 in response to the row address X_A provided from the peripheral circuit 230. The row decoder 210 can transmit the operating voltage X_V provided from the peripheral circuit 230 to the word line WL of the selected memory block.

[0027] Page buffer circuit 220 can receive page buffer control signal PB_C from peripheral circuit 230, and can send and receive data signal DATA from peripheral circuit 230. Page buffer circuit 220 can control bit lines BL arranged in memory cell array 100 in response to page buffer control signal PB_C. For example, page buffer circuit 220 can detect data stored in memory cells of memory cell array 100 by detecting the signal of bit line BL of memory cell array 100 in response to page buffer control signal PB_C, and can send data signal DATA to peripheral circuit 230 according to the detected data. Page buffer circuit 220 can apply a signal to bit line BL according to the data signal DATA received from peripheral circuit 230 in response to page buffer control signal PB_C, and can write data to memory cells of memory cell array 100 accordingly. Page buffer circuit 220 can write data to memory cells connected to word lines activated by row decoder 210, or can read data from those memory cells.

[0028] Peripheral circuitry 230 can receive command signals CMD, address signals ADDR, and control signals CTRL from outside the memory device 10, and can send and receive data DATA with external devices such as a memory controller. Peripheral circuitry 230 can output signals for writing data to or reading data from the memory cell array 100, such as row address X_A and page buffer control signal PB_C, based on the command signals CMD, ADDR, and CTRL. Peripheral circuitry 230 can generate various voltages required by the memory device 10, including operating voltage X_V.

[0029] Figure 2 It is shown Figure 1 A block diagram of the line decoder.

[0030] Reference Figure 2 The line decoder 210 may include a block selection circuit 211, a global line decoder 212, and a transistor circuit 213.

[0031] Block selection circuit 211 may include multiple block switches BLKSW1 to BLKSWn, each corresponding to a plurality of memory blocks BLK1 to BLKn. Block switches BLKSW1 to BLKSWn can be connected to transistor circuit 213 via block selection signal line BLKWL. One of the multiple block switches BLKSW1 to BLKSWn can be selected in response to a row address received from peripheral circuitry. The selected block switch can output an active block selection signal to the corresponding block selection signal line BLKWL.

[0032] The global line decoder 212 can be connected to the transistor circuit 213 via the global word line GWL. The global line decoder 212 can receive operating voltages from external circuitry and output operating voltages to the global word line GWL in response to control signals received from the external circuitry. The global line decoder 212 may include a plurality of switching elements that send operating voltages to the global word line GWL.

[0033] Transistor circuit 213 may include multiple pass transistor groups PTG1 to PTGn corresponding to multiple memory blocks BLK1 to BLKn. Each pass transistor group may include multiple pass transistors connected to the word line WL of the corresponding memory block.

[0034] Transistor groups PTG1 to PTGn can be connected to block switches BLKSW1 to BLKSWn respectively via block signal line BLKWL. The gate electrodes of the transistors included in each transistor group can be connected to a common block signal line. If a block select signal provided to the transistor group via the block signal line is activated, the transistors included in the transistor group can be turned on.

[0035] Each of the transistor groups PTG1 to PTGn can be connected to the global line decoder 212 via the global word line GWL. The global word line GWL can be connected to multiple transistor groups PTG1 to PTGn. That is, multiple transistor groups PTG1 to PTGn can share the global word line GWL.

[0036] One of the transistor groups selected from the transistor groups PTG1 to PTGn—that is, the transistor group that receives the block selection signal activated by the block selection circuit 211—can be sent from the operating voltage provided by the global row line decoder 212 to the corresponding memory block via the word line WL.

[0037] In the following text and in the accompanying drawings, two directions parallel to the upper surface of the first semiconductor layer or the second semiconductor layer are defined as the first horizontal direction HD1 and the second horizontal direction HD2, respectively, and the direction extending vertically from the upper surface of the first semiconductor layer and the second semiconductor layer is defined as the vertical direction VD. For example, the first horizontal direction HD1 can be the extension direction of word lines or the arrangement direction of bit lines, while the second horizontal direction HD2 can be the extension direction of bit lines or the arrangement direction of word lines. The first horizontal direction HD1 and the second horizontal direction HD2 can intersect each other perpendicularly.

[0038] Figure 3 This is a perspective view of a memory device according to an embodiment of the present disclosure.

[0039] Reference Figure 3The semiconductor device 10 may include a first semiconductor layer L1 and a second semiconductor layer L2. The first semiconductor layer L1 and the second semiconductor layer L2 may overlap each other in the vertical direction VD. For example, the first semiconductor layer L1 may be disposed below the second semiconductor layer L2 in the vertical direction VD.

[0040] exist Figure 3 In the diagram, the first semiconductor layer L1 and the second semiconductor layer L2 may be spaced apart from each other in the vertical direction VD, but this exploded view is for illustrative purposes only, and it should be understood that the upper surface of the first semiconductor layer L1 and the lower surface of the second semiconductor layer L2 may be in contact with each other.

[0041] In an embodiment, the line decoder ( Figure 1 210), page buffer circuit ( Figure 1 220) and peripheral circuits ( Figure 1 (230) can be disposed on the first semiconductor layer L1, and the memory cell array ( Figure 1 (110) can be set on the second semiconductor layer L2.

[0042] In the second semiconductor layer L2, multiple word lines can extend along a first horizontal direction HD1, and multiple bit lines can extend along a second horizontal direction HD2. In an embodiment, the second semiconductor layer L2 may include a first cell region CA1, a second cell region CA2, and an elongated region SA. The first cell region CA1 and the second cell region CA2 may be respectively disposed on both sides of the elongated region SA along the first horizontal direction HD1.

[0043] Although not shown, multiple word lines can be stacked vertically along the direction VD in the first cell region CA1, the second cell region CA2, and the elongated region SA to form a stacked structure. In the first cell region CA1 and the second cell region CA2, multiple semiconductor pillars can penetrate the stacked structure vertically along the direction VD. The word lines can be combined with the semiconductor pillars penetrating the stacked structure vertically along the direction VD to form a three-dimensional arrangement of memory cells. The second semiconductor layer L2 may include a first cell array arranged in the first cell region CA1 and a second cell array arranged in the second cell region CA2.

[0044] The first semiconductor layer L1 may include a substrate, as well as a line decoder, a page buffer circuit, and peripheral circuitry, which may be configured in the first semiconductor layer L1 by forming semiconductor elements such as transistors on the substrate and wiring connected to the semiconductor elements.

[0045] The first semiconductor layer L1 may include a first lower unit region UCR1 that overlaps with the first unit region CA1 along the vertical direction VD, a second lower unit region UCR2 that overlaps with the second unit region CA2 along the vertical direction VD, and an elongated lower region USR that overlaps with the elongated region SA along the vertical direction VD. The first lower unit region UCR1 and the second lower unit region UCR2 may be arranged on both sides of the elongated lower region USR along the first horizontal direction HD1, respectively.

[0046] The memory device 10 may have a POC (Peri-Over-Cell) structure. That is, the first semiconductor layer L1 and the second semiconductor layer L2 may be fabricated on different wafers and then bonded to each other using wafer bonding technology.

[0047] Figure 4 This is a schematic plan view illustrating the first cell lower region, the second cell lower region, and the elongated lower region of the first semiconductor layer according to an embodiment of the present disclosure.

[0048] Reference Figure 4 The elongated lower region USR may include a first transistor region XR1, a second transistor region XR2, a voltage switching region GR1, and a first switching region BR1.

[0049] The first unit's lower region UCR1 may include a first peripheral circuit region PR1, a first page buffer region YR1, and a second switch region BR2. The second unit's lower region UCR2 may include a second peripheral circuit region PR2, a second page buffer region YR2, and a third switch region BR3.

[0050] The first transistor region XR1 and the second transistor region XR2 can be regions containing transistor circuits, and the transistor circuits can be divided into two parts and disposed in the first transistor region XR1 and the second transistor region XR2. The first transistor region XR1 and the second transistor region XR2 can be connected to multiple word lines (not shown) respectively. Figure 3 The first unit region CA1 and the second unit region CA2.

[0051] The first page buffer region YR1 and the second page buffer region YR2 can be the regions where the page buffer circuit is located, and the page buffer circuit can be divided into two parts and set in the first page buffer region YR1 and the second page buffer region YR2. The first page buffer region YR1 and the second page buffer region YR2 can be connected to multiple bit lines (not shown) respectively. Figure 3 The first unit region CA1 and the second unit region CA2.

[0052] The voltage switching region GR1 may be a region that sets at least a portion of the voltage switching circuitry included in the global line decoder, and at least a portion of the voltage switching circuitry may be connected to the first pass transistor region XR1 and the second pass transistor region XR2 via global word lines.

[0053] The first switch area BR1, the second switch area BR2, and the third switch area BR3 can be areas where a block selection circuit is set, and the block selection circuit can be connected to the first pass transistor area XR1 and the second pass transistor area XR2 via block signal lines.

[0054] In the elongated lower region USR, the first through transistor region XR1 and the second through transistor region XR2 can be configured to be spaced apart from each other along the first horizontal direction HD1, and the voltage switching region GR1 can be configured between the first through transistor region XR1 and the second through transistor region XR2.

[0055] The dimension of the voltage switching region GR1 along the second horizontal direction HD2 is smaller than the dimension of the elongated lower region USR along the second horizontal direction HD2. Due to the dimensional difference between the dimension of the elongated lower region USR along the second horizontal direction HD2 and the dimension of the voltage switching region GR1 along the second horizontal direction HD2, an open area or empty area may be generated in the elongated lower region USR. According to an embodiment of this disclosure, a first switching region BR1 can be provided to fill the open area of ​​the elongated lower region USR.

[0056] The first switching region BR1 can be arranged between the first through transistor region XR1 and the second through transistor region XR2, and can overlap with the voltage switching region GR1 along the second horizontal direction HD2.

[0057] The second switch region BR2 and the third switch region BR3 can be configured to overlap with the first page buffer region YR1 and the second page buffer region YR2 along the first horizontal direction HD1. The second switch region BR2 can be located between the elongated lower region USR and the first page buffer region YR1, and the third switch region BR3 can be located between the elongated lower region USR and the second page buffer region YR2.

[0058] The first peripheral circuit region PR1 can be the remaining region in the lower region UCR1 of the first unit, excluding the second switch region BR2 and the first page buffer region YR1. The first peripheral circuit region PR1 can include a first region A1 that overlaps with the second switch region BR2 along the second horizontal direction HD2.

[0059] The second peripheral circuit region PR2 can be the remaining region in the lower region UCR2 of the second unit, excluding the third switch region BR3 and the second page buffer region YR2. The second peripheral circuit region PR2 can include a second region A2 that overlaps with the third switch region BR3 along the second horizontal direction HD2. The first peripheral circuit region PR1 and the second peripheral circuit region PR2 can overlap with the first switch region BR1 along the first horizontal direction HD1.

[0060] Because the first switching region BR1 is located in the elongated lower region USR, rather than in the first cell lower region UCR1 or the second cell lower region UCR2, the area available for arranging peripheral circuitry in the first cell lower region UCR1 and the second cell lower region UCR2 can be increased. In the cell lower regions, the ratio of the peripheral circuitry area and the page buffer area to the block switching region is also increased, potentially allowing for a reduction in the size of the memory device.

[0061] Figure 5 This is a schematic plan view illustrating the first cell lower region, the second cell lower region, and the elongated lower region of the first semiconductor layer according to an embodiment of the present disclosure.

[0062] Reference Figure 5 The elongated lower region USR may include a first transistor region XR1', a second transistor region XR2', a third transistor region XR3', a first switching region BR1', a second switching region BR2', and a voltage switching region GR1.

[0063] The first unit's lower region UCR1 may include a first peripheral circuit region PR1, a first page buffer region YR1, and a third switch region BR3'. The second unit's lower region UCR2 may include a second peripheral circuit region PR2, a second page buffer region YR2, and a fourth switch region BR4'.

[0064] The first transistor region XR1', the second transistor region XR2', and the third transistor region XR3' can be regions where transistor circuits are set, and the transistor circuits can be divided into three parts or groups and set in the first transistor region XR1', the second transistor region XR2', and the third transistor region XR3'.

[0065] The voltage switching region GR1 can overlap with the first transistor region XR1' along the second horizontal direction HD2. The second transistor region XR2' and the third transistor region XR3' are respectively disposed on both sides of the voltage switching region GR1 along the first horizontal direction HD1.

[0066] The first switch area BR1', the second switch area BR2', the third switch area BR3', and the fourth switch area BR4' can be areas where block selection circuits are set, and the block selection circuits can be divided into four parts or groups and set in the first switch area BR1', the second switch area BR2', the third switch area BR3', and the fourth switch area BR4'.

[0067] The first switching region BR1' and the second switching region BR2' can be respectively disposed on both sides of the first through-transistor region XR1' along the first horizontal direction HD1. The first switching region BR1' can be located between the first through-transistor region XR1' and the lower region UCR1 of the first unit. The second switching region BR2' can be located between the first through-transistor region XR1' and the lower region UCR2 of the second unit.

[0068] The first switching region BR1' can overlap with the second transistor region XR2' along the second horizontal direction HD2. The second switching region BR2' can overlap with the third transistor region XR3' along the second horizontal direction HD2.

[0069] The third switching region BR3' can be disposed between the second through transistor region XR2' and the first page buffer region YR1. The fourth switching region BR4' can be disposed between the third through transistor region XR3' and the second page buffer region YR2. The third switching region BR3' and the fourth switching region BR4' can overlap with the second through transistor region XR2' and the third through transistor region XR3' along the first horizontal direction HD1. The third switching region BR3' and the fourth switching region BR4' can overlap with the first page buffer region YR1 and the second page buffer region YR2 along the first horizontal direction HD1.

[0070] The first peripheral circuit region PR1 can be the remaining region in the lower region UCR1 of the first unit, excluding the third switch region BR3' and the first page buffer region YR1. The second peripheral circuit region PR2 can be the remaining region in the lower region UCR2 of the second unit, excluding the fourth switch region BR4' and the second page buffer region YR2.

[0071] The first peripheral circuit region PR1 may include a first region A1' that overlaps with the third switch region BR3' along the second horizontal direction HD2. The second peripheral circuit region PR2 may include a second region A2' that overlaps with the fourth switch region BR4' along the second horizontal direction HD2.

[0072] The first peripheral circuit region PR1 and the second peripheral circuit region PR2 can overlap with the first switch region BR1' and the second switch region BR2' along the first horizontal direction HD1. Because the first switch region BR1' and the second switch region BR2' are located in the elongated lower region USR, rather than in the first cell lower region UCR1 or the second cell lower region UCR2, the area available for arranging peripheral circuits in the first cell lower region UCR1 and the second cell lower region UCR2 can be increased, which can help reduce the size of the memory device.

[0073] Figure 3 A second semiconductor layer L2 comprising two cell regions and one elongated region is shown, but embodiments of this disclosure are not limited thereto. The second semiconductor layer may include at least one cell region and at least one elongated region.

[0074] Figure 4 and Figure 5 The block selection circuit is shown disposed in the elongated lower region, the first unit lower region, and the second unit lower region, but embodiments of this disclosure are not limited thereto. The entire block selection circuit may be disposed in the elongated lower region.

[0075] The above description and accompanying drawings are provided for illustrative purposes only, illustrating the technical concepts of this disclosure. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art without departing from the spirit and scope of this disclosure. Furthermore, since the embodiments disclosed herein are not intended to limit the technical concepts of this disclosure but rather to explain them, the scope of the technical concepts of this disclosure is not limited by these embodiments. The scope of protection of this disclosure should be interpreted by the claims, and all technical concepts within the equivalent scope should be interpreted as included within the scope of the rights of this disclosure.

Claims

1. A memory device, comprising: The first semiconductor layer includes an elongated region, a first unit region, and a second unit region, wherein the first unit region and the second unit region are respectively arranged on both sides of the elongated region along a first horizontal direction. as well as A second semiconductor layer, vertically overlapping the first semiconductor layer, includes a transistor circuit, a block select circuit, and a voltage switching circuit. The transistor circuit is connected to the first cell region and the second cell region via word lines. The block select circuit provides a block select signal to the transistor circuit, and the voltage switching circuit sends an operating voltage to the transistor circuit. The voltage switching circuit includes a voltage switching region disposed in the narrow lower region of the second semiconductor layer. Wherein, the elongated lower region vertically overlaps with the elongated region, and At least a portion of the block selection circuit is disposed in the narrow lower region.

2. The memory device according to claim 1, wherein, The block selection circuit includes a first switch area, a second switch area, and a third switch area. The first switch area is located in the narrow lower region. The second switching region is located in the lower region of the first unit of the second semiconductor layer, which vertically overlaps with the first unit region. The third switching region is located in the lower region of the second unit that vertically overlaps with the second unit region of the second semiconductor layer.

3. The memory device according to claim 2, wherein, The transistor circuit includes a first transistor region and a second transistor region disposed in the narrow lower region. The first transistor region and the second transistor region are spaced apart from each other along the first horizontal direction. The voltage switching region and the first switch region are disposed between the first through transistor region and the second through transistor region.

4. The memory device according to claim 3, wherein, The voltage switch region overlaps with the first switch region along a second horizontal direction perpendicular to the first horizontal direction.

5. The memory device according to claim 2, wherein, The second semiconductor layer further includes peripheral circuitry. The peripheral circuit includes a first peripheral circuit region disposed in the lower region of the first unit and a second peripheral circuit region disposed in the lower region of the second unit. The first peripheral circuit region and the second peripheral circuit region overlap with the first switch region along the first horizontal direction.

6. The memory device according to claim 5, wherein, The first peripheral circuit region includes a first region that overlaps with the second switch region along the second horizontal direction. The second peripheral circuit region includes a second region that overlaps with the third switch region along the second horizontal direction. Wherein, the second horizontal direction is perpendicular to the first horizontal direction.

7. The memory device according to claim 2, wherein, The second semiconductor layer further includes a page buffer circuit. The page buffer circuit includes a first page buffer region disposed in the lower region of the first unit and a second page buffer region disposed in the lower region of the second unit. The second switch area and the third switch area overlap with the first page buffer area and the second page buffer area along the first horizontal direction.

8. The memory device according to claim 1, wherein, The transistor circuit includes a first transistor region, a second transistor region, and a third transistor region disposed in the narrow lower region. Wherein, the first transistor region overlaps with the voltage switch region along a second horizontal direction perpendicular to the first horizontal direction. The second transistor region and the third transistor region are respectively disposed on both sides of the voltage switch region along the first horizontal direction.

9. The memory device according to claim 8, wherein, The block selection circuit includes a first switch area, a second switch area, a third switch area, and a fourth switch area. The first switching region and the second switching region are respectively disposed on both sides of the first transistor region along the first horizontal direction in the elongated lower region. The third switching region is located in the lower region of the first unit that vertically overlaps with the first unit region of the second semiconductor layer. The fourth switching region is located in the lower region of the second unit that vertically overlaps with the second unit region of the second semiconductor layer.

10. The memory device according to claim 9, wherein, The second semiconductor layer further includes peripheral circuitry. The peripheral circuit includes a first peripheral circuit region disposed in the lower region of the first unit and a second peripheral circuit region disposed in the lower region of the second unit. The first peripheral circuit region and the second peripheral circuit region overlap with the first switch region and the second switch region along the first horizontal direction.

11. The memory device according to claim 10, wherein, The first peripheral circuit region includes a first region that overlaps with the third switch region along the second horizontal direction. The second peripheral circuit region includes a second region that overlaps with the fourth switch region along the second horizontal direction.

12. The memory device according to claim 9, wherein, The second semiconductor layer further includes a page buffer circuit. The page buffer circuit includes a first page buffer region disposed in the lower region of the first unit and a second page buffer region disposed in the lower region of the second unit. The third and fourth switch regions overlap with the first and second page buffer regions along the first horizontal direction.

13. A memory device, comprising: A first semiconductor layer includes a cell region and an elongated region, wherein the cell region and the elongated region are arranged along a first horizontal direction; as well as A second semiconductor layer, vertically overlapping the first semiconductor layer, includes a transistor circuit, a block select circuit, and a voltage switching circuit. The transistor circuit is connected to the cell region via word lines. The block select circuit provides a block select signal to the transistor circuit, and the voltage switching circuit sends an operating voltage to the transistor circuit. The voltage switching circuit includes a voltage switching region disposed in the narrow lower region of the second semiconductor layer. Wherein, the elongated lower region vertically overlaps with the elongated region, and At least a portion of the block selection circuit is disposed in the narrow lower region.

14. The memory device according to claim 13, wherein, The block selection circuit includes a first switching area and a second switching area. The first switch area is located in the narrow lower region. The second switching region is disposed in the lower region of the unit of the second semiconductor layer, and the lower region of the unit overlaps vertically with the unit region.

15. The memory device according to claim 14, wherein, The voltage switching region overlaps with the first switching region along the second horizontal direction. Wherein, the second horizontal direction is perpendicular to the first horizontal direction.

16. The memory device according to claim 15, wherein, The transistor circuit includes a first transistor region and a second transistor region disposed in the narrow lower region. The voltage switching region and the first switch region are disposed between the first through transistor region and the second through transistor region.

17. The memory device according to claim 14, wherein, The second semiconductor layer further includes peripheral circuitry. The peripheral circuit includes a peripheral circuit region disposed in the lower region of the unit. The peripheral circuit area overlaps with the first switch area along the first horizontal direction.

18. The memory device according to claim 17, wherein, The peripheral circuit region includes a first region that overlaps with the second switch region along the second horizontal direction. Wherein, the second horizontal direction is perpendicular to the first horizontal direction.

19. The memory device according to claim 13, wherein, The transistor circuit includes a first transistor region, a second transistor region, and a third transistor region disposed in the narrow lower region. The voltage switching region overlaps with the first transistor region along a second horizontal direction perpendicular to the first horizontal direction. The second transistor region and the third transistor region are respectively disposed on both sides of the voltage switch region along the first horizontal direction.

20. The memory device according to claim 19, wherein, The block selection circuit includes a first switch area, a second switch area, and a third switch area. The first switching region and the second switching region are respectively disposed on both sides of the first transistor region along the first horizontal direction in the elongated lower region. The third switching region is located in the lower region of the second semiconductor layer that vertically overlaps with the unit region.

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