PWM buffer circuit and circuit output control method
By constructing a dual control path using dual diodes and resistors, the problem of the buffer erroneously outputting PWM signals when not in operation is solved, ensuring system safety and reliability, reducing costs, and enhancing anti-interference capabilities.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NINGBO ANXIN CNC TECH
- Filing Date
- 2025-12-22
- Publication Date
- 2026-05-19
AI Technical Summary
In existing power electronic conversion systems, buffers may unexpectedly output PWM signals when not in operation, causing power devices to turn on erroneously and leading to serious consequences such as overcurrent and short circuits. In particular, there is a lack of reliability guarantee when the system is powered on for initialization, reset, or when PWM is disabled.
A dual control path is constructed using dual diodes and resistors to ensure that the buffer enable input is reliably pulled high when the system is powered on, reset, or PWM is disabled. Hardware circuit design prevents erroneous outputs, and capacitors are used to filter out high-frequency noise and stabilize power supply.
It enables reliable shutdown of the buffer under various conditions, improves system safety, reduces material costs, and enhances the system's anti-interference capability and reliability.
Smart Images
Figure CN122068752A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of PWM control technology, and in particular to a PWM buffer circuit and a circuit output control method. Background Technology
[0002] In power electronic conversion systems, pulse-width modulation (PWM) signals are widely used to drive power switching devices (such as IGBTs and MOSFETs) to achieve efficient control of motors, power supplies, or inverters. To enhance the driving capability of the PWM signal, a buffer circuit is typically placed between the controller and the power device. However, in practical applications, if the buffer unexpectedly outputs a PWM signal when not in operation, it may cause the power device to turn on erroneously, leading to serious consequences such as overcurrent, short circuits, or even device burnout. Especially during system power-on initialization, reset, or when the PWM signal is disabled, the I / O pins of the main control unit may be in a high-impedance or uncertain state, causing the enable pin level of the buffer to become uncontrolled, resulting in the buffer outputting an incorrect PWM waveform. Therefore, ensuring that the buffer is always in the off state under various non-operating conditions is a critical issue for ensuring the safe operation of the system. While some existing technologies implement buffer enable control through software control or a single hardware path, they still cannot provide sufficient reliability guarantees in the face of main control unit failure, program crashes, or reset anomalies. Summary of the Invention
[0003] The technical problem to be solved by the present invention is to provide a PWM buffer circuit and a circuit output control method, which ensures that the buffer is reliably shut down in various states such as system power-on, reset and PWM disabled through hardware circuit design, thereby improving system safety.
[0004] The technical solution adopted by this invention to solve the above-mentioned technical problems is as follows: a PWM buffer circuit, including a first resistor, a second resistor, two diodes, a third resistor, a capacitor, and a buffer. One end of the first resistor is connected to the reset control signal output terminal of the external reset chip used to generate the reset control signal, and the other end of the first resistor is connected to the first anode of the dual diode. One end of the second resistor is connected to the PWM wave enable signal output terminal of the external main control chip used to generate the PWM wave enable signal, and the other end of the second resistor is connected to the second anode of the dual diode. The cathode of the dual diode, the enable input terminal of the buffer, and one end of the third resistor are connected. One end of the capacitor and the power input terminal of the buffer are connected to the external power supply. The other end of the third resistor and the other end of the capacitor are respectively grounded.
[0005] Compared with the prior art, the advantages of this invention are that it constructs a dual control path for the enable input of the buffer by using dual diodes, a first resistor, and a second resistor. This path involves the reset control signal sent by the external reset chip through the reset control signal output terminal and the PWM enable signal sent by the external main control chip through the PWM enable signal output terminal. The gating characteristics of the dual diodes ensure that the enable input of the buffer can be reliably pulled high when the system is powered on, reset, or PWM is disabled, thereby forcing the output of the buffer to be in a high-impedance state and avoiding erroneous outputs caused by floating or malfunctioning pins of the external main control chip. Furthermore, the dual diode design can save PCB area, thereby reducing bill of materials costs and improving component consistency. The capacitor provides transient current to the buffer, filters out high-frequency noise, stabilizes the power supply voltage, and prevents system instability or malfunction.
[0006] Furthermore, the model number of the buffer is U74ACT244G-ULA-R.
[0007] A circuit output control method for a PWM buffer circuit includes the following steps: Step 1: When the external reset chip starts system initialization, the external reset chip sends a high-level reset control signal to the first anode of the dual diodes through the reset control signal output terminal, so that the buffer is in a disabled state, and the external reset chip starts the system reset process. Step 2: After the external reset chip completes the system reset, the reset control signal sent by the external reset chip through the reset control signal output terminal turns to a low level, and the external main control chip sends a high-level PWM wave enable signal to the second anode of the dual diode through the PWM wave enable signal output terminal, so that the buffer is in the disabled state. Step 3: When it is necessary to enter the normal working state, the PWM wave enable signal sent by the external main control chip through the PWM wave enable signal output terminal turns to a low level, the external reset chip sends a low level reset control signal to the first anode of the dual diode through the reset control signal output terminal, the enable input terminal of the buffer is grounded through the third resistor, the buffer enters the enabled state, and the external main control chip continuously outputs the PWM control signal to the subsequent power drive circuit through the buffer. Step 4: When it is necessary to actively disable the buffer output PWM control signal to the subsequent power drive circuit, the external main control chip sends a high-level PWM wave enable signal to the second anode of the dual diodes through the PWM wave enable signal output terminal, thus disabling the buffer. By coordinating the levels of the reset control signal and the PWM wave enable signal, dynamic management of the buffer enable terminal is achieved. During key stages such as system initialization, reset completion, normal operation, and active buffer shutdown, the enable terminal level can be automatically controlled through the hardware path to ensure that the buffer outputs the PWM control signal only in the allowed state. In addition, under normal operation, the external main control chip periodically sends a normal operation signal to the external reset chip. If the external main control chip malfunctions due to a program abnormality and does not receive the normal operation signal, the external reset chip sends a high-level reset control signal to the first anode of the dual diodes through the reset control signal output terminal RST, thus disabling the buffer and reliably shutting it down, thereby cutting off the abnormal PWM control signal output. This method requires no software intervention, responds quickly, and covers the entire working cycle, significantly improving the system's anti-interference capability and reliability. Attached Figure Description
[0008] Figure 1 This is a schematic diagram of the overall circuit of the present invention; Figure 2 This is a schematic diagram of the overall process of the present invention. Detailed Implementation
[0009] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.
[0010] like Figure 1 As shown, a PWM buffer circuit includes a first resistor R1, a second resistor R2, two diodes D1, a third resistor R3, a capacitor C1, and a buffer U1. One end of the first resistor R1 is connected to the reset control signal output terminal RST on the external reset chip, which is used to generate the reset control signal. The other end of the first resistor R1 is connected to the first anode of the dual diode D1. One end of the second resistor R2 is connected to the PWM wave enable signal output terminal PWM_EN on the external main control chip, which is used to generate the PWM wave enable signal. The other end of the second resistor R2 is connected to the second anode of the dual diode D1. The cathode of the dual diode D1, the enable input terminal OE of the buffer U1, and one end of the third resistor R3 are connected. One end of the capacitor C1 and the power input terminal of the buffer U1 are connected to the external power supply P_PWR_5V. The other end of the third resistor R3 and the other end of the capacitor C1 are respectively grounded.
[0011] The core of this circuit lies in the reliable control of the enable input terminal OE of buffer U1 to ensure that it is always in an disabled state during system power-on, reset, and PWM disable phases. Specifically, when the external main control chip is not running normally or the PWM output is disabled, the output terminal of buffer U1 should remain in a high impedance state to prevent any PWM signal from being output to the subsequent power drive circuit, thus ensuring the safety and stability of the system operation.
[0012] In this embodiment, the model number of buffer U1 is U74ACT244G-ULA-R.
[0013] like Figure 2 As shown, a circuit output control method for a PWM buffer circuit includes the following steps: Step 1: When the external reset chip starts system initialization, the main control chip has not yet completed the startup process. The external reset chip sends a high-level reset control signal to the first anode of the dual diode D1 through the reset control signal output terminal RST, which conducts the path from the first anode to the cathode of the dual diode D1. Through the voltage divider network composed of the first resistor R1 and the third resistor R3, the voltage of the enable input terminal OE of the buffer U1 is maintained at a high level, so that the buffer U1 is in the disabled state, and the external reset chip starts the system reset process. Step 2: After the external reset chip completes the system reset, the reset control signal sent by the external reset chip through the reset control signal output terminal RST turns low, the path from the first anode to the cathode of the dual diode D1 is cut off, and the external main control chip sends a high-level PWM wave enable signal to the second anode of the dual diode D1 through the PWM wave enable signal output terminal PWM_EN, thus turning on the path from the second anode to the cathode of the dual diode D1, keeping the enable input terminal OE of the buffer U1 at a high level, so that the buffer U1 is in a disabled state, avoiding erroneous output during system initialization; Step 3: When it is necessary to enter the normal working state, the PWM enable signal sent by the external main control chip through the PWM_EN output terminal turns to a low level, pulling down the second anode voltage of the dual diode D1, so that the path from the second anode to the cathode of the dual diode D1 is not connected. The external reset chip sends a low-level reset control signal to the first anode of the dual diode through the reset control signal output terminal RST, so that the path from the first anode to the cathode of the dual diode D1 is not connected. The enable input terminal OE of the buffer U1 is grounded through the third resistor R3, so that the enable input terminal OE of the buffer U1 is low level, the buffer U1 enters the enabled state, and the external main control chip continuously outputs the PWM control signal to the subsequent power drive circuit through the buffer. Under normal operating conditions, the external main control chip periodically sends a normal operation signal to the external reset chip. If the external main control chip malfunctions due to a program error, the external reset chip will not receive the normal operation signal. The external reset chip will send a high-level reset control signal to the first anode of the dual diode D1 through the reset control signal output terminal RST, thus opening the path from the first anode to the cathode of the dual diode D1. After being divided and current-limited by the first resistor R1 and the third resistor R3, the signal is applied to the enable input terminal OE of the buffer U1, restoring the enable input terminal OE of the buffer U1 to a high level, thus putting the buffer U1 in a disabled state and reliably turning off the buffer U1, thereby cutting off the abnormal PWM control signal output. Step 4: When it is necessary to actively disable the output PWM control signal of the buffer to the subsequent power drive circuit, the external main control chip sends a high-level PWM wave enable signal to the second anode of the dual diode through the PWM wave enable signal output terminal PWM_EN, which conducts the path from the second anode to the cathode of the dual diode D1. The enable input terminal OE of the buffer U1 is kept at a high level through the voltage divider network formed by the second resistor R2 and the third resistor R3, so that the buffer is in the disabled state and effectively prevents the PWM control signal from continuing to be output. At this time, the reset control signal sent by the external reset chip through the reset control signal output terminal RST is still at a low level, which does not affect the current state selection of the enable input terminal OE of the buffer U1.
Claims
1. A PWM buffer circuit, characterized in that... It includes a first resistor, a second resistor, two diodes, a third resistor, a capacitor, and a buffer. One end of the first resistor is connected to the reset control signal output terminal of the external reset chip used to generate the reset control signal, and the other end of the first resistor is connected to the first anode of the dual diode. One end of the second resistor is connected to the PWM wave enable signal output terminal of the external main control chip used to generate the PWM wave enable signal, and the other end of the second resistor is connected to the second anode of the dual diode. The cathode of the dual diode, the enable input terminal of the buffer, and one end of the third resistor are connected. One end of the capacitor and the power input terminal of the buffer are connected to the external power supply. The other end of the third resistor and the other end of the capacitor are respectively grounded.
2. The PWM buffer circuit according to claim 1, characterized in that... The buffer in question is model U74ACT244G-ULA-R.
3. The circuit output control method for a PWM buffer circuit as described in claim 1, characterized in that... Includes the following steps: Step 1: When the external reset chip starts system initialization, the external reset chip sends a high-level reset control signal to the first anode of the dual diodes through the reset control signal output terminal, so that the buffer is in the disabled state, and the external reset chip starts the system reset process. Step 2: After the external reset chip completes the system reset, the reset control signal sent by the external reset chip through the reset control signal output terminal turns to a low level, and the external main control chip sends a high-level PWM wave enable signal to the second anode of the dual diode through the PWM wave enable signal output terminal, so that the buffer is in the disabled state. Step 3: When it is necessary to enter the normal working state, the PWM wave enable signal sent by the external main control chip through the PWM wave enable signal output terminal turns to a low level, the external reset chip sends a low level reset control signal to the first anode of the dual diode through the reset control signal output terminal, the enable input terminal of the buffer is grounded through the third resistor, the buffer enters the enabled state, and the external main control chip continuously outputs the PWM control signal to the subsequent power drive circuit through the buffer. Step 4: When it is necessary to actively disable the output PWM control signal of the buffer to the subsequent power drive circuit, the external main control chip sends a high-level PWM wave enable signal to the second anode of the dual diode through the PWM wave enable signal output terminal, so that the buffer is in the disabled state.