Multi-level energy storage networking inverter and inversion adjustment method

Abstract

The invention relates to the technical field of power detection management, in particular to a multi-level energy storage networking inverter and an inversion adjustment method. The main circuit module controls the charging and discharging paths of the energy storage unit group, the flying capacitor unit, the clamping diode unit and the switching tube unit and provides direct current to 13-level alternating current for conversion, and a signal enters the control circuit module; the control circuit module comprises a sampling receiving unit and an adjusting output unit; the sampling receiving unit obtains a signal according to the main circuit module and provides adjustable current and voltage values to the adjusting output module; and the adjustment output module provides error adjustment, generates a current given value, compares and adjusts to generate a modulation signal, and outputs 13-level sine waves. According to the scheme, the structure is compact, high economical efficiency is achieved, engineering is easy, and high-level output can be achieved without an additional booster circuit; fourteen-mode accurate control is combined with sine pulse width modulation, so that the harmonic content of an output waveform is low and is close to an ideal sine wave, and the dependence on a filter is reduced.

Description

Technical Field

[0001] This invention relates to the field of inverter technology, and in particular to a multi-level energy storage grid inverter and an inverter regulation method. Background Technology

[0002] Current mainstream technologies in the energy storage inverter field include multi-level topologies such as cascaded H-bridges, neutral point clamping, flying capacitors, and modular multilevel converters. These technologies achieve higher voltage output and harmonic suppression through multi-stage series connection, clamping diodes, or flying capacitor balancing. However, these traditional solutions have significant shortcomings.

[0003] The aforementioned traditional solutions typically require a large number of power switching devices, clamping diodes, and balancing capacitors, resulting in a large system size, high cost, and significant heat dissipation challenges. Furthermore, the drive circuits and control logic are extremely complex. Secondly, traditional multilevel topologies have low voltage gain, and achieving high-level output requires a large number of modules connected in series or independent DC power supplies, which not only reduces efficiency but also increases system failure points and maintenance difficulty. Flying capacitor and NPC topologies require complex dynamic voltage balance control algorithms, placing extremely high demands on controller performance. Problems such as capacitor voltage drift and uneven switching stress can easily occur when there are sudden load changes or inconsistencies in energy storage units.

[0004] Therefore, there is a need for a thirteen-level energy storage grid inverter and its control method that can effectively optimize the topology, reduce the number of power devices and auxiliary components, achieve high-quality thirteen-level output, support modular expansion and fault bypass of energy storage units, achieve balanced charging and discharging of energy storage units, and significantly improve the system's economy, reliability and engineering applicability without overly complex voltage balancing algorithms, to meet the needs of the current environment. Summary of the Invention

[0005] Therefore, the technical problem to be solved by the present invention is that: traditional solutions are bulky, costly, difficult to dissipate heat, and complex to operate; the voltage gain is low, and a large number of modules are connected in series or independent DC power supplies, which not only reduces efficiency but also increases the system's failure points and maintenance difficulty; the dynamic voltage balance control algorithm has extremely high requirements for the controller's performance; and capacitor voltage drift is prone to occur when the load changes suddenly or the energy storage units are inconsistent.

[0006] The above-mentioned technical problems are solved by the following technical solution: This invention proposes a multi-level energy storage grid-connected inverter, which includes, The main circuit module controls the charging and discharging paths of the energy storage unit group, flying capacitor unit, clamping diode unit and switching transistor unit, and provides DC to thirteen-level AC conversion, with the signal entering the control circuit module; The control circuit module includes a sampling and receiving unit and an adjustment and output unit; The sampling and receiving unit acquires signals from the main circuit module and provides adjustable current and voltage values ​​to the regulating output module. The adjustment output module receives the signal from the sampling receiving unit to provide error adjustment, generates a current setpoint, compares and adjusts to generate a modulation signal, and outputs a thirteen-level sine wave.

[0007] In a preferred embodiment of the multi-level energy storage grid inverter described in this invention: The energy storage unit group is connected to the flying capacitor unit and the clamping diode unit. The flying capacitor unit and the clamping diode unit are respectively connected in series with the capacitor group and the diode group. The flying capacitor unit and the clamping diode unit are connected to the switching transistor unit, and the switching transistor group is symmetrically distributed in the upper and lower bridge arms within the switching transistor unit.

[0008] In a preferred embodiment of the multi-level energy storage grid inverter described in this invention: The sampling receiving unit includes a current sampling circuit and a voltage sampling circuit; The sampling and receiving unit is connected to the phase comparator. The error detector receives the signal from the sampling and receiving unit and inputs it to the microprocessor to generate a modulation signal. This signal then passes through the PR controller, limiter, and sinusoidal pulse width modulation unit before entering the drive circuit unit.

[0009] An inverter regulation method includes the aforementioned multi-level energy storage grid inverter, and, The sampling and conditioning control circuit module detects the output voltage Vo and the sampling current. Error adjustment involves comparing Vo with the reference phase θref, and then adjusting the current setpoint via an error converter, microprocessor, and PR controller. The limiter generates a modulation signal, which is converted into PWM by the sinusoidal pulse width modulation unit. The PWM is then driven by the driving circuit unit to turn the switching transistor unit on and off, generating fourteen modes in a row and outputting a thirteen-level sine wave.

[0010] In a preferred embodiment of the inverter regulation method described in this invention: In the process of generating mode 1~2 by sinusoidal pulse width modulation; S1, S5, S9, and S11 in the switching transistor unit are turned on, the clamping diode unit is turned off, and the remaining switching transistors in the switching transistor unit are turned off. The DC input voltage source 2Vin charges and discharges the flying capacitor unit. Capacitors C1-C4 are not connected to the output path, and the output voltage Vo=0. The signal corresponding to the output voltage Vo is finally processed by the sinusoidal pulse width modulation unit to generate the positive half-cycle mode 2; S2, S5, S9, and S11 in the switching transistor unit are turned on, the clamping diode unit is turned off, and the remaining switching transistors in the switching transistor unit are turned off. The equivalent circuit is connected to the corresponding path, and the output voltage Vo = Vin. The signal corresponding to the output voltage Vo is finally passed through the sinusoidal pulse width modulation unit to generate mode 3.

[0011] In a preferred embodiment of the inverter regulation method described in this invention: In the sinusoidal pulse width modulation generation mode 3~4 process; S5, S9, and S11 in the switching transistor unit and D2 in the clamping diode unit are turned on, while the remaining switching transistors and diodes are turned off. The equivalent circuit is connected to the corresponding path, and the output voltage Vo = 2Vin. The signal corresponding to the output voltage Vo is finally passed through the sinusoidal pulse width modulation unit to generate mode 4. S2 and S9 in the switching transistor unit and D4 and D6 in the clamping diode unit are turned on, while the remaining switching transistors and diodes are turned off. The equivalent circuit is connected to the corresponding path, and the output voltage Vo = 3Vin. The signal corresponding to the output voltage Vo is finally passed through the sinusoidal pulse width modulation unit to generate mode 5.

[0012] In a preferred embodiment of the inverter regulation method described in this invention: In the process of generating mode 5-6 by sinusoidal pulse width modulation; In the switching transistor unit S9 and in the clamping diode unit (13) D2, D4 and D6 are turned on, while the other switching transistors and diodes are turned off; The equivalent circuit is connected to the corresponding path, and the output voltage Vo = 4Vin. The signal corresponding to the output voltage Vo is finally passed through the sinusoidal pulse width modulation unit to generate mode 6. S7 and S9 in the switching transistor unit and D2 and D6 in the clamping diode unit are turned on, while the remaining switching transistors and diodes are turned off. The equivalent circuit is connected to the corresponding path, and the output voltage Vo = 5Vin. The signal corresponding to the output voltage Vo is finally passed through the sinusoidal pulse width modulation unit to generate mode 7.

[0013] In a preferred embodiment of the inverter regulation method described in this invention: In the sinusoidal pulse width modulation generation mode 7~8 process; S5 and S9 in the switching transistor unit and D2 and D6 in the clamping diode unit are turned on, while the remaining switching transistors and diodes are turned off. The output voltage Vo = 6Vin. The signal corresponding to the output voltage Vo is finally passed through the sinusoidal pulse width modulation unit to generate mode 8. Within the switching transistor unit, S4, S8, S10, and S12 are turned on, while the remaining switching transistors and diodes are turned off. When the equivalent circuit is connected to the corresponding path, the output voltage Vo = 0. The signal corresponding to the output voltage Vo is finally used by the sinusoidal pulse width modulation unit to generate mode 9.

[0014] In a preferred embodiment of the inverter regulation method described in this invention: In the sinusoidal pulse width modulation generation mode 9~11 process; Within the switching transistor unit, S3, S8, S10, and S12 are in the conducting state, while the remaining switching transistors and diodes are cut off; The equivalent circuit is connected to the corresponding path, and the output voltage Vo = -Vin. The signal corresponding to the output voltage Vo is finally passed through the sinusoidal pulse width modulation unit to generate mode 10. In the switching transistor unit, S8, S10, and S12, and in the clamping diode unit, D1 is in the conducting state, while the remaining switching transistors and diodes are cut off. The equivalent circuit is connected to the corresponding path, and the output voltage Vo = -2Vin. The signal corresponding to the output voltage Vo is finally passed through the sinusoidal pulse width modulation unit to generate mode 11. S3 and S10 in the switching transistor unit and D3 and D5 in the clamping diode unit are in the conducting state, while the other switching transistors and diodes are cut off. The equivalent circuit is connected to the corresponding path, and the output voltage Vo = -3Vin. The signal corresponding to the output voltage Vo is finally passed through the sinusoidal pulse width modulation unit to generate mode 12.

[0015] In a preferred embodiment of the inverter regulation method described in this invention: In the process of generating modes 12~14 using sinusoidal pulse width modulation; S10 in the switching transistor unit and D1, D3, and D5 in the clamping diode unit are in the conducting state, while the remaining switching transistors and diodes are cut off. The equivalent circuit is connected to the corresponding path, and the load output voltage Vo = -4Vin. The signal corresponding to the output voltage Vo is finally passed through the sinusoidal pulse width modulation unit to generate mode 13. S6 and S10 in the switching transistor unit and D1 and D5 in the clamping diode unit are in the conducting state, while the other switching transistors and diodes are cut off. The equivalent circuit is connected to the corresponding path, the load output voltage Vo = -5Vin, and the signal corresponding to the output voltage Vo is finally used by the sinusoidal pulse width modulation unit to generate mode 14. S8 and S10 in the switching transistor unit and D1 and D5 in the clamping diode unit are in the conducting state, while the remaining switching transistors and diodes are cut off. When the equivalent circuit is connected to the corresponding path, the load output voltage Vo = -6Vin. The signal corresponding to the output voltage Vo is finally reversed to a negative level by the sinusoidal pulse width modulation unit, thus completing the fourteen-mode cycle.

[0016] The beneficial effects of this invention are as follows: the small number of components and compact structure of this solution bring high economy and ease of engineering, and high-level digital output can be achieved without additional boost circuits; the fourteen-mode precise control combined with sinusoidal pulse width modulation makes the output waveform have low harmonic content and close to the ideal sine wave, reducing the dependence on filters; it supports equalization management and fault bypass of energy storage units, improving system life and reliability, and is suitable for application scenarios that require high voltage quality, low harmonics and high reliability, such as large-capacity energy storage grid construction and distributed new energy grid connection. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings of the embodiments of the present invention will be briefly described below. Obviously, the drawings described below only relate to some embodiments of the present invention and are not intended to limit the present invention.

[0018] Figure 1 The connection framework diagram of the multi-level energy storage grid inverter in this invention is shown.

[0019] Figure 2 The schematic diagram of the voltage sampling circuit of the multi-level energy storage grid inverter in this invention is shown.

[0020] Figure 3 The schematic diagram of the current sampling circuit of the multi-level energy storage grid inverter in this invention is shown.

[0021] Figure 4 The schematic diagram of the drive circuit unit of the multi-level energy storage grid inverter in this invention is shown.

[0022] Figure 5 The equivalent circuit diagram of mode 1 of the inverter regulation method in the multi-level energy storage grid inverter of the present invention is shown.

[0023] Figure 6 The equivalent circuit diagram of mode 2 of the inverter regulation method in the multi-level energy storage grid inverter of the present invention is shown.

[0024] Figure 7 The equivalent circuit diagram of mode 3 of the inverter regulation method in the multi-level energy storage grid inverter of the present invention is shown.

[0025] Figure 8 The equivalent circuit diagram of mode 4 of the inverter regulation method in the multi-level energy storage grid inverter of the present invention is shown.

[0026] Figure 9 The equivalent circuit diagram of mode 5 of the inverter regulation method in the multi-level energy storage grid inverter of the present invention is shown.

[0027] Figure 10The diagram shows the equivalent circuit diagram of mode 6 of the inverter regulation method in the multi-level energy storage grid inverter of the present invention.

[0028] Figure 11 The equivalent circuit diagram of mode 7 of the inverter regulation method in the multi-level energy storage grid inverter of the present invention is shown.

[0029] Figure 12 The equivalent circuit diagram of mode 8 of the inverter regulation method in the multi-level energy storage grid inverter of the present invention is shown.

[0030] Figure 13 The equivalent circuit diagram of mode 9 of the inverter regulation method in the multi-level energy storage grid inverter of the present invention is shown.

[0031] Figure 14 The equivalent circuit diagram of mode 10 of the inverter regulation method in the multi-level energy storage grid inverter of the present invention is shown.

[0032] Figure 15 The equivalent circuit diagram of mode 11 of the inverter regulation method in the multi-level energy storage grid inverter of the present invention is shown.

[0033] Figure 16 The equivalent circuit diagram of mode 12 of the inverter regulation method in the multi-level energy storage grid inverter of the present invention is shown.

[0034] Figure 17 The equivalent circuit diagram of mode 13 of the inverter regulation method in the multi-level energy storage grid inverter of the present invention is shown.

[0035] Figure 18 The equivalent circuit diagram of mode 14 of the inverter regulation method in the multi-level energy storage grid inverter of the present invention is shown.

[0036] Figure 19 The diagram shows the cyclic waveform of the inverter regulation method in the multi-level energy storage grid inverter of this invention. Detailed Implementation

[0037] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0038] The terminology used in this invention refers to those general terms currently widely used in the art in consideration of the functionality of the invention; however, these terms may vary according to the intent of those skilled in the art, precedent, or new techniques. Furthermore, specific terms may be chosen independently, and in such cases, their detailed meanings will be described in the detailed description of the invention. Therefore, the terminology used in this specification should not be construed as simple names, but rather based on the meaning of the terms and the overall description of the invention.

[0039] Reference Figure 1This embodiment provides a multi-level energy storage grid inverter.

[0040] The main circuit module 1 is a symmetrical clamping type thirteen-level inverter main circuit. The entire main circuit module 1 is equipped with the energy storage unit group 11, the flying capacitor unit 12, the clamping diode unit 13 and the switching transistor unit 14 required for the entire process.

[0041] In this scheme, the switching transistor unit 14 includes twelve power switching transistors S1~S12, symmetrically distributed along the upper and lower bridge arms, and achieves thirteen-level voltage output through logic control. The flying capacitor unit 12 consists of four capacitors C1~C4, which can achieve high voltage gain through a series superposition strategy, eliminating the need for an additional boost circuit; the clamping diode unit 13 includes six fast recovery diodes D1~D6, used to provide a voltage clamping path during switching to prevent capacitor overvoltage.

[0042] The energy storage unit group 11 consists of multiple series-connected energy storage batteries and a parallel bypass switch unit, supporting modular expansion and fault bypass, and ensuring that the system maintains multi-level output when the energy storage unit fails. The main circuit module 1 controls and adjusts the charging and discharging paths of the energy storage unit group 11 and the flying capacitor unit 12, enabling the conversion of DC to thirteen-level AC, and the final generated output voltage signal Vo can enter the control circuit module 2.

[0043] The control circuit module 2 includes a sampling and receiving unit 21 and an adjustment and output unit 22. The sampling and receiving unit 21 collects the inverter output voltage Vo and current in real time, and converts them into a processable feedback signal through the adjustment and output unit 22. The adjustment and output unit 22 adjusts the voltage and current signals, and then generates a modulated signal through sinusoidal pulse width modulation, outputting the required thirteen-level sine wave.

[0044] As one embodiment provided, such as Figures 1-4 , The flying capacitor unit 12 and the clamping diode unit 13 are directly connected to the switching transistor unit 14. The switching transistor unit 14 consists of twelve power switching transistors S1~S12, symmetrically distributed along the upper and lower bridge arms, with six transistors per arm. Thirteen-level switching is achieved through complementary conduction logic. The two ends of the energy storage unit group 11 are connected to the positive and negative terminals of the switching transistor unit 14, forming a closed loop, supporting modular expansion and bypass switch control. One end of the load ZL is connected to the H-bridge to achieve AC output.

[0045] The sampling receiving unit 21 includes a current sampling circuit 211 and a voltage sampling circuit 212, which realizes real-time signal acquisition. The sampling receiving unit 21 is connected to a phase comparator 221 to lock the phase difference between the reference phase θref and the output voltage Vo.

[0046] Error converter 222 receives the signal input from sampling receiving unit 21 to microprocessor 223, performs error calculation and compensation, and generates an initial modulation signal. Subsequently, the signal undergoes proportional resonance adjustment through PR controller 224, which can eliminate steady-state error and improve grid-connected current tracking accuracy. In addition, limiter 225 limits the amplitude to prevent overmodulation. Finally, the signal enters sinusoidal pulse width modulation unit 226 for conversion, generating multiple PWM signals, which are then introduced into drive circuit unit 227 to control the on / off state of switching transistor unit 14.

[0047] The main circuit module 1 controls the switching transistor unit 14 to adjust according to the output signal of the drive circuit unit 227, continuously switching the required on and off switches, and finally outputting a thirteen-level sine wave. This solution enhances the system's stability and response speed by optimizing the connection relationship and electrical control architecture.

[0048] As one embodiment provided, such as Figures 1-19 , The control circuit module 2 first samples and conditions the initial state of the main circuit module 1. First, the reference phase θref is set. The reference phase θref is used to directly compare the error with the output voltage Vo. The error detector 222 receives this signal and calculates the error value. The microprocessor 223 combines the voltage and current signals of the sampling receiving unit 21 to perform preliminary compensation and processing.

[0049] Subsequently, the PR controller 224 performs proportional resonance adjustment on the error signal to generate a current setpoint, thereby achieving steady-state error tracking of the grid-connected current, ensuring that the power factor is close to 1 and suppressing harmonics. The current setpoint is then compared with the sampled current given by the current sampling circuit 211, and the amplitude of the modulation wave is limited by the limiter 225 to prevent increased switching stress and output distortion caused by over-modulation, thus generating the final modulation signal.

[0050] The signal eventually enters the sinusoidal pulse width modulation unit 226 for conversion. Combined with the pre-stored state table of fourteen modes corresponding to the switch combination, the sinusoidal pulse width modulation unit 226 can modulate the signal into multiple PWM pulses, which are then sent to the drive circuit unit 227 to drive the switching transistor unit 14 to turn on and off, generating a new mode 1. This mode is then sampled and detected by the control circuit module 2. This process is repeated continuously, generating fourteen modes and outputting a thirteen-level sine wave.

[0051] Reference Figure 5In the sinusoidal pulse width modulation (SPWM) mode 1 generation process, S1, S5, S9, and S11 in the switching transistor unit 14 are turned on, the clamping diode unit 13 is turned off, and the remaining switching transistors are turned off. The DC input voltage source 2Vin charges and discharges the flying capacitor unit 12 through the path, but capacitors C1~C4 are not connected to the output path. The energy storage unit group 11 remains in a bypass state, and the equivalent circuit forms a zero-level path. The output voltage Vo=0. The signal corresponding to the output voltage Vo is finally used to generate mode 2 through the sinusoidal pulse width modulation unit 226.

[0052] Reference Figure 6 In the process of generating mode 2 by sinusoidal pulse width modulation, S2, S5, S9, and S11 in the switching transistor unit 14 are turned on, the clamping diode unit 13 is turned off, and the other switching transistors are turned off. At this time, the equivalent circuit DC input voltage source 2Vin provides the basic voltage gain, and the output voltage Vo=Vin, realizing the first positive level of the positive half-cycle. The signal corresponding to the output voltage Vo is finally used to generate mode 3 by the sinusoidal pulse width modulation unit 226.

[0053] Reference Figure 7 In the sinusoidal pulse width modulation generation mode 3 process, S5, S9, and S11 in the switching transistor unit 14 are turned on, D2 in the clamping diode unit 13 is turned on, and the remaining switching transistors and diodes are turned off. The equivalent circuit DC input voltage source 2Vin forms a clamp with D2 to ensure a smooth voltage transition. The output voltage Vo = 2Vin. The signal corresponding to the output voltage Vo is finally used by the sinusoidal pulse width modulation unit 226 to generate mode 4.

[0054] Reference Figure 8 In the sinusoidal pulse width modulation generation mode 4 process, S2 and S9 in the switching transistor unit 14 are turned on, D4 and D6 in the clamping diode unit 13 are turned on, and the remaining switching transistors and diodes are turned off; the equivalent circuit DC input voltage source 2Vin provides clamping protection through D4 and D6 to prevent overvoltage, and the output voltage Vo=3Vin. The signal corresponding to the output voltage Vo is finally used to generate mode 5 through the sinusoidal pulse width modulation unit 226.

[0055] Reference Figure 9 In the sinusoidal pulse width modulation generation mode 5 process, S9 in the switching transistor unit 14 is turned on, D2, D4, and D6 in the clamping diode unit 13 are turned on, and the remaining switching transistors and diodes are turned off; the equivalent circuit DC input voltage source 2Vin forms a balanced voltage division with the multi-stage clamping diodes, and the output voltage Vo=4Vin. The signal corresponding to the output voltage Vo is finally used to generate mode 6 by the sinusoidal pulse width modulation unit 226.

[0056] Reference Figure 10In the process of generating mode 6 by sinusoidal pulse width modulation, S7 and S9 in the switching transistor unit 14 are turned on, D2 and D6 in the clamping diode unit 13 are turned on, and the remaining switching transistors and diodes are turned off; the equivalent circuit output voltage Vo=5Vin, and the signal corresponding to the output voltage Vo is finally used to generate mode 7 by the sinusoidal pulse width modulation unit 226.

[0057] Reference Figure 11 In the sinusoidal pulse width modulation generation mode 7 process, S5 and S9 in the switching transistor unit 14 are turned on, D2 and D6 in the clamping diode unit 13 are turned on, and the remaining switching transistors and diodes are turned off; the equivalent circuit DC input voltage source 2Vin provides peak gain, and the output voltage Vo=6Vin, completing the step-by-step rise of the positive half-cycle level. The signal corresponding to the output voltage Vo is finally used by the sinusoidal pulse width modulation unit 226 to generate mode 8.

[0058] Reference Figure 12 In the process of generating mode 8 by sinusoidal pulse width modulation, S4, S8, S10, and S12 in the switching unit 14 are turned on, while the remaining switching tubes and diodes are turned off. The equivalent circuit is symmetrical to mode 1 and is reverse-conducted through the H-bridge module to form a zero-level path. The output voltage Vo = 0, and the negative half-cycle begins at this time. The signal corresponding to the output voltage Vo is finally used to generate mode 9 by the sinusoidal pulse width modulation unit 226.

[0059] Reference Figure 13 In the process of generating mode 9 by sinusoidal pulse width modulation, S3, S8, S10 and S12 in the switching unit 14 are turned on, while the other switching units and diodes are turned off; the equivalent circuit is put into the reverse path, and the output voltage Vo = -Vin; the signal corresponding to the output voltage Vo is finally used to generate mode 10 by the sinusoidal pulse width modulation unit 226.

[0060] Reference Figure 14 In the process of generating mode 10 by sinusoidal pulse width modulation, S8, S10, and S12 in the switching transistor unit 14 are turned on, D1 in the clamping diode unit 13 is turned on, and the remaining switching transistors and diodes are turned off; the equivalent circuit output voltage Vo = -2Vin, and the signal corresponding to the output voltage Vo is finally used to generate mode 11 by the sinusoidal pulse width modulation unit 226.

[0061] Reference Figure 15 In the process of generating mode 11 by sinusoidal pulse width modulation, S3 and S10 in the switching transistor unit 14 are turned on, D3 and D5 in the clamping diode unit 13 are turned on, and the remaining switching transistors and diodes are turned off; the equivalent circuit output voltage Vo = -3Vin; the signal corresponding to the output voltage Vo is finally used by the sinusoidal pulse width modulation unit 226 to generate mode 12.

[0062] Reference Figure 16In the process of generating mode 12 by sinusoidal pulse width modulation, S10 in the switching transistor unit 14 is turned on, D1, D3, and D5 in the clamping diode unit 13 are turned on, and the remaining switching transistors and diodes are turned off; the equivalent circuit has multi-stage clamping to ensure balance, and the output voltage Vo = -4Vin; the signal corresponding to the output voltage Vo is finally used by the sinusoidal pulse width modulation unit 226 to generate mode 13.

[0063] Reference Figure 17 In the process of generating mode 13 by sinusoidal pulse width modulation, S6 and S10 in the switching transistor unit 14 are turned on, D1 and D5 in the clamping diode unit 13 are turned on, and the remaining switching transistors and diodes are turned off; the equivalent circuit output voltage Vo = -5Vin; the signal corresponding to the output voltage Vo is finally used by the sinusoidal pulse width modulation unit 226 to generate mode 14.

[0064] Reference Figure 18 In the sinusoidal pulse width modulation generation mode 14 process, S8 and S10 in the switching transistor unit 14 are turned on, D1 and D5 in the clamping diode unit 13 are turned on, and the remaining switching transistors and diodes are turned off; the equivalent circuit completes the negative half-cycle level decreasing step by step, and the output voltage Vo = -6Vin. The signal corresponding to the output voltage Vo is finally reversed to achieve a negative level through the sinusoidal pulse width modulation unit 226, completing the fourteen-mode cycle.

[0065] After the above fourteen modes are generated, thirteen-level voltage waveforms of 0, ±Vin, ±2Vin, ±3Vin, ±4Vin, ±5Vin, and ±6Vin are obtained. The system can select the closest mode from the switch state table based on the instantaneous value of the reference voltage to achieve low harmonics and high efficiency output.

[0066] Finally, it should be noted that the methods and devices described in detail above are merely embodiments, and those skilled in the art can modify these embodiments in different ways as long as they do not depart from the scope of the present invention.

Claims

1. A multi-level energy storage grid-connected inverter, characterized in that: include, The main circuit module (1) controls the charging and discharging paths of the energy storage unit group (11), the flying capacitor unit (12), the clamping diode unit (13) and the switching transistor unit (14), and provides DC to thirteen-level AC conversion. The signal enters the control circuit module (2). The control circuit module (2) includes a sampling receiving unit (21) and an adjustment output unit (22); The sampling receiving unit (21) acquires the signal according to the main circuit module (1) and provides adjustable current and voltage values ​​to the regulating output module (22). The adjustment output module (22) receives the signal from the sampling receiving unit (21) to provide error adjustment, generates a current setpoint, compares and adjusts to generate a modulation signal, and outputs a thirteen-level sine wave.

2. The multi-level energy storage grid inverter according to claim 1, characterized in that: The energy storage unit group (11) is connected to the flying capacitor unit (12) and the clamping diode unit (13). The flying capacitor unit (12) and the clamping diode unit (13) are respectively connected in series with the capacitor group and the diode group. The flying capacitor unit (12) and the clamping diode unit (13) are connected to the switching transistor unit (14), and the switching transistor group is symmetrically distributed in the upper and lower bridge arms of the switching transistor unit (14).

3. The multi-level energy storage grid inverter according to claim 1, characterized in that: The sampling receiving unit (21) includes a current sampling circuit (211) and a voltage sampling circuit (212). The sampling receiving unit (21) is connected to the phase comparator (221), and the error device (222) receives the signal input from the sampling receiving unit (21) to the microprocessor (223), generates a modulation signal, and enters the driving circuit unit (227) through the PR controller (224), the limiter (225), and the sinusoidal pulse width modulation unit (226).

4. An inverter control method, characterized in that: Including the multi-level energy storage grid inverter as described in claim 3, and, Sampling and conditioning, control circuit module (2) detects output voltage Vo and sampling current; Error adjustment involves comparing Vo with the reference phase θref and adjusting the generated current setpoint via an error converter (222), a microprocessor (223), and a PR controller (224). The limiter (225) generates a modulation signal, which is converted into PWM by the sinusoidal pulse width modulation unit (226). The switching transistor unit (14) is driven to turn on and off through the driving circuit unit (227), generating fourteen modes in a row and outputting a thirteen-level sine wave.

5. The inverter regulation method according to claim 4, characterized in that: In the process of generating mode 1~2 by sinusoidal pulse width modulation; S1, S5, S9, and S11 in the switching transistor unit (14) are turned on, the clamping diode unit (13) is turned off, and the remaining switching transistors in the switching transistor unit (14) are turned off. DC input voltage source 2Vin charge and discharge flying capacitor unit (12), capacitors C1-C4 are not connected to the output path, output voltage Vo=0; The signal corresponding to the output voltage Vo is finally processed by the sinusoidal pulse width modulation unit (225) to generate the positive half-cycle mode 2; S2, S5, S9, and S11 in the switching transistor unit (14) are turned on, the clamping diode unit (13) is turned off, and the remaining switching transistors in the switching transistor unit (14) are turned off. The equivalent circuit is connected to the corresponding path, and the output voltage Vo = Vin. The signal corresponding to the output voltage Vo is finally passed through the sinusoidal pulse width modulation unit (225) to generate mode 3.

6. The inverter regulation method according to claim 5, characterized in that: In the sinusoidal pulse width modulation generation mode 3~4 process; S5, S9, and S11 in the switching transistor unit (14) and D2 in the clamping diode unit (13) are turned on, while the remaining switching transistors and diodes are turned off. The equivalent circuit is connected to the corresponding path, and the output voltage Vo = 2Vin. The signal corresponding to the output voltage Vo is finally passed through the sinusoidal pulse width modulation unit (225) to generate mode 4. S2 and S9 in the switching transistor unit (14) and D4 and D6 in the clamping diode unit (13) are turned on, while the remaining switching transistors and diodes are turned off. The equivalent circuit is connected to the corresponding path, and the output voltage Vo = 3Vin. The signal corresponding to the output voltage Vo is finally passed through the sinusoidal pulse width modulation unit (225) to generate mode 5.

7. The inverter regulation method according to claim 6, characterized in that: In the process of generating mode 5-6 by sinusoidal pulse width modulation; S9 in the switching transistor unit (14) and D2, D4 and D6 in the clamping diode unit (13) are turned on, while the remaining switching transistors and diodes are turned off. The equivalent circuit is connected to the corresponding path, and the output voltage Vo = 4Vin. The signal corresponding to the output voltage Vo is finally used by the sinusoidal pulse width modulation unit (225) to generate mode 6. S7 and S9 in the switching transistor unit (14) and D2 and D6 in the clamping diode unit (13) are turned on, while the remaining switching transistors and diodes are turned off. The equivalent circuit is connected to the corresponding path, and the output voltage Vo = 5Vin. The signal corresponding to the output voltage Vo is finally passed through the sinusoidal pulse width modulation unit (225) to generate mode 7.

8. The inverter regulation method according to claim 7, characterized in that: In the sinusoidal pulse width modulation generation mode 7~8 process; S5 and S9 in the switching transistor unit (14) and D2 and D6 in the clamping diode unit (13) are turned on, while the remaining switching transistors and diodes are turned off. The output voltage Vo = 6Vin, and the signal corresponding to the output voltage Vo is finally passed through the sinusoidal pulse width modulation unit (225) to generate mode 8; In the switching transistor unit (14), S4, S8, S10, and S12 are turned on, while the remaining switching transistors and diodes are turned off. When the equivalent circuit is connected to the corresponding path, the output voltage Vo = 0. The signal corresponding to the output voltage Vo is finally passed through the sinusoidal pulse width modulation unit (225) to generate mode 9.

9. The inverter regulation method according to claim 8, characterized in that: In the sinusoidal pulse width modulation generation mode 9~11 process; In the switching transistor unit (14), S3, S8, S10, and S12 are in the on state, while the other switching transistors and diodes are off. The equivalent circuit is connected to the corresponding path, and the output voltage Vo = -Vin. The signal corresponding to the output voltage Vo is finally passed through the sinusoidal pulse width modulation unit (225) to generate mode 10. S8, S10, and S12 in the switching transistor unit (14) and D1 in the clamping diode unit (13) are in the conducting state, while the other switching transistors and diodes are cut off. The equivalent circuit is connected to the corresponding path, and the output voltage Vo = -2Vin. The signal corresponding to the output voltage Vo is finally used by the sinusoidal pulse width modulation unit (225) to generate mode 11. S3 and S10 in the switching transistor unit (14) and D3 and D5 in the clamping diode unit (13) are in the conducting state, while the other switching transistors and diodes are cut off; The equivalent circuit is connected to the corresponding path, and the output voltage Vo = -3Vin. The signal corresponding to the output voltage Vo is finally passed through the sinusoidal pulse width modulation unit (225) to generate mode 12.

10. The inverter regulation method according to claim 9, characterized in that: In the process of generating modes 12~14 using sinusoidal pulse width modulation; In the switching transistor unit (14), S10 and in the clamping diode unit (13), D1, D3, and D5 are in the conducting state, while the other switching transistors and diodes are cut off. The equivalent circuit is connected to the corresponding path, the load output voltage Vo = -4Vin, and the signal corresponding to the output voltage Vo is finally used by the sinusoidal pulse width modulation unit (225) to generate mode 13. S6 and S10 in the switching transistor unit (14) and D1 and D5 in the clamping diode unit (13) are in the conducting state, while the other switching transistors and diodes are cut off. The equivalent circuit is connected to the corresponding path, the load output voltage Vo = -5Vin, and the signal corresponding to the output voltage Vo is finally used to generate mode 14 by the sinusoidal pulse width modulation unit (225). S8 and S10 in the switching transistor unit (14) and D1 and D5 in the clamping diode unit (13) are in the conducting state, while the other switching transistors and diodes are cut off. The equivalent circuit is connected to the corresponding path, and the load output voltage Vo = -6Vin. The signal corresponding to the output voltage Vo is finally reversed to achieve a negative level by the sinusoidal pulse width modulation unit (225) to complete the fourteen-mode cycle.

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