Output jitter suppression circuit, signal processing circuit and microprocessor architecture

Abstract

The invention provides an output jitter suppression circuit, a signal processing circuit and a microprocessor architecture, the circuit comprises a clock regulation module and a first sampling module, and an automatic zeroing comparator operates according to a sampling clock output by the clock regulation module and outputs a first output signal; the first sampling module samples the first output signal according to the sampling clock and outputs a second output signal to the load circuit, and the clock adjusting module outputs the first sampling clock when the second output signal is not detected to jitter and outputs the second sampling clock when the second output signal is detected to jitter. The sampling process is periodically triggered according to the sampling clock, so that the probability that the first sampling module acquires a jittering signal peak of the first output signal is reduced, and sampling is performed at the lower clock frequency under the condition that the second output signal jitters; the probability of collecting the signal peak is further reduced, and the jitter of the output signal of the automatic return-to-zero comparator is effectively inhibited.

Description

Technical Field

[0001] This application relates to the field of computer technology, specifically to an output jitter suppression circuit, a signal processing circuit, and a microprocessor architecture. Background Technology

[0002] Auto-zero comparators have been widely used in the field of integrated circuits in recent years due to their simple circuit structure, ability to perform periodic calibration using a sampling clock, and elimination of offset voltage.

[0003] However, in actual working scenarios, auto-zero comparators are easily affected by input signal jitter or power supply noise, which can cause the output signal of the auto-zero comparator to be prone to false flips. Furthermore, the higher the sensitivity of the auto-zero comparator, the more times the output will be falsely flipped, and the more severe the jitter will be. This will cause the load circuit of the auto-zero comparator to make incorrect judgments, affecting the operation of the circuit system and reducing the accuracy and reliability of the circuit system. Summary of the Invention

[0004] In view of this, this application aims to provide an output jitter suppression circuit, a signal processing circuit, and a microprocessor architecture to solve the problem that the output jitter of the automatic zero comparator causes the load circuit to misjudge, thereby reducing the operating accuracy and reliability of the circuit system.

[0005] In a first aspect, this application provides an output jitter suppression circuit, comprising: a clock adjustment module and a first sampling module, wherein, The clock input terminal of the clock adjustment module receives the first sampling clock, and the clock output terminal of the clock adjustment module is connected to the automatic zero comparator and the clock input terminal of the first sampling module, respectively. The signal acquisition terminal of the first sampling module is connected to the signal output terminal of the automatic zero comparator; the signal output terminal of the first sampling module is connected to the load circuit of the automatic zero comparator. The automatic zeroing comparator operates according to the sampling clock output by the clock adjustment module and outputs a first output signal; The first sampling module samples the first output signal according to the sampling clock output by the clock adjustment module, and outputs a second output signal based on the sampling result; The signal acquisition terminal of the clock adjustment module is connected to the signal output terminal of the first sampling module. It detects whether there is jitter in the second output signal. If no jitter is detected in the second output signal, it outputs the first sampling clock. If jitter is detected in the second output signal, it outputs the second sampling clock based on the first sampling clock. The clock frequency of the first sampling clock is higher than the clock frequency of the second sampling clock.

[0006] In one optional implementation, the clock adjustment module includes: a jitter detection circuit and a clock processing circuit, wherein, The input terminal of the jitter detection circuit serves as the signal acquisition terminal of the clock adjustment module, and the output terminal of the jitter detection circuit is connected to the selection control terminal of the clock processing circuit. The clock input terminal of the clock processing circuit serves as the clock input terminal of the clock adjustment module, and the clock output terminal of the clock processing circuit serves as the clock output terminal of the clock adjustment module. The jitter detection circuit detects whether there is jitter in the second output signal. If no jitter is detected in the second output signal, it outputs a first selection signal. If jitter is detected in the second output signal, it outputs a second selection signal. The clock processing circuit outputs the first sampling clock in response to the first selection signal, or divides the first sampling clock in response to the second selection signal and outputs the resulting sampling clock as the second sampling clock.

[0007] In one optional implementation, the jitter detection circuit includes: a level verification circuit and a phase shift register, wherein, The clock input terminal of the phase shift register receives the first sampling clock, and the phase shift input terminal of the phase shift register receives the second output signal; The phase-shift register has multiple phase-shift output terminals and performs phase-shift transmission on the second output signal according to the first sampling clock, so that the signals output by any two adjacent phase-shift output terminals are time-separated by one clock cycle of the first sampling clock. The level verification circuit is connected to the phase-shift input terminal and each of the phase-shift output terminals of the phase-shift register, respectively. When the second output signal corresponds to the same level as the signal output by each of the phase-shifting output terminals, the level verification circuit outputs the first selection signal; When the second output signal corresponds to a different level from the signal output by each of the phase-shifted output terminals, the level verification circuit outputs the second selection signal.

[0008] In one optional implementation, the level verification circuit includes: a first AND gate, a first OR gate, and a XNOR gate, wherein, Each phase-shifted input terminal and each phase-shifted output terminal are respectively connected to one input terminal of the first AND gate circuit; Each phase-shifting input terminal and each phase-shifting output terminal are respectively connected to one input terminal of the first OR gate circuit; The output of the first AND gate is connected to one input of the NAND gate, and the output of the first OR gate is connected to the other input of the NAND gate. The output of the XOR gate circuit serves as the output of the level verification circuit.

[0009] In one optional implementation, the clock processing circuit includes: a second AND gate, a second OR gate, a NOT gate, and a frequency divider, wherein, The second AND gate has two input terminals, one of which is connected to the input terminal of the NOT gate, and the resulting connection point serves as the selection control terminal of the clock processing circuit. The output terminal of the NOT gate circuit is connected to the enable terminal of the frequency divider. The other input terminal of the second AND gate is connected to the clock input terminal of the frequency divider, and the resulting connection point serves as the clock input terminal of the clock processing circuit. The second OR gate has two input terminals, one of which is connected to the output terminal of the second AND gate, and the other input terminal is connected to the output terminal of the frequency divider. The output of the second OR gate circuit serves as the clock output of the clock processing circuit.

[0010] In an optional implementation, the output jitter suppression circuit provided in the first aspect of this application further includes: a second sampling module, wherein, The signal acquisition terminal of the second sampling module is connected to the signal output terminal of the first sampling module, and the signal output terminal of the second sampling module is connected to the load circuit. The clock input terminal of the second sampling module is connected to the clock output terminal of the clock adjustment module. The second output signal is sampled according to the sampling clock output by the clock adjustment module, and a third output signal is output based on the sampling result.

[0011] In one optional implementation, the first sampling module and the second sampling module are sampling modules with the same structure, and the sampling module includes a register.

[0012] In an optional implementation, the output jitter suppression circuit provided in the first aspect of this application further includes: a delay module, wherein, The delay module receives a reference clock, performs a delay processing on the reference clock, and outputs it as the first sampling clock.

[0013] Secondly, this application provides a signal processing circuit, including: an automatic zero-return comparator and an output jitter suppression circuit as described in any of the first aspects of this application, wherein... The automatic zeroing comparator is connected to the clock output terminal of the clock adjustment module in the output jitter suppression circuit and the signal acquisition terminal of the first sampling module in the output jitter suppression circuit.

[0014] Thirdly, this application provides a microprocessor architecture, including: the signal processing circuit as provided in the second aspect of this application.

[0015] Based on the above, the output jitter suppression circuit provided in this application, when no jitter is detected in the second output signal, outputs a first sampling clock by the clock adjustment module; when jitter is detected in the second output signal, the clock adjustment module outputs a second sampling clock. The first sampling module samples the first output signal based on the sampling clock output by the clock adjustment module, and outputs a second output signal to the load circuit of the auto-zero comparator based on the sampling result. The load circuit receives the output signal processed by the first sampling module. Since the sampling process is periodically triggered according to the sampling clock, the probability of the first sampling module acquiring signal spikes from the jitter of the first output signal is reduced. Furthermore, since the clock frequency of the second sampling clock is lower than that of the first sampling clock, when jitter exists in the second output signal, the first sampling module samples at a lower clock frequency, further reducing the probability of acquiring signal spikes. This effectively suppresses the jitter of the output signal of the auto-zero comparator, reduces the possibility of misjudgment by the load circuit of the auto-zero comparator, and addresses the issues of reduced operating accuracy and reliability of the circuit system. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of an automatic zero-reset comparator in related technologies.

[0018] Figure 2 This is a schematic diagram of another automatic zeroing comparator in related technologies.

[0019] Figure 3This is a structural block diagram of an output jitter suppression circuit provided in an embodiment of this application.

[0020] Figure 4 This is a block diagram of another output jitter suppression circuit provided in an embodiment of this application.

[0021] Figure 5 This is a structural block diagram of a level verification circuit provided in an embodiment of this application.

[0022] Figure 6 This is a structural block diagram of a clock processing circuit provided in an embodiment of this application.

[0023] Figure 7 This is a block diagram of another output jitter suppression circuit provided in the embodiments of this application.

[0024] Figure 8 This is a schematic diagram of the timing relationship of the output jitter suppression circuit provided in the embodiments of this application. Detailed Implementation

[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] Auto-zero comparators have been widely used in the integrated circuit field in recent years due to their simple circuit structure, ability to perform periodic calibration using a sampling clock, and elimination of offset voltage. (See also...) Figure 1 As shown, a typical single-stage automatic zero-reset comparator is implemented based on an inverter, controllable switches S1 and S2, and capacitors Ca and Ci. Figure 1 Based on the implementation shown, other forms of automatic zero-return comparators can be further extended, such as... Figure 2 The example shown is a two-stage auto-zero comparator. Of course, there are other forms of auto-zero comparators, which will not be listed here. As for the working principle of the auto-zero comparator, you can refer to the relevant technologies for implementation, which will not be described in detail here.

[0027] In the field of computer technology, automatic return-to-zero (ARZ) comparators are widely used in high-speed interfaces of microprocessor architectures. Due to the special nature of their actual working environment, ARZ comparators are easily affected by input signal jitter or power supply noise during operation, which can cause the output signal of the ARZ comparator to erroneously flip. Furthermore, the higher the sensitivity of the ARZ comparator, the more times the output erroneously flips, and the more severe the jitter. This will cause the load circuit of the ARZ comparator to make incorrect judgments, affecting the operation of the circuit system and reducing the accuracy and reliability of the circuit system.

[0028] To address the aforementioned issues, this application provides an output jitter suppression circuit. The load circuit receives the output signal processed by the first sampling module. Since the sampling process is periodically triggered according to the sampling clock, the probability of the first sampling module capturing signal spikes from the jitter in the first output signal is reduced. Furthermore, when jitter exists in the second output signal, the first sampling module samples at a lower clock frequency, further reducing the probability of capturing signal spikes. This effectively suppresses the jitter in the output signal of the auto-zero comparator, reduces the possibility of misjudgment by the load circuit of the auto-zero comparator, and addresses the issues of reduced operating accuracy and reliability of the circuit system.

[0029] Based on the above, see Figure 3 The output jitter suppression circuit provided in this embodiment includes: a clock adjustment module 10 and a first sampling module 20, wherein, Combination Figure 3 As shown, the clock adjustment module 10 has a clock input terminal, a clock output terminal, and a signal acquisition terminal. The clock input terminal of the clock adjustment module 10 receives the first sampling clock CLK1, and the clock output terminal of the clock adjustment module 10 is connected to the clock input terminal of the automatic return-to-zero comparator U1 and the clock input terminal of the first sampling module 20, respectively.

[0030] The first sampling module 20, in addition to having a clock input terminal, also includes a signal acquisition terminal and a signal output terminal. The signal acquisition terminal of the first sampling module 20 is connected to the signal output terminal of the automatic return-to-zero comparator U1, and the signal output terminal of the first sampling module 20 is connected to the load circuit of the automatic return-to-zero comparator U1. It should be noted that the load circuit of the automatic return-to-zero comparator U1 mentioned in this application embodiment refers to a circuit that operates based on the output signal provided by the automatic return-to-zero comparator, and is not limited to a circuit directly driven by the automatic return-to-zero comparator. In other words, any circuit connected to the signal output terminal of the automatic return-to-zero comparator in related technologies and receiving the output signal of the automatic return-to-zero comparator can be used as the load circuit mentioned in this application embodiment. Furthermore, it can be understood that the first sampling module 20 is connected between the automatic return-to-zero comparator U1 and the load circuit. After processing the output signal of the automatic return-to-zero comparator U1, it outputs it to the load circuit, thereby achieving the purpose of suppressing the output jitter of the automatic return-to-zero comparator. The specific process of suppressing jitter can be found in the following text.

[0031] The signal output terminal of the first sampling module 20 is connected to the signal acquisition terminal of the clock adjustment module 10. The output signal of the first sampling module 20 will be fed back to the clock adjustment module 10, thus forming a closed-loop control architecture.

[0032] Based on the above connection relationship, the clock adjustment module 10 outputs a sampling clock to the automatic return-to-zero comparator U1 and the first sampling module 20 based on the obtained first sampling clock CLK1. The automatic return-to-zero comparator U1 compares and processes the output signal Vi according to the sampling clock output by the clock adjustment module 10, and outputs the first output signal Out1. Figure 1 as well as Figure 2 The implementation of the automatic return-to-zero comparator shown is such that each controllable switch in the automatic return-to-zero comparator U1 is driven by the sampling clock output by the clock adjustment module 10. Based on the input signal Vi and the reference signal Vref, it outputs a first output signal Out1. The specific working process of the automatic return-to-zero comparator U1 is not detailed here; please refer to relevant technical implementations. Furthermore, the first sampling module 20 samples the first output signal Out1 according to the sampling clock output by the clock adjustment module 10, and outputs a second output signal Out2 based on the sampling result. Figure 2 As shown, the second output signal Out2 corresponds to two transmission paths. One path is output to the load circuit, which operates according to the obtained second output signal Out2. The other path is fed back to the clock adjustment module 10.

[0033] The clock adjustment module 10 detects whether there is jitter in the second output signal Out2. If no jitter is detected in the second output signal Out2, the clock adjustment module 10 outputs the first sampling clock CLK1, that is, keeps the first sampling clock CLK1 unchanged. Conversely, if jitter is detected in the second output signal Out2, the clock adjustment module 10 outputs the second sampling clock CLK2 based on the first sampling clock CLK1, and the clock frequency of the first sampling clock CLK1 is higher than the clock frequency of the second sampling clock CLK2. The subsequent automatic return-to-zero comparator U1 and the first sampling module 20 both operate according to the second sampling clock CLK2.

[0034] If the output jitter suppression circuit provided in this application embodiment is not provided, the signal output terminal of the automatic return-to-zero comparator U1 will be directly connected to the load circuit, providing the first output signal Out1 to the load circuit. In this case, every jitter in the first output signal Out1, i.e. signal spike, will be directly received by the load circuit, thereby affecting the load circuit's recognition and judgment of the output signal of the automatic return-to-zero comparator U1. This is the technical problem that this application wants to solve.

[0035] When connected to the output jitter suppression circuit provided in the embodiments of this application, if the clock adjustment module 10 outputs a first sampling clock CLK1, the first sampling module 20 samples the first output signal Out1 of the automatic return-to-zero comparator U1 according to the first sampling clock CLK1, and outputs a second output signal based on the sampling result. Specifically, if a high level is sampled, a high level is output, and if a low level is sampled, a low level is output. In other words, the probability of the first sampling module 20 sampling jitter (i.e., error signal) is completely determined by the clock frequency of its own sampling clock. Compared with the related technology where every jitter of the first output signal Out1 is output to the load circuit, the probability of the second output signal Out2 sampled and output by the first sampling module 20 including jitter is significantly reduced, thereby achieving the purpose of suppressing output signal jitter.

[0036] Furthermore, the second output signal Out2 output by the first sampling module 20 is also fed back to the clock adjustment module 10. If the clock adjustment module 10 detects that there is still jitter in the second output signal Out2, it indicates that the clock frequency of the first sampling clock is too high, and there is still a situation where jitter is collected, resulting in jitter in the second output signal Out2 output to the load circuit. Based on this, the clock adjustment module 10 outputs a second sampling clock CLK2 with a lower clock frequency, reducing the sampling frequency of the first sampling module 20, that is, reducing the probability of the first sampling module 20 collecting jitter, avoiding the transmission of jitter in the first output signal Out1 to the load circuit, and further improving the jitter suppression effect.

[0037] In summary, the output jitter suppression circuit provided in this embodiment outputs a first sampling clock when no jitter is detected in the second output signal, and a second sampling clock when jitter is detected in the second output signal. The first sampling module samples the first output signal based on the sampling clock output by the clock adjustment module, and outputs a second output signal to the load circuit of the auto-zero comparator based on the sampling result. The load circuit receives the output signal processed by the first sampling module. Since the sampling process is periodically triggered according to the sampling clock, the probability of the first sampling module acquiring signal spikes from the jitter of the first output signal is reduced. Furthermore, since the clock frequency of the second sampling clock is lower than that of the first sampling clock, the first sampling module samples at a lower clock frequency when jitter exists in the second output signal, further reducing the probability of acquiring signal spikes. This effectively suppresses the jitter of the output signal of the auto-zero comparator, reduces the possibility of misjudgment by the load circuit of the auto-zero comparator, and addresses the issues of reduced operating accuracy and reliability of the circuit system.

[0038] This application also provides another output jitter suppression circuit, see [link to relevant documentation] Figure 4 As shown, in the output jitter suppression circuit provided in this application embodiment, the clock adjustment module 10 includes: a jitter detection circuit 110 and a clock processing circuit 120.

[0039] Combination Figure 4 As shown, the input terminal of the jitter detection circuit 110 serves as the signal acquisition terminal of the clock adjustment module 10, and is connected to the signal output terminal of the first sampling module 20 to receive the second output signal Out2. The output terminal of the jitter detection circuit 110 is connected to the selection control terminal of the clock processing circuit 120. The clock input terminal of the clock processing circuit 120 serves as the clock input terminal of the clock adjustment module 10, and receives the first sampling clock CLK1. The clock output terminal of the clock processing circuit 120 serves as the clock output terminal of the clock adjustment module 10, and is connected to the clock input terminal of the automatic zeroing comparator U1 and the clock input terminal of the first sampling module 20, respectively.

[0040] Based on the above connection, the jitter detection circuit 110 detects whether jitter exists in the second output signal Out2. If no jitter is detected in the second output signal Out2, it outputs a first selection signal, such as a high level. Conversely, if jitter is detected in the second output signal Out2, it outputs a second selection signal, such as a low level. The clock processing circuit 120 responds to the first selection signal by outputting a first sampling clock CLK1, or, responds to the second selection signal by dividing the first sampling clock CLK1 and outputting the resulting sampling clock as the second sampling clock CLK2. It can be understood that since the second sampling clock CLK2 is obtained by dividing the first sampling clock CLK1, it can be guaranteed that the clock frequency of the second sampling clock CLK2 is lower than the clock frequency of the first sampling clock CLK1.

[0041] Furthermore, this application provides an optional implementation of a jitter detection circuit, including a phase-shift register and a level verification circuit, wherein the phase-shift register is implemented by multiple (i.e., at least two) registers connected in series, see [link to relevant documentation]. Figure 5 As shown, in Figure 5 In the embodiment shown, the phase shift register 1101 includes registers DFF1, DFF2 and DFF3, and the level verification circuit 1102 includes a first AND gate circuit U2, a first OR gate circuit U3 and an XNOR gate circuit U4.

[0042] The signal input terminal D of register DFF1 serves as the phase-shifting input terminal of phase-shift register 1101, which is also the signal acquisition terminal of clock adjustment module 10, receiving the second output signal Out2. The signal output terminal Q of register DFF1 is connected to the signal input terminal D of register DFF2, and the signal output terminal Q of register DFF2 is connected to the signal input terminal D of register DFF3. The clock input terminal of each register serves as the clock input terminal of phase-shift register 1101, receiving the first sampling clock CLK1. The signal output terminal of each register serves as the phase-shifting output terminal of phase-shift register 1101. That is, phase-shift register 1101 has multiple phase-shifting output terminals.

[0043] Phase shift register 1101 performs phase shift transmission on the second output signal Out2 according to the first sampling clock CLK1, and outputs the phase shift result through the signal output terminals of registers DFF1, DFF2 and DFF3. Based on the working principle of the phase shift register, it can be known that the signals output by any two adjacent phase shift output terminals in phase shift register 1101 are separated by one clock cycle of the first sampling clock CLK1 in terms of timing. Based on this, if the second output signal Out2 does not contain jitter, the level of each phase shift output terminal in phase shift register 1101 is the same as the level of the phase shift input terminal. Conversely, if the second output signal Out2 contains jitter, the jitter will be transmitted sequentially between each phase shift output terminal of phase shift register 1101 according to the clock frequency of the first sampling clock CLK1, resulting in different levels of each phase shift output terminal and phase shift input terminal of phase shift register 1101.

[0044] The level verification circuit 1102 is connected to the phase-shift input terminal and each phase-shift output terminal of the phase-shift register 1101, respectively. Specifically, in conjunction with... Figure 5 As shown, the phase-shifting input and each phase-shifting output of the phase-shifting register 1101 are connected to one input of the first AND gate circuit U2. Specifically, the first input of the first AND gate circuit U2 is connected to the phase-shifting input to receive the second output signal Out2; the second input of the first AND gate circuit U2 is connected to the signal output of register DFF1 to receive the output signal D1; the third input of the first AND gate circuit U2 is connected to the signal output of register DFF2 to receive the output signal D2; and the fourth input of the first AND gate circuit U2 is connected to the signal output of register DFF3 to receive the output signal D3. Based on the working principle of the AND gate, the first AND gate circuit U2 outputs a high level when all input signals are high, and conversely, outputs a low level when any input signal is low.

[0045] The phase-shifting input and each phase-shifting output of the phase-shifting register 1101 are also connected to one input of the first OR gate circuit U3. For specific connection details, please refer to [link to relevant documentation]. Figure 5 The specific connection details of the first AND gate circuit U2 shown in the diagram and the preceding content will not be elaborated here. Based on the working principle of the OR gate, the first OR gate circuit U3 outputs a low level when all input signals are low, and conversely, outputs a high level when any input signal is high.

[0046] The output of the first AND gate U2 is connected to one input of the XNOR gate U4, and the output of the first OR gate U3 is connected to the other input of the XNOR gate U4. The output of the XNOR gate U4 serves as the output of the level verification circuit 1102, which is also the output of the jitter detection circuit 110. Based on the working principle of the XNOR gate, when the two inputs of the XNOR gate U4 receive the same level, the XNOR gate U4 outputs a high level; conversely, when the two inputs of the XNOR gate U4 receive different levels, the XNOR gate U4 outputs a low level.

[0047] Based on the above, the jitter detection circuit provided in this embodiment outputs a high level when the second output signal Out2 corresponds to the same level as the signals output from each phase-shifted output terminal of the phase-shift register 1101, i.e., the first selection signal ( Figure 5 (represented by C1); when the second output signal Out2 corresponds to different levels of the signals output from each phase-shifting output terminal, the level verification circuit 1102 outputs a low level, i.e., the second selection signal ( Figure 5 (represented by C2 in Chinese).

[0048] Furthermore, this application also provides an optional implementation of the clock processing circuit, see [link to relevant documentation]. Figure 6 As shown, the clock processing circuit provided in this embodiment includes a frequency divider U6, a second AND gate U5, a second OR gate U7, and a NOT gate U8.

[0049] Combination Figure 6 As shown, the second AND gate U5 has two input terminals, one of which is connected to the input terminal of the NOT gate U8. The connection point between the second AND gate U5 and the NOT gate U8 serves as the selection control terminal of the clock processing circuit and is connected to the output terminal of the jitter detection circuit to receive the first selection signal or the second selection signal. The output terminal of the NOT gate U8 is connected to the enable terminal of the frequency divider U6. When the NOT gate U8 outputs an enable signal, i.e., a high level, the frequency divider U6 is in the working state. Conversely, when the NOT gate U8 outputs an enable signal, i.e., a low level, the frequency divider U6 is in the non-working state.

[0050] The other input of the second AND gate U5 is connected to the clock input of the frequency divider U6. The connection point between the second AND gate U5 and the frequency divider U6 serves as the clock input of the clock processing circuit, receiving the first sampled clock CLK1. When the NOT gate U8 outputs an enable signal, the frequency divider U6 is in operation, dividing the first sampled clock according to a preset division ratio. The resulting sampled clock is output as the second sampled clock CLK2. Conversely, when the NOT gate U8 outputs an enable signal, the frequency divider U6 is in operation and does not output a sampled clock. It can be understood that the specific frequency difference between the second sampled clock CLK2 and the first sampled clock CLK1 is determined by the division ratio of the frequency divider U6. The larger the division ratio, the smaller the clock frequency difference between the second sampled clock CLK2 and the first sampled clock CLK1; conversely, the larger the division ratio, the larger the clock frequency difference between the second sampled clock CLK2 and the first sampled clock CLK1. In practical applications, the specific clock frequency of the second sampled clock CLK2 can be adjusted by configuring different division ratios. As for the specific implementation of the frequency divider U6, you can refer to the relevant technologies, which will not be detailed here.

[0051] The second OR gate circuit U7 also has two input terminals. One input terminal is connected to the output terminal of the second AND gate circuit U5, and the other input terminal is connected to the output terminal of the frequency divider U6. The output terminal of the second OR gate circuit U7 serves as the clock output terminal of the clock processing circuit, used to output the first sampling clock CLK1 or the second sampling clock CLK2.

[0052] Based on the above, when the jitter detection circuit outputs the first selection signal (i.e., a high level), after being inverted by the NOT gate U8, the frequency divider U6 receives a low level (i.e., an enable signal). The frequency divider U6 is in a non-working state and will not perform frequency division processing on the first sampling clock CLK1. The second AND gate U5 normally outputs the first sampling clock CLK1. Correspondingly, one input of the second OR gate U7 receives a low level, and its output state is determined by the level change of the other input. Therefore, the first sampling clock CLK1 can be output normally. Conversely, when the jitter detection circuit outputs the second selection signal (i.e., a low level), the second AND gate U5 can be considered to be in a closed state, continuously outputting a low level. After being inverted by the NOT gate U8, the frequency divider U6 receives a high level (i.e., an enable signal). The frequency divider U6 performs frequency division processing on the first sampling clock CLK1 and outputs the corresponding second sampling clock CLK2. One input of the second OR gate U7 receives a low level, and its output state is determined by the level change of the other input. Therefore, the first sampling clock CLK2 can be output normally.

[0053] Based on the first sampling clock or the second sampling clock output by the clock adjustment module, the output jitter suppression circuit suppresses the jitter of the first output signal of the automatic return-to-zero comparator. For the specific working process, please refer to the relevant content of the foregoing embodiment, which will not be repeated here.

[0054] This application embodiment further provides another output jitter suppression circuit, see [link to embodiment]. Figure 7 As shown, the output jitter suppression circuit provided in this embodiment further includes a second sampling module 30 and a delay module 40.

[0055] As an optional implementation, the first sampling module 20 and the second sampling module 30 are sampling modules with identical structures, both implemented based on registers. See [link to relevant documentation]. Figure 7 As shown, the first sampling module 20 includes register DFF4, and the second sampling module 30 includes register DFF5. Taking the second sampling module 30 as an example, the input terminal of register DFF5 serves as the signal acquisition terminal of the second sampling module 30, the output terminal of register DFF5 serves as the signal output terminal of the second sampling module 30, and the clock terminal of register DFF5 serves as the clock input terminal of the second sampling module 30.

[0056] In the output jitter suppression circuit provided in this embodiment, the first sampling module 20 further includes inverters U9 and U10, combined with... Figure 7 As shown, the input terminal of inverter U9 serves as the signal acquisition terminal of the first sampling module 20, connected to the signal output terminal of the automatic return-to-zero comparator U1, receiving the first output signal Out1 and inverting it. The output terminal of inverter U9 is connected to the input terminal of register DFF4, and the output terminal of register DFF4 is connected to the input terminal of inverter U10. The output terminal of inverter U10 serves as the signal output terminal of the first sampling module 20, outputting the second output signal Out2. The clock terminal of register DFF4 serves as the clock input terminal of the first sampling module 20, receiving the sampling clock output by the clock adjustment module 10. It can be understood that, due to the two inversion processes by inverters U9 and U10, the final output second output signal Out2 has the same level change as the first output signal Out1. By setting up inverters, not only can signal shaping be achieved, but also the output signal can be ensured to drive the related circuits connected in subsequent stages, thereby improving the overall circuit reliability.

[0057] The signal acquisition terminal of the second sampling module 30 is connected to the signal output terminal of the first sampling module 20. The signal output terminal of the second sampling module 30 is connected to the load circuit. The clock input terminal of the second sampling module 30 is connected to the clock output terminal of the clock adjustment module 10. The second output signal is sampled according to the sampling clock output by the clock adjustment module 10, and the third output signal is output based on the sampling result.

[0058] Based on the above, the output jitter suppression circuit provided in this embodiment allows the clock adjustment module 10 to adjust the actual output sampling clock according to the actual situation of the second output signal Out2, so that the clock frequency of the sampling clock changes with the actual output of the automatic return-to-zero comparator U1. By sampling the first output signal Out1 through the first sampling module 20, the output second output signal Out2 has eliminated a lot of jitter compared to the first output signal Out1, and the clock frequency of the sampling clock can be adjusted according to the actual situation of the second output signal Out2. Furthermore, by sampling the second output signal Out2 using the second sampling module 30, the probability that the third output signal Out3 may contain jitter is further reduced compared to the second output signal Out2, thereby effectively ensuring the reliability and stability of the output signal finally output to the load circuit.

[0059] Furthermore, the output jitter suppression circuit provided in this embodiment also includes a delay module 40, combined with... Figure 7 As shown, the signal input terminal of the delay module 40 receives the reference clock CLK0, and after delaying the reference clock CLK0, it is output as the first sampling clock CLK1 to the clock adjustment module 10. The delay module 40 is used to readjust the sampling position in the output jitter suppression circuit with a fixed sampling position, realizing the change of different sampling positions in the front, middle and rear stages. As an optional implementation, the delay module 40 is based on a buffer. The specific delay duration of the delay module 40 can be changed by changing the number of buffers connected in series. The fewer the number of buffers connected in series, the shorter the delay time of the reference clock CLK0, and the sampling position is in the front stage of the clock cycle. The more the number of buffers connected in series, the longer the delay time, and the sampling position is in the rear stage of the clock cycle. Of course, in practical applications, the delay module 40 can also be implemented based on other types of digital delay units, or it can be built based on analog devices, which will not be described in detail here.

[0060] Figure 7 The output jitter suppression circuit provided in the illustrated embodiment can be referenced in practical applications for the level changes of each relevant node within the circuit. Figure 8 As shown. Where Vref represents the reference voltage during the operation of the auto-zero comparator, and Vi represents the input signal of the auto-zero comparator, according to... Figure 8 As shown, both registers DFF4 and DFF5 are rising-edge triggered, meaning sampling begins when the clock input receives the rising edge of the sampling clock. Based on this, the first output signal Out1 ( Figure 8(Not shown) The signal after being inverted by inverter U9 is S1. The jitter in S1 is also the jitter in the first output signal Out1. When the register DFF4 in the first sampling module 20 samples according to the first sampling clock CLK1, it collects this jitter. After being inverted by inverter U10, the second output signal Out2 also contains jitter. After the clock adjustment module 10 detects this jitter, it switches the sampling clock CLKs it provides from the first sampling clock CLK1 to the second sampling clock CLK2. Figure 8 The sampling frequency is reduced by CLK1 / N (where N represents the frequency division ratio), thereby reducing the probability of jitter being captured. The second sampling module 30 samples the second output signal Out2 based on the sampling clock output by the clock adjustment module 10 (which has now been switched to the second sampling clock). Since the sampling clock has been switched to the second sampling clock with a lower clock frequency, the second sampling module 30 will not capture the jitter in the second output signal Out2, ensuring that the third output signal Out3 finally output to the load circuit does not contain jitter. This effectively suppresses the jitter of the output signal of the automatic return-to-zero comparator, reduces the possibility of misjudgment by the load circuit of the automatic return-to-zero comparator, and reduces the problem of reduced operating accuracy and reliability of the circuit system.

[0061] This application embodiment also provides a signal processing circuit, including: an automatic return-to-zero comparator and an output jitter suppression circuit provided in any of the foregoing embodiments. The automatic return-to-zero comparator is connected to the clock output terminal of the clock adjustment module in the output jitter suppression circuit and the signal acquisition terminal of the first sampling module in the output jitter suppression circuit, respectively, and the jitter in the output signal of the automatic return-to-zero comparator is suppressed by the output jitter suppression circuit.

[0062] This application also provides a microprocessor architecture, including the signal processing circuit provided in the foregoing embodiments.

[0063] Those skilled in the art will understand that the contents disclosed herein can be varied and modified in many ways. For example, the various devices or components described above can be implemented in hardware, or in software, firmware, or a combination of some or all of the three.

[0064] Furthermore, while this disclosure makes various references to certain elements of systems according to embodiments of this disclosure, any number of different elements may be used and operated on clients and / or servers. Elements are merely illustrative, and different aspects of the system and method may use different elements.

[0065] This disclosure uses flowcharts to illustrate the steps of a method according to embodiments of this disclosure. It should be understood that the preceding or following steps are not necessarily performed in exact order. Instead, the steps can be processed in reverse order or simultaneously. Furthermore, other operations can be added to these processes.

[0066] Those skilled in the art will understand that all or part of the steps in the above methods can be implemented by a computer program instructing related hardware, and the program can be stored in a computer-readable storage medium, such as a read-only memory. Optionally, all or part of the steps in the above embodiments can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiments can be implemented in hardware or as a software functional module. This disclosure is not limited to any particular combination of hardware and software.

[0067] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms such as those defined in a common dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or highly formalized meaning, unless expressly defined herein.

[0068] The foregoing description is intended to illustrate the present disclosure and should not be construed as limiting it. While several exemplary embodiments of the present disclosure have been described, those skilled in the art will readily understand that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined by the claims. It should be understood that the foregoing description is intended to illustrate the present disclosure and should not be construed as limiting it to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. An output jitter suppression circuit, characterized in that, include: The clock adjustment module and the first sampling module, wherein, The clock input terminal of the clock adjustment module receives the first sampling clock, and the clock output terminal of the clock adjustment module is connected to the automatic zero comparator and the clock input terminal of the first sampling module, respectively. The signal acquisition terminal of the first sampling module is connected to the signal output terminal of the automatic zero comparator; the signal output terminal of the first sampling module is connected to the load circuit of the automatic zero comparator. The automatic zeroing comparator operates according to the sampling clock output by the clock adjustment module and outputs a first output signal; The first sampling module samples the first output signal according to the sampling clock output by the clock adjustment module, and outputs a second output signal based on the sampling result; The signal acquisition terminal of the clock adjustment module is connected to the signal output terminal of the first sampling module. It detects whether there is jitter in the second output signal. If no jitter is detected in the second output signal, it outputs the first sampling clock. If jitter is detected in the second output signal, it outputs the second sampling clock based on the first sampling clock. The clock frequency of the first sampling clock is higher than the clock frequency of the second sampling clock.

2. The output jitter suppression circuit according to claim 1, characterized in that, The clock adjustment module includes: a jitter detection circuit and a clock processing circuit, wherein, The input terminal of the jitter detection circuit serves as the signal acquisition terminal of the clock adjustment module, and the output terminal of the jitter detection circuit is connected to the selection control terminal of the clock processing circuit. The clock input terminal of the clock processing circuit serves as the clock input terminal of the clock adjustment module, and the clock output terminal of the clock processing circuit serves as the clock output terminal of the clock adjustment module. The jitter detection circuit detects whether there is jitter in the second output signal. If no jitter is detected in the second output signal, it outputs a first selection signal. If jitter is detected in the second output signal, it outputs a second selection signal. The clock processing circuit outputs the first sampling clock in response to the first selection signal, or divides the first sampling clock in response to the second selection signal and outputs the resulting sampling clock as the second sampling clock.

3. The output jitter suppression circuit according to claim 2, characterized in that, The jitter detection circuit includes: a level verification circuit and a phase shift register, wherein... The clock input terminal of the phase shift register receives the first sampling clock, and the phase shift input terminal of the phase shift register receives the second output signal; The phase-shift register has multiple phase-shift output terminals and performs phase-shift transmission on the second output signal according to the first sampling clock, so that the signals output by any two adjacent phase-shift output terminals are time-separated by one clock cycle of the first sampling clock. The level verification circuit is connected to the phase-shift input terminal and each of the phase-shift output terminals of the phase-shift register, respectively. When the second output signal corresponds to the same level as the signal output by each of the phase-shifting output terminals, the level verification circuit outputs the first selection signal; When the second output signal corresponds to a different level from the signal output by each of the phase-shifted output terminals, the level verification circuit outputs the second selection signal.

4. The output jitter suppression circuit according to claim 3, characterized in that, The level verification circuit includes: a first AND gate, a first OR gate, and a XNOR gate, wherein... Each phase-shifted input terminal and each phase-shifted output terminal are respectively connected to one input terminal of the first AND gate circuit; Each phase-shifting input terminal and each phase-shifting output terminal are respectively connected to one input terminal of the first OR gate circuit; The output of the first AND gate is connected to one input of the NAND gate, and the output of the first OR gate is connected to the other input of the NAND gate. The output of the XOR gate circuit serves as the output of the level verification circuit.

5. The output jitter suppression circuit according to claim 2, characterized in that, The clock processing circuit includes: a second AND gate, a second OR gate, a NOT gate, and a frequency divider, wherein... The second AND gate has two input terminals, one of which is connected to the input terminal of the NOT gate, and the resulting connection point serves as the selection control terminal of the clock processing circuit. The output terminal of the NOT gate circuit is connected to the enable terminal of the frequency divider. The other input terminal of the second AND gate is connected to the clock input terminal of the frequency divider, and the resulting connection point serves as the clock input terminal of the clock processing circuit. The second OR gate has two input terminals, one of which is connected to the output terminal of the second AND gate, and the other input terminal is connected to the output terminal of the frequency divider. The output of the second OR gate circuit serves as the clock output of the clock processing circuit.

6. The output jitter suppression circuit according to claim 1, characterized in that, Also includes: The second sampling module, wherein, The signal acquisition terminal of the second sampling module is connected to the signal output terminal of the first sampling module, and the signal output terminal of the second sampling module is connected to the load circuit. The clock input terminal of the second sampling module is connected to the clock output terminal of the clock adjustment module. The second output signal is sampled according to the sampling clock output by the clock adjustment module, and a third output signal is output based on the sampling result.

7. The output jitter suppression circuit according to claim 6, characterized in that, The first sampling module and the second sampling module are sampling modules with the same structure, and the sampling module includes a register.

8. The output jitter suppression circuit according to any one of claims 1 to 7, characterized in that, Also includes: Delay module, in which, The delay module receives a reference clock, performs a delay processing on the reference clock, and outputs it as the first sampling clock.

9. A signal processing circuit, characterized in that, include: The automatic zero-reset comparator and the output jitter suppression circuit as described in any one of claims 1 to 8, wherein, The automatic zeroing comparator is connected to the clock output terminal of the clock adjustment module in the output jitter suppression circuit and the signal acquisition terminal of the first sampling module in the output jitter suppression circuit.

10. A microprocessor architecture, characterized in that, include: The signal processing circuit as described in claim 9.

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