Master-slave station gateway conversion method and system for clock synchronization of upper-layer and lower-layer EtherCAT (Ethernet Control Automation Technology) network

Abstract

The invention belongs to the related technical field of communication, and provides a master-slave station gateway conversion method and system for clock synchronization of upper and lower layers of EtherCAT networks, a gateway performs role adaptive conversion on a lower master station and an upper slave station without additionally deploying independent master station or slave station equipment, so that the hardware architecture of interconnection of multiple EtherCAT networks is simplified, and the communication efficiency is improved. The system deployment complexity and the hardware cost are reduced; the limitation that only cross-network data communication can be realized in a traditional scheme is broken through, and while efficient bidirectional data conversion between a lower-layer EtherCAT subnetwork and an upper-layer EtherCAT main network is completed, an upper-layer network time reference is accurately transmitted to the lower-layer subnetwork through a distributed clock synchronization mechanism, so that cross-network equipment runs at a unified time scale, and the efficiency of the cross-network equipment is improved. The problem of data intercommunication but time asynchronization in multi-network cooperative control is thoroughly solved, and core support is provided for high-precision cooperative operation.

Description

Technical Field

[0001] This invention belongs to the field of communication-related technology, and in particular relates to a master-slave gateway conversion method and system for clock synchronization in upper and lower layer EtherCAT networks. Background Technology

[0002] The statements in this section are merely background information related to the present invention and do not necessarily constitute prior art.

[0003] In the field of industrial automation, the requirements for the real-time performance, reliability, and control precision of equipment communication are becoming increasingly stringent, leading to the widespread research and application of industrial fieldbus technology. Among these, EtherCAT, an industrial fieldbus system launched in 2003 by Beckhoff Automation GmbH in Germany, is a real-time industrial Ethernet technology with significant advantages. Its core architecture employs a master-slave structure, and thanks to its high data transmission rate and low communication latency, it is widely used in various industrial control scenarios.

[0004] In actual industrial production, as production scale expands and control requirements become more complex, a single EtherCAT network often cannot meet the overall control requirements. Therefore, multiple independently operating EtherCAT networks are typically constructed to achieve refined management by region and function. For example, in a hierarchical control system at the workshop and factory levels, workshop-level equipment subnets and factory-level upper-level control networks are set up: the workshop-level equipment subnet uses a local controller as the EtherCAT master station, mainly responsible for managing various sensors and actuators within its area, completing data acquisition and motion control of field equipment; the factory-level upper-level control network uses a central controller as the EtherCAT master station, undertaking the functions of global scheduling and overall management, requiring monitoring the operating status of each workshop-level equipment subnet, and issuing unified control commands.

[0005] To achieve hierarchical control, existing technologies have proposed various schemes for connecting multiple independent EtherCAT networks. Most of these schemes utilize communication gateways to enable data exchange between workshop-level equipment subnets and the factory-level upper-level control network, meeting the upper-level master station's requirements for status monitoring and command issuance to lower-level subnets. However, in industrial scenarios with high time consistency requirements, such as multi-device collaborative processing and high-precision synchronous control, simply implementing data communication is far from sufficient; further clock synchronization between multiple EtherCAT networks is also necessary.

[0006] Current multi-EtherCAT network connection solutions generally suffer from the technical limitation of only enabling data interaction and failing to address clock synchronization. Even those solutions that attempt to introduce clock synchronization mechanisms suffer from low synchronization accuracy, high deployment complexity, and incompatibility with EtherCAT's real-time communication characteristics, making it difficult to meet the application requirements of high-precision collaborative control scenarios. Therefore, how to ensure high-precision clock synchronization between multiple independent EtherCAT networks while achieving cross-network data interaction has become a pressing technical challenge in the field of industrial automation. Summary of the Invention

[0007] To overcome the shortcomings of the prior art, this invention provides a master-slave gateway conversion method and system for clock synchronization between upper and lower EtherCAT networks. The gateway transmits the time base of the upper master network to the lower subnet, enabling devices across networks to operate on a unified time scale, ultimately achieving high-precision collaboration among multiple network devices.

[0008] To achieve the above objectives, the present invention adopts the following technical solution: In a first aspect, the present invention provides a master-slave gateway conversion method for clock synchronization in upper and lower layer EtherCAT networks, applied to upper and lower layer EtherCAT architectures, wherein the upper and lower layer EtherCAT architectures are interconnected through a master-slave conversion gateway, the gateway acting as the EtherCAT master station in the lower layer EtherCAT subnet, and the gateway acting as the EtherCAT slave station in the upper layer EtherCAT master network; the method includes: The gateway obtains the distributed time of the upper-layer EtherCAT network; The gateway master core will receive the distributed time of the upper-layer EtherCAT network and configure it as the system time for itself as the reference clock of the lower-layer EtherCAT subnet master station; The gateway master core uses the system time of the reference clock as a benchmark, starts the distributed clock mode, and distributes the time to all slave devices in the lower layer EtherCAT subnet. It maintains the synchronization state through dynamic drift compensation and transmission delay updates, thereby achieving time synchronization between the upper and lower layer EtherCAT networks.

[0009] Furthermore, the gateway constructs a master interface for connecting to the lower-layer EtherCAT subnet through GMAC0 and a network isolation transformer, and constructs a slave interface for connecting to the upper-layer EtherCAT master network through M0 core SPI0 and FCE1100 slave chip.

[0010] Furthermore, the specific process by which the gateway obtains the distributed time of the upper-layer EtherCAT network is as follows: Before configuring the distributed clock mode, the gateway master core sends a pulse signal. The pulse signal synchronously triggers the pin interrupt of M0 and the LATCH pin of the FCE1100 slave chip, causing the FCE1100 slave chip to store the local time of the current upper-layer EtherCAT network into the time register. After the M0 co-core responds to the interrupt, it reads the time data in the time register through the SPI bus and then transmits it to the gateway master core through the RPMsg emergency data channel.

[0011] Furthermore, the M0 co-core runs the RTThread4.1.1 operating system and the SSCv5.11EtherCAT slave protocol stack, and creates and opens communication endpoints through the preset RPMsg program to realize data interaction with the gateway master core.

[0012] Furthermore, the dynamic drift compensation is implemented by the gateway master core periodically sending xRMW instructions to ensure timely correction of clock drift; the transmission delay update is executed synchronously with the dynamic drift compensation to correct the delay error in the data transmission process in real time.

[0013] Furthermore, the gateway main core and the M0 co-core communicate via the RPMsg protocol and manage the shared memory region based on the VirtIO virtual queue.

[0014] Furthermore, the communication process of the RPMsg protocol is as follows: the RPMsg programs of the main core and the co-core respectively create and open communication endpoints, construct data packets and send them through the corresponding channels, while continuously waiting to receive data packets from the other party, and repeatedly executing sending and receiving operations to achieve bidirectional data interaction.

[0015] Furthermore, after the gateway master core configures the distributed time of the upper-layer EtherCAT network as the reference clock system time, before starting the distributed clock mode, it needs to calculate the initial offset and transmission delay value between the reference time and the local clock of each slave device in the lower-layer EtherCAT subnet, write the offset and delay value to the corresponding address, perform static drift compensation by distributing the reference system time thousands of times, and finally verify whether the universal time base has been established.

[0016] Secondly, this invention provides a master-slave gateway conversion system for clock synchronization in upper and lower layer EtherCAT networks, applied to upper and lower layer EtherCAT architectures. The upper and lower layer EtherCAT architectures are interconnected through a master-slave gateway conversion system. The gateway acts as the EtherCAT master station in the lower layer EtherCAT subnet and as the EtherCAT slave station in the upper layer EtherCAT master network; comprising: The gateway co-core is configured to: obtain the distributed time of the upper-layer EtherCAT network; The gateway core is configured to: receive the distributed time from the upper-layer EtherCAT network and set it as the system time of its own reference clock as the master station of the lower-layer EtherCAT subnet; based on the system time of the reference clock, start the distributed clock mode and distribute the time to all slave devices in the lower-layer EtherCAT subnet, and maintain the synchronization state through dynamic drift compensation and transmission delay updates, thereby achieving time synchronization between the upper and lower-layer EtherCAT networks.

[0017] Thirdly, the present invention provides an electronic device including a memory and a processor, and computer instructions stored in the memory and running on the processor, wherein the computer instructions, when executed by the processor, perform the method described in the first aspect.

[0018] The above one or more technical solutions have the following beneficial effects: In this invention, the gateway adaptively switches between its roles as a master station and a slave station, eliminating the need for additional independent master or slave station devices. This simplifies the hardware architecture of multi-EtherCAT network interconnection and reduces system deployment complexity and hardware costs. Breaking through the limitations of traditional solutions that only enable cross-network data communication, this invention achieves efficient bidirectional data conversion between the lower-level EtherCAT subnet and the upper-level EtherCAT master network. Simultaneously, through a distributed clock synchronization mechanism, it accurately transmits the upper-level network time base to the lower-level subnet, ensuring that cross-network devices operate on a unified time scale. This completely solves the pain point of data interoperability but time asynchrony in multi-network collaborative control, providing core support for high-precision collaborative operations.

[0019] In this invention, the gateway serves as the EtherCAT master station in the lower-layer EtherCAT subnet and as the EtherCAT slave station in the upper-layer EtherCAT master network. The integrated gateway design reduces the number of intermediate devices required for multi-network interconnection, thereby reducing the workload of equipment deployment, cabling, and subsequent maintenance. The heterogeneous multi-core architecture allocates hardware resources on demand, avoiding system instability caused by excessive load on a single core, improving the overall system reliability, and reducing downtime due to failures.

[0020] In this invention, the DC synchronization process following the EtherCAT protocol standard is optimized through initial offset compensation, static drift compensation and dynamic drift compensation, combined with real-time updates of transmission delay, so that the clock synchronization deviation between the upper and lower layers of the network is controlled at the microsecond level, which meets the time synchronization requirements of high-precision scenarios such as industrial robot collaboration and precision manufacturing.

[0021] Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0022] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0023] Figure 1 This is a hardware architecture diagram in an embodiment of the present invention; Figure 2 This is a flowchart of the system operation module in an embodiment of the present invention; Figure 3 This is a schematic diagram of the data flow direction and two Ethercat networks in an embodiment of the present invention; Figure 4 This is a schematic diagram illustrating how the master station, M0, and slave station chip ECS obtain the local time from the upper-layer ethercat in an embodiment of the present invention. Figure 5 This is a flowchart illustrating the process of obtaining the system time of the upper-layer EtherCAT network and synchronizing the lower-layer system time in an embodiment of the present invention. Detailed Implementation

[0024] It should be noted that the following detailed descriptions are exemplary and intended to provide further illustration of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0025] It should be noted that the terminology used herein is for the purpose of describing particular implementations only and is not intended to limit the exemplary implementations of the present invention.

[0026] Where there is no conflict, the embodiments and features in the embodiments of the present invention can be combined with each other.

[0027] Terminology Explanation: System time: The globally unified timing benchmark in the distributed clock mechanism is the core time scale for clock synchronization between upper and lower layer EtherCAT network devices, and is used to unify the time measurement standards of each device.

[0028] Reference clock: According to the EtherCAT protocol definition, it refers to the first slave clock with distributed clock function connected to the master station, or the master station's own local clock, which serves as the reference source for clock synchronization of the entire EtherCAT network.

[0029] Slave Clock: In an EtherCAT network, except for the slave station that acts as the reference clock, the built-in clocks of all other slave devices must be kept in sync with the reference clock through a synchronization mechanism.

[0030] Master clock: The timing module built into the EtherCAT master device has an independent timing function. It can be used as an alternative source of reference clock and participates in the offset and delay calculation during the clock synchronization process.

[0031] Local clock: The physical timing unit built into each slave device that supports distributed clock functionality, providing basic timing for local operation of the slave, but it deviates from the reference clock in the initial state.

[0032] Initial offset: In the early stages of EtherCAT network startup, there is an inherent time difference between the local clock of each slave station and the reference clock. It is a core parameter that needs to be compensated first during clock synchronization.

[0033] Clock drift: Because each DC slave station uses an independent clock source, there are slight differences in their timing cycles. As the running time progresses, the deviation between the local clock and the reference clock gradually accumulates, eventually disrupting the clock synchronization state.

[0034] Local system time: The local clock of each DC slave station is calibrated with the reference clock, offset compensation and drift correction, and the resulting local time is consistent with the global system time. It is the time basis for the slave station to perform collaborative operations.

[0035] Transmission delay: The total delay in which data frames are transmitted between stations in an EtherCAT network. It includes both the processing delay of data in the internal circuitry of the device and the propagation delay on the physical transmission medium. It is a key parameter that needs to be accurately measured and compensated for in clock synchronization.

[0036] Example 1 like Figures 1-5 As shown, this embodiment discloses a master-slave gateway conversion method for clock synchronization in upper and lower layer EtherCAT networks. This method is applied to upper and lower layer EtherCAT architectures, which are interconnected through a master-slave gateway. The gateway acts as the EtherCAT master in the lower layer EtherCAT subnet and as the EtherCAT slave in the upper layer EtherCAT master network. The method includes: The gateway obtains the distributed time of the upper-layer EtherCAT network; The gateway master core will receive the distributed time of the upper-layer EtherCAT network and configure it as the system time for itself as the reference clock of the lower-layer EtherCAT subnet master station; The gateway master core uses the system time of the reference clock as a benchmark, starts the distributed clock mode, and distributes the time to all slave devices in the lower layer EtherCAT subnet. It maintains the synchronization state through dynamic drift compensation and transmission delay updates, thereby achieving time synchronization between the upper and lower layer EtherCAT networks.

[0037] In this embodiment, it is applied to an upper and lower layer EtherCAT architecture. The upper and lower layer EtherCAT architectures are interconnected through a master-slave conversion gateway. The role definition and architectural logic of the gateway are as follows: Gateway to lower-layer EtherCAT subnet: As an EtherCAT master station, it is responsible for collecting status data of devices within the subnet and issuing local control commands; Gateway to upper-layer EtherCAT master network: As an EtherCAT slave station, it is responsible for receiving global scheduling instructions from the upper-layer EtherCAT master station and transmitting data back to the lower-layer subnet; The upper-layer EtherCAT main network uses the central controller as the EtherCAT master station to achieve global scheduling; the lower-layer EtherCAT subnet uses the gateway as the master station to manage the slave devices such as sensors and actuators within the subnet.

[0038] Distributed clock synchronization between two different EtherCAT networks at different layers is achieved through a gateway. This mechanism enables both collaborative control of the upper and lower EtherCAT networks and high-precision coordination among multiple network devices. The DC (Distributed Clock) mechanism synchronizes all slave stations to a single reference clock. The first slave station with distributed clock functionality connected to the master station, or the master station's local time, serves as the reference clock for synchronizing the slave clocks of other slave devices. To achieve precise clock synchronization control, data transmission delay and local clock skew must be measured and calculated, and local clock drift must be compensated for.

[0039] The principle of clock synchronization: Each device's local clock runs freely and will drift from the reference clock. To ensure all devices operate at the same absolute system time, the master station calculates the offset between the reference clock and each slave device's clock and writes this offset to the slaves to calculate their local system time (this part is done by the master station). Using this offset, clock synchronization can be achieved without altering the freely running local clock. Clock drift, on the other hand, is caused by the distributed clocks self-calibrating by comparing the speed of the reference clock and the local clock.

[0040] As a specific implementation method, after the gateway master core configures the distributed time of the upper-layer EtherCAT network as the reference clock system time, before starting the distributed clock mode, it needs to calculate the initial offset and transmission delay value between the reference time and the local clock of each slave device in the lower-layer EtherCAT subnet, write the offset and delay value to the corresponding address, perform static drift compensation by distributing the reference system time thousands of times, and finally verify whether the universal time base has been established.

[0041] Specifically, the core of EtherCAT network distributed clock (DC) synchronization is to establish and continuously maintain a globally unified universal time, i.e., the system time. This process is completed autonomously by the master station without any additional external intervention. Its standard execution flow is divided into a universal time base establishment phase and a system time maintenance phase, with the specific steps as follows: I. Universal Time Base Establishment Phase.

[0042] 1. Determine which slaves support DC mode and identify the synchronous clock bit width: The master station identifies slave devices with distributed clock function in the network by accessing the slave's 0x0008 register address, and confirms the synchronous clock bit width parameters of each DC slave, laying the foundation for subsequent synchronization calibration.

[0043] 2. Network topology detection: The master station obtains the physical connection topology of the entire EtherCAT network by reading the link status register 0x0110 of the slave station, and clarifies the connection relationship and data transmission path between slave stations.

[0044] 3. Reference clock distribution: The master station will send the preset reference clock (which can be the master station's local clock or the clock of the first connected DC slave station, according to the EtherCAT protocol) signal to all slave devices in the EtherCAT network, providing a unified synchronization reference source.

[0045] 4. Acquisition of multi-port reception time and EPU reception time: The master station reads the reception time of all ports (ports 0-3) of each slave station by sending the APRD (AutoIncrementPhysicalRead) instruction to the 0x0900 register address, and at the same time acquires the reception time data of the corresponding 0x0918 register address of the reception time processing unit (EPU).

[0046] 5. Initial offset and transmission delay calculation: Based on the collected multi-port reception time and EPU reception time, the master station accurately calculates the initial offset between the local clock of each slave station and the reference clock, as well as the transmission delay value generated by the data frame during network transmission, through a preset algorithm.

[0047] 6. Offset and delay value configuration writing: The master station writes the calculated initial offset to the slave station's 0x0920 register address and writes the transmission delay value to the slave station's 0x0928 register address to complete the basic synchronization parameter configuration.

[0048] 7. Static drift compensation: The master station repeatedly sends xRMW (Read-Modify-Write) instructions to the 0x0910 register address, distributing the reference system time thousands of times to correct the remaining deviation between the reference system time and the local time of each slave station, and dynamically adjusts the running speed of the slave station clocks to further improve synchronization accuracy.

[0049] 8. Universal Time Base Verification: The master station verifies whether the global universal time base has been successfully established by reading the value at register address 0x092C or register address 0x0932 of the slave station, ensuring that the deviation between each slave station's clock and the reference clock is within a preset threshold range. The value at register address 0x092C reflects the system time difference, and the value at register address 0x0932 reflects the speed counter difference.

[0050] II. System Time Maintenance Phase.

[0051] 1. Dynamic drift compensation: The master station continuously sends xRMW instructions to the slave station's 0x0910 register address according to a periodic strategy (typical period not exceeding 1 millisecond) to correct the cumulative drift of each slave station's clock caused by the characteristics of independent clock sources in real time, and maintain long-term synchronization stability.

[0052] 2. Dynamic update of transmission delay: The master station monitors the network transmission status in real time and dynamically updates the transmission delay parameters of each slave station to ensure the accuracy of delay compensation under scenarios such as network load fluctuations and environmental changes, and to ensure that the clock synchronization accuracy is not affected.

[0053] In one specific implementation, the gateway constructs a master interface for connecting to the lower-layer EtherCAT subnet through GMAC0 and a network isolation transformer, and constructs a slave interface for connecting to the upper-layer EtherCAT master network through M0 core SPI0 and FCE1100 slave chip.

[0054] Specifically, the gateway uses the Rockchip RK3562J chip as its hardware core. This chip integrates four Cortex-A53 application processing cores and one Cortex-M0 real-time coprocessing core, enabling independent deployment and efficient collaboration of master and slave station functions through a heterogeneous multi-core architecture.

[0055] The three Cortex-A53 application cores, running on the Linux operating system and supporting applications, are mainly responsible for non-real-time tasks such as network parameter configuration, control logic operations, and data cleaning and preprocessing, providing basic support for the overall operation of the gateway.

[0056] Dedicated main core deployment: A single Cortex-A53 core (CPU3) is allocated as the main core using core isolation technology. This main core runs the Linux operating system and binds the EtherCAT master station program to this core, enabling independent scheduling of master station tasks. This avoids real-time performance loss caused by task switching between cores and ensures efficient connection management and data interaction for the lower-level EtherCAT subnet.

[0057] Cortex-M real-time co-core function positioning: The Cortex-M real-time co-core is equipped with the lightweight real-time operating system RT-Thread and is dedicated to the EtherCAT slave function. It achieves stable access to the upper-layer EtherCAT main network through standardized protocol adaptation and completes command reception and data backhaul.

[0058] Heterogeneous Core Communication Mechanism: The RPMsg (Remote Processor Messaging) protocol is adopted as the cross-core communication scheme between the main core and the co-core. This protocol manages the shared memory area based on the virtqueue mechanism in the VirtIO architecture, ensuring the security and efficiency of data transmission. Through the interaction of the RPMsg protocol between the main core and the co-core, the forwarding of data from the lower-level subnet to the upper layer and the precise delivery of global scheduling commands from the upper layer to the lower layer are realized. At the same time, multiple independent data channels (including PDO data channels, SDO data channels, and emergency data channels) are opened to further optimize the transmission efficiency of different types of data and meet the differentiated communication needs in industrial control scenarios. As a specific implementation method, the gateway obtains the distributed time of the upper-layer EtherCAT network as follows: Before configuring the distributed clock mode, the gateway master core sends a pulse signal. The pulse signal synchronously triggers the pin interrupt of M0 and the LATCH pin of the FCE1100 slave chip, causing the FCE1100 slave chip to store the local time of the current upper-layer EtherCAT network into the time register. After the M0 co-core responds to the interrupt, it reads the time data in the time register through the SPI bus and then transmits it to the gateway master core through the RPMsg emergency data channel.

[0059] In this embodiment, the hardware configuration is as follows: Core processor configuration: It adopts Rockchip RK3562J heterogeneous multi-core processor, which integrates 4 Cortex-A53 application processing cores (1.6GHz) and 1 Cortex-M0 real-time coprocessor core (200MHz). Through multi-core division of labor and cooperation, it realizes independent deployment and efficient collaboration of master and slave station functions.

[0060] Master station interface design: Configure the GMAC0 interface (operating in RMII mode), and use it with the network isolation transformer to form the master station communication interface of the lower EtherCAT subnet, so as to realize a stable physical connection and data transmission with the slave devices in the device subnet.

[0061] Slave interface design: Based on the M0 co-core extended SPI0 interface (communication rate 20MHz), an external FCE1100 EtherCAT slave controller chip is connected. Through the chip's ETH port and an isolation transformer, a slave access interface with the upper-layer EtherCAT main network is constructed to ensure the reliability of cross-network communication.

[0062] Storage and Power System: Equipped with a 2GB DDR4 memory module and a 16GB eMMC storage module to meet the requirements of system operation, protocol stack loading and data caching; the power system adopts a DC12V input design, which is converted to a stable 3.3V / 1.8V power supply by a dedicated power management chip to provide the processor, interface chip and peripherals with the specified operating voltage.

[0063] In this embodiment, the software implementation steps are as follows: (a) Single Cortex-A53 main core (Linux system) configuration.

[0064] Kernel environment setup: The system uses Linux kernel version 5.10 and integrates the RT_PREEMPT real-time patch to improve the system interrupt response speed and task scheduling real-time performance, meeting the real-time control requirements of the EtherCAT master station.

[0065] Runtime environment isolation: Dedicated isolation of the 3 CPU cores is achieved through system environment variable configuration, which are used only to run the EtherCAT master station program, avoiding scheduling delays caused by task switching between multiple cores and ensuring the real-time performance and stability of the master station function.

[0066] Master station protocol stack deployment: EtherCAT master station protocol stack of IGHv1.5.2 is installed, the master station identifier is configured as "ec_master0", the default communication period of the master station is set to T1=1000μs, and the periodic data acquisition and command issuance to the slave station devices of the lower subnet are realized.

[0067] RPMsg communication program development: Create and open communication endpoints, construct data packets and send them through the corresponding channels, while continuously waiting to receive data packets from the other party. Execute the sending and receiving operations in a loop to achieve bidirectional data interaction, realizing efficient data interaction with the co-core slave program; simultaneously, open PDO (Process Data Object) channels, SDO (Service Data Object) channels, and emergency data channels to respectively carry the transmission of real-time process data, configuration data, and emergency event information, optimizing communication efficiency and data transmission security.

[0068] (ii) Cortex-M0 co-core (RTThread system) configuration.

[0069] Real-time operating system deployment: Equipped with the lightweight real-time operating system RTThread 4.1.1, which leverages its high real-time performance and low resource consumption to meet the operational requirements of EtherCAT slave functions.

[0070] Slave protocol stack deployment: Integrate the SSCv5.11 version EtherCAT slave protocol stack, configure it as a standard slave working mode, set the default communication period of the slave T2=1000μs, and realize protocol adaptation and data interaction with the upper layer EtherCAT master station.

[0071] RPMsg communication program development: Through processes such as endpoint creation, connection initialization, data packet construction, and send / receive loop, bidirectional data interaction with the main core master station program is realized; PDO data channels, SDO data channels, and emergency data channels are opened simultaneously, corresponding one-to-one with the main core communication channels, to ensure the classification, transmission, and interaction compatibility of different types of data.

[0072] In this embodiment, the specific steps of distributed clock synchronization are as follows: I. Clock synchronization establishment phase.

[0073] Before the EtherCAT master station initiates the distributed clock (DC) mode configuration, it sends a synchronization pulse signal to a designated pin. This pulse signal triggers two actions simultaneously: first, the Cortex-M0 co-core (M0 core) running the EtherCAT slave program generates a pin interrupt; second, it triggers the LATCH pin of the slave controller chip (ESC chip FCE1100), causing the chip to latch the local time of the slave in the current upper-layer EtherCAT network into the chip's built-in time register, thus completing the real-time acquisition of time data.

[0074] After the Cortex-M0 co-core responds to the interrupt signal triggered by the pulse, it accesses the time register of the FCE1100 chip via the SPI bus (communication rate 20MHz) to accurately read the latched local time data of the upper-layer EtherCAT network slave, ensuring the accuracy and real-time performance of time acquisition.

[0075] After the Cortex-M0 co-core obtains the time data from the upper-layer network, it transmits the time data at high speed to the Cortex-A53 main core (CPU3) running the EtherCAT master program through a pre-established RPMsg emergency data channel, ensuring the priority and security of time data transmission.

[0076] Before the EtherCAT master station starts the DC synchronization function, the master core will receive the upper-layer network time data and configure it as the distributed clock (DC) reference clock system time for itself as the master station of the lower-layer EtherCAT subnet, so as to achieve the alignment of the time base of the upper and lower layers of the network.

[0077] The master core uses the calibrated reference clock system time as a benchmark, starts the DC synchronization function, and distributes the unified time benchmark to all slave devices in the lower-level EtherCAT subnet through the EtherCAT master station protocol stack, thus completing the initial synchronization of the lower-level network clock.

[0078] II. System Time Maintenance Phase The master station operates continuously according to the DC synchronization maintenance mechanism of the EtherCAT protocol standard. It achieves dynamic drift compensation by periodically sending xRMW (Read-Modify-Write) instructions to the slave station's 0x0910 register address (typically with a period of no more than 1 millisecond). At the same time, it updates the transmission delay parameters in real time to ensure the long-term stability of the clock synchronization state of the upper and lower layer EtherCAT networks and maintain the consistency of the global time base.

[0079] This embodiment employs a time acquisition mechanism that combines synchronous pulse triggering, chip latching, and high-speed cross-core transmission: the synchronous pulse sent by the master station simultaneously triggers the M0 co-core interrupt and the LATCH pin of the FCE1100 chip, enabling real-time latching of the upper-layer network time. This is then read at high speed via the SPI bus and transmitted through the RPMsg emergency channel, minimizing errors during time acquisition and transmission and ensuring accurate acquisition of the upper-layer time reference.

[0080] This embodiment follows the DC synchronization process of the EtherCAT protocol standard. Through the optimization of the entire process of initial offset compensation, static drift compensation and dynamic drift compensation, combined with real-time updates of transmission delay, the clock synchronization deviation between the upper and lower layers of the network is controlled at the microsecond level, which meets the time synchronization requirements of high-precision scenarios such as industrial robot collaboration and precision manufacturing.

[0081] Example 2 The purpose of this embodiment is to provide a master-slave gateway conversion system for clock synchronization in upper and lower layer EtherCAT networks. This system is applied to upper and lower layer EtherCAT architectures, which are interconnected through a master-slave conversion gateway. The gateway acts as the EtherCAT master in the lower layer EtherCAT subnet and as the EtherCAT slave in the upper layer EtherCAT master network. The system includes: The gateway co-core is configured to: obtain the distributed time of the upper-layer EtherCAT network; The gateway core is configured to: receive the distributed time from the upper-layer EtherCAT network and set it as the system time of its own reference clock as the master station of the lower-layer EtherCAT subnet; based on the system time of the reference clock, start the distributed clock mode and distribute the time to all slave devices in the lower-layer EtherCAT subnet, and maintain the synchronization state through dynamic drift compensation and transmission delay updates, thereby achieving time synchronization between the upper and lower-layer EtherCAT networks.

[0082] In further embodiments, the following is also provided: An electronic device includes a memory and a processor, as well as computer instructions stored in the memory and running on the processor. When executed by the processor, the computer instructions perform the method described in Embodiment 1. For brevity, further details are omitted here.

[0083] It should be understood that in this embodiment, the processor can be a central processing unit (CPU), or it can be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor, etc.

[0084] Memory may include read-only memory and random access memory, and provides instructions and data to the processor. A portion of memory may also include non-volatile random access memory. For example, memory may also store information about the device type.

[0085] A computer-readable storage medium for storing computer instructions, which, when executed by a processor, perform the method described in Embodiment 1.

[0086] The method in Embodiment 1 can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor. The software modules can reside in readily available storage media in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method. To avoid repetition, a detailed description is not provided here.

[0087] A computer program product includes a computer program that, when executed by a processor, implements the method described in Embodiment 1.

[0088] The present invention also provides at least one computer program product tangibly stored on a non-transitory computer-readable storage medium. The computer program product includes computer-executable instructions, such as instructions included in program modules, which execute in a device on a target real or virtual processor to perform the processes / methods described above. Typically, program modules include routines, programs, libraries, objects, classes, components, data structures, etc., that perform specific tasks or implement specific abstract data types. In various embodiments, the functionality of program modules can be combined or divided among program modules as needed. The machine-executable instructions for the program modules can execute within a local or distributed device. In a distributed device, the program modules can reside in both local and remote storage media.

[0089] The computer program code used to implement the methods of the present invention may be written in one or more programming languages. This computer program code may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the computer or other programmable data processing device, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a computer, partially on a computer, as a stand-alone software package, partially on a computer and partially on a remote computer, or entirely on a remote computer or server.

[0090] In the context of this invention, computer program code or related data may be carried by any suitable carrier to enable a device, apparatus, or processor to perform the various processes and operations described above. Examples of carriers include signals, computer-readable media, and the like. Examples of signals may include electrical, optical, radio, sound, or other forms of propagation signals, such as carrier waves, infrared signals, etc.

[0091] Those skilled in the art will recognize that the units and algorithm steps described in conjunction with the embodiments herein can be implemented in electronic hardware or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0092] While the specific embodiments of the present invention have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solutions of the present invention are still within the scope of protection of the present invention.

Claims

1. A master-slave gateway conversion method for clock synchronization in upper and lower layer EtherCAT networks, characterized in that, This method is applied to upper and lower layer EtherCAT architectures, where the upper and lower layer EtherCAT architectures are interconnected through a master-slave conversion gateway. The gateway acts as the EtherCAT master station in the lower layer EtherCAT subnet and as the EtherCAT slave station in the upper layer EtherCAT master network. The method includes: The gateway obtains the distributed time of the upper-layer EtherCAT network; The gateway master core will receive the distributed time of the upper-layer EtherCAT network and configure it as the system time for itself as the reference clock of the lower-layer EtherCAT subnet master station; The gateway master core uses the system time of the reference clock as a benchmark, starts the distributed clock mode, and distributes the time to all slave devices in the lower layer EtherCAT subnet. It maintains the synchronization state through dynamic drift compensation and transmission delay updates, thereby achieving time synchronization between the upper and lower layer EtherCAT networks.

2. The master-slave gateway conversion method for clock synchronization in an upper and lower layer EtherCAT network as described in claim 1, characterized in that, The gateway constructs a master interface for connecting to the lower-level EtherCAT subnet through GMAC0 and a network isolation transformer, and constructs a slave interface for connecting to the upper-level EtherCAT master network through M0 core SPI0 and FCE1100 slave chip.

3. The master-slave gateway conversion method for therCAT network clock synchronization as described in claim 1, characterized in that, The specific process by which the gateway obtains the distributed time of the upper-layer EtherCAT network is as follows: Before configuring the distributed clock mode, the gateway master core sends a pulse signal. The pulse signal synchronously triggers the pin interrupt of M0 and the LATCH pin of the FCE1100 slave chip, causing the FCE1100 slave chip to store the local time of the current upper-layer EtherCAT network into the time register. After the M0 co-core responds to the interrupt, it reads the time data in the time register through the SPI bus and then transmits it to the gateway master core through the RPMsg emergency data channel.

4. The master-slave gateway conversion method for therCAT network clock synchronization as described in claim 3, characterized in that, The M0 co-core runs the RTThread4.1.1 operating system and the SSCv5.11EtherCAT slave protocol stack. It creates and opens communication endpoints through the preset RPMsg program to achieve data interaction with the gateway master core.

5. The master-slave gateway conversion method for therCAT network clock synchronization as described in claim 1, characterized in that, The dynamic drift compensation is achieved by periodically sending xRMW instructions through the gateway master core to ensure timely correction of clock drift; the transmission delay update is executed synchronously with the dynamic drift compensation to correct the delay error in the data transmission process in real time.

6. The master-slave gateway conversion method for therCAT network clock synchronization as described in claim 1, characterized in that, The gateway main core and the M0 co-core communicate via the RPMsg protocol and manage the shared memory region based on the VirtIO virtual queue.

7. The master-slave gateway conversion method for therCAT network clock synchronization as described in claim 6, characterized in that, The communication process of the RPMsg protocol is as follows: the RPMsg programs of the main core and the co-core respectively create and open communication endpoints, construct data packets and send them through the corresponding channels, while continuously waiting to receive data packets from the other party, and repeatedly executing sending and receiving operations to achieve bidirectional data interaction.

8. A master-slave gateway conversion method for therCAT network clock synchronization as described in claim 1 or 5, characterized in that, After configuring the distributed time of the upper-layer EtherCAT network as the reference clock system time, the gateway master core needs to calculate the initial offset and transmission delay value between the reference time and the local clock of each slave device in the lower-layer EtherCAT subnet before starting the distributed clock mode. The offset and delay value are written to the corresponding address, static drift compensation is performed by distributing the reference system time thousands of times, and finally the universal time base is verified to be established.

9. A master-slave gateway conversion system for clock synchronization in upper and lower layer EtherCAT networks, characterized in that, It is applied to upper and lower layer EtherCAT architectures, which are interconnected through master-slave conversion gateways. The gateway acts as the EtherCAT master station of the lower layer EtherCAT subnet and as the EtherCAT slave station of the upper layer EtherCAT master network. include: The gateway co-core is configured to: obtain the distributed time of the upper-layer EtherCAT network; The gateway core is configured to: receive the distributed time from the upper-layer EtherCAT network and set it as the system time of its own reference clock as the master station of the lower-layer EtherCAT subnet; based on the system time of the reference clock, start the distributed clock mode and distribute the time to all slave devices in the lower-layer EtherCAT subnet, and maintain the synchronization state through dynamic drift compensation and transmission delay updates, thereby achieving time synchronization between the upper and lower-layer EtherCAT networks.

10. An electronic device, characterized in that, It includes a memory and a processor, as well as computer instructions stored in the memory and running on the processor, which, when executed by the processor, perform the method according to any one of claims 1-8.

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