8T SRAM (Static Random Access Memory) unit, 8T SRAM and preparation method thereof

Abstract

The invention provides an 8T SRAM (Static Random Access Memory) unit, an 8T SRAM and a preparation method thereof, the 8T SRAM unit comprises a substrate, a pull-up transistor group, a pull-down transistor group and a transmission gate transistor group, the pull-up transistor group and the transmission gate transistor group are integrated on the front surface of the substrate, the pull-down transistor group is integrated on the back surface of the substrate, and the transmission gate transistor group is integrated on the back surface of the substrate. The first pull-down group comprises a first pull-down transistor and a second pull-down transistor which are arranged in parallel, and the second pull-down group comprises a third pull-down transistor and a fourth pull-down transistor which are arranged in parallel; the first pull-up transistor and the first pull-down group form a first phase inverter, the second pull-up transistor and the second pull-down group form a second phase inverter, and the first phase inverter and the second phase inverter are in cross coupling; the transmission gate transistor group comprises a first transmission gate transistor and a second transmission gate transistor, the first transmission gate transistor is connected with the first phase inverter, and the second transmission gate transistor is connected with the second phase inverter. According to the invention, the stability of the SRAM unit is improved.

Description

Technical Field

[0001] This application belongs to the field of semiconductor design and manufacturing technology, and in particular relates to an 8T SRAM cell, an 8T SRAM and its fabrication method. Background Technology

[0002] With the continuous evolution of semiconductor process nodes, Static Random Access Memory (SRAM), as an indispensable key component of System-on-Chip (SoC), faces increasingly severe challenges in terms of integration density and performance. Because SRAM occupies a considerable area on the chip, it has become a key bottleneck restricting the overall area efficiency and cost of the chip.

[0003] For a traditional 6-transistor (6T) SRAM cell, read and write operations share the same pair of transistors and data path. At low operating voltages, read operations can temporarily cause voltage disturbances on the memory node. Due to fluctuations in the transistor threshold voltage, these disturbances can easily exceed the cell's noise margin, causing abnormal flips. This leads to a significant decrease in the SRAM cell's read static noise margin (RSNM), directly affecting chip yield and reliability.

[0004] To address these challenges, academia and industry have proposed various multi-transistor SRAM cell solutions, such as 8T and 10T. These solutions typically eliminate read interference by adding independent read ports. However, increasing the number of transistors usually increases the cell area, which contradicts the trend towards high-density memory. Therefore, how to improve the stability of SRAM cells without sacrificing or even optimizing cell area is a key technical bottleneck that urgently needs to be solved in the current memory design field. Summary of the Invention

[0005] To address all or part of the problems of the prior art, this application provides an 8T SRAM cell, an 8TSRAM, and a method for fabricating the same, so as to improve the stability of the SRAM cell without sacrificing or even optimizing the cell area.

[0006] To achieve the above objectives, a first aspect of this application provides an 8T SRAM cell, comprising: a substrate, and a pull-up transistor group, a pull-down transistor group, and a transmission gate transistor group formed on the substrate, wherein the pull-up transistor group and the transmission gate transistor group are integrated on the front side of the substrate, and the pull-down transistor group is integrated on the back side of the substrate, wherein... The pull-up transistor group includes a first pull-up transistor and a second pull-up transistor; The pull-down transistor group includes a first pull-down group and a second pull-down group; the first pull-down group includes a first pull-down transistor and a second pull-down transistor connected in parallel, and the second pull-down group includes a third pull-down transistor and a fourth pull-down transistor connected in parallel; the first pull-up transistor and the first pull-down group form a first inverter, and the second pull-up transistor and the second pull-down group form a second inverter, and the first inverter and the second inverter are cross-coupled; The transmission gate transistor group connects word lines and bit lines, including a first transmission gate transistor and a second transmission gate transistor. The first transmission gate transistor is connected to the first inverter, and the second transmission gate transistor is connected to the second inverter.

[0007] In some embodiments, the first pull-up transistor and the first pull-down group are connected to form a first memory node n1, and the second pull-up transistor and the second pull-down group are connected to form a second memory node n2. The positions of the first memory node n1 and the second memory node n2 include: The first storage node n1 and the second storage node n2 are disposed on the same surface of the substrate; or One of the first storage node n1 and the second storage node n2 is disposed on the front side of the substrate, and the other is disposed on the back side of the substrate.

[0008] In some embodiments, the bit line pair includes bit line BL and bit line inverse BLB; in the transmission gate transistor group, The gates of the first and second transmission gate transistors are connected to the word line WL; The drain of the first transmission gate transistor is connected to the bit line BL, and the source of the first transmission gate transistor is connected to the first inverter; the bit line pair includes the bit line BL and the bit line inverse BLB; The drain of the second transmission gate transistor is connected to the bit line inverted BLB, and the source of the second transmission gate transistor is connected to the second inverter.

[0009] In some embodiments, the first pull-up transistor and the second transmission gate transistor are arranged side by side along a first direction, and the second pull-up transistor and the first transmission gate transistor are arranged side by side along the first direction; the first pull-up transistor and the first transmission gate transistor are arranged side by side along a second direction, and the second pull-up transistor and the second transmission gate transistor are arranged side by side along a second direction, the second direction being perpendicular to the first direction. The first pull-up transistor on the front side of the substrate is self-aligned with the first pull-down transistor on the back side of the substrate; the first transmission gate transistor on the front side of the substrate is self-aligned with the second pull-down transistor on the back side of the substrate; the second pull-up transistor on the front side of the substrate is self-aligned with the third pull-down transistor on the back side of the substrate; and the second transmission gate transistor on the front side of the substrate is self-aligned with the fourth pull-down transistor on the back side of the substrate.

[0010] In some embodiments, in the first pull-down group, the gate, source, and drain of the first pull-down transistor are shared with the gate, source, and drain of the second pull-down transistor, respectively; In the second pull-down group, the gate, source, and drain of the third pull-down transistor are shared with the gate, source, and drain of the fourth pull-down transistor.

[0011] In some embodiments, the gate of the first pull-up transistor and the gate of the first pull-down group are connected by a first gate coupling metal through the substrate, the drain of the first pull-up transistor and the source of the first transmission gate transistor are connected to a first M0 metal, the drain of the first pull-down group is connected to a first B_M0 metal, and the first M0 metal and the first B_M0 metal are connected by a first source-drain coupling metal through the substrate. The gate of the second pull-up transistor and the gate of the second pull-down group are connected by a second gate coupling metal that penetrates the substrate. The drain of the second pull-up transistor and the source of the second transmission gate transistor are connected to the first M0 metal. The drain of the second pull-down group is connected to the first B_M0 metal. The first M0 metal and the first B_M0 metal are connected by a second source-drain coupling metal that penetrates the substrate. A cutting layer is provided on the first M0 metal located between the first source-drain coupling metal and the second source-drain coupling metal; a cutting layer is provided on the first B_M0 metal located between the first source-drain coupling metal and the second source-drain coupling metal.

[0012] In some embodiments, the gate of the first transmission gate transistor and the gate of the second transmission gate transistor are connected to the word line in sequence through the first M1 metal and the M2 metal, respectively; The drain of the first transmission gate transistor is connected to the second M0 metal, and the second M0 metal is connected to the bit line BL through the second M1 metal; the drain of the second transmission gate transistor is connected to the third M0 metal, and the third M0 metal is connected to the bit line BLB in reverse through the third M1 metal.

[0013] In some embodiments, the source of the first pull-up transistor is connected to the first B_M1 metal in sequence through the third M0 metal, the third source-drain coupling metal penetrating the substrate, and the third B_M0 metal; the source of the second pull-up transistor is connected to the first B_M1 metal in sequence through the second M0 metal, the fourth source-drain coupling metal penetrating the substrate, and the second B_M0 metal, and the first B_M1 metal is connected to the power supply Vdd. In the first pull-down group, the source of the first pull-down transistor is connected to the second B_M1 metal through the third B_M0 metal, the source of the second pull-down transistor is connected to the second B_M1 metal through the second B_M0 metal, and the second B_M1 metal is connected to ground Vss. In the second pull-down group, the source of the third pull-down transistor is connected to the third B_M1 metal through the second B_M0 metal, the source of the fourth pull-down transistor is connected to the third B_M1 metal through the third B_M0 metal, and the third B_M1 metal is connected to ground Vss.

[0014] In some embodiments, the first source-drain coupling metal and the second source-drain coupling metal are disposed inside the 8T SRAM cell, wherein the inside of the 8T SRAM cell refers to the area between each transistor in the 8T SRAM cell, and the outside of the 8T SRAM cell refers to the area outside the inside of the 8T SRAM cell.

[0015] A second aspect of this application provides an 8T SRAM, comprising an array-arranged 8T SRAM group, wherein, Each of the 8T SRAM groups includes at least four 8T SRAM cells as described in the first aspect above, wherein adjacent 8T SRAM cells in each of the 8T SRAM groups are symmetrically arranged.

[0016] A third aspect of this application provides a method for preparing an 8T SRAM as described in the second aspect above, comprising the following steps: Forming a substrate; The pull-up transistor group and the transmission gate transistor group are selected as the front structure of the substrate, and the pull-down transistor group is selected as the back structure of the substrate. A first process for forming the front structure is performed. The formation of the front structure includes the first process and the second process performed sequentially, and the second process includes a metal gate process. The substrate is flipped at least twice to form the back side structure of the substrate, and a second process for forming the front side structure is performed.

[0017] In some embodiments, the process of flipping the substrate at least twice to form the back side structure of the substrate, and performing the second stage process for forming the front side structure, includes: The substrate is first flipped during wafer bonding and then a third process for forming the backside structure is performed; the formation of the backside structure includes the third and fourth processes performed sequentially; the third or fourth process includes a metal gate process; The substrate is flipped a second time to perform the second stage of the process for forming the front-side structure; The substrate is flipped a third time to perform the fourth process for forming the backside structure.

[0018] The 8T SRAM cell provided in this application has the following beneficial effects: (1) This application improves the traditional 6T SRAM by setting a pull-down transistor group including a first pull-down group and a second pull-down group; the first pull-down group includes a first pull-down transistor and a second pull-down transistor connected in parallel, and the second pull-down group includes a third pull-down transistor and a fourth pull-down transistor connected in parallel. This effectively increases the effective width of the pull-down transistors and thus increases the current flowing through the pull-down transistors. This solves the problem of low static noise tolerance and easy data error caused by read interference in traditional 6T SRAM under advanced process nodes and low voltage, and improves read stability.

[0019] (2) Existing SRAM improves stability by adding transistors, but this results in an excessively large SRAM cell area, which is difficult to meet the requirements of high-density integration. The 8T SRAM cell of this application adopts the flip FET process to build N / P type transistors on both the front and back sides of the wafer, realizing the device design of double-sided active regions. Moreover, the two added pull-down transistors do not introduce additional area, effectively reducing the overall area of ​​SRAM. This not only improves the stability and anti-interference ability of SRAM cells, but also maintains high integration density, achieving a balance between performance and area.

[0020] (3) In traditional SRAM planar layout, power and signal compete for wiring resources in the same metal layer plane. As transistor density increases, wiring becomes extremely crowded, leading to increased interconnect resistance and capacitance (RC) delay, which seriously affects the read and write speed of SRAM and increases power consumption. The technical solution of this application can flexibly route the wiring, greatly reducing the problems caused by wiring. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the specific embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 A schematic diagram of the circuit structure of an 8T SRAM cell provided in an embodiment of this application.

[0023] Figure 2 This application provides a front-middle section layout of an 8T SRAM cell according to an embodiment of the present application, wherein... Figure 2 A represents the front view. Figure 2 B represents the reverse side of the design.

[0024] Figure 3 for Figure 2 The embodiment provides a back-end structure layout of an 8T SRAM cell, wherein, Figure 3 A represents the front view. Figure 3 B represents the reverse side of the design.

[0025] Figure 4 for Figure 2 A schematic cross-sectional view of the 8T SRAM cell provided in the embodiment along the a - a' direction.

[0026] Figure 5 for Figure 2 A schematic cross-sectional view of the 8T SRAM cell along the b-b' direction provided in the embodiment.

[0027] Figure 6 for Figure 2 A schematic cross-sectional view of the 8T SRAM cell along the c-c' direction provided in the embodiment.

[0028] Figure 7 This is a front-side structural layout of the substrate of an 8T SRAM group in an embodiment of this application.

[0029] Figure 8 for Figure 7 Enlarged schematic diagram of point M in the middle.

[0030] Figure 9 This is a back-side structure layout of the substrate of an 8T SRAM group in an embodiment of this application.

[0031] Figure 10 for Figure 9 A magnified diagram of point N in the middle.

[0032] Figure 11A front-middle section layout of an 8T SRAM cell is provided in another embodiment of this application, wherein, Figure 11 A represents the front view. Figure 11 B represents the reverse side of the design.

[0033] Figure 12 for Figure 11 The embodiment provides a back-end structure layout of an 8T SRAM cell, wherein, Figure 12 A represents the front view. Figure 12 B represents the reverse side of the design.

[0034] Figure 13 A front-middle section layout of an 8T SRAM cell is provided in another embodiment of this application, wherein, Figure 13 A represents the front view. Figure 13 B represents the reverse side of the design.

[0035] Figure 14 for Figure 13 The embodiment provides a back-end structure layout of an 8T SRAM cell, wherein, Figure 14 A represents the front view. Figure 14 B represents the reverse side of the design.

[0036] Figure 15 This is a schematic flowchart illustrating the preparation method of the 8T SRAM provided in this application embodiment.

[0037] Figure descriptions: 10, M0 metal layer; 11, First M0 metal; 12, Second M0 metal; 13, Third M0 metal; 14, M0G metal; 20, B_M0 metal layer; 21, First B_M0 metal; 22, Second B_M0 metal; 23, Third B_M0 metal; 24, B_M0G metal; 30, M1 metal layer; 31, First M1 metal; 32, Second M1 metal; 33, Third M1 metal; 40, B_M1 metal layer; 41, First B_M1 metal; 42, Second B_M1 metal; 43, Third B_M1 metal; 50, M2 metal layer; 51, M2 metal; DM1, First source / drain coupling metal; DM2, Second source / drain coupling metal; DM3, Third source / drain coupling metal; DM4, Fourth source / drain coupling metal; GM1, First gate coupling metal; GM2, Second gate coupling metal. Detailed Implementation

[0038] The foregoing and other technical contents, features, and effects of this application will be clearly presented in the following detailed description of preferred embodiments with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front, or back, are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the scope of this application.

[0039] Static Random Access Memory (SRAM) is an important type of memory widely used in computers, embedded systems, and various electronic devices. A basic SRAM storage cell typically consists of six transistors (6-Transistor, 6T), forming a flip-flop circuit to store one bit of data. Due to its fast access speed and the fact that it does not require periodic refresh, SRAM has become an indispensable component of many systems.

[0040] For a traditional 6T SRAM cell, read and write operations share the same pair of transistors and data path. At low operating voltages, read operations can temporarily cause voltage disturbances on the memory node. Due to fluctuations in the transistor threshold voltage, these disturbances can easily exceed the cell's noise margin, causing abnormal flips. This leads to a severe decrease in the SRAM cell's read stability (RSNM), directly affecting the chip's yield and reliability.

[0041] To address these challenges, multi-transistor SRAM cell solutions (such as 8T SRAM) typically eliminate read interference by adding independent read ports. However, increasing the number of transistors usually increases cell area, which contradicts the trend towards high-density memory. Therefore, improving the stability of SRAM cells without sacrificing or even optimizing cell area is a key technical bottleneck that urgently needs to be solved in the current memory design field.

[0042] Based on this, this application provides an 8T SRAM cell, including: a substrate, and a pull-up (PU) transistor group, a pull-down (PD) transistor group and a pass gate (PG) transistor group formed on the substrate.

[0043] The substrate includes a front side and a back side. In this embodiment, the PU transistor group and the PG transistor group are integrated on the front side of the substrate, and the PD transistor group is integrated on the back side of the substrate. It is understood that "front side" and "back side" are relative terms, depending on the substrate placement and design requirements. In this application, by flexibly defining "front side" and "back side," some transistor groups are integrated on the back side to fully utilize the back side space of the substrate, enabling a device design with double-sided active regions. This effectively reduces the area of ​​the 8T SRAM, frees up wiring space, greatly simplifies signal line layout design, relaxes design constraints, significantly increases the manufacturing process window, effectively reduces parasitic capacitance and resistance, and improves the stability and operating speed of the 8T SRAM cell.

[0044] At extremely small physical dimensions, transistor performance is highly sensitive to process variation. Asymmetric 8T SRAM layouts amplify this variation, leading to decreased cell read / write stability (noise margin, SNM), which in turn affects the yield and reliability of large-scale 8T SRAM cell arrays.

[0045] Based on this, such as Figures 1-10 As shown, the PU transistor group in this application is connected to the power supply Vdd and includes a first pull-up transistor PU1 and a second pull-up transistor PU2. The PD transistor group is connected to ground Vss and includes a first pull-down group PD10 and a second pull-down group PD20.

[0046] In this embodiment, the first pull-up transistor PU1 and the first pull-down group PD10 form a first inverter. The source of the first pull-up transistor PU1 is connected to the power supply Vdd, and its drain is connected to the drain of the first pull-down group PD10. The source of the first pull-down group PD10 is connected to ground Vss. The gates of the first pull-up transistor PU1 and the first pull-down group PD10 together serve as the input terminal of the first inverter, and their drains together serve as the output terminal of the first inverter. The second pull-up transistor PU2 and the second pull-down group PD20 form a second inverter. The source of the second pull-up transistor PU2 is connected to the power supply Vdd, and its drain is connected to the drain of the second pull-down group PD20. The source of the second pull-down group PD20 is connected to ground Vss. The gates of the second pull-up transistor PU2 and the second pull-down group PD20 together serve as the input terminal of the second inverter, and their drains together serve as the output terminal of the second inverter. For the first inverter, the first pull-up transistor PU1 and the first pull-down group PD10 are connected to form a first memory node n1. For the second inverter, the second pull-up transistor PU2 and the second pull-down group PD20 are connected to form the second memory node n2. The output terminal of the first inverter (first memory node n1) is connected to the input terminal of the second inverter, and the output terminal of the second inverter (second memory node n2) is connected to the input terminal of the first inverter. The two inverters are cross-coupled to form a stable memory cell.

[0047] The transmission gate transistor group connects the word line (WL) and bit line pairs, where each bit line pair includes a bit line (BL) and a bit line bar (BLB). The transmission gate transistor group includes a first transmission gate transistor PG1 and a second transmission gate transistor PG2. The first transmission gate transistor PG1 is connected to the first inverter, and the second transmission gate transistor PG2 is connected to the second inverter, thereby enabling control and access to stored data. Specifically, in the transmission gate transistor group, the gate of the first transmission gate transistor PG1 is connected to the word line WL, and its source and drain are connected to the output of the first inverter and the bit line BL, respectively. Similarly, the gate of the second transmission gate transistor PG2 is connected to the word line WL, and its source and drain are connected to the output of the second inverter and the bit line bar (BLB), respectively.

[0048] This configuration integrates the two pull-up transistors (PU1, PU2), two pull-down groups (PD10, PD20), and two transmission gate transistors (PG1, PG2) onto the same side plane of the substrate, reducing interference caused by process variations (for example, in semiconductor manufacturing, the thermal budget has a significant impact on device performance; if the two transmission gate transistors PG1 and PG2 are on different sides, their electrical performance may differ significantly). The matching of each transistor group is better, improving read / write stability. Furthermore, the PU, PD, and PG transistor groups can be easily adjusted individually in the process, offering greater flexibility. Whether adjusting the channel length, work function, or other different process conditions, the electrical characteristics of the transistors can be effectively optimized, thereby improving the performance of the 8T SRAM. Simultaneously, this adjustment method eliminates the need for additional photomask steps, helping to reduce costs and manufacturing complexity.

[0049] To ensure stable read operations of 8T SRAM, the drive capability of the pull-down transistor group needs to be stronger than that of the transmission gate transistor group. This is typically characterized by the β ratio, defined as β ratio = IPD / IPG. In planar transistor technology, when the PD width > PG width, the β ratio is greater than 1. In FinFET technology, when the number of fins in the PD is greater than that in the PG, the β ratio is also greater than 1. Simultaneously, to ensure stable write operations, the drive capability of the PG needs to be stronger than that of the PU. This is typically characterized by the γ ratio, defined as γ ratio = IPG / IPU. In planar transistor technology, when the PG width > PU width, the γ ratio is greater than 1. In FinFET technology, when the number of fins in the PG is greater than that in the PU, the γ ratio is also greater than 1.

[0050] In this embodiment, the first pull-down group PD10 includes a first pull-down transistor PD11 and a second pull-down transistor PD12 connected in parallel, and the second pull-down group PD20 includes a third pull-down transistor PD21 and a fourth pull-down transistor PD22 connected in parallel. Specifically, in the first pull-down group PD10, the gate, source, and drain of the first pull-down transistor PD11 are shared with the gate, source, and drain of the second pull-down transistor PD12, respectively; and in the second pull-down group PD20, the gate, source, and drain of the third pull-down transistor PD21 are shared with the gate, source, and drain of the fourth pull-down transistor PD22, respectively.

[0051] In the above embodiment, the core latch structure is innovatively improved, consisting of two PU transistors and four PD transistors. The four PD transistors are divided into two pull-down groups (PD11 and PD12, PD21 and PD22), with two PD transistors in each pull-down group operating in parallel. This parallel structure effectively increases the effective width and drive current of the pull-down transistors, significantly improving the β ratio of the 8T SRAM cell (the ratio of the PD transistor drive capability to the PG transistor drive capability). This makes the memory node more stable when facing external disturbances, particularly improving the reliability of read operations. Furthermore, the two newly added pull-down transistors PD12 and PD22 are positioned in the same horizontal direction as the original pull-down transistors PD11 and PD21, occupying the back side of the substrate of PG1 and PG2, without introducing additional area. This also avoids problems such as parasitic transistors or electric field concentration caused by the PD transistors being wider than the PG transistors and the active region AA forming a bend.

[0052] In some embodiments, along the gate length direction (i.e., the first direction), the active region width of each transistor (PD11, PD12, PD21, and PD22) in the pull-down transistor group is equal to the active region width of each transistor (PG1 and PG2) in the transmission gate transistor group, and the active region width of each transistor (PG1 and PG2) in the transmission gate transistor group is equal to the active region width of each transistor (PU1 and PU2) in the pull-up transistor group. Specifically, for fin field-effect transistors, the ratio of fins (PG:PD:PU) in the pull-up transistor group, pull-down transistor group, and transmission gate transistor group is 1:1:1. This configuration minimizes the area of ​​the 8TSRAM.

[0053] In other embodiments, along the gate length direction (i.e., the first direction), the active region width of each transistor in the pull-down transistor group can be greater than the active region width of each transistor in the transmission gate transistor group, and / or along the gate length direction, the active region width of each transistor in the transmission gate transistor group can be greater than the active region width of each transistor in the pull-up transistor group, so that the β ratio is greater than 1, and / or the γ ratio is greater than 1, making the read and write operations more stable.

[0054] In the above, this application uses a finned field-effect transistor (FinFET) as an example. The number of Fins in the corresponding PU transistor group, PD transistor group, and PG transistor group is 1:1:1. It can also be a high conduction current structure, with commonly used Fin ratios of 2:2:1, 3:3:1, or other settings. The transistor can also be a planar transistor. Of course, the transistor can also be a GAAFET (Gate-All-Around Field-Effect Transistor), and this application does not make specific limitations.

[0055] This application allows for different numbers of fins to be set for PU, PG, and PD, enabling designers to make more precise trade-offs and optimizations between area, performance, and power consumption. For example, when area is limited, a more compact fin configuration can be selected, and electrical properties can be compensated by adjusting the work function (WF) of PG / PD / PU. When pursuing ultimate performance, a more flexible fin configuration can be used to optimize electrical properties.

[0056] This application provides multiple layout design structures for 8T SRAM. Through innovative cell structures and routing strategies, it achieves high-performance, high-density, and easy-to-manufacture 8T SRAM, addressing the pain points of existing 8T SRAM designs in terms of area efficiency and routing complexity. It also improves the flexibility of 8T SRAM design to adapt to different performance and area trade-offs, allowing the selection of the optimal solution based on specific application scenarios.

[0057] In some embodiments, this application employs a front and back self-aligned layout. Figures 2-3 The figure shows a front and back layout of an 8T SRAM provided in an embodiment of this application. As shown, the PU transistor group and the PG transistor group are integrated on the front side of the substrate, and the PD transistor group (including the first pull-down group PD10 and the second pull-down group PD20) is formed on the back side of the substrate.

[0058] Specifically, the first pull-up transistor PU1 and the second transmission gate transistor PG2 are arranged side by side along a first direction, and the second pull-up transistor PU2 and the first transmission gate transistor PG1 are arranged side by side along the first direction; the first pull-up transistor PU1 and the first transmission gate transistor PG1 are arranged side by side along a second direction, and the second pull-up transistor PU2 and the second transmission gate transistor PG2 are arranged side by side along a second direction, the second direction being perpendicular to the first direction; for example, the first direction can be a vertical direction, and the second direction can be a horizontal direction.

[0059] The first pull-up transistor PU1 on the front side of the substrate is self-aligned with the first pull-down transistor PD11 on the back side of the substrate; the first transmission gate transistor PG1 on the front side of the substrate is self-aligned with the second pull-down transistor PD12 on the back side of the substrate; the second pull-up transistor PU2 on the front side of the substrate is self-aligned with the third pull-down transistor PD21 on the back side of the substrate; and the second transmission gate transistor PG2 on the front side of the substrate is self-aligned with the fourth pull-down transistor PD22 on the back side of the substrate. This self-alignment allows for a more compact arrangement of transistor groups in three-dimensional space, fully utilizing the space on both the front and back sides of the substrate to improve integration. Furthermore, it enables automatic transistor alignment through process steps, ensuring more precise connections and reducing parasitic coupling and power consumption.

[0060] Furthermore, by employing a flip FET process, N / P type transistors can be fabricated on both the front and back sides of the wafer, enabling a device design with bifacial active regions. Specifically, two PU transistors and two PG transistors are placed on the front side of the substrate, while four pull-down transistors are innovatively placed on the back side, with PD11 and PD12, and PD21 and PD22 aligned in the same X-direction. This arrangement allows the two newly added pull-down transistors to occupy the back side space of PG1 and PG2 without introducing additional area. This significantly reduces the area of ​​the 8T SRAM cell on a two-dimensional plane, resolving the trade-off between performance improvement and area increase, and facilitating inter-cell wiring.

[0061] In some embodiments, please continue reading Figures 2-6 This application provides a layout structure for an 8T SRAM. For example, taking FinFET technology as an example, such as... Figure 2 , Figure 11 and Figure 13As shown, in the front-middle section structure on the front side of the substrate, along the second direction, corresponding to each transistor in the PU transistor group and the PG transistor group, at least four fins are formed on the substrate, forming four active regions (AA). Each active region AA includes a source and a drain. An EPI epitaxial layer is grown on the fins. A MO metal layer 10 is disposed above the EPI epitaxial layer. The MO metal layer 10 includes a first MO metal 11, a second MO metal 12, a third MO metal 13, and a MOG metal 14. The first MO metal 11, the second MO metal 12, and the third MO metal 13 are connected to the source and the drain. The MOG metal 14 is connected to the gate (PO). The MO metal layer 10 can be connected to the back side of the substrate through an active drain coupling metal (drainmer, DM). The first pull-up transistor PU1 and the Fin of the first transmission gate transistor PG1 are fused together and formed simultaneously by the same photolithography and etching process. The second pull-up transistor PU2 and the Fin of the second transmission gate transistor PG2 are fused together and formed simultaneously by the same photolithography and etching process. Along the first direction, two gates span across each Fin and cover the top and sidewalls of the Fin. The first pull-up transistor PU1 and the second transmission gate transistor PG2 share a first gate. A polycut layer (P2) is provided on the first gate between the first pull-up transistor PU1 and the second transmission gate transistor PG2. The second pull-up transistor PU2 and the first transmission gate transistor PG1 share a second gate. A polycut layer (P2) is provided on the second gate between the second pull-up transistor PU2 and the first transmission gate transistor PG1. The two gates can be connected to the back side of the substrate through a gate coupling metal (GM) or connected to the MO metal layer 10.

[0062] In the front-middle section structure on the back side, along the second direction, corresponding to each transistor in the first pull-down group PD10 and the first and second pull-down groups PD20, at least four Fins are formed on the substrate, forming four active regions (B_AA). Each active region B_AA includes a source and a drain. An EPI epitaxial layer is grown on the Fins. A B_MO metal layer 20 is disposed above the EPI epitaxial layer. The B_MO metal layer 20 includes a first B_MO metal 21, a second B_MO metal 22, a third B_MO metal 23, and a B_MOG metal 24. The first B_MO metal 21, the second B_MO metal 22, and the third B_MO metal 23 are connected to the source and the drain. The B_MOG metal 24 is connected to the gate (B_PO). The B_MO metal layer 20 can be connected to the front side of the substrate through an active drain-coupled metal (drain merge, DM). The first pull-down transistor PD11 and the second pull-down transistor PD21 are fused together and formed simultaneously by the same photolithography and etching process. The third pull-down transistor PD21 and the fourth pull-down transistor PD22 are fused together and formed simultaneously by the same photolithography and etching process. Along the first direction, two gates span each Fin and cover the top and sidewalls of the Fin. The first pull-down transistor PD11 and the fourth pull-down transistor PD22 share a third gate, and a cut-off layer (B_Poly cut, B_P2) is provided on the third gate between the first pull-down transistor PD11 and the fourth pull-down transistor PD22. The second pull-down transistor PD12 and the third pull-down transistor PD21 share a fourth gate, and a cut-off layer (B_P2) is provided on the fourth gate between the second pull-down transistor PD12 and the third pull-down transistor PD21. The two gates can be connected to the front side of the substrate through a gate merge (GM) or connected to the B_M0 metal layer 20.

[0063] Specifically, the gate of the first pull-up transistor PU1 and the gate of the first pull-down group PD10 are connected through a first gate coupling metal GM1 penetrating the substrate. The drain of the first pull-up transistor PU1 and the source of the first transmission gate transistor PG1 are connected to a first M0 metal 11. The drain of the first pull-down group PD10 is connected to a first B_M0 metal 21. The first M0 metal 11 and the first B_M0 metal 21 are connected through a first source-drain coupling metal DM1 penetrating the substrate. The gate of the second pull-up transistor PU2 and the gate of the second pull-down group PD20 are connected through a second gate coupling metal GM2 penetrating the substrate. The drain of the second pull-up transistor PU2 and the source of the second transmission gate transistor PG2 are connected to a first M0 metal 11. The drain of the second pull-down group PD20 is connected to a first B_M0 metal 21. The first M0 metal 11 and the first B_M0 metal 21 are connected through a second source-drain coupling metal DM2 penetrating the substrate.

[0064] In this embodiment, a cut-off layer (MO cut, MOC) is provided on the first MO metal 11 located between the first source-drain coupling metal DM1 and the second source-drain coupling metal DM2; a cut-off layer (B_MO cut, B_MOC) is provided on the first B_MO metal 21 located between the first source-drain coupling metal DM1 and the second source-drain coupling metal DM2, so as to cut off the circuit connection between the two storage nodes n1 and n2.

[0065] In some embodiments, such as Figures 2-6As shown, the 8T SRAM cell has a first structure: the drain of the first pull-down group PD10 and the drain of the first pull-up transistor PU1 are connected through a first source-drain coupling metal DM1 penetrating the substrate to form a first memory node n1; the second pull-up transistor PU2 and the second pull-down group PD20 are connected through a second source-drain coupling metal DM2 penetrating the substrate to form a second memory node n2. The first memory node n1 and the second memory node n2 are disposed on the back side of the substrate. The first memory node n1 is connected to the drain of the first pull-down group PD10 and the gate of the second pull-down group PD20 on the back side of the substrate through a first B_M0 metal 21 and a B_M0G metal 24, respectively. The gate of the second pull-up transistor PU2 and the gate of the second pull-down group PD20 are connected through a second gate coupling metal GM2 penetrating the substrate. Correspondingly, the second memory node n2 is connected to the drain of the second pull-down group PD20 and the gate of the first pull-down group PD10 on the back side of the substrate via the first B_M0 metal 21 and B_M0G metal 24, respectively. The gate of the first pull-up transistor PU1 and the gate of the first pull-down group PD10 are connected via the first gate coupling metal GM1 that penetrates the substrate. This simplifies the manufacturing process, reduces process fluctuations and deviations that may be caused by the asymmetrical layout of the front and back sides of the substrate, ensures that the two memory nodes maintain consistent electrical characteristics, and improves production yield.

[0066] Of course, in other embodiments, such as Figures 13-14 As shown, the first storage node n1 and the second storage node n2 can both be disposed on the front side of the substrate, which will not be elaborated here.

[0067] In other embodiments, the 8T SRAM cell has a second structure: one of the first memory node n1 and the second memory node n2 is disposed on the front side of the substrate, and the other is disposed on the back side of the substrate. For example... Figure 11 and Figure 12As shown, the drain of the first pull-up transistor PU1 and the drain of the first pull-down group PD10 are connected through a first source-drain coupling metal DM1 penetrating the substrate to form a first memory node n1. On the back side of the substrate, the first memory node n1 is connected to the drain of the first pull-down group PD10 and the gate of the second pull-down group PD20 through a first B_MO metal 21 and a B_MOG metal 24, respectively. The gate of the second pull-down group PD20 and the gate of the second pull-up transistor PU2 are connected through a second gate coupling metal GM2 penetrating the substrate. The drain of the second pull-up transistor PU2 and the drain of the second pull-down group PD20 are connected through a second source-drain coupling metal DM2 penetrating the substrate to form a second memory node n2. On the front side of the substrate, the second memory node n2 is connected to the drain of the second pull-up transistor PU2 and the gate of the first pull-up transistor PU1 through a first MO metal 11 and a MOG metal 14, respectively. The gate of the first pull-up transistor PU1 and the gate of the first pull-down group PD10 are connected through a first gate coupling metal GM1 penetrating the substrate.

[0068] In the above embodiments, compared with the first structure, the second structure reduces the fin pitch by one along the first direction. Specifically, ① the first memory node n1 and the second memory node n2 are respectively disposed on the back side and the front side of the substrate; ② at the same time, since the second memory node n2 is disposed on the front side of the substrate, compared with the first structure, the front side of the substrate adds one MOG metal 14 and the back side removes one B_MOG metal 24. The positional relationships of local metal interconnect layer cutoff (MOC / B_MOC) and polysilicon cutoff (P2 / B_P2) are different from those of the first structure, and the downstream metal wiring process window is reduced.

[0069] In traditional planar layouts, power lines and signal lines compete for wiring resources within the same metal plane. As transistor density increases, wiring becomes extremely congested, leading to increased interconnect resistance and capacitance (RC) delays, severely impacting SRAM read / write speeds and increasing power consumption. Therefore, as... Figure 3 , Figure 12 and Figure 14 This application also provides a flexible routing architecture for the back-end structure of the 8T SRAM cell. Using this architecture, critical signal lines such as word lines (WL) and bit line pairs (BL / BLB), as well as power lines (VDD) and ground lines (VSS) in the 8T SRAM are routed to the front and back sides of the substrate. This layered arrangement allows for pre-routing to the lower metal layer, enabling the connection of all critical signals to be completed in the second metal layer M2 or even the first metal layer M1, resulting in extremely high routing efficiency. This not only saves on upper-layer metal resources and reduces manufacturing complexity but may also reduce signal delay caused by long-distance routing.

[0070] Specifically, in some embodiments, word lines (WL) and bit line pairs (BL and BLB) are routed on the front side of the substrate, while power lines (Vdd) and ground lines (Vss) are routed on the back side. By routing the signal on the front side and the power on the back side of the substrate, the signal path and the power supply path are separated, eliminating wiring contention and parasitic coupling between them, improving electrical performance, and reducing power consumption.

[0071] Specifically, on the front side of the substrate, the back-end structure includes an M1 metal layer 30 and an M2 metal layer 50. The M0 metal layer 10 is connected to the M1 metal layer 30 through a via V0, and the M1 metal layer 30 is connected to the M2 metal layer 50 through a via V1. The M1 metal layer 30 includes a first M1 metal 31, a second M1 metal 32, and a third M1 metal 33. The M2 metal layer 50 includes an M2 metal 51. The gates of the first transmission gate transistor PG1 and the second transmission gate transistor PG2 are connected to the word line WL sequentially through the first M1 metal 31 and the M2 metal 51. The drain of the first transmission gate transistor PG1 is connected to the second M0 metal 12, and the second M0 metal 12 is connected to the bit line BL through the second M1 metal 32. The drain of the second transmission gate transistor PG2 is connected to the third M0 metal 13, and the third M0 metal 13 is connected to the reverse bit line BLB through the third M1 metal 33.

[0072] On the back side of the substrate, the rear structure includes a B_M1 metal layer 40. The B_M0 metal layer 20 is connected to the B_M1 metal layer 40 through a via B_V0. The B_M1 metal layer 40 includes a first B_M1 metal 41, a second B_M1 metal 42, and a third B_M1 metal 43. The source of the first pull-up transistor PU1 is connected to the first B_M1 metal 41 sequentially through the third M0 metal 13, a third source-drain coupling metal DM3 penetrating the substrate, and the third B_M0 metal 23. The source of the second pull-up transistor PU2 is connected to the first B_M1 metal 41 sequentially through the second M0 metal 12, a fourth source-drain coupling metal DM4 penetrating the substrate, and the second B_M0 metal 22. The first B_M1 metal 41 is connected to the power supply Vdd.

[0073] In the first pull-down group PD10, the source of the first pull-down transistor PD11 is connected to the second B_M1 metal 42 through the third B_M0 metal 23, and the source of the second pull-down transistor PD12 is connected to the second B_M1 metal 42 through the second B_M0 metal 22. The second B_M1 metal 42 is connected to ground Vss. In the second pull-down group PD20, the source of the third pull-down transistor PD21 is connected to the third B_M1 metal 43 through the second B_M0 metal 22, and the source of the fourth pull-down transistor PD22 is connected to the third B_M1 metal 43 through the third B_M0 metal 23. The third B_M1 metal 43 is connected to ground Vss.

[0074] In the above embodiments, by routing signal lines on the front side of the substrate and power lines on the back side, the signal path and power path are separated, eliminating wiring competition and parasitic coupling between them, which improves electrical performance and reduces power consumption to a certain extent.

[0075] In the above embodiments, by integrating two pull-up transistors, two transmission gate transistors, and four pull-down transistors onto the same side plane of the substrate, interference caused by process fluctuations is reduced. For example, thermal budgeting can cause a shift in the device threshold voltage (Vts). If the first pull-up transistor PU1 and the second pull-up transistor PU2 are on different sides, different thermal budgeting processes can lead to a mismatch in the threshold voltage Vts, resulting in a performance mismatch between the first pull-up transistor PU1 and the second pull-up transistor PU2, which can easily cause read / write failures in the 8T SRAM cells. In terms of process, pull-up transistors, pull-down transistors, and transmission gate transistors that are not on the same plane can be easily adjusted individually. Whether by adjusting the channel length, work function, or other different process conditions, the electrical characteristics of the transistors can be effectively optimized, thereby improving the performance of the 8T SRAM. At the same time, this adjustment method does not require an additional photomask step, which helps reduce costs and manufacturing complexity.

[0076] Of course, in addition to the above wiring structure, word lines (WL), bit pairs (BL / BLB), power lines (Vdd), and ground lines (VSS) can be adjusted according to the actual process window to ultimately run from the front M1 / M2 / M3 layer or other metal layers of the substrate, or from the back B_M1 / B_M2 / B_M3 layer or other metal layers of the substrate. For example, bit lines (BL / BLB) can also be routed separately from the front and back of the substrate, and ground lines Vss and power lines Vdd can also be routed from the front of the substrate, etc., providing a more flexible layout basis for complex 8T SRAM designs.

[0077] In some embodiments, an 8T SRAM cell consists of eight transistors. The inner side of the 8T SRAM cell refers to the area between the active regions of the individual transistors within the 8T SRAM cell, and the outer side of the 8T SRAM cell refers to the area outside the inner side of the 8T SRAM cell. The first source-drain coupling metal DM1, the second source-drain coupling metal DM2, the third source-drain coupling metal DM3, and the fourth source-drain coupling metal DM4 can be disposed on either the inner or outer side of the 8T SRAM cell. When disposed on the inner side of the 8T SRAM cell, the process window between the transistors is larger, and the wiring space is greater; when disposed on the outer side of the 8T SRAM cell, the distance between the transistors is closer, and the device matching is better. This application is not limited to this.

[0078] In the above embodiments, the source-drain coupling metals DM1, DM2, DM3, and DM4 are not limited to using the same photomask, and the gate coupling metals GM1 and GM2 are not limited to using the same photomask. Double or multiple photomasks can be used to increase the process window. The dimensions of the source-drain coupling metals DM, the distance from DM to the source / drain, the distance from DM to the gate PO / B_PO, MOG / B_MOG, and DM, and the distances from GM to GM, the source / drain, the gate PO / B_PO, MOG / B_MOG, and DM, etc., can all be adjusted according to the process window, and this application does not limit them.

[0079] like Figures 7-10 As shown, this application also provides an 8T SRAM, including an array of 8T SRAM groups, wherein each 8T SRAM group includes at least four 8T SRAM cells as described in any of the above embodiments, forming a 2×2 array. The structure and connection configuration of the 8T SRAM cells have been described in detail in the above embodiments, and will not be repeated here.

[0080] In this embodiment, adjacent 8T SRAM cells in each group of 8T SRAM are symmetrically arranged. Specifically, in a 2×2 8T SRAM cell array, the 8T SRAM cells in two rows are mirrored, allowing the two rows of 8T SRAM cells to share word lines (WL); the 8T SRAM cells in two columns are also mirrored, allowing the two columns of 8T SRAM cells to share bit line pairs (BL / BLB, Vdd, Vss, etc.), thus further improving area efficiency.

[0081] like Figure 15 As shown, this application also provides a method for preparing an 8T SRAM, which is used to prepare an 8T SRAM as described in any of the above embodiments, including the following steps S101-S103.

[0082] Step S101: Forming a substrate. The substrate can be a bulk silicon substrate, but is not limited to this; other types of semiconductor substrates can also be used, such as germanium (Ge) substrates or silicon-germanium (SiGe) substrates. The substrate provides physical support for the transistor and serves as a conductive substrate.

[0083] Step S102: Select the pull-up PU transistor group and the transmission gate PG transistor group as the front structure of the substrate, and the pull-down transistor group PD as the back structure of the substrate, and perform the first process for forming the front structure.

[0084] In this embodiment, a device design with double-sided active regions is achieved through a flip-flop process to effectively reduce the area of ​​the 8T SRAM, freeing up wiring space. The PU transistor group and the PG transistor group are integrated on the front side of the substrate, while the first pull-down group PD10 and the second pull-down group PD20 in the PD transistor group are integrated on the back side of the substrate.

[0085] In the fabrication of the 8T SRAM cells in this application, the timing of the flip-flop is selected based on thermal budget control. Because the metal gate process generates high heat, which can easily cause diffusion and electrical shift, it is performed as late as possible to reduce the cumulative thermal impact. Based on this, the formation of the front-side structure includes a first process stage and a second process stage performed sequentially. The second process stage includes the metal gate process; that is, the first process stage of the front-side structure includes processes performed according to the transistor process flow up to the metal gate process stage.

[0086] Specifically, the first process for forming the front structure is performed on the substrate, including an active layer AA (including source and drain), a shallow trench isolation layer (STI), polycrystalline silicon (PO), an epitaxial layer (epithelial layer), etc. The process steps or sequence can be adaptively adjusted according to the requirements of different process nodes to ensure process compatibility and optimized performance. This application does not make specific limitations.

[0087] Step S103: Flip the substrate at least twice to form the back side structure of the substrate, and perform the second process for forming the front side structure.

[0088] In this embodiment, after the first process for forming the front structure is completed, wafer bonding and a Flip FET three-flip process can be performed to form the back structure of the substrate, followed by the second process for forming the front structure. The formation of the back structure includes a third and a fourth process performed sequentially. The fourth process includes a metal gate process, which can be the same as the second process. Specifically, wafer bonding is performed first. After the wafer bonding is completed and the substrate is flipped for the first time, the third process for forming the back structure is performed, including: substrate thinning to expose the active region on the back side, then etching the shallow trench isolation layer (STI) to form the Fin structure on the back side of the substrate, forming the active layer AA (including source and drain), polycrystalline silicon (PO), epitaxial layer (epi), etc. The process steps or sequence can be adaptively adjusted according to different process node requirements to ensure process compatibility and optimized performance; this application does not impose specific limitations. Then, the substrate is flipped a second time to perform the second stage process for forming the front structure, including the metal gate (MG) and the middle and back metal interconnect layer process. Then, the substrate is flipped a third time to perform the fourth stage process for forming the back structure, including the metal gate (MG) process and the middle and back metal interconnect layer process, to complete the fabrication of the 8T SRAM cell.

[0089] Of course, in other embodiments, the third process stage may include a metal gate (MG) process, in which case the fourth process stage includes a mid-to-back metal interconnect layer process. Specifically, after the substrate is flipped for the first time, the metal gate (MG) process to complete the back structure is performed, then the substrate is flipped to the front side for the second process to form the front structure, and finally flipped to the back side for the fourth process to form the back structure. This application is not limited here, and can be adaptively adjusted according to the specific settings of the SRAM and application requirements to optimize transistor performance and circuit reliability. For example, the PU transistor group is integrated on the front side of the substrate, and the PD transistor group is integrated on the back side of the substrate, wherein the PU transistor group is a P-type transistor and the PD transistor group is an N-type transistor. When the performance of the PD transistor group is more critical, the metal gate process of the back structure can be arranged in the fourth process stage to avoid the adverse effect of the front annealing of the substrate on the performance of the N-type PD transistor group.

[0090] In another embodiment, a two-flip FET process can be used to form the back-side structure of the substrate, followed by a second process for forming the front-side structure. Specifically, wafer bonding is performed first. After wafer bonding, the substrate is flipped for the first time to form the back-side structure, including the third and fourth processes performed sequentially. These processes include: substrate thinning until complete removal; etching the shallow trench isolation layer (STI) to form the Fin structure on the back side of the substrate; forming the active layer AA (including source and drain), polycrystalline silicon (PO), epitaxial layer (epi), metal gate (MG), and mid-to-back metal interconnect layer. Then, the substrate is flipped a second time to perform the second process for forming the front-side structure, including the metal gate (MG) and mid-to-back metal interconnect layer processes, completing the fabrication of the 8T SRAM cell.

[0091] It is understood that in the above embodiments, the process steps or sequence can be adaptively adjusted according to different process node requirements to ensure process compatibility and optimized performance. This application does not make any specific limitations.

[0092] For adjusting the read and write performance of 8T SRAM, the embodiments of this application are more convenient in terms of process technology to adjust the PU transistor group, PD transistor group and PG transistor group separately compared to other structures.

[0093] ① Electrical properties can be adjusted by changing the channel length. Since the PD transistor group and the PU transistor group are not on the same plane, different channel lengths can be set for the PD transistor group and the PU transistor group. For example, increasing the channel length of the PU transistor group reduces the current flow, which is beneficial to improving the write capability of the 8T SRAM. Conversely, decreasing the channel length of the PD transistor group increases the current flow, which is beneficial to improving the read capability of the 8T SRAM. However, if the PD transistor group and the PU transistor group are on the same plane, the layout usually does not allow the same gate to have a bend, meaning that the channel lengths of the PU transistor group and the PD transistor group are the same, and they cannot be adjusted separately.

[0094] ② The electrical properties can be adjusted by adjusting the work function (WF). The PD transistor group and PG transistor group do not need to be added with an additional photomask. Different processes can be used to adjust them on the front and back sides of the substrate. For example, the current of the PD transistor group can be increased by changing the thickness of the work function metal deposition, thereby improving the read capability of the SRAM.

[0095] ③ The electrical properties can be adjusted by controlling the number of fins. This application can select different design structures according to the process window and also provides a variety of fin number configuration schemes. This flexibility allows the design to be customized and optimized according to different performance / area / power consumption requirements.

[0096] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0097] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. An 8T SRAM cell, characterized in that, It includes: a substrate, and a pull-up transistor group, a pull-down transistor group, and a transmission gate transistor group formed on the substrate, wherein the pull-up transistor group and the transmission gate transistor group are integrated on the front side of the substrate, and the pull-down transistor group is integrated on the back side of the substrate, wherein... The pull-up transistor group includes a first pull-up transistor and a second pull-up transistor; The pull-down transistor group includes a first pull-down group and a second pull-down group; the first pull-down group includes a first pull-down transistor and a second pull-down transistor connected in parallel, and the second pull-down group includes a third pull-down transistor and a fourth pull-down transistor connected in parallel; the first pull-up transistor and the first pull-down group form a first inverter, and the second pull-up transistor and the second pull-down group form a second inverter, and the first inverter and the second inverter are cross-coupled; The transmission gate transistor group connects word lines and bit lines, including a first transmission gate transistor and a second transmission gate transistor. The first transmission gate transistor is connected to the first inverter, and the second transmission gate transistor is connected to the second inverter.

2. The 8T SRAM cell according to claim 1, characterized in that, The first pull-up transistor and the first pull-down group are connected to form a first memory node n1, and the second pull-up transistor and the second pull-down group are connected to form a second memory node n2. The positions of the first memory node n1 and the second memory node n2 include: The first storage node n1 and the second storage node n2 are disposed on the same surface of the substrate; or One of the first storage node n1 and the second storage node n2 is disposed on the front side of the substrate, and the other is disposed on the back side of the substrate.

3. The 8T SRAM cell according to claim 1, characterized in that, The bit line pair includes bit line BL and bit line inverse BLB; in the transmission gate transistor group The gates of the first and second transmission gate transistors are connected to the word line WL; The drain of the first transmission gate transistor is connected to the bit line BL, and the source of the first transmission gate transistor is connected to the first inverter. The drain of the second transmission gate transistor is connected to the bit line inverted BLB, and the source of the second transmission gate transistor is connected to the second inverter.

4. The 8T SRAM cell according to claim 3, characterized in that, The first pull-up transistor and the second transmission gate transistor are arranged side by side along a first direction, and the second pull-up transistor and the first transmission gate transistor are arranged side by side along the first direction; the first pull-up transistor and the first transmission gate transistor are arranged side by side along a second direction, and the second pull-up transistor and the second transmission gate transistor are arranged side by side along a second direction, the second direction being perpendicular to the first direction; The first pull-up transistor on the front side of the substrate is self-aligned with the first pull-down transistor on the back side of the substrate; the first transmission gate transistor on the front side of the substrate is self-aligned with the second pull-down transistor on the back side of the substrate; the second pull-up transistor on the front side of the substrate is self-aligned with the third pull-down transistor on the back side of the substrate; and the second transmission gate transistor on the front side of the substrate is self-aligned with the fourth pull-down transistor on the back side of the substrate.

5. The 8T SRAM cell according to claim 4, characterized in that, In the first pull-down group, the gate, source, and drain of the first pull-down transistor are shared with the gate, source, and drain of the second pull-down transistor, respectively; In the second pull-down group, the gate, source, and drain of the third pull-down transistor are shared with the gate, source, and drain of the fourth pull-down transistor.

6. The 8T SRAM cell according to claim 4, characterized in that, The gate of the first pull-up transistor and the gate of the first pull-down group are connected through a first gate coupling metal that penetrates the substrate. The drain of the first pull-up transistor and the source of the first transmission gate transistor are connected to the first M0 metal. The drain of the first pull-down group is connected to the first B_M0 metal. The first M0 metal and the first B_M0 metal are connected through a first source-drain coupling metal that penetrates the substrate. The gate of the second pull-up transistor and the gate of the second pull-down group are connected by a second gate coupling metal that penetrates the substrate. The drain of the second pull-up transistor and the source of the second transmission gate transistor are connected to the first M0 metal. The drain of the second pull-down group is connected to the first B_M0 metal. The first M0 metal and the first B_M0 metal are connected by a second source-drain coupling metal that penetrates the substrate. A cutting layer is provided on the first MO metal located between the first source / drain coupling metal and the second source / drain coupling metal; A cutting layer is provided on the first B_M0 metal located between the first source-drain coupling metal and the second source-drain coupling metal.

7. The 8T SRAM cell according to claim 6, characterized in that, The gates of the first transmission gate transistor and the second transmission gate transistor are connected to the word line in sequence through the first M1 metal and the M2 metal, respectively; The drain of the first transmission gate transistor is connected to the second M0 metal, and the second M0 metal is connected to the bit line BL through the second M1 metal; the drain of the second transmission gate transistor is connected to the third M0 metal, and the third M0 metal is connected to the bit line BLB in reverse through the third M1 metal.

8. The 8T SRAM cell according to claim 6, characterized in that, The source of the first pull-up transistor is connected to the first B_M1 metal in sequence through the third M0 metal, the third source-drain coupling metal penetrating the substrate, and the third B_M0 metal; the source of the second pull-up transistor is connected to the first B_M1 metal in sequence through the second M0 metal, the fourth source-drain coupling metal penetrating the substrate, and the second B_M0 metal, and the first B_M1 metal is connected to the power supply Vdd. In the first pull-down group, the source of the first pull-down transistor is connected to the second B_M1 metal through the third B_M0 metal, the source of the second pull-down transistor is connected to the second B_M1 metal through the second B_M0 metal, and the second B_M1 metal is connected to ground Vss; In the second pull-down group, the source of the third pull-down transistor is connected to the third B_M1 metal through the second B_M0 metal, the source of the fourth pull-down transistor is connected to the third B_M1 metal through the third B_M0 metal, and the third B_M1 metal is connected to ground Vss.

9. The 8T SRAM cell according to any one of claims 6-8, characterized in that, The first source-drain coupling metal and the second source-drain coupling metal are disposed on the inner side of the 8T SRAM cell, wherein the inner side of the 8T SRAM cell refers to the area between each transistor in the 8T SRAM cell, and the outer side of the 8T SRAM cell refers to the area outside the inner side of the 8T SRAM cell.

10. An 8T SRAM, characterized in that, Includes an 8T SRAM array, wherein, Each group of the 8T SRAM includes at least four 8T SRAM cells as described in any one of claims 1-9, wherein adjacent 8T SRAM cells in each group of the 8T SRAM are symmetrically arranged.

11. A method for preparing an 8T SRAM, used to prepare the 8T SRAM as described in claim 10, characterized in that, Includes the following steps: Forming a substrate; The pull-up transistor group and the transmission gate transistor group are selected as the front structure of the substrate, and the pull-down transistor group is selected as the back structure of the substrate. A first process for forming the front structure is performed. The formation of the front structure includes the first process and the second process performed sequentially, and the second process includes a metal gate process. The substrate is flipped at least twice to form the back side structure of the substrate, and a second process for forming the front side structure is performed.

12. The method for preparing 8T SRAM according to claim 11, characterized in that, The process of flipping the substrate at least twice to form the back side structure of the substrate, and performing the second stage process for forming the front side structure, includes: The substrate is first flipped during wafer bonding and then a third process for forming the backside structure is performed; the formation of the backside structure includes the third and fourth processes performed sequentially; the third or fourth process includes a metal gate process; The substrate is flipped a second time to perform the second stage of the process for forming the front-side structure; The substrate is flipped a third time to perform the fourth process for forming the backside structure.

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