Semiconductor device and method of manufacturing semiconductor device

Abstract

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a peripheral circuit region and a cell array region, in which the cell array region includes: a molding structure extending in a first horizontal direction; a channel layer on a sidewall of the molding structure, where the channel layer includes a first oxide semiconductor material; a word line on a sidewall of the channel layer; a landing pad on a top surface of the channel layer; a bit line on a bottom surface of the channel layer opposite to the top surface, in which the bit line extends in a second horizontal direction intersecting the first horizontal direction; an oxide semiconductor layer on the bottom surface and the one or more sidewalls of the landing pad, where the oxide semiconductor layer includes a second oxide semiconductor material; and a cell capacitor electrically connected to the channel layer through the landing pad and the oxide semiconductor layer.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2024-0164389 filed with the Korean Intellectual Property Office on November 18, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device, and more specifically, to a semiconductor device including a vertical channel transistor and a method for manufacturing a semiconductor device. Background Technology

[0004] As the size of semiconductor devices shrinks, the size of dynamic random access memory (DRAM) devices also decreases. Furthermore, as DRAM devices with a 1T-1C structure (where one transistor is connected to a capacitor) become smaller, leakage current through the channel region increases. Summary of the Invention

[0005] The present invention provides a semiconductor device with improved electrical performance.

[0006] The present invention provides a method for manufacturing a semiconductor device with improved electrical performance.

[0007] However, the inventive concept is not limited to those described above. Other inventive concepts will be clearly understood by those skilled in the art from the following description.

[0008] According to one aspect of the present invention, a semiconductor device is provided, comprising a peripheral circuit region and a cell array region on the peripheral circuit region, wherein the cell array region comprises: a molded structure extending in a first horizontal direction; a channel layer on a sidewall of the molded structure, wherein the channel layer comprises a first oxide semiconductor material; word lines on a sidewall of the channel layer; landing pads on a top surface of the channel layer; bit lines on a bottom surface of the channel layer opposite to the top surface, wherein the bit lines extend in a second horizontal direction intersecting the first horizontal direction; an oxide semiconductor layer on the bottom surface of the landing pads and one or more sidewalls, wherein the oxide semiconductor layer comprises a second oxide semiconductor material; and a cell capacitor electrically connected to the channel layer via the landing pads and the oxide semiconductor layer.

[0009] According to one aspect of the present invention, a semiconductor device is provided, including a peripheral circuit region and a cell array region on the peripheral circuit region. The peripheral circuit region includes a substrate and peripheral circuit transistors. The cell array region includes: a molded structure extending in a first horizontal direction; a channel layer on a sidewall of the molded structure, wherein the channel layer includes a first oxide semiconductor material; a word line on a sidewall of the channel layer; a gate insulating layer between the channel layer and the word line; a landing pad on a top surface of the channel layer; an oxide semiconductor layer on a bottom surface of the landing pad and one or more sidewalls, wherein the oxide semiconductor layer includes a second oxide semiconductor material; a cell capacitor vertically separated from the channel layer by the landing pad and the oxide semiconductor layer; a bit line on a bottom surface of the channel layer opposite to the top surface and extending in a second horizontal direction intersecting the first horizontal direction; a bit line insulating layer on the bit line; and a shielding metal layer separated from the bit line by the bit line insulating layer.

[0010] According to one aspect of the present invention, a method for manufacturing a semiconductor device is provided, the method comprising forming a peripheral circuit region and forming a cell array region on the peripheral circuit region, wherein forming the cell array region comprises: forming a cell capacitor and a first insulating layer on the sidewalls of the cell capacitor on a carrier substrate; forming a landing pad on the cell capacitor; forming a first oxide semiconductor layer on one or more sidewalls of the landing pad; forming a second insulating layer on the first oxide semiconductor layer; performing an etch-back process on the top surface of the landing pad to form a landing pad recess; forming a second oxide semiconductor layer in the landing pad recess; and forming a molding structure on the first oxide semiconductor layer, the second oxide semiconductor layer and the second insulating layer, forming a channel layer on the sidewalls of the molding structure, forming word lines on the sidewalls of the channel layer, and forming bit lines on the bottom surface of the channel layer. Attached Figure Description

[0011] The embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 These are schematic diagrams of a semiconductor device according to some embodiments;

[0013] Figure 2 yes Figure 1 An enlarged layout diagram of the cell array region;

[0014] Figure 3 It is along Figure 2 A cross-sectional view taken by line A1-A1' in the diagram;

[0015] Figure 4 It is along Figure 2 A cross-sectional view taken by line A2-A2' in the diagram;

[0016] Figure 5 yes Figure 3 A magnified view of the middle section of CX1;

[0017] Figure 6A These are diagrams of a semiconductor device according to some embodiments;

[0018] Figure 6B These are diagrams of a semiconductor device according to some embodiments;

[0019] Figure 7 and Figure 8 These are diagrams of a semiconductor device according to some embodiments;

[0020] Figure 9 yes Figure 7 A magnified view of the middle section of CX2;

[0021] Figure 10 These are schematic diagrams of landing structures according to some embodiments;

[0022] Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A ,picture

[0023] 18B Figure 18C , Figure 19A , Figure 19B , Figure 19C , Figure 20A , Figure 20B , Figure 20C ,picture

[0024] 21A, Figure 21B , Figure 21C , Figure 22A , Figure 22B , Figure 23A , Figure 23B , Figure 24A ,picture

[0025] 24B Figure 25A , Figure 25B , Figure 25C , Figure 26A , Figure 26B , Figure 26C , Figure 27 , Figure 28 and Figure 29The figures sequentially illustrate methods for manufacturing a semiconductor device according to some embodiments; and

[0026] Figure 30A , Figure 30B , Figure 31A , Figure 31B , Figure 32A , Figure 32B and Figure 32C This is a diagram showing, in sequence, a method for manufacturing a semiconductor device according to some embodiments. Detailed Implementation

[0027] In the following description, embodiments will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same components, and redundant descriptions thereof are omitted.

[0028] As used herein, the terms “first,” “second,” etc., may modify various elements regardless of their order and / or priority, and are used only to distinguish one element from another, without limiting the exemplary embodiments. When used herein, the terms “comprising,” “including,” “containing,” and / or “covering” specify the presence of the stated element but do not exclude the presence of additional elements. The term “and / or” includes any and all combinations of one or more of the associated listed items. As used herein, the term “connection” refers to an electrical and / or physical connection between elements or components, and does not exclude the presence of additional elements or components therebetween.

[0029] When used herein, the term “overlap” may specify that an element is positioned on, in contact with, and / or covers another element. When viewed along a line extending in a particular direction or in a plane perpendicular to that direction, components or layers described as “overlapping” in that particular direction may at least partially obstruct each other. The term “in contact with” may be used herein to specify an element or layer directly on another element or layer, without at least one other element or layer between them. As used herein, the terms “fill,” “cover,” etc., may refer to a process in which an element or assembly may partially, completely, or excessively fill a void or cavity. The terms “around,” “cover,” etc., as used herein, do not necessarily need to completely surround or cover the described element or layer, but may refer, for example, to partially surround or cover the described element or layer, for example, where voids or other spaces are always present. As used herein, the term “vertical height” refers to the height of an element or assembly relative to a common reference element, line, or axis.

[0030] The horizontal direction may include a first horizontal direction (e.g., the X direction) and a second horizontal direction (e.g., the Y direction) that intersect each other. The direction intersecting the first horizontal direction (e.g., the X direction) and the second horizontal direction (e.g., the Y direction) may be referred to as the vertical direction (e.g., the Z direction). The vertical horizontal height may be referred to as the height level in any configured vertical direction (e.g., the Z direction). Additionally, in the following text, the horizontal width of any element or component may refer to its length in the horizontal direction (e.g., the X direction and / or the Y direction), and the height of any element or component may refer to its length in the vertical direction (e.g., the Z direction).

[0031] Figure 1 This is a schematic diagram of a semiconductor device 100 according to some embodiments. Figure 2 yes Figure 1 An enlarged layout diagram of the cell array region MCA in the diagram. Figure 3 It is along Figure 2 The cross-sectional view taken by line A1-A1' in the diagram. Figure 4 It is along Figure 2 The cross-sectional view taken from line A2-A2' in the diagram. Figure 5 yes Figure 3 An enlarged view of the CX1 section.

[0032] Reference Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5 The semiconductor device 100 may include a peripheral circuit region PCA and a cell array region MCA disposed at a vertical horizontal height higher than the peripheral circuit region PCA. In other words, the cell array region MCA may be located on the peripheral circuit region PCA.

[0033] In some embodiments, the cell array region (MCA) may include a memory cell region of a dynamic random access memory (DRAM) device, and the peripheral circuit region (PCA) may include a core region or a peripheral circuit region of the DRAM device. For example, the PCA may include peripheral circuit transistors (PTRs) that transmit signals and / or power to the memory cell array within the MCA. In some embodiments, the PTRs may be configured to include various circuitry, such as command decoders, control logic, address buffers, row decoders, column decoders, sense amplifiers, and data input / output circuitry.

[0034] like Figure 2As shown, multiple word lines WL extending in a first horizontal direction (e.g., the X direction) and multiple bit lines BL extending in a second horizontal direction (e.g., the Y direction) can be arranged in the cell array region MCA. Multiple cell transistors CTR can be arranged at the intersections of the multiple word lines WL and the multiple bit lines BL. Multiple cell capacitors CAP can be arranged on top of the multiple cell transistors CTR.

[0035] Multiple word lines WL may include first word lines WL1 and second word lines WL2 arranged alternately in a second horizontal direction (e.g., the Y direction). Multiple unit transistors CTR may include first unit transistors CTR1 and second unit transistors CTR2 arranged alternately in a second horizontal direction (e.g., the Y direction). First unit transistors CTR1 may be arranged adjacent to first word line WL1, and second unit transistors CTR2 may be arranged adjacent to second word line WL2. First unit transistors CTR1 and second unit transistors CTR2 may have a mirror-symmetric structure relative to each other. In other words, first unit transistors CTR1 and second unit transistors CTR2 may have mirror symmetry such that the order of the components is flipped (i.e., reversed or reflected) relative to the plane of symmetry. For example, first unit transistors CTR1 and second unit transistors CTR2 may have a mirror-symmetric structure relative to a center line (i.e., the plane of symmetry) between first unit transistors CTR1 and second unit transistors CTR2, wherein the center line extends in a first horizontal direction (e.g., the X direction) or a second horizontal direction (e.g., the Y direction).

[0036] In some embodiments, the spacing between the multiple bit lines BL (e.g., the sum of the width of a bit line BL and the spacing between two adjacent bit lines BL) can be 2F. In other words, each of the width of a bit line BL and the spacing between two adjacent bit lines BL can be a distance F. The spacing of the first word line WL1 can be 2F and / or the spacing of the second word line WL2 can be 2F. The unit area used to form a single-cell transistor CTR can be 4F. 2 In other words, the length and width of a single-unit transistor (CTR) can both be 2F, allowing the unit area of ​​a single-unit transistor to be 4F. 2 .

[0037] Vertical channel transistors (CTRs) incorporating oxide semiconductor materials as the channel layer have been proposed to reduce leakage current. Furthermore, CTRs incorporating oxide semiconductor materials as the channel layer have demonstrated improved electrical performance and reliability. The unit transistor (CTR) can have a cross-point type (i.e., a cross-architecture) that requires a relatively small unit area, thereby increasing the integration density of the semiconductor device 100.

[0038] Although not shown, an edge region may be arranged around the cell array region MCA. The edge region may include a region in which electrical connection members for word lines WL and / or for bit lines BL are arranged, and a region in which electrical connection members for electrical connection between the cell array region MCA and the peripheral circuit region PCA are arranged.

[0039] In the following text, such as Figure 3 and Figure 4 The diagram illustrates a configuration where the cell array region MCA is arranged at a higher vertical level than the peripheral circuit region PCA (e.g., the cell array region MCA is arranged on top of the peripheral circuit region PCA). However, the semiconductor device 100 can be arranged in reverse such that the cell array region MCA is located at a lower vertical level than the peripheral circuit region PCA. In this case, spatial relative terms such as "top surface" or "bottom surface" of a component in the following description should be understood to refer to the "bottom surface" or "top surface" of the component, respectively. Components described as "above" or "below" any component should be understood to refer to "below" or "above" any component, respectively. Components described as "arranged at a higher vertical level than any component" should be understood to refer to "arranged at a lower vertical level than any component." It should be understood that, in addition to the orientation shown in the figures, these spatial relative terms are also intended to include different orientations of the device during use or operation.

[0040] Substrate 110 may include silicon, such as monocrystalline silicon, polycrystalline silicon, or amorphous silicon. In some embodiments, substrate 110 may include at least one selected from germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and / or indium phosphide (InP). In some embodiments, substrate 110 may include conductive regions (e.g., doped wells or doped structures).

[0041] In the peripheral circuit region PCA, an active region AC can be defined in the substrate 110, and a peripheral circuit transistor PTR can be disposed on the active region AC of the substrate 110. The peripheral circuit transistor PTR may include a gate electrode PTG, a gate insulating layer PTI, and a source / drain region PTS.

[0042] A peripheral circuit transistor (PTR) can be disposed on the substrate 110. A peripheral circuit wiring structure 120 can be disposed on the PTR. The peripheral circuit wiring structure 120 may include peripheral circuit wiring 122, peripheral circuit contacts 124, and a peripheral circuit insulating layer 126. The peripheral circuit wiring 122 and peripheral circuit contacts 124 may be electrically connected to the PTR and / or the substrate 110, and the peripheral circuit insulating layer 126 may cover the PTR, peripheral circuit wiring 122, and peripheral circuit contacts 124 on the substrate 110. The peripheral circuit insulating layer 126 may include an oxide film, a nitride film, a low-k dielectric film, and / or combinations thereof, and may be formed by a stacked structure of multiple insulating layers.

[0043] The peripheral circuit region (PCA) can be attached to the cell array region (MCA) using a bonding method. In some embodiments, the boundary between the PCA and the MCA can be referred to as the bonding interface (BIF). For example, Figure 3 The portion of the semiconductor device 100 shown that is arranged at a vertical horizontal height lower than the bonding interface BIF can be referred to as the peripheral circuit region PCA, and the portion of the semiconductor device 100 that is arranged at a vertical horizontal height higher than the bonding interface BIF can be referred to as the cell array region MCA.

[0044] In some embodiments, the peripheral circuit wiring structure 120 may contact the unit wiring structure 160, wherein a bonding interface (BIF) is located between the two. The unit wiring structure 160 may include a unit wiring layer 162, a unit contact 164, and a unit insulating layer 166.

[0045] Bonding pads BP can be arranged at the interface (e.g., bonding interface BIF) between the cell wiring structure 160 and the peripheral circuit wiring structure 120. Bonding pads BP may include a first bonding pad BP1 and a second bonding pad BP2. The bottom surface of the first bonding pad BP1 may be arranged at the same horizontal height (i.e., height) as the bottom surface of the cell insulating layer 166, and the top surface of the second bonding pad BP2 may be arranged at the same horizontal height (i.e., height) as the top surface of the peripheral circuit insulating layer 126, wherein the top surface of the second bonding pad BP2 may partially or completely contact the bottom surface of the first bonding pad BP1.

[0046] In some embodiments, the cell wiring structure 160 can be bonded to the peripheral circuit wiring structure 120 using a metal-oxide hybrid bonding method. In this case, the interface between the peripheral circuit insulating layer 126 and the cell insulating layer 166 can be arranged on the same plane as (i.e., coplanar with) the interface between the first bonding pad BP1 and the second bonding pad BP2 (e.g., the interface between the peripheral circuit insulating layer 126 and the cell insulating layer 166 and the interface between the first bonding pad BP1 and the second bonding pad BP2 can be arranged along the bonding interface BIF). The plane serving as the interface (i.e., the bonding interface BIF) can extend in a horizontal direction (e.g., the X direction or the Y direction).

[0047] In some embodiments, the cell wiring structure 160 can be bonded to the peripheral circuit wiring structure 120 by an oxide bonding method. In this case, the bonding pad BP can be omitted.

[0048] Multiple bit lines BL can be arranged above the cell wiring structure 160. Cell transistors CTR can be arranged on the multiple bit lines BL. Cell capacitors CAP can be arranged on the cell transistors CTR. In some embodiments, the bit lines BL can be arranged closer to the bonding interface BIF than the cell transistors CTR or the cell capacitors CAP. Therefore, the vertical distance between the bit lines BL and the peripheral circuit transistors PTR can be smaller than the vertical distance between the cell capacitors CAP and the peripheral circuit transistors PTR.

[0049] In some embodiments, multiple bit lines BL may extend in a second horizontal direction (e.g., the Y direction) and may be arranged such that a shielding metal layer SS partially or completely fills the space between the multiple bit lines BL. For example, the multiple bit lines BL may extend in a second horizontal direction (e.g., the Y direction). Some portions of the shielding metal layer SS may partially or completely fill the space between the multiple bit lines BL and extend in the second horizontal direction (e.g., the Y direction), and other portions of the shielding metal layer SS may be arranged between the bottom surface of the multiple bit lines BL and the top surface of the unit wiring structure 160. The sidewalls and bottom surface of the bit lines BL may be covered by a first bit insulation layer 152 and a second bit insulation layer 154. The first bit insulation layer 152 and the second bit insulation layer 154 may be arranged between the sidewalls of the bit lines BL and the shielding metal layer SS, and between the bottom surface of the bit lines BL and the shielding metal layer SS.

[0050] In some embodiments, the bit line BL may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), ruthenium (Ru), tungsten (W), tungsten nitride (WN), cobalt (Co), nickel (Ni), titanium silicide (TiSi), titanium silicon nitride (TiSiN), tungsten silicide (WSi), tungsten silicon nitride (WSiN), tantalum silicide (TaSi), tantalum silicon nitride (TaSiN), ruthenium titanium nitride (RuTiN), cobalt silicide (CoSi), nickel silicide (NiSi), polycrystalline silicon, and / or combinations thereof. In some embodiments, the shielding metal layer SS may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, Co, Ni, Cu, Al, TiSi, TiSiN, WSi, WSiN, TaSi, TaSiN, RuTiN, CoSi, NiSi, and / or combinations thereof.

[0051] Bit line contact 156 can be disposed between the bottom surface of bit line BL and unit wiring layer 162, wherein the sidewalls of bit line contact 156 can be surrounded by bit line contact isolator 158. Bit line contact 156 can be electrically insulated from shielding metal layer SS through bit line contact isolator 158.

[0052] Multiple intermediate lines BUL can be arranged separately on the top surface of multiple bit lines BL. The multiple intermediate lines BUL can extend in a second horizontal direction (e.g., the Y direction) and can each cover the top surface of the multiple bit lines BL. The sidewalls of the multiple intermediate lines BUL can be covered by the first bit insulation layer 152.

[0053] In some embodiments, the multiple intermediate lines BUL may comprise an oxide semiconductor material. For example, the oxide semiconductor material may comprise zinc tin oxide (ZnO). x Sn y O), Indium zinc oxide (In) x Zn y O), zinc oxide (ZnO) x Indium gallium zinc oxide (In) x Ga y Zn z O), Indium gallium silicon oxide (In) x Ga y Si z O), indium tungsten oxide (In) x W y O), indium oxide (In) x O), tin oxide (Sn) x O), titanium dioxide (Ti) x O), zinc oxide (Zn) x ON z ), magnesium zinc oxide (Mg x Zn yO), Zirconia indium zinc (Zr) x In y Zn z O), hafnium indium zinc oxide (Hf) x In y Zn z O), tin indium zinc oxide (Sn) x In y Zn z O), aluminum tin indium zinc (Al) x Sn y In z Zn a O), silicon indium zinc (Si) x In y Zn z O), aluminum zinc tin oxide (Al) x Zn y Sn z O), gallium zinc tin oxide (Ga) x Zn y Sn z O) and / or zirconium zinc tin oxide (Zr) x Zn y Sn z At least one of (O). In some embodiments, the multiple intermediate line BULs may comprise semiconductor materials such as Si, Ge, and / or SiGe. In some embodiments, the multiple intermediate line BULs may further comprise n-type impurity ions. For example, n-type impurity ions may be doped into the multiple intermediate line BULs by means of an ion implantation process or the like.

[0054] In some embodiments, the sidewall of each of the plurality of center lines BUL may be aligned with the sidewall of each of the plurality of bit lines BL. In some embodiments, each of the plurality of center lines BUL may have a first width in a first horizontal direction (e.g., the X direction), and each of the plurality of bit lines BL may have a second width in the first horizontal direction (e.g., the X direction), wherein the first width may be the same as or similar to the second width. The first width being the same as or similar to the second width may mean that the second width has a value within a tolerance range (i.e., error tolerance) from the first width (e.g., a value within a tolerance range or acceptable error during the manufacturing process, such as a value within ±5% or ±10% of the difference compared to the first width).

[0055] In some embodiments, during the patterning process of multiple bit lines BL, multiple intermediate lines BUL can be patterned together. For example, intermediate line layer BULp (see Figure 24A and Figure 24B ) and bitline layer BLp (see Figure 24A and Figure 24BThe intermediate line layer BULp and the bit line layer BLp can be sequentially formed on the molded structure 130 and the unit transistor CTR, and then the intermediate line layer BULp and the bit line layer BLp can be patterned into lines to form multiple intermediate lines BUL and multiple bit lines BL. In this case, the sidewall of each of the multiple intermediate lines BUL can be aligned with the sidewall of each of the multiple bit lines BL.

[0056] In some embodiments, during the patterning process that forms multiple intermediate lines BUL and multiple bit lines BL, portions of the multiple bit lines BL may be exposed to the etching environment for an extended period. In this case, the sidewalls of the multiple bit lines BL may be tilted at a specific angle.

[0057] In some embodiments, the bit line BL may have a flat top surface and a flat bottom surface. For example, the bit line BL may have a uniform thickness in the vertical direction (e.g., the Z direction) over its entire length along a second horizontal direction (e.g., the Y direction). Additionally, the intermediate line BUL may have a flat top surface and a flat bottom surface. For example, the intermediate line BUL may have a uniform thickness in the vertical direction (e.g., the Z direction) over its entire length along a second horizontal direction (e.g., the Y direction).

[0058] By placing the intermediate line BUL between the bit line BL and the channel layer AP, the resistance between the bit line BL and the channel layer AP can be significantly reduced, thereby improving the electrical performance.

[0059] Multiple molded structures 130 and multiple unit transistors CTRs can be arranged on the top surface of multiple center lines BUL. For example, the multiple molded structures 130 can each extend in a first horizontal direction (e.g., the X direction), and the multiple unit transistors CTRs can be disposed on two sidewalls of each molded structure 130.

[0060] Each of the plurality of molding structures 130 may include a first molding layer 132, a second molding layer 134, and a third molding layer 136, each arranged in a vertical direction (e.g., the Z direction). For example, the third molding layer 136 may be disposed on the center line BUL and the first line insulation layer 152. For example, the third molding layer 136 may be in contact with the center line BUL and the first line insulation layer 152. The second molding layer 134 may be disposed on the third molding layer 136, and the first molding layer 132 may be disposed on the second molding layer 134.

[0061] In some embodiments, each of the first molding layer 132, the second molding layer 134, and the third molding layer 136 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and / or a low-k dielectric material. In some embodiments, the first molding layer 132 and the third molding layer 136 may include silicon nitride and / or silicon oxynitride, and the second molding layer 134 may include silicon oxide and / or a low-k dielectric material.

[0062] In some embodiments, the unit transistor CTR may include a channel layer AP, a gate insulating layer GI, and a word line WL sequentially arranged on the sidewall of the molded structure 130.

[0063] In some embodiments, the channel layer AP may extend in a vertical direction (e.g., the Z direction) and may have a top surface disposed in the same plane as (i.e., coplanar with) the top surface of the molding structure 130 and a bottom surface disposed in the same plane as (i.e., coplanar with) the bottom surface of the molding structure 130. The bottom surface of the channel layer AP and the bottom surface of the molding structure 130 may partially or completely contact the top surface of the centerline BUL.

[0064] When the process of forming the recess by removing a portion of the channel layer AP is not performed, the channel layer AP extends in the vertical direction (e.g., the Z direction), and the bit line BL has a linear shape extending in a second horizontal direction (e.g., the Y direction). Therefore, the vertical distance between the bit line BL and the shielding metal layer SS can be relatively small. Consequently, since the bit line BL is easily shielded by the shielding metal layer SS, the coupling capacitance due to bit line coupling can be significantly low.

[0065] In some embodiments, the channel layer AP may include an oxide semiconductor material, wherein the oxide semiconductor material may include, for example, zinc tin oxide (ZnO). x Sn y O), Indium zinc oxide (In) x Zn y O), zinc oxide (ZnO) x Indium gallium zinc oxide (In) x Ga y Zn z O), Indium gallium silicon oxide (In) x Ga y Si z O), indium tungsten oxide (In) x W y O), indium oxide (In) x O), tin oxide (Sn) x O), titanium dioxide (Ti) x O), zinc oxide (Zn) x ON z ), magnesium zinc oxide (Mgx Zn y O), Zirconia indium zinc (Zr) x In y Zn z O), hafnium indium zinc oxide (Hf) x In y Zn z O), tin indium zinc oxide (Sn) x In y Zn z O), aluminum tin indium zinc (Al) x Sn y In z Zn a O), silicon indium zinc (Si) x In y Zn z O), aluminum zinc tin oxide (Al) x Zn y Sn z O), gallium zinc tin oxide (Ga) x Zn y Sn z O) and / or zirconium zinc tin oxide (Zr) x Zn y Sn z At least one of (O). In some embodiments, the channel layer AP may further include n-type impurity ions. For example, n-type impurity ions can be doped into the channel layer AP by an ion implantation process or the like.

[0066] The gate insulating layer GI can be disposed on the sidewall of the channel layer AP. In some embodiments, the gate insulating layer GI may include at least one selected from ferroelectric materials and high-k dielectric materials having a higher dielectric constant than silicon oxide. In some embodiments, the gate insulating layer GI may include at least one material selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium oxysilane (HfSiON), lanthanum oxide (LaO), aluminum lanthanum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium oxysilane (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconate titanate (PbZrTiO), strontium bismuth tantalate (StTsBiP), bismuth iron bismuth oxide (FeBiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and / or lead scandium tantalum oxide (PbTaScO).

[0067] Word lines WL may be disposed on the sidewalls of the gate insulating layer GI. In some embodiments, two word lines WL may be spaced apart from each other and extend in a first horizontal direction (e.g., the X direction) between two adjacent molding structures 130. The top surface of the word line WL may be covered by the gate insulating layer GI, and the bottom surface of the word line WL may be disposed at a vertical horizontal height (e.g., height) higher than the bottom surface of the channel layer AP. In some embodiments, the word line WL may comprise Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, polysilicon, and / or combinations thereof.

[0068] The insulating pad 142 and the buried insulating layer 144 can be disposed between two adjacent word lines WL. The insulating pad 142 can be conformally disposed on the sidewalls and bottom surfaces of the two adjacent word lines WL, and can be disposed between the word line WL and the buried insulating layer 144, as well as between the gate insulating layer GI and the buried insulating layer 144.

[0069] Multiple landing pads (LPs) and oxide semiconductor layers (LPOs) covering the sidewalls and bottom surfaces of the multiple landing pads (CTRs) can be disposed on multiple unit transistors (CTRs). In other words, the sidewalls and bottom surface of each of the multiple landing pads (LPs) can be surrounded by oxide semiconductor layers (LPOs). Any one of the multiple landing pads (LPs) and the oxide semiconductor layers (LPOs) covering the sidewalls and bottom surfaces of that landing pad (LP) can constitute a landing pad structure (LPS). A unit capacitor (CAP) can be disposed on the landing pad structure (LPS).

[0070] In some embodiments, the oxide semiconductor layer LPO may include a portion disposed between the cell transistor CTR and the landing pad LP, for example, a portion disposed between the channel layer AP and the landing pad LP. The channel layer AP may be in contact with the oxide semiconductor layer LPO and may be spaced apart from the landing pad LP, with a portion of the oxide semiconductor layer LPO disposed between them. In some embodiments, the channel layer AP may be electrically connected to the landing pad LP through the oxide semiconductor layer LPO, and may be electrically connected to the cell capacitor CAP through the oxide semiconductor layer LPO and the landing pad LP.

[0071] In some embodiments, the oxide semiconductor layer LPO may conformally extend on the sidewalls and bottom surface of the landing pad LP. In some embodiments, the sidewalls of the oxide semiconductor layer LPO may be formed with a slope equal to or similar to that of the sidewalls of the landing pad LP. The fact that the sidewalls of the oxide semiconductor layer LPO have a slope equal to or similar to that of the sidewalls of the landing pad LP may mean that the slope has a value within a tolerance range (e.g., a value within a tolerance range or error tolerance during the manufacturing process, such as a value within ±5% or ±10% of the difference compared to the slope of the landing pad LP).

[0072] In some embodiments, the vertical horizontal height (i.e., height) of the top surface of the oxide semiconductor layer LPO can be the same as the vertical horizontal height (i.e., height) of the top surface of the landing pad LP. In other words, the contact surface between the unit capacitor CAP and the oxide semiconductor layer LPO can be located on the same plane as the contact surface between the unit capacitor CAP and the landing pad LP.

[0073] In some embodiments, the landing pad LP may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polysilicon, and / or combinations thereof. The unit capacitor CAP may have a metal-insulator-metal type capacitor structure. For example, the unit capacitor CAP may include a first electrode, a second electrode, and a capacitor dielectric layer disposed between the first and second electrodes.

[0074] In some embodiments, the oxide semiconductor layer LPO may comprise an oxide semiconductor material. For example, the oxide semiconductor material may comprise zinc tin oxide (ZnO). x Sn y O), Indium zinc oxide (In) x Zn y O), zinc oxide (ZnO) x Indium gallium zinc oxide (In) x Ga y Zn z O), Indium gallium silicon oxide (In) x Ga y Si z O), indium tungsten oxide (In) x W y O), indium oxide (In) x O), tin oxide (Sn) x O), titanium dioxide (Ti) x O), zinc oxide (Zn) x ON z ), magnesium zinc oxide (Mg x Zn y O), Zirconia indium zinc (Zr) x In y Zn z O), hafnium indium zinc oxide (Hf) x In y Zn z O), tin indium zinc oxide (Sn) x In y Zn z O), aluminum tin indium zinc (Al) x Sn y In z Zn aO), silicon indium zinc (Si) x In y Zn z O), aluminum zinc tin oxide (Al) x Zn y Sn z O), gallium zinc tin oxide (Ga) x Zn y Sn z O) and / or zirconium zinc tin oxide (Zr) x Zn y Sn z At least one of (O). In some embodiments, the oxide semiconductor layer LPO may further include n-type impurity ions. For example, n-type impurity ions can be doped into the oxide semiconductor layer LPO by an ion implantation process or the like.

[0075] The oxide semiconductor materials included in the channel layer AP, the oxide semiconductor layer LPO, and the intermediate line BUL can be defined as a first oxide semiconductor material, a second oxide semiconductor material, and a third oxide semiconductor material, respectively. The first oxide semiconductor material, the second oxide semiconductor material, and the third oxide semiconductor material can be configured independently and can include oxide semiconductors having the same or different compositions.

[0076] like Figure 5 As shown, the oxide semiconductor layer LPO may include a first oxide semiconductor layer LPO1 covering the sidewall of the landing pad LP or on the sidewall of the landing pad LP, and a second oxide semiconductor layer LPO2 covering the bottom surface of the landing pad LP or on the bottom surface of the landing pad LP. In some embodiments, a portion of the first oxide semiconductor layer LPO1 may partially or completely overlap with the second oxide semiconductor layer LPO2 in a first horizontal direction (e.g., the X direction) and a second horizontal direction (e.g., the Y direction), and another portion thereof may partially or completely overlap with the landing pad LP in the first horizontal direction (e.g., the X direction) and the second horizontal direction (e.g., the Y direction). In some embodiments, the second oxide semiconductor layer LPO2 may partially or completely overlap with the landing pad LP in a vertical direction (e.g., the Z direction). The first oxide semiconductor layer LPO1 may be electrically connected to the channel layer AP through the second oxide semiconductor layer LPO2, and the second oxide semiconductor layer LPO2 may be partially or completely contacted with the channel layer AP for electrical connection to the channel layer AP.

[0077] In some embodiments, the first oxide semiconductor layer LPO1 and the second oxide semiconductor layer LPO2 may be formed to have the same thickness. For example, the first oxide semiconductor layer LPO1 may have a first thickness T1 and the second oxide semiconductor layer LPO2 may have a second thickness T2, wherein the first thickness T1 and the second thickness T2 may be the same. However, since the first oxide semiconductor layer LPO1 and the second oxide semiconductor layer LPO2 are formed by separate manufacturing processes, the first oxide semiconductor layer LPO1 and the second oxide semiconductor layer LPO2 may also have different thicknesses. (Refer to below...) Figure 6A and Figure 6B The first oxide semiconductor layer LPO1 and the second oxide semiconductor layer LPO2, which have different thicknesses, are described in detail.

[0078] In some embodiments, the first oxide semiconductor layer LPO1 and the second oxide semiconductor layer LPO2 may comprise the same material. In some embodiments, the first oxide semiconductor layer LPO1 and the second oxide semiconductor layer LPO2 may comprise different materials. For example, the first oxide semiconductor layer LPO1 may comprise zinc tin oxide (ZnO). x Sn y The second oxide semiconductor layer LPO2 may include indium gallium zinc oxide (In₂O). x Ga y Zn z O). Since the first oxide semiconductor layer LPO1 and the second oxide semiconductor layer LPO2 are formed through separate manufacturing processes, the first oxide semiconductor layer LPO1 and the second oxide semiconductor layer LPO2 can be formed independently.

[0079] An insulating layer 176 may be disposed on the oxide semiconductor layer LPO and the unit capacitor CAP. The insulating layer 176 may partially or completely cover the outer wall of the oxide semiconductor layer LPO and the portion of the surface of the unit capacitor CAP not covered by the landing pads LP and the oxide semiconductor layer LPO. In some embodiments, the insulating layer 176 may be configured as a single-layer structure or a multi-layer structure and may include, for example, silicon oxide, silicon nitride, and / or combinations thereof. For example, as... Figure 13A As shown, insulating layer 176 may include a first insulating layer 176_1 on or around the sidewalls of the unit capacitor CAP and a second insulating layer 176_2 on or around the sidewalls of the oxide semiconductor layer LPO. The first insulating layer 176_1 may include silicon oxide, and the second insulating layer 176_2 may include silicon nitride. In some embodiments, when hydrogen plasma treatment is performed on the first insulating layer 176_1 and the second insulating layer 176_2, an insulating layer 176 having a relatively high hydrogen content may be provided.

[0080] Figure 6A This is a diagram of a semiconductor device 100A according to some embodiments.

[0081] Figure 6B This is a diagram of a semiconductor device 100B according to some embodiments.

[0082] because Figure 6A and Figure 6B Semiconductor devices 100A and 100B are each related to a reference. Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5 The semiconductor device 100 described is similarly configured, so the differences from the semiconductor device 100 will be mainly described below. Figure 6A and Figure 6B yes Figure 3 A magnified view of the middle section of CX1.

[0083] Reference Figure 6A and Figure 6B The semiconductor device 100A may include multiple unit transistors (CTRs) (see Figure 3 Multiple landing pads LP and multiple oxide semiconductor layers LPO respectively on or covering the sidewalls and bottom surfaces of the multiple landing pads LP can be respectively disposed on multiple unit transistors CTR.

[0084] In some embodiments, the first oxide semiconductor layer LPO1 and the second oxide semiconductor layer LPO2 may be formed with different thicknesses. For example, the first oxide semiconductor layer LPO1 may have a first thickness T1 and the second oxide semiconductor layer LPO2 may have a second thickness T2, wherein the first thickness T1 may be different from the second thickness T2. For example, as... Figure 6A As shown, the first thickness T1 of the first oxide semiconductor layer LPO1 can be smaller than the second thickness T2 of the second oxide semiconductor layer LPO2. For example, as... Figure 6B As shown, the first thickness T1 of the first oxide semiconductor layer LPO1 can be greater than the second thickness T2 of the second oxide semiconductor layer LPO2. Since the first oxide semiconductor layer LPO1 and the second oxide semiconductor layer LPO2 are each formed by separate manufacturing processes, the first oxide semiconductor layer LPO1 and the second oxide semiconductor layer LPO2 can be formed independently.

[0085] Figure 7 and Figure 8 This is a cross-sectional view of a semiconductor device according to some embodiments.

[0086] Figure 9 yes Figure 7A magnified view of the middle section of CX2.

[0087] because Figures 7 to 9 Semiconductor device 200 and reference Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5 The semiconductor device 100 described is similarly configured, so the differences from the semiconductor device 100 will be mainly described below. Figure 7 It corresponds to along Figure 2 A diagram of the region segmented by line A1-A1' in the diagram. Figure 8 It corresponds to along Figure 2 The diagram shows the area of ​​the section intercepted by line A2-A2'.

[0088] Reference Figure 7 , Figure 8 and Figure 9 The semiconductor device 200 may include multiple bit lines BL', wherein the multiple bit lines BL' may include multiple first bit lines BL1 and multiple second bit lines BL2.

[0089] In some embodiments, a plurality of first line BL1 may be spaced apart from each other in a first horizontal direction (e.g., the X direction), each may extend in a second horizontal direction (e.g., the Y direction), and may be arranged such that a shielding metal layer SS partially or completely fills the space between the plurality of first line BL1. Some portions of the shielding metal layer SS may partially or completely fill the space between the plurality of first line BL1 and extend along the second horizontal direction (e.g., the Y direction), and other portions of the shielding metal layer SS may be disposed between the bottom surface of the plurality of first line BL1 and the top surface of the unit wiring structure 160. The sidewalls and bottom surface of the first line BL1 may be covered by or located on the first line insulation layer 152 and the second line insulation layer 154, wherein the first line insulation layer 152 and the second line insulation layer 154 may be disposed between the sidewalls of the first line BL1 and the shielding metal layer SS and between the bottom surface of the first line BL1 and the shielding metal layer SS.

[0090] In some embodiments, each of the plurality of second bit lines BL2 may include a portion extending from the first bit line BL1 to partially or completely fill a portion of a recess RS1 on the channel layer AP. The recess RS1 may be formed by removing a portion of the channel layer AP during a manufacturing process. The plurality of second bit lines BL2 may be spaced apart from each other in a first horizontal direction (e.g., the X direction) and a second horizontal direction (e.g., the Y direction). The plurality of second bit lines BL2 may each be arranged between the channel layer AP and the first bit line BL1 and between a plurality of molded structures 130 facing each other. One end of each of the plurality of second bit lines BL2 may contact the channel layer AP, and the other end of each of the plurality of second bit lines BL2 may contact the first bit line BL1.

[0091] Bit line contact 156 can be disposed between the bottom surface of the first bit line BL1 and the unit wiring layer 162. The sidewalls of bit line contact 156 can be surrounded by bit line contact isolator 158. Bit line contact 156 can be electrically insulated from shielding metal layer SS through bit line contact isolator 158.

[0092] Multiple molded structures 130 and multiple unit transistors CTRs can be arranged on the top surface of multiple bit lines BL'. For example, the multiple molded structures 130 can each extend in a first horizontal direction (e.g., the X direction), and the multiple unit transistors CTRs can be arranged on two sidewalls of each molded structure 130.

[0093] Each of the plurality of molding structures 130 may include a first molding layer 132, a second molding layer 134, and a third molding layer 136, each arranged in a vertical direction (e.g., the Z direction). For example, the third molding layer 136 may be disposed on the bit line BL' and the first bit line insulating layer 152. For example, the third molding layer 136 may contact (i.e., on) the bit line BL' and on the first bit line insulating layer 152. In some embodiments, the bottom surface of the third molding layer 136 may contact the first bit line BL1. At least a portion of the sidewall of the third molding layer 136 may contact a portion of the second bit line BL2. The second molding layer 134 may be disposed on the third molding layer 136, and the first molding layer 132 may be disposed on the second molding layer 134.

[0094] In some embodiments, the unit transistor CTR may include a channel layer AP, a gate insulating layer GI, and a word line WL sequentially arranged on the sidewall of the molded structure 130.

[0095] In some embodiments, the channel layer AP may extend in a vertical direction (e.g., the Z direction) and may have a top surface disposed in the same plane as the top surface of the molding structure 130 (i.e., coplanar with it) and a bottom surface disposed in a different plane from the bottom surface of the molding structure 130 (i.e., not coplanar with it). The bottom surface of the channel layer AP and the bottom surface of the molding structure 130 may each contact the top surface of the bit line BL'. For example, the bottom surface of the channel layer AP may contact the top surface of the second bit line BL2, and the bottom surface of the molding structure 130 may contact the top surface of the first bit line BL1.

[0096] The gate insulating layer GI can be disposed on the sidewall of the channel layer AP and the sidewall of the second bit line BL2. The word line WL can be disposed on the sidewall of the gate insulating layer GI. The top surface of the word line WL can be covered by the gate insulating layer GI, and the bottom surface of the word line WL can be disposed at a vertical horizontal height (i.e., height) higher than the bottom surface of the channel layer AP. The insulating pad 142 and the buried insulating layer 144 can be disposed between two adjacent word lines WL.

[0097] Each of the plurality of landing pads LP and the oxide semiconductor layer LPO on or covering the sidewalls and bottom surfaces of each of the plurality of landing pads LP can be disposed on the plurality of cell transistors CTR. Each of the plurality of landing pads LP and the oxide semiconductor layer LPO can be related to the above reference. Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5 The same configuration is described above. The insulating layer 176 can be arranged to partially or completely surround the oxide semiconductor layer LPO and the unit capacitor CAP.

[0098] Figure 10 This is a schematic diagram of the landing pad structure LPS according to some embodiments.

[0099] Reference Figure 10 The landing pad structure LPS may include a landing pad LP and an oxide semiconductor layer LPO on or covering the sidewalls and bottom surfaces of the landing pad LP. The landing pad structure LPS may have a first height H1 and a first radius R1, and the landing pad LP may have a second height H2 and a second radius R2.

[0100] In this case, the first thickness T1 of the first oxide semiconductor layer LPO1 can be a value obtained by subtracting the second radius R2 from the first radius R1, and the second thickness T2 of the second oxide semiconductor layer LPO2 can be a value obtained by subtracting the second height H2 from the first height H1. Each of the first thickness T1 and the second thickness T2 can be relatively (i.e., approximately) constant.

[0101] The contact area between the landing pad LP and the oxide semiconductor layer LPO can be obtained from Equation 1 below:

[0102] [Equation 1]

[0103] A c =π(R²) 2 +2πR²×H²

[0104] In equation 1, A c R2 is the contact area between the landing pad LP and the oxide semiconductor layer LPO, R2 is the second radius R2, and H2 is the second height H2.

[0105] According to the comparative example, since the landing pad is directly electrically connected to the channel layer without the presence of an oxide semiconductor layer that electrically connects the landing pad to the channel layer, and the contact area between the landing pad and the channel layer is relatively small (e.g., within approximately 80 to 100 square nanometers), the contact resistance between the landing pad and the channel layer can be relatively large.

[0106] According to some embodiments, since an oxide semiconductor layer LPO is introduced to electrically connect the landing pad LP to the channel layer AP, and the oxide semiconductor layer LPO partially or completely surrounds the sidewalls and bottom surface of the landing pad LP to increase the contact area between the oxide semiconductor layer LPO and the landing pad LP (e.g., the contact area is within about 500 square nanometers to about 550 square nanometers), the contact resistance between the landing pad LP and the channel layer AP can be reduced by the oxide semiconductor layer LPO, thereby providing a semiconductor device with relatively improved electrical characteristics.

[0107] For example, it has been confirmed that the semiconductor device according to the comparative example has 5.0 × 10 -4 Ωcm 2 The contact resistance, while the semiconductor device according to some embodiments has a contact resistance of 6.3 × 10⁻⁶. -7 Ωcm 2 The contact resistance was reduced by approximately 790 to 800 times.

[0108] Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 18C , Figure 19A , Figure 19B , Figure 19C , Figure 20A , Figure 20B , Figure 20C , Figure 21A , Figure 21B , Figure 21C , Figure 22A , Figure 22B , Figure 23A , Figure 23B , Figure 24A , Figure 24B , Figure 25A , Figure 25B , Figure 25C , Figure 26A , Figure 26B , Figure 26C , Figure 27 , Figure 28 and Figure 29 The diagram sequentially illustrates methods for manufacturing a semiconductor device according to some embodiments.

[0109] Reference Figure 11A and Figure 11B Multiple unit capacitors CAP and a first insulating layer 176_1 on or around the sidewalls of the multiple unit capacitors CAP can be formed on the carrier substrate 210, and multiple landing pads LP can be formed on the multiple unit capacitors CAP respectively.

[0110] In some embodiments, such as Figure 11B As shown, multiple unit capacitors CAP and multiple landing pads LP can be arranged in a matrix shape. In some embodiments, the multiple unit capacitors CAP and multiple landing pads LP can be arranged in a hexagonal shape.

[0111] To form multiple landing pads LP, a conformally formed landing pad conductive layer (not shown) can first be formed on or covering the top surface of multiple unit capacitors CAP and the first insulating layer 176_1. Then, the multiple landing pads LP can be formed by patterning the landing pad conductive layer. The landing pad conductive layer may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polysilicon, and / or combinations thereof.

[0112] Reference Figure 12A and Figure 12B An oxide semiconductor material layer (not shown) can be formed to conformally cover the sidewalls and top surface of multiple landing pads LP, the exposed portion of the top surface of multiple unit capacitors CAP, and the top surface of the first insulating layer 176_1.

[0113] Subsequently, an etch-back process can be performed on the exposed portions of the top surfaces of the multiple landing pads LP, the top surfaces of the multiple unit capacitors CAP, and the top surface of the first insulating layer 176_1 to remove the exposed portions of the oxide semiconductor material layer on or covering the top surfaces of the multiple landing pads LP, the top surfaces of the multiple unit capacitors CAP, and the top surface of the first insulating layer 176_1. Other portions of the oxide semiconductor material layer on or covering the sidewalls of the multiple landing pads LP can be retained to form the first oxide semiconductor layer LPO1 on or covering the sidewalls of the multiple landing pads LP. The etch-back process can include wet and / or dry etching processes.

[0114] The oxide semiconductor material layer may include zinc tin oxide (ZnO) x Sn y O), Indium zinc oxide (In) x Zn y O), zinc oxide (ZnO) x Indium gallium zinc oxide (In) x Ga y Zn z O), Indium gallium silicon oxide (In) x Ga y Si z O), indium tungsten oxide (In) x W y O), indium oxide (In) x O), tin oxide (Sn) x O), titanium dioxide (Ti) x O), zinc oxide (Zn) x ON z ), magnesium zinc oxide (Mg x Zn yO), Zirconia indium zinc (Zr) x In y Zn z O), hafnium indium zinc oxide (Hf) x In y Zn z O), tin indium zinc oxide (Sn) x In y Zn z O), aluminum tin indium zinc (Al) x Sn y In z Zn a O), silicon indium zinc (Si) x In y Zn z O), aluminum zinc tin oxide (Al) x Zn y Sn z O), gallium zinc tin oxide (Ga) x Zn y Sn z O) and / or zirconium zinc tin oxide (Zr) x Zn y Sn z At least one of O).

[0115] After depositing the oxide semiconductor material layer, further processes such as ion implantation can be performed to dope n-type impurity ions into the oxide semiconductor material layer.

[0116] Reference Figure 13A and Figure 13B A second insulating layer 176_2 can be formed to partially or completely cover the sidewalls of the first oxide semiconductor layer LPO1, the exposed portions of the top surface of the plurality of unit capacitors CAP, and the top surface of the first insulating layer 176_1. For example, after depositing a silicon nitride film on or covering the sidewalls of the first oxide semiconductor layer LPO1, the exposed portions of the top surface of the plurality of unit capacitors CAP, and the top surface of the first insulating layer 176_1, the top surface of the silicon nitride film can be planarized by chemical mechanical polishing (CMP) to form the second insulating layer 176_2.

[0117] After depositing a silicon nitride film, the surface of the silicon nitride film can be further treated with hydrogen plasma to increase the hydrogen content in the silicon nitride film.

[0118] Reference Figure 14A and Figure 14BA metal back etching process can be performed on the top surface of the landing pad LP to remove a portion of the landing pad LP, thereby forming the landing pad recess RS2. The metal back etching process can include wet and / or dry etching processes. Considering the thickness of the second oxide semiconductor layer to be formed in the landing pad recess RS2, the metal back etching process can be performed for a certain period of time, and the metal back etching process can be performed such that a portion of the landing pad LP is removed while the rest is retained.

[0119] Reference Figure 15A and Figure 15B A second oxide semiconductor layer LPO2 can be formed in the landing pad recess RS2. To form the second oxide semiconductor layer LPO2, an oxide semiconductor material layer can be formed on or covering the top surface of the second insulating layer 176_2 and conformally on or covering the sidewalls and bottom surfaces of the landing pad recess RS2 to fill the landing pad recess RS2. Subsequently, a CMP process can be performed on the top surface of the oxide semiconductor material layer to remove the unfilled portion of the oxide semiconductor material layer in the landing pad recess RS2, while leaving the oxide semiconductor material layer partially or completely filling the remaining portions of the landing pad recess RS2.

[0120] The oxide semiconductor material layer may include zinc tin oxide (ZnO) x Sn y O), Indium zinc oxide (In) x Zn y O), zinc oxide (ZnO) x Indium gallium zinc oxide (In) x Ga y Zn z O), Indium gallium silicon oxide (In) x Ga y Si z O), indium tungsten oxide (In) x W y O), indium oxide (In) x O), tin oxide (Sn) x O), titanium dioxide (Ti) x O), zinc oxide (Zn) x ON z ), magnesium zinc oxide (Mg x Zn y O), Zirconia indium zinc (Zr) x In y Zn z O), hafnium indium zinc oxide (Hf) x In y Zn z O), tin indium zinc oxide (Sn) x Iny Zn z O), aluminum tin indium zinc (Al) x Sn y In z Zn a O), silicon indium zinc (Si) x In y Zn z O), aluminum zinc tin oxide (Al) x Zn y Sn z O), gallium zinc tin oxide (Ga) x Zn y Sn z O) and / or zirconium zinc tin oxide (Zr) x Zn y Sn z At least one of O).

[0121] After depositing the oxide semiconductor material layer, further processes such as ion implantation can be performed to dope n-type impurity ions into the oxide semiconductor material layer.

[0122] In some embodiments, after forming the second oxide semiconductor layer LPO2, a surface treatment process using plasma may be further performed on the first oxide semiconductor layer LPO1 and the second oxide semiconductor layer LPO2. For example, a surface treatment process using fluorine (F), boron (B), or argon (Ar), such as an ion bombardment process, may be further performed. The surface treatment process may include processes performed to increase or impart conductivity to the first oxide semiconductor layer LPO1 and the second oxide semiconductor layer LPO2.

[0123] Since the first oxide semiconductor layer LPO1 and the second oxide semiconductor layer LPO2 are formed sequentially through separate manufacturing processes, the first oxide semiconductor layer LPO1 and the second oxide semiconductor layer LPO2 can be formed independently. In some embodiments, the first oxide semiconductor layer LPO1 and the second oxide semiconductor layer LPO2 may comprise the same material. In some embodiments, the first oxide semiconductor layer LPO1 and the second oxide semiconductor layer LPO2 may comprise different materials. In some embodiments, the first oxide semiconductor layer LPO1 and the second oxide semiconductor layer LPO2 may be formed to have the same thickness. In some embodiments, the first oxide semiconductor layer LPO1 and the second oxide semiconductor layer LPO2 may be formed to have different thicknesses.

[0124] Reference Figure 16A and Figure 16B It can be applied to the oxide semiconductor layer LPO (i.e., Figure 15A and Figure 15BThe first oxide semiconductor layer LPO1 and the second oxide semiconductor layer LPO2) and the insulating layer 176 (i.e., Figure 15A and Figure 15B A molding structure 130 extending in a first horizontal direction (e.g., the X direction) is formed on a first insulating layer 176_1 and a second insulating layer 176_2. The molding structure 130 may include a first molding layer 132, a second molding layer 134, and a third molding layer 136 sequentially disposed on the oxide semiconductor layer LPO and the insulating layer 176. The molding structure 130 may include a sidewall 130H extending in the first horizontal direction (e.g., the X direction).

[0125] In some embodiments, the width of the molding structure 130 in the second horizontal direction (e.g., the Y direction) can be determined such that two oxide semiconductor layers LPO are exposed between two adjacent molding structures 130, each of the two oxide semiconductor layers LPO partially or completely on or covering the two landing pads LP in the second horizontal direction (e.g., the Y direction).

[0126] Reference Figure 17A and Figure 17B An initial channel layer APL can be formed on the sidewall 130H of the molded structure 130. The initial channel layer APL can be conformally disposed on the sidewall 130H and the top surface of the molded structure 130, and can also be conformally disposed on the top surface of the oxide semiconductor layer LPO and the top surface of the insulating layer 176. For example, the thickness of the initial channel layer APL disposed on the sidewall 130H of the molded structure 130 can be the same as or similar to the thickness of the initial channel layer APL disposed on the top surface of the molded structure 130, the top surface of the oxide semiconductor layer LPO, and the top surface of the insulating layer 176.

[0127] Reference Figure 18A , Figure 18B and Figure 18C An anisotropic etching process or a back etching process can be performed on the initial channel layer APL to remove the portion of the initial channel layer APL disposed on the top surface of the molded structure 130 and the top surface of the insulating layer 176, thereby leaving only the remaining portion of the initial channel layer APL disposed on the sidewall 130H of the molded structure 130.

[0128] The top surface of the molded structure 130 (e.g., the top surface of the third molding layer 136) can be exposed again using an anisotropic etching process or a re-etching process. The top surface of the molded structure 130 (e.g., the top surface of the third molding layer 136) can be positioned at the same horizontal height (i.e., height) as the top surface of the initial channel layer APL. Furthermore, as... Figure 18AAs shown, the bottom surface of the initial channel layer APL may be on or in contact with the top surface of the oxide semiconductor layer LPO. The initial channel layer APL may extend along a first horizontal direction (e.g., the X direction) on the sidewall 130H of the molded structure 130.

[0129] Reference Figure 19A , Figure 19B and Figure 19C A mask pattern M10 extending in a second horizontal direction (e.g., the Y direction) can be formed on the molded structure 130 and the initial channel layer APL.

[0130] In some embodiments, the mask pattern M10 may include a lower mask layer M14 that partially or completely fills the space between two adjacent initial channel layers APL, and an upper mask layer M12 on the lower mask layer M14. For example, the lower mask layer M14 may include silicon on a hard mask, and the upper mask layer M12 may include silicon oxynitride.

[0131] Reference Figure 20A , Figure 20B and Figure 20C The portion of the initial channel layer APL not covered by the mask pattern M10 can be removed. The portion of the initial channel layer APL on or covered by the mask pattern M10 can be retained without removal and can be referred to as the channel layer AP. The channel layers AP can be spaced apart from each other in a first horizontal direction (e.g., the X direction) between two adjacent molding structures 130, wherein one channel layer AP can be disposed on a landing pad LP.

[0132] Reference Figure 21A , Figure 21B and Figure 21C A gate insulating layer GI and a word line WL can be formed on the sidewall of the channel layer AP.

[0133] In some embodiments, the gate insulating layer GI may be conformally formed on the top surface of the molded structure 130, the sidewalls of the channel layer AP, and the top surface of the insulating layer 176.

[0134] Subsequently, word lines WL can be formed on the sidewalls of the channel layer AP, with the gate insulating layer GI disposed therebetween. In the process of forming word lines WL, after the word lines WL are conformally formed on the top surface and sidewalls of the gate insulating layer GI, an anisotropic etching process or a recessing process can be performed on the word lines WL to leave word lines WL only between two adjacent molded structures 130 (e.g., only on the sidewalls of the gate insulating layer GI).

[0135] like Figure 21CAs shown, between two adjacent molding structures 130, one word line WL can be disposed on the side wall of one of the two molding structures 130, while the other word line WL is disposed on the side wall of the other of the two molding structures 130.

[0136] Reference Figure 22A and Figure 22B Insulating pads 142 and buried insulating layers 144 can be sequentially formed on the word line WL.

[0137] Reference Figure 23A and Figure 23B A portion of the insulating pad 142 and a portion of the gate insulating layer GI, which are both disposed on the top surface of the molded structure 130, can be removed to expose the top surface of the molded structure 130 and the top surface of the channel layer AP again.

[0138] The process of removing a portion of the insulating pad 142 and a portion of the gate insulating layer GI may include a polishing or CMP process. After the polishing or CMP process, the top surface of the buried insulating layer 144, the top surface of the channel layer AP, and the top surface of the molded structure 130 may be arranged on the same plane.

[0139] Reference Figure 24A and Figure 24B The intermediate line layer BULp can be formed on the top surface of the buried insulation layer 144, the top surface of the trench layer AP, and the top surface of the molded structure 130.

[0140] In some embodiments, the intermediate line layer BULp may comprise an oxide semiconductor material and may comprise, for example, the same material as the material constituting the channel layer AP. In some embodiments, the intermediate line layer BULp may comprise an oxide semiconductor material and may comprise, for example, a material different from the material constituting the channel layer AP.

[0141] Subsequently, a bit line layer BLp can be formed on the intermediate line layer BULp. In some embodiments, the bit line layer BLp may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, Co, Ni, TiSi, TiSiN, WSi, WSiN, TaSi, TaSiN, RuTiN, CoSi, NiSi, polysilicon, and / or combinations thereof.

[0142] Reference Figure 25A , Figure 25B and Figure 25C In the bitline layer BLp (see Figure 24AMultiple mask patterns are formed on the surface, spaced apart from each other along a first horizontal direction (e.g., the X direction) and extending along a second horizontal direction (e.g., the Y direction). The multiple mask patterns can be used as etch masks to pattern the bit line layer BLp and the intermediate line layer BULp to form the bit line BL and the intermediate line BUL.

[0143] In some embodiments, bit line BL and intermediate line BUL may be patterned sequentially during the same process, such that the sidewalls of bit line BL can be aligned with the sidewalls of intermediate line BUL.

[0144] like Figure 25A As shown, the intermediate line BUL may have a line shape extending along a second horizontal direction (e.g., the Y direction), a portion of the bottom surface of the intermediate line BUL may be located on or in contact with the top surface of the channel layer AP, and the entire top surface of the intermediate line BUL may be located on or in contact with the entire bottom surface of the bit line BL.

[0145] Reference Figure 26A , Figure 26B and Figure 26C A first bit insulation layer 152 and a second bit insulation layer 154 can be sequentially formed on the intermediate line BUL and the bit line BL, and a shielding metal layer SS can be formed on the second bit insulation layer 154.

[0146] Reference Figure 27 A unit wiring structure 160 can be formed on the shielding metal layer SS. The unit wiring structure 160 may include a unit wiring layer 162, unit contacts 164, and a unit insulating layer 166. Furthermore, bit line contacts 156 may be formed to connect (i.e., electrically and / or physically connect) the unit wiring layer 162 to the bit line BL. The sidewalls of the bit line contacts 156 may be surrounded by bit line contact isolators 158. The bit line contacts 156 may be electrically insulated from the shielding metal layer SS by the bit line contact isolators 158.

[0147] A first bonding pad BP1 may be provided in the cell insulating layer 166 of the cell wiring structure 160. The first bonding pad BP1 may be electrically connected to the cell wiring layer 162. The top surface of the cell insulating layer 166 may be arranged on the same plane as the top surface of the first bonding pad BP1 (i.e., coplanar with it), and the top surface of the cell insulating layer 166 may be referred to as the bonding interface BIF.

[0148] Reference Figure 28 An active region AC can be formed on the substrate 110, and a peripheral circuit transistor PTR can be formed on the active region AC. For example, the peripheral circuit transistor PTR may include a gate electrode PTG, a gate insulating layer PTI, and a source / drain region PTS.

[0149] Then, peripheral circuit wiring 122 and peripheral circuit contacts 124 electrically connected to the substrate 110 and the peripheral circuit transistor PTR can be formed, and a peripheral circuit insulating layer 126 can be formed on the substrate 110 on or covering the peripheral circuit wiring 122 and peripheral circuit contacts 124. The peripheral circuit insulating layer 126 can be formed using oxide films, nitride films, low-k dielectric films and / or combinations thereof.

[0150] A second bonding pad BP2 can be provided in the peripheral circuit insulating layer 126. The second bonding pad BP2 can be electrically connected to the peripheral circuit wiring 122. The top surface of the peripheral circuit insulating layer 126 can be arranged on the same plane as the top surface of the second bonding pad BP2, and the top surface of the peripheral circuit insulating layer 126 can be referred to as the bonding interface BIF.

[0151] Reference Figure 29 The peripheral circuit area PCA and the cell array area MCA can be bonded to each other, such that the cell wiring structure 160 and the peripheral circuit wiring structure 120 are in partial or complete contact with each other. In some embodiments, the first bonding pad BP1 and the second bonding pad BP2 can be in partial or complete contact with each other at the bonding interface BIF, and the cell insulating layer 166 and the peripheral circuit insulating layer 126 can be in partial or complete contact with each other at the bonding interface BIF.

[0152] Then, the carrier substrate 210 can be removed.

[0153] The semiconductor device 100 can be completed by performing the above-described process.

[0154] According to some embodiments, the peripheral circuit area PCA and the cell array area MCA can be fabricated using separate wafers and then bonded to each other using bonding pads BP. When forming the cell array area MCA, the cell capacitor CAP can be formed first, and then the cell transistor CTR can be formed. Therefore, thermal damage to the cell transistor CTR can be prevented or minimized.

[0155] Figure 30A , Figure 30B , Figure 31A , Figure 31B , Figure 32A , Figure 32B and Figure 32C This is a diagram showing, in sequence, a method for manufacturing a semiconductor device according to some embodiments.

[0156] Specifically, Figure 30A and Figure 30B It is shown Figure 23A and Figure 23B The following process diagrams, Figure 32A , Figure 32B and Figure 32CIt is shown Figure 26A , Figure 26B and Figure 26C Diagram of the previous process.

[0157] Reference Figure 30A and Figure 30B ,from Figure 23A and Figure 23B As a result, the upper part of the channel layer AP can be removed to form the recess RS1. The sidewall of the recess RS1 may include a portion of the sidewall of the third molding layer 136, and the bottom surface of the recess RS1 may include the top surface of the channel layer AP.

[0158] Reference Figure 31A and Figure 31B A bit line layer BLp can be formed on the recess RS1 and the molding structure 130. In some embodiments, the bit line layer BLp may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, Co, Ni, TiSi, TiSiN, WSi, WSiN, TaSi, TaSiN, RuTiN, CoSi, NiSi, polysilicon, and / or combinations thereof. The bit line layer BLp may include a first bit line layer BLp1 extending in a first horizontal direction (e.g., the X direction) and a second horizontal direction (e.g., the Y direction), and a second bit line layer BLp2 extending from the first bit line layer BLp1 in a vertical direction (e.g., the Z direction) to partially or completely fill the recess RS1.

[0159] Reference Figure 32A , Figure 32B and Figure 32C It can be done in the bitline layer BLp (see Figure 31A Multiple mask patterns are formed on the surface, spaced apart from each other in a first horizontal direction (e.g., the X direction) and extending in a second horizontal direction (e.g., the Y direction), and the multiple mask patterns can be used as etch masks to pattern the bit line layer BLp to form the bit line BL.

[0160] Subsequently, through comparison with the above references Figure 26A , Figure 26B , Figure 26C , Figure 27 , Figure 28 and Figure 29 The manufacturing process described is similar to that described, and can be completed by reference. Figure 7 , Figure 8 and Figure 9 The semiconductor device 200 is described.

[0161] According to the comparative example, since the landing pad is directly electrically connected to the channel layer without the presence of an oxide semiconductor layer that electrically connects the landing pad to the channel layer, and the contact area between the landing pad and the channel layer is relatively small (e.g., within approximately 80 to 100 square nanometers), the contact resistance between the landing pad and the channel layer can be relatively large.

[0162] According to some embodiments, since an oxide semiconductor layer LPO is introduced to electrically connect the landing pad LP to the channel layer AP, and the oxide semiconductor layer LPO partially or completely surrounds the sidewalls and bottom surface of the landing pad LP to increase the contact area between the oxide semiconductor layer LPO and the landing pad LP (e.g., the contact area is within about 500 square nanometers to about 550 square nanometers), the contact resistance between the landing pad LP and the channel layer AP can be reduced by the oxide semiconductor layer LPO, thereby providing a semiconductor device with relatively improved electrical characteristics.

[0163] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made without departing from the scope of the appended claims.

Claims

1. A semiconductor device, comprising: Peripheral circuit area; as well as A cell array region on the peripheral circuit region, wherein the cell array region includes: A molded structure that extends in a first horizontal direction; A channel layer on the sidewall of the molded structure, wherein the channel layer comprises a first oxide semiconductor material; The letter line is located on the sidewall of the channel layer; Landing pads are located on the top surface of the trench layer; A bit line is provided on the bottom surface of the channel layer opposite to the top surface, wherein the bit line extends in a second horizontal direction intersecting the first horizontal direction. An oxide semiconductor layer is disposed on the bottom surface and one or more sidewalls of the landing pad, wherein the oxide semiconductor layer comprises a second oxide semiconductor material; and A unit capacitor, which is electrically connected to the channel layer via the landing pad and the oxide semiconductor layer.

2. The semiconductor device according to claim 1, wherein, Each of the first oxide semiconductor material and the second oxide semiconductor material comprises zinc tin oxide (ZnO). x Sn y O), Indium zinc oxide (In) x Zn y O), zinc oxide (ZnO) x Indium gallium zinc oxide (In) x Ga y Zn z O), Indium gallium silicon oxide (In) x Ga y Si z O), indium tungsten oxide (In) x W y O), indium oxide (In) x O), tin oxide (Sn) x O), titanium dioxide (Ti) x O), zinc oxide (Zn) x ON z ), magnesium zinc oxide (Mg x Zn y O), Zirconia indium zinc (Zr) x In y Zn z O), hafnium indium zinc oxide (Hf) x In y Zn z O), tin indium zinc oxide (Sn) x In y Zn z O), aluminum tin indium zinc (Al) x Sn y In z Zn a O), silicon indium zinc (Si) x In y Zn z O), aluminum zinc tin oxide (Al) x Zn y Sn z O), gallium zinc tin oxide (Ga) x Zn y Sn z O) and zirconium zinc tin oxide (Zr) x Zn y Sn z At least one of O).

3. The semiconductor device according to claim 1, wherein, The top surface of the channel layer is coplanar with the top surface of the molded structure, and The bottom surface of the channel layer is coplanar with the bottom surface of the molded structure.

4. The semiconductor device of claim 1, further comprising an intermediate line between the channel layer and the bit line. in, The center line extends in the second horizontal direction and includes a third oxide semiconductor material.

5. The semiconductor device according to claim 4, wherein, The third oxide semiconductor material includes zinc tin oxide (ZnO). x Sn y O), Indium zinc oxide (In) x Zn y O), zinc oxide (ZnO) x Indium gallium zinc oxide (In) x Ga y Zn z O), Indium gallium silicon oxide (In) x Ga y Si z O), indium tungsten oxide (In) x W y O), indium oxide (In) x O), tin oxide (Sn) x O), titanium dioxide (Ti) x O), zinc oxide (Zn) x ON z ), magnesium zinc oxide (Mg x Zn y O), Zirconia indium zinc (Zr) x In y Zn z O), hafnium indium zinc oxide (Hf) x In y Zn z O), tin indium zinc oxide (Sn) x In y Zn z O), aluminum tin indium zinc (Al) x Sn y In z Zn a O), silicon indium zinc (Si) x In y Zn z O), aluminum zinc tin oxide (Al) x Zn y Sn z O), gallium zinc tin oxide (Ga) x Zn y Sn z O) and zirconium zinc tin oxide (Zr) x Zn y Sn z At least one of O).

6. The semiconductor device according to claim 4, further comprising: A shielding metal layer is located on the bit line; as well as The bit line insulation layer is located on the sidewalls of the bit lines and the sidewalls of the intermediate lines. The bit line insulation layer is located between the shielding metal layer and the bit line, and between the shielding metal layer and the intermediate line.

7. The semiconductor device according to claim 1, wherein, The top surface of the channel layer is coplanar with the top surface of the molded structure, and The bottom surface of the channel layer is not coplanar with the bottom surface of the molded structure.

8. The semiconductor device according to claim 1, wherein, The bit line includes: The first line extends in the second horizontal direction; and The second line extends vertically between the first line and the channel layer.

9. The semiconductor device according to claim 1, wherein, The oxide semiconductor layer includes: A first oxide semiconductor layer is disposed on one or more sidewalls of the landing pad; and A second oxide semiconductor layer is formed on the bottom surface of the landing pad. The first oxide semiconductor layer comprises a material different from that of the second oxide semiconductor layer.

10. The semiconductor device according to claim 1, wherein, The oxide semiconductor layer includes: A first oxide semiconductor layer is disposed on one or more sidewalls of the landing pad; and A second oxide semiconductor layer is formed on the bottom surface of the landing pad. The thickness of the first oxide semiconductor layer is different from the thickness of the second oxide semiconductor layer.

11. A semiconductor device, comprising: The peripheral circuit region includes the substrate and peripheral circuit transistors; as well as A cell array region on the peripheral circuit region, wherein the cell array region includes: A molded structure that extends in a first horizontal direction; A channel layer on the sidewall of the molded structure, wherein the channel layer comprises a first oxide semiconductor material; The letter line is located on the sidewall of the channel layer; A gate insulating layer is located between the channel layer and the word line; Landing pads are located on the top surface of the trench layer; An oxide semiconductor layer is provided on the bottom surface and one or more sidewalls of the landing pad, wherein the oxide semiconductor layer comprises a second oxide semiconductor material; A unit capacitor, which is vertically separated from the channel layer by the landing pad and the oxide semiconductor layer; The position line extends on the bottom surface of the channel layer opposite to the top surface and in a second horizontal direction intersecting the first horizontal direction; Bit line insulating layer, on the bit line; and A shielding metal layer, which is separated from the bit line by the bit line insulation layer.

12. The semiconductor device according to claim 11, wherein, Each of the first oxide semiconductor material and the second oxide semiconductor material comprises zinc tin oxide (ZnO). x Sn y O), Indium zinc oxide (In) x Zn y O), zinc oxide (ZnO) x Indium gallium zinc oxide (In) x Ga y Zn z O), Indium gallium silicon oxide (In) x Ga y Si z O), indium tungsten oxide (In) x W y O), indium oxide (In) x O), tin oxide (Sn) x O), titanium dioxide (Ti) x O), zinc oxide (Zn) x ON z ), magnesium zinc oxide (Mg x Zn y O), Zirconia indium zinc (Zr) x In y Zn z O), hafnium indium zinc oxide (Hf) x In y Zn z O), tin indium zinc oxide (Sn) x In y Zn z O), aluminum tin indium zinc (Al) x Sn y In z Zn a O), silicon indium zinc (Si) x In y Zn z O), aluminum zinc tin oxide (Al) x Zn y Sn z O), gallium zinc tin oxide (Ga) x Zn y Sn z O) and zirconium zinc tin oxide (Zr) x Zn y Sn z At least one of O).

13. The semiconductor device of claim 11, further comprising an intermediate line between the bit line and the channel layer and between the bit line and the molding structure. in, The center line extends in the second horizontal direction and includes a third oxide semiconductor material.

14. The semiconductor device according to claim 13, wherein, The intermediate line is on the bit line insulation layer, and The bit line insulation layer is located between the intermediate line and the shielding metal layer.

15. The semiconductor device according to claim 13, wherein, The third oxide semiconductor material includes zinc tin oxide (ZnO). x Sn y O), Indium zinc oxide (In) x Zn y O), zinc oxide (ZnO) x Indium gallium zinc oxide (In) x Ga y Zn z O), Indium gallium silicon oxide (In) x Ga y Si z O), indium tungsten oxide (In) x W y O), indium oxide (In) x O), tin oxide (Sn) x O), titanium dioxide (Ti) x O), zinc oxide (Zn) x ON z ), magnesium zinc oxide (Mg x Zn y O), Zirconia indium zinc (Zr) x In y Zn z O), hafnium indium zinc oxide (Hf) x In y Zn z O), tin indium zinc oxide (Sn) x In y Zn z O), aluminum tin indium zinc (Al) x Sn y In z Zn a O), silicon indium zinc (Si) x In y Zn z O), aluminum zinc tin oxide (Al) x Zn y Sn z O), gallium zinc tin oxide (Ga) x Zn y Sn z O) and zirconium zinc tin oxide (Zr) x Zn y Sn z At least one of O).

16. The semiconductor device according to claim 11, wherein, The bit line includes: The first line extends in the second horizontal direction; and The second line extends in the vertical direction between the first line and the channel layer.

17. The semiconductor device according to claim 11, wherein, The oxide semiconductor layer includes: A first oxide semiconductor layer is disposed on one or more sidewalls of the landing pad; and A second oxide semiconductor layer is formed on the bottom surface of the landing pad. Wherein, the first oxide semiconductor layer comprises a material different from that of the second oxide semiconductor layer, and The thickness of the first oxide semiconductor layer is different from the thickness of the second oxide semiconductor layer.

18. A method of manufacturing a semiconductor device, the method comprising: A peripheral circuit region is formed, and a cell array region is formed on the peripheral circuit region, wherein forming the cell array region includes: A unit capacitor and a first insulating layer on the sidewalls of the unit capacitor are formed on a carrier substrate; A landing pad is formed on the unit capacitor; A first oxide semiconductor layer is formed on one or more sidewalls of the landing pad; A second insulating layer is formed on the first oxide semiconductor layer; An etching process is performed on the top surface of the landing pad to form a landing pad recess; A second oxide semiconductor layer is formed in the landing pad recess; and A molded structure is formed on the first oxide semiconductor layer, the second oxide semiconductor layer, and the second insulating layer. A channel layer is formed on the sidewall of the molded structure, word lines are formed on the sidewall of the channel layer, and bit lines are formed on the bottom surface of the channel layer.

19. The method of claim 18, further comprising: After the second oxide semiconductor layer is formed, a surface treatment process is performed on the first oxide semiconductor layer and the second oxide semiconductor layer using fluorine, boron or argon.

20. The method according to claim 18, wherein, The first oxide semiconductor layer comprises a different material than the second oxide semiconductor layer.

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