Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. A semiconductor device includes a first bit line extending in a first direction, a first word line extending in a second direction crossing the first direction, a first active region in contact with the first bit line, a back gate extending in parallel with the first word line, and a memory transistor in contact with the first active region. The first active region is disposed between the first word line and the back gate, and includes a vertical portion extending in a third direction crossing the first direction and the second direction, and a horizontal portion in contact with one end of the vertical portion and the first bit line.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority and benefit to Korean Patent Application No. 10-2024-0165698, filed on November 19, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The techniques and embodiments of this disclosure generally relate to semiconductor devices, and more specifically to semiconductor devices including memory cells. Background Technology

[0004] With miniaturization and high integration becoming major challenges in semiconductor devices, memory cells included in semiconductor devices can be formed with three-dimensional (3D) patterns. Miniaturized memory cells with three-dimensional (3D) patterns can be equipped with configurations that improve the operating characteristics of the memory cells. Summary of the Invention

[0005] Various embodiments of this disclosure relate to a 3D semiconductor memory device (also simply referred to as a semiconductor device) with higher integration and including two transistors.

[0006] Various embodiments of this disclosure relate to semiconductor memory devices configured to perform multiply-accumulate (MAC) operations.

[0007] According to one embodiment of the present disclosure, a semiconductor device may include: a first bit line extending along a first direction; a first word line extending along a second direction intersecting the first direction; a first active region contacting the first bit line; a back gate extending parallel to the first word line; and a memory transistor contacting the first active region, wherein the first active region is disposed between the first word line and the back gate, and includes a vertical portion and a horizontal portion, the vertical portion extending along a third direction intersecting the first and second directions, and the horizontal portion contacting the first bit line at one end of the vertical portion.

[0008] In one embodiment, the storage transistor may include: a storage gate formed to contact the other end of the vertical portion; a storage gate insulating layer formed to overlap with the storage gate; and a second active region formed to overlap with the storage gate insulating layer.

[0009] In one embodiment, the semiconductor device may further include: a second bit line extending along a first direction and contacting a second active region; and a second word line extending along the first direction and contacting the second active region.

[0010] In one embodiment, the second bit line may be configured to contact a plurality of second active regions arranged parallel to each other in a first direction; and the second word line may be configured to contact a plurality of second active regions arranged parallel to each other in a first direction.

[0011] In one embodiment, the semiconductor device may further include: an insulating layer disposed between the second bit line and the second word line and extending along a first direction.

[0012] In one embodiment, the storage gate may include a trench region disposed within the storage gate and extending upwardly from one surface of the storage gate toward another surface facing or opposite said one surface. A storage gate insulating layer may be formed to overlap with the sidewalls and bottom surface of the trench region. A second active region may be formed to overlap with the gate insulating layer.

[0013] In one embodiment, the memory transistor may include: a memory gate formed to contact the other end of a vertical portion; a memory gate insulating layer formed as a sidewall surrounding the memory gate; and a second active region formed to surround the memory gate insulating layer, wherein the second active region contacts a second bit line extending in a first direction and a second word line extending in a second direction.

[0014] In one embodiment, at least a portion of the second bit line may be configured to overlap with the second word line.

[0015] In one embodiment, the semiconductor device may further include: an isolation insulating layer disposed above the second bit line, wherein the second word line is disposed above the isolation insulating layer.

[0016] In one embodiment, the second bit line may be configured to contact a plurality of second active regions arranged parallel to each other in a first direction.

[0017] In one embodiment, the second word line may be configured to contact a plurality of second active regions arranged parallel to each other in a second direction.

[0018] In one embodiment, the second word line may be formed to surround at least a portion of the second active region.

[0019] In one embodiment, the second bit line may be formed around at least a portion of the second active region.

[0020] According to one embodiment of this disclosure, a method for manufacturing a semiconductor device may include: forming a first bit line extending along a first direction on a substrate; forming a back gate extending along a second direction intersecting the first direction on the first bit line; forming a first active region in contact with the first bit line; forming a first word line extending along the second direction on the first bit line; and forming a memory transistor in contact with the first active region, wherein the first active region is disposed between the first word line and the back gate, and includes a vertical portion and a horizontal portion, the vertical portion extending along a third direction intersecting the first and second directions, and the horizontal portion contacting one end of the vertical portion and the first bit line.

[0021] In one embodiment, forming a memory transistor may include: forming a memory gate in contact with the other end of a vertical portion; forming a trench region disposed in the memory gate and extending along a third direction from one surface of the memory gate toward another surface facing or opposite to the one surface; forming a memory gate insulating layer overlapping the bottom surface and side surfaces of the trench region; and forming a second active region overlapping the memory gate insulating layer.

[0022] In one embodiment, the method may further include: forming an isolation insulating layer on a second active region; forming a second bit line in the isolation insulating layer that contacts the second active region; and forming a second word line isolated from the second bit line by the isolation insulating layer, wherein the second bit line and the second word line are formed to extend along a first direction.

[0023] In one embodiment, forming a memory transistor may include: forming a memory gate in contact with the other end of a vertical portion; forming a memory gate insulating layer surrounding a sidewall of the memory gate; and forming a second active region surrounding the memory gate insulating layer.

[0024] In one embodiment, the method may further include: forming a second bit line extending along a first direction and surrounding at least a portion of a second active region; forming an isolation insulating layer disposed on the second bit line; and forming a second word line extending along a second direction and surrounding at least a portion of the second active region, wherein the second bit line is formed to overlap with at least a portion of the second word line.

[0025] According to one embodiment of this disclosure, a semiconductor device may include: a write bit line extending along a first direction; a write word line extending along a second direction intersecting the first direction; a back gate extending parallel to the write word line; a first active region contacting the write bit line and extending between the write word line and the back gate; a memory transistor contacting the first active region; a read bit line extending along the first direction; and a read word line extending along the first direction, wherein the memory transistor includes: a memory gate contacting the first active region and including a trench region; a memory gate insulating layer overlapping the sidewalls and bottom surface of the trench region; and a second active region overlapping the memory gate insulating layer, wherein the second active region contacts the read bit line and the read word line.

[0026] According to another embodiment of this disclosure, a semiconductor device may include: a write bit line extending along a first direction; a write word line extending along a second direction intersecting the first direction; a back gate extending parallel to the write word line; a first active region contacting the write bit line and extending between the write word line and the back gate; a memory transistor contacting the first active region; a read bit line extending along the first direction; and a read word line extending along the second direction, wherein the memory transistor includes: a pillar-shaped memory gate contacting the first active region; a memory gate insulating layer surrounding the sidewalls of the memory gate; and a second active region surrounding the memory gate insulating layer, wherein the second active region contacts the read bit line and the read word line.

[0027] It should be understood that the foregoing general description and the following detailed description of this disclosure are illustrative and descriptive, and are intended to provide further description of embodiments of the claimed disclosure. Attached Figure Description

[0028] The above and other features and advantages of embodiments of this disclosure will become apparent when considered in conjunction with the accompanying drawings and the following detailed description.

[0029] Figure 1A This is a cross-sectional view showing a portion of a semiconductor device according to an embodiment of the present disclosure.

[0030] Figure 1B This illustrates an embodiment according to the present disclosure. Figure 1A A cross-sectional view of the configuration of the semiconductor device taken by the first cutting line (A1-A1').

[0031] Figure 2 This is a circuit diagram illustrating a memory cell array of a semiconductor device according to an embodiment of the present disclosure.

[0032] Figure 3A This is a diagram illustrating a portion of a semiconductor device according to another embodiment of the present disclosure.

[0033] Figure 3B This illustrates another embodiment according to the present disclosure. Figure 3A A cross-sectional view of the configuration of the semiconductor device taken by the second cutting line (A2-A2').

[0034] Figure 4 This is a circuit diagram illustrating the connection relationship between read bit lines and read word lines of a semiconductor device according to another embodiment of the present disclosure.

[0035] Figures 5A to 15B This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0036] Figures 16A to 26B This is a diagram illustrating a method for manufacturing a semiconductor device according to another embodiment of the present disclosure. Detailed Implementation

[0037] This disclosure provides an embodiment of a semiconductor device including a memory cell, which can be used in a configuration that fundamentally solves one or more technical or engineering problems and mitigates limitations or disadvantages encountered in other semiconductor devices. Some embodiments of this disclosure relate to a semiconductor memory device with higher integration and including two transistors. Some embodiments of this disclosure relate to a semiconductor memory device that performs a multiply-accumulate (MAC) operation. In view of the above problems, this disclosure can provide a semiconductor device including a channel region having a vertical portion, thereby improving the integration of the semiconductor device. This disclosure can provide a semiconductor device that performs a multiply-accumulate (MAC) operation and has a storage transistor.

[0038] Reference will now be made in detail to embodiments of this disclosure as illustrated in the accompanying drawings. Where possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts. Although various modifications and alternatives may be made to embodiments of this disclosure, specific embodiments are shown in the drawings. However, these embodiments should not be construed as limited to the embodiments described herein, but rather include various modifications, equivalents, and / or alternatives to the embodiments described.

[0039] The embodiments of this disclosure can provide a variety of beneficial effects that can be directly or indirectly recognized by those skilled in the art.

[0040] In the following description, detailed descriptions of relevant known configurations or functions incorporated herein will be omitted to avoid obscuring the subject matter.

[0041] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the embodiments described. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the terms “comprises,” “includes,” “including,” and / or “comprising” as used in this specification specify the presence of the stated constituent elements, steps, operations, and / or components, but do not exclude the presence or addition of one or more other constituent elements, steps, operations, and / or components. The term “and / or” can include a combination of multiple items or any one of multiple items.

[0042] The semiconductor device and its manufacturing method according to embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0043] Figure 1A This is a cross-sectional view showing a portion of a semiconductor device 1 according to an embodiment of the present disclosure.

[0044] Figure 1B It shows along Figure 1A A cross-sectional view of the configuration of semiconductor device 1 taken by the first cutting line (A1-A1').

[0045] The following will refer to Figure 1A and Figure 1B The detailed structure of the semiconductor device 1 according to an embodiment of the present disclosure is described.

[0046] Semiconductor device 1 may include a write transistor region 10 and a storage transistor region 20. The storage transistor region 20 may be positioned relative to the write transistor region 10 along a third direction (D3). The storage transistor region 20 may be disposed on the transistor region 10.

[0047] Write transistor region 10 may include a plurality of write transistors 100. Storage transistor region 20 may include a plurality of storage transistors 300.

[0048] The write transistor region 10 may include: a substrate 110, a first stacked layer 120 formed on the substrate 110, a second stacked layer 130 formed on the first stacked layer 120, and a third stacked layer 140 formed on the second stacked layer 130.

[0049] The substrate 110 may include a silicon semiconductor material. For example, the substrate 110 may include silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium, monocrystalline silicon-germanium, polycrystalline silicon-germanium, and carbon-doped silicon, etc. The substrate 110 may include a plurality of control circuits configured to control the operation of the semiconductor device 1, and the area in which the control circuits are disposed will be referred to hereinafter as the peripheral circuit portion.

[0050] The first stacked layer 120 disposed above the substrate 110 may include a metal silicide material, such as cobalt silicide (CoSi). Because the first stacked layer 120 includes a metal silicide material, the operating resistance of the semiconductor device can be reduced. Furthermore, the first stacked layer 120 can serve as a protective layer for the substrate 110, helping to prevent damage to the substrate 110 during semiconductor manufacturing processes.

[0051] The second stacked layer 130 is disposed above the first stacked layer 120 and may be a layer comprising silicon nitride. Because the second stacked layer 130 comprises silicon nitride, damage to the substrate layer 110 can be prevented during high-temperature semiconductor manufacturing processes.

[0052] The third stacked layer 140 may be disposed on top of the second stacked layer 130. The third stacked layer 140 may be a layer including silicon oxide, etc.

[0053] The second stacked layer 130 and the third stacked layer 140 electrically isolate the control circuitry in the substrate layer 110 from the write bit line 150.

[0054] The write transistor region 10 may include a write bit line 150, a first write bit line isolation layer 160, a second write bit line isolation layer 170 and a third write bit line isolation layer 180, which are disposed on the third stacked layer 140.

[0055] The write bit line 150 may include multiple layers extending along a first direction (D1). For example, as Figure 1A As shown in the embodiments, the write bit line 150 may include: a first write bit line layer 152, a second write bit line layer 154 disposed on the first write bit line layer 152, and a third write bit line layer 156 disposed on the second write bit line layer 154. For example, the first write bit line layer 152 may include titanium nitride (TiN), the second write bit line layer 154 may include tungsten (W), and the third write bit line layer 156 may include titanium nitride (TiN).

[0056] The resistance of the write bit line 150 can be adjusted by controlling the material of the multiple layers included in the write bit line 150.

[0057] When the second write bit line layer 154 is exposed to oxygen, tungsten (W) can be oxidized, leading to short circuits and defects. The first write bit line layer 152 and the third write bit line layer 156 included in the write bit line 150 prevent the second write bit line layer 154 from being exposed to oxygen and oxidized.

[0058] In addition, since the titanium nitride (TiN) included in the first write bit line layer 152 has a higher adhesion to silicon oxide than tungsten (W), the first write bit line layer 152 is disposed between the third stacked layer 140 and the second write bit line layer 154, thereby improving the interface stability of the write bit line 150.

[0059] The write bit line 150 can be formed by depositing multiple layers and then using a mask for etching.

[0060] Write bit line 150 can be referred to as the first bit line.

[0061] The first write bit line isolation layer 160 and the second write bit line isolation layer 170 may be disposed between adjacent write bit lines 150. In one embodiment, the first write bit line isolation layer 160 may comprise silicon nitride, while the second write bit line isolation layer 170 may comprise silicon oxide.

[0062] The third write bit line isolation layer 180 may be arranged to overlap at least a portion of the write bit line 150. The third write bit line isolation layer 180 may include carbon-containing silicon oxide (SiCO). The third write bit line isolation layer 180 may electrically isolate the back gate 190 from the write bit line 150. The third write bit line isolation layer 180 may extend along a second direction (D2) and may overlap with multiple write bit lines 150.

[0063] Additionally, the write transistor region 10 may include: a back gate 190 formed on the third write bit line isolation layer 180, a first back gate isolation layer 200 formed on the back gate 190, a second back gate isolation layer 210, a first active region 220, a first write word line isolation layer 230, a write word line 240, a second write word line isolation layer 250, and a third write word line isolation layer 260.

[0064] The write transistor 100 may include: a back gate 190, a second back gate isolation layer 210, a first active region 220, a first write word line isolation layer 230, and a write word line 240.

[0065] The back gate 190 may extend along a second direction (D2). The back gate 190 may include: a metal, a metal mixture, a metal alloy, titanium nitride, tungsten, polysilicon, or a combination thereof. In one embodiment, the back gate 190 may include titanium nitride.

[0066] A voltage different from the voltage supplied to the write word line 240 can be provided to the back gate 190 to prevent interference between adjacent write word lines 240. For example, when an activation voltage level is provided to the write word line 240, a ground voltage can be provided to the back gate 190.

[0067] A first back gate isolation layer 200 may be formed on the back gate 190. The back gate 190 and the storage transistor region 20 may be electrically isolated from each other by the first back gate isolation layer 200. In one embodiment, the first back gate isolation layer 200 may comprise silicon nitride.

[0068] The second back gate isolation layer 210 may extend along the side surface of the back gate 190 and may be formed on top of the third write bit line isolation layer 180. In one embodiment, the second back gate isolation layer 210 may comprise silicon oxide.

[0069] According to one embodiment, the second back gate isolation layer 210 may include a high dielectric constant (high k) material, such as, for example, hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanate (SrTiO3).

[0070] The first active region 220 may include a channel region and a source / drain region of the write transistor 100. The first active region 220 may be the region in which the channel is formed during the operation of the write transistor 100.

[0071] The first active region 220 may include a semiconductor material or an oxide semiconductor material. In one embodiment, the first active region 220 may include an oxide semiconductor material, such as, for example, indium gallium zinc oxide (IGZO).

[0072] According to one embodiment, the first active region 220 may include: doped polycrystalline silicon, undoped polycrystalline silicon, amorphous silicon, indium zinc oxide (IZO), indium tin oxide (ITO), indium oxide (InO3), etc.

[0073] The first active region 220 may include: a horizontal portion extending along a first direction (D1) and a vertical portion extending along a third direction (D3).

[0074] The horizontal portion of the first active region 220 may contact the write bit line 150. Additionally, the vertical portion of the first active region 220 may have one side that contacts the horizontal portion and another side that contacts the storage transistor 300.

[0075] The first write word line isolation layer 230 may be disposed along the top (horizontal portion) and side surface (vertical portion) of the first active region 220. The first write word line isolation layer 230 may be disposed between the first active region 220 and the write word line 240, and may electrically isolate the write word line 240 from the first active region 220. In one embodiment, the first write word line isolation layer 230 may comprise silicon oxide.

[0076] According to one embodiment, the first write word line isolation layer 230 may include a high dielectric constant (high k) material, such as hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanate (SrTiO3).

[0077] The write word line 240 may extend along a second direction (D2). The write word line 240 may include: a metal, a metal mixture, a metal alloy, titanium nitride, tungsten, polysilicon, or a combination thereof, and may include titanium nitride as an example.

[0078] Write word line 240 can be used as the gate of write transistor 100. Write word line 240 can be a gate electrode that is provided with an activation voltage level during operation of write transistor 100.

[0079] For example, the write word line 240 can be referred to as the first word line.

[0080] A second write word line isolation layer 250 may be formed on the write word line 240 and may be disposed between adjacent write word lines 240. The second write word line isolation layer 250 can electrically isolate adjacent write word lines 240 from each other. Furthermore, the second write word line isolation layer 250 can electrically isolate the write word line 240 from the storage transistor 300. In one embodiment, the second write word line isolation layer 250 may include silicon nitride.

[0081] A third write word line isolation layer 260 may be formed over the second write word line isolation layer 250. In one embodiment, the third write word line isolation layer 260 may comprise silicon oxide.

[0082] The storage transistor region 20, including the storage transistor 300, can be formed on or on the write transistor region 10.

[0083] The storage transistor region 20 may include: a storage gate 310 formed to contact the other end of a vertical portion of the first active region 220; a storage gate isolation layer 320 disposed between adjacent storage gates 310; a storage gate insulating layer 330 formed to overlap with the storage gate 310; a second active region 340 formed to overlap with the storage gate insulating layer 330; and a second active region insulating layer 350 formed on the second active region 340.

[0084] In addition, the storage transistor region 20 may include: a storage gate isolation layer 320, a storage gate insulating layer 330, a second active region 340, and an isolation insulating layer 360, a read bit line 370, and a read word line 380 formed on the second active region insulating layer 350.

[0085] Each storage transistor 300 may include: a storage gate 310, a storage gate insulating layer 330, a second active region 340, and a second active region insulating layer 350.

[0086] The storage gate 310 may include a trench region. The trench region may extend in a third direction from one surface of the storage gate 310 toward another surface opposite to said one surface. For example, the other surface of the storage gate 310 may be the surface of the storage gate 310 that contacts a vertical portion of the first active region 220. More specifically, the storage gate 310 may have a flat bottom surface that extends parallel to and contacts a portion of the top surface of the second write word line isolation layer 250, a portion of the top surface of the first back gate isolation layer 200, the top surface of the first active region 220, the top surface of the second back gate isolation layer 210, and the top surface of the first write word line isolation layer 230. The storage gate 310 may also have vertically extending side surfaces with a height less than the height of the storage gate isolation layer 320.

[0087] Multiple memory gates 310 may be arranged in a matrix shape over the write transistor region 10. Each memory gate 310 may be configured to contact a vertical portion of a corresponding first active region in the first active region 220.

[0088] The storage gate insulating layer 330, the second active region 340, and the second active region insulating layer 350 can be disposed in the trench included in the storage gate 310.

[0089] According to one embodiment, the storage gate 310 may be formed in a cylindrical shape including trenches. According to one embodiment, the storage gate 310 may be formed in a pillar shape extending in a third direction and may include trenches formed inside the pillar.

[0090] The storage gate 310 may include: a metal, a metal mixture, a metal alloy, titanium nitride, tungsten, polysilicon, or a combination thereof, and as an example, may include titanium nitride.

[0091] Since the storage gate 310 includes a trench, the storage gate 310 can have a shape that surrounds the sidewalls of the second active region 340.

[0092] More specifically, the storage gate insulating layer 330 may be formed along the sidewalls and bottom surface formed within the trench included in the storage gate 310, and the second active region 340 may be formed along the sidewalls and bottom surface of the storage gate insulating layer 330. Therefore, the storage gate 310 may have a shape surrounding the sidewalls and bottom surface of the second active region 340. Thus, the storage gate 310 can be considered to have a gate all-around (GAA) shape.

[0093] The storage gate isolation layer 320 may be disposed between adjacent storage gates 310. The storage gate isolation layer 320 may include, for example, silicon oxide.

[0094] Since the storage gate isolation layer 320 is disposed between adjacent storage gates 310, adjacent storage gates 310 can be electrically isolated from each other.

[0095] The storage gate insulating layer 330 may be formed to overlap with the storage gate 310 and may be disposed in a trench included in the storage gate 310. According to one embodiment, the storage gate insulating layer 330 may be arranged to overlap with the sidewalls and bottom surface of the trench.

[0096] The storage gate insulating layer 330 may include silicon oxide. The storage gate insulating layer 330 may be disposed between the storage gate 310 and the second active region 340, and may electrically isolate the storage gate 310 and the second active region 340 from each other.

[0097] The second active region 340 may be arranged to overlap with the storage gate insulating layer 330. More specifically, the second active region 340 may be arranged to overlap with the storage gate insulating layer 330 disposed along the sidewalls and bottom surface of the trench.

[0098] The second active region 340 may include a semiconductor material or an oxide semiconductor material. In one embodiment, the second active region 340 may include an oxide semiconductor material, such as indium gallium zinc oxide (IGZO).

[0099] According to one embodiment, the second active region 340 may include doped polycrystalline silicon, undoped polycrystalline silicon, amorphous silicon, indium zinc oxide (IZO), indium tin oxide (ITO), indium oxide (InO3), etc.

[0100] The second active region insulating layer 350 may be formed to fill at least a portion of the trench included in the storage gate 310. The second active region insulating layer 350 may include silicon oxide.

[0101] Furthermore, the storage transistor region 20 may include an isolation insulating layer 360, a read bit line 370, and a read word line 380. The isolation insulating layer 360, the read bit line 370, and the read word line 380 may be formed on the storage gate isolation layer 320, the storage gate insulating layer 330, the second active region 340, and the second active region insulating layer 350.

[0102] The insulating layer 360 may include, for example, silicon nitride, and may be disposed between the read bit line 370 and the read word line 380. The insulating layer 360 can electrically isolate the read bit line 370 and the read word line 380 from each other.

[0103] According to one embodiment, at least a portion of the silicon nitride layer used as an insulating layer 360 may be removed, and read bit lines 370 and read word lines 380 may be formed in the region where the silicon nitride layer is partially removed.

[0104] Read bit line 370 and read word line 380 may include: metal, metal mixture, metal alloy, titanium nitride, tungsten, polysilicon, or combinations thereof. For example, read bit line 370 may include copper (Cu).

[0105] The read bit line 370 and read word line 380 can be arranged to contact the second active region 340. The read bit line 370 and read word line 380 can have a shape extending along a first direction (D1).

[0106] The adjacent read bit lines 370 and read word lines 380 can jointly contact a plurality of second active regions 340 arranged parallel to each other in the first direction (D1).

[0107] For example, read bit line 370 and read word line 380 can be referred to as the second bit line and the second word line, respectively.

[0108] A plurality of second active regions 340 arranged parallel to each other in the first direction (D1) can be respectively included in a plurality of memory transistors adjacent to each other in the column direction on the memory cell array. Therefore, the semiconductor device according to the present disclosure can output the sum of signals output from a plurality of memory cells arranged parallel to each other in the column direction.

[0109] For example, each storage transistor 300 according to an embodiment of the present disclosure can store arbitrary cell data. The cell data stored in each storage transistor 300 can vary depending on the voltage supplied to the write bit line 150 and the write word line 240. Furthermore, by adjusting the voltage supplied to each of the write bit line 150 and the write word line 240, arbitrary cell data can be stored in each storage cell.

[0110] Since adjacent read bit lines 370 and read word lines 380 are included in different storage transistors 300 and are jointly connected to a plurality of second active regions 340 arranged parallel to each other along the first direction (D1), the current value corresponding to the data of all cells stored in all storage transistors 300 sharing the read word line 380 can be provided to a single read bit line 370. Therefore, this configuration enables the collective reading of data from multiple storage transistors via a single read bit line, thereby improving read efficiency.

[0111] The cell data stored in each of the plurality of storage transistors 300 arranged along the first direction (D1) can correspond to weights used in a multiply-accumulate (MAC) operation. For example, each cell in the storage transistors 300 arranged along the first direction (D1) can hold data representing the weights used in the multiply-accumulate (MAC) operation, which is a fundamental building block in neural networks and digital signal processing. This arrangement enables the direct storage of weight values ​​in the storage cells, thereby facilitating efficient hardware-based MAC computation.

[0112] When an activation voltage level is provided to the read word line 380, a current corresponding to the cell data (e.g., weights) stored in each of the plurality of storage transistors 300 sharing the read word line 380 is provided to the read bit line 370 which is in common contact with the plurality of storage transistors 300, and the read bit line 370 can output a current value corresponding to the sum of the cell data.

[0113] Therefore, a semiconductor device according to an embodiment of the present disclosure may include a memory cell array that performs multiplication-accumulation (MAC) operations.

[0114] Figure 2 This is a circuit diagram illustrating a memory cell array of a semiconductor device according to an embodiment of the present disclosure.

[0115] Figure 2 The circuit diagram shows the first to third write word lines (WWL0, WWL1, WWL2) and the first to third write bit lines (WBL0, WBL1, WBL2).

[0116] also, Figure 2 Nine different write transistors are shown, each configured such that the write word line interfaces with the gate region, while the write bit line connects to either the source or drain region. Specifically, Figure 2 The first to ninth write transistors (WTR00, WTR01, WTR02, WTR10, WTR11, WTR12, WTR20, WTR21, WTR22) are shown. Each write transistor is configured such that the write word line is in contact with the gate region, while the write bit line is connected to the source region or the drain region.

[0117] Another of the source / drain regions of the first to ninth write transistors (WTR00, WTR01, WTR02, WTR10, WTR11, WTR12, WTR20, WTR21, WTR22) can be formed to make contact with the gate of any one of the first to ninth storage transistors (STR00, STR01, STR02, STR10, STR11, STR12, STR20, STR21, STR22).

[0118] Any one of the source / drain regions of the first to ninth storage transistors (STR00, STR01, STR02, STR10, STR11, STR12, STR20, STR21, STR22) can be configured to contact any one of the first to third read bit lines (RBL0, RBL1, RBL2).

[0119] In addition, another of the source / drain regions of the first to ninth storage transistors (STR00, STR01, STR02, STR10, STR11, STR12, STR20, STR21, STR22) can be formed to contact the first to third read word lines (RWL0, RWL1, RWL2).

[0120] Write transistors according to embodiments of this disclosure may share write word lines extending in the row direction. For example, a first write word line (WWL0) may share contact with the gates of a first write transistor (WTR00), a second write transistor (WTR01), and a third write transistor (WTR02) that are adjacent to each other in the row direction.

[0121] Furthermore, the write transistors according to embodiments of this disclosure may share a write bit line extending along the column direction. For example, the first write bit line (WBL0) may share contact with the source / drain regions of the first write transistor (WTR00), the fourth write transistor (WTR10), and the seventh write transistor (WTR20) that are adjacent to each other in the column direction.

[0122] According to embodiments of this disclosure, memory transistors can share read bit lines and read word lines extending along the column direction. For example, the first read bit line (RBL0) can share contact with the source / drain regions of the first memory transistor (STR00), the fourth memory transistor (STR10), and the seventh memory transistor (STR20) that are adjacent to each other in the column direction. Furthermore, the first read word line (RWL0) can share contact with the remaining source / drain regions of the first memory transistor (STR00), the fourth memory transistor (STR10), and the seventh memory transistor (STR20) that are adjacent to each other in the column direction.

[0123] When an activation voltage level is provided to any write word line and any write bit line, cell data can be supplied to the gate of the storage transistor through the write transistor.

[0124] The cell data provided to the storage transistor can be, for example, weights used in multiply-accumulate (MAC) operations.

[0125] According to one embodiment, any memory transistors included in the memory cell array share a read word line extending along the column direction, thereby enabling read word line signals to be provided jointly to a plurality of memory transistors arranged along the column direction.

[0126] For example, a read word line signal with an activation voltage level can be provided through a first read word line (RWL0) that is in common contact with the first storage transistor (STR00), the fourth storage transistor (STR10), and the seventh storage transistor (STR20) that are adjacent to each other in the column direction.

[0127] When a read word line signal with an activation voltage level is provided to the storage transistor, the current corresponding to the cell data stored in each of the multiple storage transistors sharing the read word line is provided to the read bit line that is in common contact with the multiple storage transistors, and the read bit line can output a current value corresponding to the sum of the cell data.

[0128] For example, a first read bit line (RBL0) that is in common contact with the first storage transistor (STR00), the fourth storage transistor (STR10), and the seventh storage transistor (STR20) that are adjacent to each other in the column direction can output a current corresponding to the sum of the cell data stored in each of the first storage transistor (STR00), the fourth storage transistor (STR10), and the seventh storage transistor (STR20).

[0129] According to one embodiment, for a memory cell array of a semiconductor device, the cell data stored in a plurality of memory transistors (e.g., a first memory transistor STR00, a fourth memory transistor STR10, and a seventh memory transistor STR20) arranged along the column direction can correspond to a weight matrix for multiply-accumulate (MAC) operations.

[0130] exist Figure 2 In the memory cell array, when an activation voltage level is provided to the first read word line (RWL0), a current corresponding to the value obtained by performing a MAC (multiplication-accumulation) operation between the activation voltage level provided to the first read word line (RWL0) and the cell data stored in the first memory transistor (STR00), the fourth memory transistor (STR10), and the seventh memory transistor (STR20) can be output through the first read bit line (RBL0).

[0131] Therefore, the semiconductor device according to embodiments of the present disclosure can provide a memory cell array that performs MAC (multiplication-accumulation) operations.

[0132] Figure 3A This is a diagram illustrating a portion of a semiconductor device according to another embodiment of the present disclosure.

[0133] Figure 3B This illustrates another embodiment according to the present disclosure. Figure 3A A cross-sectional view of the configuration of the semiconductor device taken by the second cutting line (A2-A2').

[0134] Semiconductor device 2 may include a write transistor region 10 and a storage transistor region 30 arranged along a third direction (D3).

[0135] The write transistor region 10 may include a plurality of write transistors 100, while the storage transistor region 30 may include a plurality of storage transistors 400.

[0136] refer to Figure 3A and Figure 3B The described write transistor region 10 and reference Figure 1A and Figure 1B The description of the write transistor region 10 is essentially the same, so for the sake of brevity, redundant descriptions of it will be omitted in this article.

[0137] According to one embodiment, the storage transistor region 30, which includes the storage transistor 400, may be arranged on or over the write transistor region 10.

[0138] The storage transistor region 30 may include: a read bit line 410, a read bit line isolation layer 420, an isolation insulating layer 430, a read word line 440, a read word line isolation layer 450, a second active region 460, a storage gate insulating layer 470, and a storage gate 480.

[0139] Each storage transistor 400 may include a storage gate 480, a storage gate insulating layer 470, and a second active region 460.

[0140] Multiple memory gates 480 can be arranged in a matrix on the write transistor region 10. Each memory gate 480 can be arranged to contact the vertical portion of the first active region 220.

[0141] According to one embodiment, the storage gate 480 may have a cylindrical shape extending along a third direction (D3). According to one embodiment, the storage gate 480 may have a cylindrical shape extending along a third direction (D3).

[0142] The storage gate 480 may include: a metal, a metal mixture, a metal alloy, titanium nitride, tungsten, polysilicon, or a combination thereof, and as an example, may include titanium nitride.

[0143] The storage gate insulating layer 470 can be formed as a sidewall surrounding the storage gate 480.

[0144] The storage gate insulating layer 470 may include silicon oxide. The storage gate insulating layer 470 may be disposed between the storage gate 480 and the second active region 460, and may electrically isolate the storage gate 480 and the second active region 460 from each other.

[0145] The second active region 460 can be arranged to surround the sidewall of the storage gate insulating layer 470. Therefore, the second active region 460 can be considered to have a full-around channel (CAA) shape.

[0146] The second active region 460 may include a semiconductor material or an oxide semiconductor material. In one embodiment, the second active region 460 may include an oxide semiconductor material, such as, for example, IGZO (indium gallium zinc oxide).

[0147] According to one embodiment, the second active region 460 may include: doped polycrystalline silicon, undoped polycrystalline silicon, amorphous silicon, indium zinc oxide (IZO), indium tin oxide (ITO), indium oxide (InO3), etc.

[0148] Furthermore, the storage transistor region 30 may include: a read bit line 410 formed to contact the upper part of the write transistor region 10; a read bit line isolation layer 420 disposed between adjacent read bit lines 410; an isolation insulating layer 430 formed on the read bit lines 410 and the read bit line isolation layer 420; a read word line 440 formed on the isolation insulating layer 430; and a read word line isolation layer 450 disposed between adjacent read word lines 440.

[0149] The read bit line 410 may include: a metal, a metal mixture, a metal alloy, titanium nitride, tungsten, polysilicon, or a combination thereof. In one embodiment, it may include copper (Cu).

[0150] The read bit line 410 may extend along a first direction (D1), and the read bit line isolation layer 420 may be disposed between adjacent read bit lines 410. The read bit line isolation layer 420 may include, for example, silicon nitride.

[0151] For example, read bit line 410 can be referred to as the second bit line.

[0152] The insulating layer 430 may include, for example, silicon nitride and may be disposed between the read bit line 410 and the read word line 440.

[0153] Furthermore, an isolation insulating layer 430 may be formed over the read bit line 410 and the read bit line isolation layer 420, and may electrically isolate the read bit line 410 and the read word line 440 from each other. According to one embodiment, the isolation insulating layer 430 may comprise silicon nitride.

[0154] The read word line 440 may extend along the second direction (D2), and the read word line isolation layer 450 may be disposed between adjacent read word lines 440. The read word line isolation layer 450 may include, for example, silicon nitride.

[0155] Read word line 440 can also be referred to as the second word line in the following text.

[0156] The read bit line 410 and read word line 440 may be arranged to contact the sidewall of the second active region 460. More specifically, each of the read bit line 410 and read word line 440 may be formed as at least a portion of the sidewall surrounding the second active region 460.

[0157] The read bit line 410 can be in contact with a plurality of second active regions 460 arranged parallel to each other in the first direction (D1).

[0158] The read word line 440 can make contact with a plurality of second active regions 460 arranged parallel to each other in the second direction (D2).

[0159] According to one embodiment, the storage gate 480 and the second active region 460 may be formed in the region where the read bit line 410 and the read word line 440 overlap.

[0160] Furthermore, the storage gate 480 may be formed to overlap with the vertical portion of the first active region 220.

[0161] According to one embodiment, the storage unit may include a write transistor 100 and a storage transistor 400, such that the storage unit can use the write transistor 100 and the storage transistor 400 to perform write and read operations.

[0162] When a signal corresponding to the activation voltage level is provided to the write word line 240, the write transistor 100 can be turned on. When the write transistor 100 is turned on, a voltage fluctuation occurs in the storage gate 480 due to the voltage provided to the write bit line 150. At this time, the data type (e.g., 0 or 1) stored in the storage gate 480 can be determined based on the voltage provided to the write bit line 150. The above operation can be referred to as a write operation.

[0163] When a signal other than the activation voltage level is provided to the write word line 240, the write transistor 100 can be turned off. When the write transistor 100 is turned off, the on / off operation of the storage transistor 400 can be determined based on voltage fluctuations that occur in the storage gate 480 during the write operation.

[0164] During a read operation, an activation voltage level can be provided to the read word line 440. Therefore, when the storage transistor 400 is turned on, a signal corresponding to the activation voltage level can be output through the read bit line 410, and when the storage transistor 400 is turned off, a signal corresponding to the deactivation voltage level (also called the inactive voltage level or deactivation voltage level) can be output through the read bit line 410. The operation of outputting a signal corresponding to the voltage fluctuations occurring in the storage gate 480 during a write operation can be called a read operation.

[0165] The semiconductor device according to embodiments of this disclosure can provide an array of memory cells that perform data write operations and data read operations.

[0166] Figure 4 This is a circuit diagram illustrating a memory cell array of a semiconductor device according to another embodiment of the present disclosure.

[0167] As from Figure 4 As can be seen in the circuit diagram, the first to third write word lines (WWL0, WWL1, WWL2) and the first to third write bit lines (WBL0, WBL1, WBL2) are shown.

[0168] also, Figure 4 The first through ninth write transistors (WTR00, WTR01, WTR02, WTR10, WTR11, WTR12, WTR20, WTR21, WTR22) are shown, each write transistor being configured such that the write word line contacts the gate region and the write bit line contacts one of the source / drain regions.

[0169] Another of the source / drain regions of the first to ninth write transistors (WTR00, WTR01, WTR02, WTR10, WTR11, WTR12, WTR20, WTR21, WTR22) can be formed to make contact with the gate of one of the first to ninth storage transistors (STR00, STR01, STR02, STR10, STR11, STR12, STR20, STR21, STR22).

[0170] One of the source / drain regions of the first to ninth storage transistors (STR00, STR01, STR02, STR10, STR11, STR12, STR20, STR21, STR22) can be formed to contact one of the first to third read bit lines (RBL0, RBL1, RBL2).

[0171] Furthermore, another of the source / drain regions of the first to ninth storage transistors (STR00, STR01, STR02, STR10, STR11, STR12, STR20, STR21, STR22) can be configured to contact one of the first to third read word lines (RWL0, RWL1, RWL2).

[0172] Write transistors according to embodiments of this disclosure may share write word lines extending in the row direction. For example, a first write word line (WWL0) may share contact with the gates of a first write transistor (WTR00), a second write transistor (WTR01), and a third write transistor (WTR02) that are adjacent to each other in the row direction.

[0173] Furthermore, the write transistors according to embodiments of this disclosure may share a write bit line extending along the column direction. For example, the first write bit line (WBL0) may share contact with the source / drain regions of the first write transistor (WTR00), the fourth write transistor (WTR10), and the seventh write transistor (WTR20) that are adjacent to each other in the column direction.

[0174] According to embodiments of this disclosure, memory transistors can share read bit lines extending along the column direction. For example, a first read bit line (RBL0) can share contact with the source / drain regions of a first memory transistor (STR00), a fourth memory transistor (STR10), and a seventh memory transistor (STR20) that are adjacent to each other in the column direction.

[0175] According to embodiments of this disclosure, memory transistors can share read word lines extending in the row direction. For example, a first read word line (RWL0) can share contact with the source / drain regions of a first memory transistor (STR00), a second memory transistor (STR01), and a third memory transistor (STR03) that are adjacent to each other in the row direction.

[0176] When an activation voltage level is provided to any write word line and any write bit line, cell data can be supplied to the gate of the storage transistor through the write transistor.

[0177] For example, when a signal corresponding to the activation voltage level is provided to the first write word line (WWL0), the first write transistor (WTR00), the second write transistor (WTR01), and the third write transistor (WTR02) can be turned on.

[0178] When a signal corresponding to the activation voltage level is provided to any write word line, voltage fluctuations may occur in the memory gate included in the memory transistor due to the voltage provided to the arbitrary write bit line.

[0179] For example, when a signal corresponding to the activation voltage level is provided to the first write word line (WWL0), voltage fluctuations may occur in the memory gate included in the first memory transistor (STR00) due to the voltage provided to the first write bit line (WBL0).

[0180] At this point, the type of data stored in the memory gate (e.g., 0 or 1) can be determined based on the voltage supplied to the write bit line. This operation can be referred to as a write operation.

[0181] The write transistor can be turned off when an inactive voltage level (also known as a deactivated voltage level or a deactivated voltage level) is provided to the write word line. When the write transistor is turned off, the on / off operation of the storage transistor can be determined based on the voltage fluctuations generated during the write operation.

[0182] The operation that outputs a signal corresponding to the voltage fluctuation that occurs in the storage gate during a write operation can be called a read operation.

[0183] For example, during a write operation, when signals corresponding to the activation voltage level are supplied to the first write word line (WWL0) and the first write bit line (WBL0), voltage fluctuations may occur in the memory gate included in the first memory transistor (STR00). Although an inactive voltage level (also known as a deactivated voltage level or deactivation voltage level) is supplied to the first write word line (WWL0), the first memory transistor (STR00) can still remain on.

[0184] Therefore, during a read operation, when an activation voltage level is provided to the first read word line (RWL0), a signal corresponding to the activation voltage level can be output to the first read bit line (RBL0) by keeping the first storage transistor (STR00) on.

[0185] When no data is stored in the gate of the first storage transistor (STR00) during a write operation, the first storage transistor (STR00) can remain in the off state during a read operation, so that a signal corresponding to the inactive voltage level (i.e., the deactivated voltage level or the inactive voltage level) can be output through the first read bit line (RBL0).

[0186] The semiconductor device according to embodiments of this disclosure can store data in any of the memory cells included in a memory cell array, or selectively output the stored data. The semiconductor device according to embodiments of this disclosure can read and / or write data.

[0187] Figures 5A to 15B This is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0188] exist Figure 5A and Figure 5B The shape of the write transistor region 10 is specifically shown in the figure.

[0189] Figure 5A This is a 3D view of the transistor region 10. (Reference) Figure 5A The front of the perspective view can be a cross-sectional view of the write transistor region 10 taken along a cutting line that passes through the center of the write bit line 150 and extends in the first direction (D1).

[0190] Alternatively, the side surface of the perspective view can be a cross-sectional view of the write transistor region 10 taken by a cutting line extending along the second direction (D2) of the write transistor region 10.

[0191] Figure 5B This illustrates an embodiment based on the present disclosure. Figure 5A The cross-sectional view of the semiconductor device configuration shown is taken by the third cutting line (A3-A3').

[0192] The third cutting line (A3-A3') may be a cutting line that passes through the center of the vertical portion included in the first active region 220 and extends along the second direction (D2).

[0193] The structure of the written transistor region 10 has been referenced. Figure 1A and Figure 1B It has been described in detail, so for the sake of brevity, redundant descriptions will be omitted here.

[0194] refer to Figure 5A and Figure 5B The vertical portions included in the plurality of first active regions 220 may be arranged to be spaced apart from each other by a predetermined distance relative to the second direction (D2). In addition, the first active region 220 may include, for example, two vertical portions and one horizontal portion.

[0195] Figure 6A and Figure 6B The process of forming a conductive material layer 310a on the write transistor region 10 is shown.

[0196] Figure 6A This is a perspective view of a semiconductor device, wherein a conductive material layer 310a is formed on the write transistor region 10.

[0197] Figure 6B This illustrates an embodiment based on the present disclosure. Figure 6A A cross-sectional view of the configuration of the semiconductor device taken by the fourth cutting line (A4-A4').

[0198] According to one embodiment, the conductive material layer 310a may include a metal, a metal mixture, a metal alloy, titanium nitride, tungsten, polycrystalline silicon, or a combination thereof, and titanium nitride may be included as an example.

[0199] A conductive material layer 310a can be formed by depositing a conductive material on the write transistor region 10.

[0200] The conductive material layer 310a can be arranged such that at least a portion of the conductive material layer 310a overlaps with the vertical portion of the first active region 220.

[0201] Figure 7A and Figure 7B A process for etching a portion of the conductive material layer 310a and forming a pre-storage gate 310b is shown.

[0202] Figure 7A This is a perspective view showing the configuration of a semiconductor device in which a pre-storage gate 310b is formed on the write transistor region 10.

[0203] Figure 7B This illustrates an embodiment based on the present disclosure. Figure 7A A cross-sectional view of the configuration of the semiconductor device taken by the fifth cutting line (A5-A5').

[0204] The pre-storage gate 310b can be formed by selectively etching regions of the conductive material layer 310a that do not overlap with the vertical portion of the first active region 220.

[0205] The pre-storage gate 310b may overlap with the vertical portion of the first active region 220.

[0206] Figure 8A and Figure 8B A process for forming a pre-storage gate isolation layer 320a over a pre-storage gate 310b is shown.

[0207] Figure 8A This is a perspective view showing the pre-storage gate isolation layer 320a formed on the pre-storage gate 310b.

[0208] Figure 8B This illustrates an embodiment based on the present disclosure. Figure 8A A cross-sectional view of the configuration of the semiconductor device taken by the sixth cutting line (A6-A6').

[0209] For example, the pre-storage gate isolation layer 320a may include silicon oxide.

[0210] A pre-storage gate isolation layer 320a can be deposited between adjacent pre-storage gates 310b to electrically isolate the pre-storage gates 310b from each other.

[0211] Figure 9A and Figure 9B The process for etching at least a portion of each pre-storage gate 310b to form the storage gate 310 and the trench region (T1) is shown.

[0212] Figure 9A This is a perspective view showing at least a portion of the pre-storage gate 310b that has been etched.

[0213] Figure 9B This illustrates an embodiment based on the present disclosure. Figure 9A A cross-sectional view of the configuration of the semiconductor device taken by the seventh cutting line (A7-A7').

[0214] Trench regions (T1) can be formed by selectively etching a portion of the pre-storage gate isolation layer 320a and each pre-storage gate 310b.

[0215] Each storage gate 310 can be formed by forming a trench region (T1) within each pre-storage gate 310b.

[0216] Figure 10A and Figure 10B The process for forming a pre-storage gate insulating layer 330a within the trench region is shown.

[0217] Figure 10A This is a perspective view showing the configuration of a semiconductor device in which a pre-storage gate insulating layer 330a is formed in the trench region (T1).

[0218] Figure 10B It shows along Figure 10A A cross-sectional view of the configuration of the semiconductor device taken by the eighth cutting line (A8-A8').

[0219] The pre-storage gate insulating layer 330a may include, for example, silicon oxide. The pre-storage gate insulating layer 330a may be formed to contact the side and bottom surfaces of the trench region (T1) formed within the storage gate 310.

[0220] Figure 11A and Figure 11B A process for forming a semiconductor material layer 340a on a pre-storage gate insulating layer 330a is shown.

[0221] Figure 11A This is a perspective view showing the semiconductor material layer 340a formed on the pre-storage gate insulating layer 330a.

[0222] Figure 11B It shows along Figure 11A A cross-sectional view of the configuration of the semiconductor device taken by the ninth cutting line (A9-A9').

[0223] The semiconductor material layer 340a may include, for example, a semiconductor material or an oxide semiconductor material. For example, the semiconductor material layer 340a may include an oxide semiconductor material, and the oxide semiconductor material may include IGZO (indium gallium zinc oxide).

[0224] According to another embodiment, the semiconductor material layer 340a may include: doped polycrystalline silicon, undoped polycrystalline silicon, amorphous silicon, indium zinc oxide (IZO), indium tin oxide (ITO), indium oxide (InO3), etc.

[0225] The semiconductor material layer 340a can contact the side surface and bottom surface of the pre-storage gate insulating layer 330a.

[0226] Figure 12A and Figure 12B The process for forming a pre-active region insulating layer 350a on a semiconductor material layer 340a is shown.

[0227] Figure 12A This is a perspective view showing the configuration of a semiconductor device in which a pre-active region insulating layer 350a is formed on a semiconductor material layer 340a.

[0228] Figure 12B It shows along Figure 12A A cross-sectional view of the configuration of the semiconductor device taken by the tenth cutting line (A10-A10').

[0229] The pre-active region insulating layer 350a may include, for example, silicon oxide.

[0230] The pre-active region insulating layer 350a can be formed to fill at least a portion of the trench region disposed in each storage gate 310. In addition, at least a portion of the pre-active region insulating layer 350a can contact the side surface and bottom surface of the semiconductor material layer 340a.

[0231] Figure 13A and Figure 13B A process for etching at least a portion of the pre-active region insulating layer 350a, the semiconductor material layer 340a, the pre-storage gate insulating layer 330a, and the pre-storage gate isolation layer 320a is shown.

[0232] Figure 13A This is a perspective view of a semiconductor device, wherein at least a portion of the pre-active region insulating layer 350a, at least a portion of the semiconductor material layer 340a, at least a portion of the pre-storage gate insulating layer 330a, and at least a portion of the pre-storage gate isolation layer 320a are etched.

[0233] Figure 13B It shows along Figure 13AA cross-sectional view of the configuration of the semiconductor device taken by the eleventh cutting line (A11-A11').

[0234] At least a portion of the pre-active region insulating layer 350a, at least a portion of the semiconductor material layer 340a, at least a portion of the pre-storage gate insulating layer 330a, and at least a portion of the pre-storage gate isolation layer 320a are etched to form the second active region insulating layer 350, the second active region 340, the storage gate insulating layer 330, and the storage gate isolation layer 320.

[0235] Furthermore, as the pre-active region insulating layer 350a is etched, at least a portion of the second active region 340 may be exposed.

[0236] Figure 14A and Figure 14B The process for forming a pre-isolation insulating layer 360a over the second active region insulating layer 350, the second active region 340, the storage gate insulating layer 330, and the storage gate isolation layer 320 is shown.

[0237] Figure 14A This is a perspective view of a semiconductor device, wherein a pre-isolation insulating layer 360a is formed on the second active region insulating layer 350, the second active region 340, the storage gate insulating layer 330, and the storage gate isolation layer 320.

[0238] Figure 14B It shows along Figure 14A A cross-sectional view of the configuration of the semiconductor device taken by the twelfth cutting line (A12-A12').

[0239] Reference Figure 14B The pre-isolation insulating layer 360a may include, for example, silicon nitride.

[0240] Figure 15A and Figure 15B The process for etching at least a portion of the pre-isolation insulating layer 360a and forming the read word line 380 and read bit line 370 is shown.

[0241] Figure 15A This is a perspective view showing the configuration of a semiconductor device forming an isolation insulating layer 360, a read word line 380, and a read bit line 370.

[0242] Figure 15B It shows along Figure 15A A cross-sectional view of the configuration of the semiconductor device taken by the thirteenth cutting line (A13-A13').

[0243] refer to Figure 15B The read word line 380 and the read bit line 370 may have a shape that extends along a first direction (D1).

[0244] The read word line 380 and read bit line 370 may include a metal mixture, a metal alloy, titanium nitride, tungsten, polysilicon, or a combination thereof, and, as an example, may include copper (Cu).

[0245] The read word line 380 and read bit line 370 can be formed by etching at least a portion of a pre-isolation insulating layer 360a that overlaps with the second active region 340 and then depositing a conductive material.

[0246] An insulating layer 360 can be disposed between the read word line 380 and the read bit line 370.

[0247] Figures 16A to 26B This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0248] exist Figure 16A and Figure 16B The shape of the write transistor region 10 is specifically shown in the figure.

[0249] Figure 16A This is a 3D view of the transistor region 10.

[0250] Figure 16B It shows along Figure 16A A cross-sectional view of the configuration of the semiconductor device taken by the fourteenth cutting line (A14-A14').

[0251] Figure 16A and Figure 16B Structure and Figure 5A and Figure 5B Since they are the same, redundant descriptions of them will be omitted here for the sake of brevity.

[0252] Figure 17A and Figure 17B The process for forming a pre-read bit line 410a and a read bit line isolation layer 420 over the write transistor region 10 is shown.

[0253] Figure 17A This is a perspective view showing the configuration of a semiconductor device in which a pre-read bit line 410a and a read bit line isolation layer 420 are formed on the write transistor region 10.

[0254] Figure 17B It shows along Figure 17A A cross-sectional view of the configuration of the semiconductor device taken by the fifteenth cutting line (A15-A15').

[0255] For example, the prefetch bit line 410a may include a metal, a metal mixture, a metal alloy, titanium nitride, tungsten, polysilicon, or a combination thereof. In one embodiment, it may include copper (Cu).

[0256] A read-before bit line material layer is deposited on the write transistor region 10, and the deposited read-before bit line material layer is isolated using a read-before bit line isolation layer 420, thereby forming a read-before bit line 410a.

[0257] The read bit line isolation layer 420 can be set between adjacent read bit lines 410a.

[0258] At least a portion of the deposited conductive material layer is etched into a shape extending along a first direction (D1), and silicon nitride or the like is deposited on the etched area to form a read bit line isolation layer 420.

[0259] Figure 18A and Figure 18B The process for forming an isolation insulating layer 430 over the pre-read bit line 410a and the read bit line isolation layer 420 is shown.

[0260] Figure 18A This is a perspective view showing the configuration of a semiconductor device in which an isolation insulating layer 430 is formed over a prefetch bit line 410a and a read bit line isolation layer 420.

[0261] Figure 18B It shows along Figure 18A A cross-sectional view of the configuration of the semiconductor device taken by the sixteenth cutting line (A16-A16').

[0262] refer to Figure 18B The insulating layer 430 may include, for example, silicon nitride.

[0263] Figure 19A and Figure 19B The process for forming a preread word line 440a and a read word line isolation layer 450 on the isolation insulating layer 430 is shown.

[0264] Figure 19A This is a perspective view showing the configuration of a semiconductor device in which a pre-read word line 440a and a read word line isolation layer 450 are formed on an isolation insulating layer 430.

[0265] Figure 19B It shows along Figure 19A A cross-sectional view of the configuration of the semiconductor device taken by the seventeenth cutting line (A17-A17').

[0266] For example, the prefetch word line 440a may include a metal, a metal mixture, a metal alloy, titanium nitride, tungsten, polysilicon, or a combination thereof. In one embodiment, it may include copper (Cu).

[0267] A prefetch word line material layer is deposited on the isolation insulating layer 430, and the deposited prefetch word line material layer is isolated using a read word line isolation layer 450, thereby forming a prefetch word line 440a.

[0268] The read word line isolation layer 450 can be set between adjacent pre-read word lines 440a.

[0269] At least a portion of the deposited conductive material layer is etched into a shape extending along the second direction (D2), and silicon nitride or the like is deposited on the etched area to form a read word line isolation layer 450.

[0270] Figure 20A and Figure 20B The process for etching at least a portion of the prefetch word line 440a, the isolation insulating layer 430, and the prefetch bit line 410a is shown.

[0271] Figure 20A This is a perspective view showing the configuration of a semiconductor device with etched prefetch word line 440a, isolation insulating layer 430, and prefetch bit line 410a.

[0272] Figure 20B It shows along Figure 20A A cross-sectional view of the configuration of a semiconductor device taken by the eighteenth cutting line (A18-A18').

[0273] refer to Figure 20B At least a portion of the prefetch word line 440a and prefetch bit line 410a, which are selectively etched to overlap with the vertical portion of the first active region 220, can be formed such that the read word line 440 and read bit line 410 can be formed.

[0274] Figure 21A and Figure 21B The process for forming a semiconductor material layer 460a in contact with the read word line 440, the isolation insulating layer 430, and the read bit line 410 is shown.

[0275] Figure 21A This is a perspective view of a semiconductor device, in which a semiconductor material layer 460a is formed in contact with the read word line 440, the isolation insulating layer 430 and the read bit line 410.

[0276] Figure 21B It shows along Figure 21A A cross-sectional view of the configuration of the semiconductor device taken by the nineteenth cutting line (A19-A19').

[0277] The semiconductor material layer 460a may include, for example, a semiconductor material or an oxide semiconductor material. For example, the semiconductor material may include an oxide semiconductor material, and the oxide semiconductor material may include IGZO (indium gallium zinc oxide).

[0278] According to another embodiment, the semiconductor material layer 460a may include doped polycrystalline silicon, undoped polycrystalline silicon, amorphous silicon, indium zinc oxide (IZO), indium tin oxide (ITO), indium oxide (InO3), etc.

[0279] The semiconductor material layer 460a can contact the etched side surfaces of the read word line 440 and the read bit line 410. The semiconductor material layer 460a can also contact the insulating layer 430 disposed between the read word line 440 and the read bit line 410. The semiconductor material layer 460a can also be formed on the exposed top surface of the first active region 220 and the exposed top surface of the portion of the first write word line insulating layer 230 that does not overlap with the read word line 440.

[0280] Figure 22A and Figure 22B The process for selectively etching semiconductor material layer 460a to form second active region 460 is shown.

[0281] Figure 22A This is a perspective view showing the configuration of a semiconductor device having a second active region 460.

[0282] Figure 22B It shows along Figure 22A A cross-sectional view of the configuration of the semiconductor device taken by the twentieth cutting line (A20-A20').

[0283] Through an etching process, the semiconductor material layer 460a that contacts the sidewalls of the read word line 440, the isolation insulating layer 430, and the read bit line 410 can be selectively kept unused (or selectively retained). In this case, the semiconductor material layer 460a that is selectively kept unused can be referred to as the active region 460.

[0284] The second active region 460 can be formed by selectively etching the bottom and top surfaces of the semiconductor material layer 460a. For example, the bottom and top surfaces of the semiconductor material layer 460a can be selectively etched using a dry etching process.

[0285] The second active region 460 can be arranged to be spaced apart from the vertical portion of the first active region 220.

[0286] Figure 23A and Figure 23B The process for forming a pre-storage gate insulating layer 470a in contact with the second active region 460 is shown.

[0287] Figure 23A This is a perspective view showing the configuration of a semiconductor device in which a pre-storage gate insulating layer 470a is formed in contact with the active region 460.

[0288] Figure 23B It shows along Figure 22A A cross-sectional view of the configuration of the semiconductor device taken by the 21st cutting line (A21-A21').

[0289] refer to Figure 23B As an example, the pre-stored gate insulating layer 470a may include silicon oxide.

[0290] The pre-storage gate insulating layer 470a can be formed to contact the side surface of the second active region 460. For example... Figure 23B As shown, the pre-stored gate insulating layer 470a can also contact the top surface of the read word line 440 and the top surface of the first active region 220.

[0291] Figure 24A and Figure 24B The process for selectively etching the pre-storage gate insulating layer 470a to form the storage gate insulating layer 470 is shown.

[0292] Figure 24A This is a perspective view showing the configuration of a semiconductor device in which a storage gate insulating layer 470 is formed.

[0293] Figure 24B It shows along Figure 24A A cross-sectional view of the configuration of the semiconductor device taken by the 22nd cutting line (A22-A22').

[0294] refer to Figure 24A and Figure 24B The pre-storage gate insulating layer 470a, which contacts the sidewall of the second active region 460, can be selectively retained using an etching process. In this case, the selectively retained pre-storage gate insulating layer 470a can be referred to as the storage gate insulating layer 470. For example, the bottom and top surfaces of the pre-storage gate insulating layer 470a can be selectively etched using a dry etching process.

[0295] Figure 25A and Figure 25B The process for forming a pre-storage gate 480a in contact with the storage gate insulating layer 470 is shown.

[0296] Figure 25A This is a perspective view showing the configuration of a semiconductor device in which a pre-storage gate 480a is formed.

[0297] Figure 25B It shows along Figure 25A A cross-sectional view of the configuration of the semiconductor device taken by the 23rd cutting line (A23-A23').

[0298] For example, the pre-storage gate 480a may include a metal, a metal mixture, a metal alloy, titanium nitride, tungsten, polysilicon, or a combination thereof. In one embodiment, as an example, the pre-storage gate 480a may include titanium nitride.

[0299] The pre-storage gate 480a can contact the storage gate insulating layer 470 and can fill at least a portion of the etched read word line 440 and at least a portion of the etched read bit line 410.

[0300] The bottom surface of the pre-storage gate 480a can contact the vertical portion of the first active region 220.

[0301] Figure 26A and Figure 26B The process for selectively etching the pre-storage gate 480a to form the storage gate 480 is shown.

[0302] Figure 26A This is a perspective view showing the configuration of the semiconductor device in which the memory gate 480 is formed.

[0303] Figure 26B It shows along Figure 26A A cross-sectional view of the configuration of the semiconductor device taken by the 24th cutting line (A24-A24').

[0304] The bottom surface of the memory gate 480 may contact the vertical portion of the first active region 220. Each memory gate 480 may be configured to be spaced apart from adjacent memory gates 480.

[0305] As can be clearly seen from the above description, the semiconductor device based on the embodiments of this disclosure includes a channel region having a vertical portion, thereby enabling the semiconductor device to have a higher degree of integration.

[0306] The semiconductor device based on embodiments of this disclosure has a storage transistor and performs a multiply-accumulate (MAC) operation.

[0307] The embodiments of this disclosure can provide a variety of beneficial effects that can be directly or indirectly recognized by those skilled in the art.

[0308] Those skilled in the art will understand that this disclosure can be implemented in other specific ways than those described herein. Furthermore, claims not expressly set forth in the appended claims may be combined to form embodiments, or incorporated as new claims through subsequent amendments after the filing of the application.

[0309] Although several exemplary embodiments have been described, it should be understood that modifications and enhancements to the disclosed embodiments and other embodiments can be devised based on the content described and / or illustrated in this disclosure. Furthermore, these embodiments can be combined to form additional embodiments.

Claims

1. A semiconductor device, comprising: The first line extends along the first direction; The first character line extends along a second direction that intersects the first direction; The first active region is in contact with the first bit line; The back grille extends parallel to the first letter line; as well as A storage transistor, which contacts the first active region. in The first active region is disposed between the first word line and the back gate, and includes a vertical portion and a horizontal portion. The vertical portion extends along a third direction that intersects the first direction and the second direction, and the horizontal portion contacts the first bit line at one end of the vertical portion.

2. The semiconductor device according to claim 1, wherein, The storage transistor includes: A storage gate is formed to contact the other end of the vertical portion; A storage gate insulating layer, which is formed to overlap the storage gate; and The second active region is formed to overlap with the storage gate insulating layer.

3. The semiconductor device according to claim 2, further comprising: The second bit line extends along the first direction and contacts the second active region; as well as The second line extends along the first direction and contacts the second active region.

4. The semiconductor device according to claim 3, wherein: The second bit line contacts a plurality of second active regions arranged parallel to each other in the first direction; and The second word line contacts a plurality of second active regions arranged parallel to each other in the first direction.

5. The semiconductor device according to claim 3, further comprising: An insulating layer is disposed between the second bit line and the second word line and extends along the first direction.

6. The semiconductor device according to claim 2, wherein: The storage gate includes a trench region disposed in the storage gate and extending along the third direction from one surface of the storage gate toward another surface facing or opposite to the one surface; The storage gate insulating layer overlaps with the sidewalls and bottom surface of the trench region; as well as The second active region overlaps with the gate insulating layer.

7. The semiconductor device according to claim 1, wherein, The storage transistor includes: A storage gate, which is in contact with the other end of the vertical portion; A storage gate insulating layer surrounding the sidewalls of the storage gate; and The second active region surrounds the storage gate insulating layer. in The second active region is in contact with the second bit line extending along the first direction and the second word line extending along the second direction.

8. The semiconductor device according to claim 7, wherein, At least a portion of the second bit line overlaps with the second word line.

9. The semiconductor device according to claim 7, further comprising: An insulating layer is disposed above the second bit line. The second digit is disposed on the insulating layer.

10. The semiconductor device according to claim 7, wherein The second bit line contacts a plurality of second active regions arranged parallel to each other in the first direction.

11. The semiconductor device according to claim 7, wherein The second word line contacts a plurality of second active regions arranged parallel to each other in the second direction.

12. The semiconductor device according to claim 7, wherein, The second word line surrounds at least a portion of the second active region.

13. The semiconductor device according to claim 7, wherein, The second bit line surrounds at least a portion of the second active region.

14. A method for manufacturing a semiconductor device, the method comprising: A first line extending in a first direction is formed on the substrate; A back gate is formed above the first line, extending in a second direction that intersects the first direction; A first active region is formed that contacts the first bit line; A first letter line extending in the second direction is formed above the first letter line; as well as A memory transistor is formed in contact with the first active region. in The first active region is disposed between the first word line and the back gate, and includes a vertical portion and a horizontal portion. The vertical portion extends along a third direction that intersects the first direction and the second direction, and the horizontal portion contacts the first bit line at one end of the vertical portion.

15. The method according to claim 14, wherein, Forming the memory transistor includes: A memory gate is formed that contacts the other end of the vertical portion; A trench region is formed, the trench region being disposed in the memory gate and extending along the third direction from one surface of the memory gate toward another surface facing or opposite to the one surface; A storage gate insulating layer overlapping the bottom and side surfaces of the trench region is formed; and A second active region is formed that overlaps with the storage gate insulating layer.

16. The method of claim 15, further comprising: An isolation insulating layer is formed on the second active region; A second bit line is formed within the insulating layer to contact the second active region; as well as A second word line is formed, isolated from the second bit line by the insulating layer. The second bit line and the second word line are formed to extend along the first direction.

17. The method of claim 14, wherein, Forming the memory transistor includes: A memory gate is formed that contacts the other end of the vertical portion; A storage gate insulating layer is formed around the sidewalls of the storage gate; and A second active region is formed around the storage gate insulating layer.

18. The method of claim 17, further comprising: A second bit line is formed that extends along the first direction and surrounds at least a portion of the second active region; An isolation insulating layer is formed on the second bit line; as well as A second word line is formed that extends along the second direction and surrounds at least a portion of the second active region. in The second bit line is formed to overlap with at least a portion of the second word line.

19. A semiconductor device, comprising: Write the bit line, which extends along the first direction; Write word lines that extend along a second direction that intersects the first direction; A back gate that extends parallel to the write word line; A first active region is in contact with the write bit line and extends between the write word line and the back gate; A storage transistor is in contact with the first active region; Read the bit line, which extends along the first direction; as well as Read the word line, which extends along the first direction. The storage transistor includes: A storage gate, which contacts the first active region and includes a trench region; A storage gate insulating layer that overlaps with the sidewalls and bottom surface of the trench region; and The second active region overlaps with the storage gate insulating layer. in The second active region is in contact with the read bit line and the read word line.

20. A semiconductor device, comprising: Write the bit line, which extends along the first direction; Write word lines that extend along a second direction that intersects the first direction; A back gate that extends parallel to the write word line; A first active region is in contact with the write bit line and extends between the write word line and the back gate; A storage transistor is in contact with the first active region; Read the bit line, which extends along the first direction; as well as Read the word line, which extends along the second direction. The storage transistor includes: A columnar storage gate is in contact with the first active region; A storage gate insulating layer surrounding the sidewalls of the storage gate; and The second active region surrounds the storage gate insulating layer. in The second active region is in contact with the read bit line and the read word line.

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