Semiconductor device with contact structure

Abstract

A semiconductor device includes: a substrate; an active region in the substrate; a device isolation layer defining an active region; a gate structure in the substrate and extending across the active region in a first horizontal direction; a bit line structure on the substrate, extending in a second horizontal direction intersecting the first horizontal direction, and intersecting the gate structure; and a contact structure between the bit line structures, where the contact structure includes: a first contact plug in contact with the active region; a second contact plug on the first contact plug; and a third contact plug on the second contact plug, and wherein the first vertical center axis of the active region, the second vertical center axis of the first contact plug, and the third vertical center axis of the third contact plug are offset from each other in the first horizontal direction.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0164364, filed on November 18, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes. Technical Field

[0002] This disclosure relates to semiconductor devices including contact structures. Background Technology

[0003] As the demand for high performance, high speed, and / or versatility in semiconductor devices increases, the integration level of semiconductor devices is rising. In manufacturing semiconductor devices with fine patterns corresponding to this trend of high integration, it is necessary to implement patterns with fine widths or fine spacing. Summary of the Invention

[0004] One or more example embodiments provide a semiconductor device including a contact structure having a first contact plug, a second contact plug, and a third contact plug.

[0005] According to one aspect of this disclosure, a semiconductor device includes: a substrate; an active region located in the substrate; a device isolation layer defining the active region; a gate structure located in the substrate and extending across the active region in a first horizontal direction; a bit line structure located on the substrate, extending in a second horizontal direction intersecting the first horizontal direction and intersecting the gate structure; and contact structures located between the bit line structures, wherein the contact structure includes: a first contact plug contacting the active region; a second contact plug located on the first contact plug; and a third contact plug located on the second contact plug, and wherein a first vertical central axis of the active region, a second vertical central axis of the first contact plug, and a third vertical central axis of the third contact plug are offset from each other in the first horizontal direction.

[0006] According to one aspect of this disclosure, a semiconductor device includes: a substrate; an active region located in the substrate; a device isolation layer defining the active region; a gate structure located in the substrate and extending across the active region in a first horizontal direction; a bit line structure located on the substrate, extending in a second horizontal direction intersecting the first horizontal direction and intersecting the gate structure; and contact structures located between the bit line structures, wherein the contact structures include: a first contact plug contacting the active region; a second contact plug located on the first contact plug; and a third contact plug located on the second contact plug, and wherein the device isolation layer includes a lower portion below the upper surface of the active region and an upper portion above the upper surface of the active region.

[0007] According to one aspect of this disclosure, a semiconductor device includes: a substrate; an active region located in the substrate and including a first impurity region and a second impurity region; a device isolation layer defining the active region; a gate structure located in the substrate and extending across the active region in a first horizontal direction; a bit line structure located on the substrate, extending in a second horizontal direction intersecting the first horizontal direction and intersecting the gate structure; contact structures located between the bit line structures; a landing pad located on the contact structures; and a capacitor structure located on the landing pad, wherein the bit line structure includes a bit line contact contacting the first impurity region, wherein the contact structure includes: a first contact plug contacting the active region; a second contact plug located on the first contact plug; and a third contact plug located on the second contact plug, wherein the first contact plug, the second contact plug, and the third contact plug comprise monocrystalline silicon, and wherein a first vertical central axis of the second impurity region, a second vertical central axis of the first contact plug, and a third vertical central axis of the third contact plug are offset from each other in the first horizontal direction. Attached Figure Description

[0008] The above and other aspects, features and advantages of this disclosure will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 It is a plan view of a semiconductor device according to one or more embodiments; Figure 2 yes Figure 1 The vertical cross-sectional view of the semiconductor device shown is taken along lines I-I' and II-II'; Figure 3 yes Figure 1 A vertical cross-sectional view of the semiconductor device shown, taken along line III-III'; Figure 4 yes Figure 2 A magnified view of a portion; Figure 5 , Figure 6 and Figure 7 It is a vertical cross-sectional view of a semiconductor device according to one or more embodiments; and Figure 8A , Figure 8B , Figure 8C , Figure 9A , Figure 9B , Figure 9C , Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 13C , Figure 14A , Figure 14B , Figure 14C , Figure 15A , Figure 15B , Figure 15C , Figure 16A , Figure 16B , Figure 16C , Figure 17A , Figure 17B , Figure 17C , Figure 18A , Figure 18B and Figure 18C These are plan views and vertical cross-sectional views shown according to the process sequence illustrating a method for manufacturing a semiconductor device according to one or more embodiments. Detailed Implementation

[0009] In the following description, exemplary embodiments will be illustrated with reference to the accompanying drawings.

[0010] It will be understood that when an element is referred to as being “connected” to or “attached” to another element, the element may be directly or indirectly connected to the other element.

[0011] Furthermore, when a component "comprises" or "includes" an element, the component may also include other elements, without excluding other elements, unless there is a specific description to the contrary.

[0012] Throughout the description, when a component is “on” another component, this includes not only when the component is in contact with the other component, but also when there is another component between the two components.

[0013] As used herein, the expression “at least one of a, b and c” indicates “only a”, “only b”, “only c”, “both a and b”, “both a and c”, “both b and c”, and “all of a, b and c”.

[0014] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, this disclosure should not be limited by these terms. These terms are used only to distinguish one element from another.

[0015] As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “one,” and “the” are intended to include the plural forms as well.

[0016] Identification codes may be used for the purpose of description of any method or process described herein, but are not intended to indicate the order of each step or operation. Each step or operation may be performed in a different order than shown unless the context clearly indicates otherwise. One or more steps or operations may be omitted unless the context of this disclosure explicitly indicates otherwise.

[0017] Figure 1 It is a plan view of a semiconductor device according to one or more embodiments. Figure 2 yes Figure 1 The diagram shows a vertical cross-sectional view of the semiconductor device taken along lines I-I' and II-II'. Figure 3 yes Figure 1 The diagram shows a vertical cross-sectional view of the semiconductor device taken along line III-III'. Figure 4 yes Figure 2 A magnified view of a portion of it.

[0018] Reference Figures 1 to 4 The semiconductor device 100 according to one or more embodiments may include an active region 6a, a device isolation layer 6s, a gate structure GS, a buffer layer 21, a bit line structure BLS, a spacer structure SP, a contact structure CS, a landing pad 69, and a capacitor structure 80. The semiconductor device 100 can be applied to, for example, a cell array of dynamic random access memory (DRAM), but this disclosure is not limited thereto. The active region 6a and the gate structure GS can be used as memory cell transistors in the cell array.

[0019] Substrate 3 may include semiconductor materials, such as group IV semiconductors, group III-V compound semiconductors, or group II-VI compound semiconductors. For example, group IV semiconductors may include silicon, germanium, or silicon-germanium. Substrate 3 may be a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate including an epitaxial layer.

[0020] An active region 6a and a device isolation layer 6s can be disposed within the substrate 3. The device isolation layer 6s can be an insulating layer extending downward from the upper surface of the substrate 3 and can define the active region 6a. For example, the active region 6a can correspond to the portion of the upper surface of the substrate 3 surrounded by the device isolation layer 6s. In a plan view, the active region 6a can have a strip shape having a minor axis and a major axis, and can extend in an inclined direction relative to the X and Y directions. However, the active region 6a can have other shapes such as a column shape. Similarly, the active region can be tapered in the vertical direction.

[0021] The active region 6a may include a first impurity region 9a and a second impurity region 9b extending from its upper surface to a predetermined depth. The first impurity region 9a and the second impurity region 9b may be spaced apart from each other. The first impurity region 9a and the second impurity region 9b may be configured as the source / drain regions of a memory cell transistor. For example, for an active region 6a, two gate structures GS may intersect with this active region 6a, a drain region may be formed between the two gate structures GS, and a source region may be formed in the region opposite to the drain regions of the two gate structures GS. For example, the first impurity region 9a may correspond to the drain region, and the second impurity region 9b may correspond to the source region. The source and drain regions are formed by the first impurity region 9a and the second impurity region 9b by doping or ion implantation of substantially the same impurity, and the source and drain regions may be interchangeably referenced according to the circuit configuration of the final transistor to be formed. The first impurity region 9a and the second impurity region 9b may include impurities having a conductivity type opposite to that of the substrate 3. For example, the active region 6a may include p-type impurities, and the first impurity region 9a and the second impurity region 9b may have n-type impurities.

[0022] The device isolation layer 6s can extend downward from the upper surface of the substrate 3 and can define the active region 6a. The device isolation layer 6s can surround the active region 6a while separating the active region 6a from each other. The device isolation layer 6s can include silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof, and can be formed as a single layer or multiple layers.

[0023] In one or more embodiments, the device isolation layer 6s may include a lower portion 6s_1 and an upper portion 6s_2 on the lower portion 6s_1. The lower portion 6s_1 may refer to the portion of the device isolation layer 6s that is lower than the upper surface of the active region 6a in the vertical (Z) direction, and the upper portion 6s_2 may refer to the portion of the device isolation layer 6s that is higher than the upper surface of the active region 6a in the vertical direction. The upper portion 6s_2 may contact the upper surface of the active region 6a. In one or more embodiments, the horizontal width of the upper portion 6s_2 along the X direction may be greater than the horizontal width of the lower portion 6s_1 along the X direction, but this disclosure is not limited thereto.

[0024] In the plan view, the gate structures GS can extend in the X direction and can be spaced apart from each other in the Y direction. Transistors, each including a gate structure GS and a first impurity region 9a and a second impurity region 9b, can form a buried channel array transistor (BCAT), but this disclosure is not limited thereto.

[0025] In the cross-sectional view, the gate structure GS can be embedded in the substrate 3, and for example, the gate structure GS can be disposed within a gate trench 12 formed in the substrate 3. The gate structure GS may include a gate dielectric layer 14, a gate electrode 16, and a gate capping layer 18 disposed within the gate trench 12. The gate dielectric layer 14 may be conformally formed on the inner wall of the gate trench 12. The gate electrode 16 may be disposed on the lower part of the gate trench 12, and the gate capping layer 18 may be disposed on the upper part of the gate structure GS and may fill the gate trench 12.

[0026] The gate dielectric layer 14 may comprise silicon oxide or a material having a high dielectric constant. In one or more embodiments, the gate dielectric layer 14 may be a layer formed by oxidizing the first active region 6a or by deposition. The gate electrode 16 may comprise a first electrode layer 16a, a second electrode layer 16b, and a third electrode layer 16c sequentially stacked.

[0027] The first electrode layer 16a may include at least one selected from titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and aluminum (Al). In one or more embodiments, the first electrode layer 16a may include titanium nitride (TiN). The second electrode layer 16b may include cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), or other metal silicides. The third electrode layer 16c may include polysilicon. The gate cap layer 18 may include silicon nitride.

[0028] A buffer layer 21 may be disposed on the active region 6a, the device isolation layer 6s, and the gate structure GS, and may extend in the horizontal direction. The buffer layer 21 may contact the upper surface of the device isolation layer 6s. For example, the lower surface of the buffer layer 21 may contact the upper portion 6s_2 of the device isolation layer 6s. The buffer layer 21 may contact the gate structure GS. For example, the lower surface of the buffer layer 21 may contact the gate dielectric layer 14 and the gate cap layer 18. The buffer layer 21 may comprise silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. The buffer layer 21 may consist of a single layer or multiple layers.

[0029] The bit line structure BLS extends in the Y direction and may be spaced apart from each other in the X direction. The bit line structure BLS may have a strip shape extending in the Y direction. The bit line structure BLS may include a bit line BL and a bit line capping layer 28 on the bit line BL. The bit line BL may include a first conductive layer 25a, a second conductive layer 25b, and a third conductive layer 25c sequentially stacked on a buffer layer 21. The first conductive layer 25a may include polysilicon. The second conductive layer 25b may include a metal semiconductor compound. The metal semiconductor compound may be, for example, a layer in which a portion of the first conductive layer 25a is silicided. For example, the metal semiconductor compound may include cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), or other metal silicides, or may include nitrides such as TiSiN. The third conductive layer 25c may include a metallic material such as titanium (Ti), tantalum (Ta), tungsten (W), and aluminum (Al). The bit line BL may further include a bit line contact 25p, which is disposed below the first conductive layer 25a and extends downward to contact the first impurity region 9a. The bit line contact 25p may be located within a contact hole H formed on the upper surface of the substrate 3. In a plan view, the bit line contact 25p may contact the first impurity region 9a, which is the central portion of the active region 6a. The bit line contact 25p can electrically connect the active region 6a to the bit line structure BLS. The bit line contact 25p may include the same material as the first conductive layer 25a and may be integrally formed with the first conductive layer 25a.

[0030] The bit line capping layer 28 may include a first capping layer 28a, a second capping layer 28b, and a third capping layer 28c disposed on the bit line BL. The side surface of the first capping layer 28a may be coplanar with the first conductive layer 25a, the second conductive layer 25b, and the third conductive layer 25c. The first capping layer 28a, the second capping layer 28b, and the third capping layer 28c may include silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof, and may include, for example, silicon nitride.

[0031] Spacer structures SP can be respectively disposed on both sides of bit line structure BLS and can extend along the side surface of bit line structure BLS in the Y direction. Spacer structure SP can include a first spacer SP1, a second spacer SP2, a third spacer SP3, and a fourth spacer SP4 disposed on the side surface of bit line structure BLS. The first spacer SP1 can be conformally disposed along the side surface of bit line structure BLS and contact hole H. The second spacer SP2 can be disposed on the first spacer SP1 and can fill contact hole H. The third spacer SP3 can cover the side surface of the first spacer SP1, and the fourth spacer SP4 can cover the side surface of the third spacer SP3. The third spacer SP3 and the fourth spacer SP4 can cover the upper surface of the second spacer SP2. The first spacer SP1, second spacer SP2, third spacer SP3, and fourth spacer SP4 can include silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. The spacer structure SP disclosed herein is illustrative, and the materials and number of layers are not limited thereto and can be varied.

[0032] The contact structure CS can be disposed between the bit line structures BLS and can contact the spacer structure SP. The contact structure CS can be disposed between the bit line structures BLS and between the gate structures GS. The contact structure CS can electrically connect the active region 6a to the landing pad 69.

[0033] The contact structure CS may include a first contact plug 20, a second contact plug 30, and a third contact plug 40 stacked sequentially. The first contact plug 20 may contact the upper surface of the active region 6a. For example, the lower surface of the first contact plug 20 may be coplanar with the upper surface of the second impurity region 9b and may be electrically connected to the second impurity region 9b. In a cross-sectional view, the first contact plug 20 may be configured to offset from the second impurity region 9b in the X direction. For example, the side surface of the first contact plug 20 may offset from the side surface of the second impurity region 9b in the X direction, and a portion of the first contact plug 20 may be configured to offset from the second impurity region 9b in the X direction without vertically overlapping it. In a cross-sectional view, the vertical central axis of the second impurity region 9b may be configured to offset from the vertical central axis of the first contact plug 20 in the X direction without aligning with it. The first contact plug 20 may contact the device isolation layer 6s. For example, the lower surface of the first contact plug 20 may contact the lower portion 6s_1 of the device isolation layer 6s, and the side surface of the first contact plug 20 may contact the upper portion 6s_2 of the device isolation layer 6s. The upper surface of the first contact plug 20 may contact the buffer layer 21 and may be coplanar with the upper portion 6s_2 of the device isolation layer 6s. In a plan view, the side surface of the first contact plug 20 may include a recess R1. The recess R1 may correspond to a portion of the contact hole H. The recess R1 may contact the first spacer SP1 of the spacer structure SP.

[0034] Reference Figure 1 In the plan view, the maximum horizontal width W1 of the first contact plug 20 along the X direction can be greater than the maximum horizontal width W2 of the second contact plug 30 along the X direction. The maximum horizontal width W2 of the third contact plug 40 along the X direction can be the same as the maximum horizontal width W2 of the second contact plug 30 along the X direction. The horizontal width of the first contact plug 20 along the Y direction can be the same as the horizontal width of the second contact plug 30 and the horizontal width of the third contact plug 40 along the Y direction.

[0035] The second contact plug 30 may contact the first contact plug 20. In one or more embodiments, the upper surface of the first contact plug 20 may include a recess R2, and a portion of the side surface and a portion of the lower surface of the second contact plug 30 may contact the recess R2. The lower surface of the second contact plug 30 may be positioned at a level lower than the top of the first contact plug 20 and the upper surface of the upper portion 6s_2 of the device isolation layer 6s. The second contact plug 30 may contact the buffer layer 21 and the spacer structure SP. In one or more embodiments, the second contact plug 30 may be offset from the first contact plug 20 in the X direction. For example, a portion of the second contact plug 30 may not vertically overlap with the first contact plug 20. In a cross-sectional view, the vertical central axis of the second contact plug 30 may be configured to be offset from the vertical central axis of the first contact plug 20 in the X direction and not aligned with the vertical central axis of the first contact plug 20. In one or more embodiments, the upper surface of the second contact plug 30 may not be parallel to the upper surface of the substrate 3 and may be inclined relative to the upper surface of the substrate 3.

[0036] The third contact plug 40 can contact the second contact plug 30. The third contact plug 40 can contact the spacer structure SP. The horizontal width of the third contact plug 40 along the X direction can be the same as the horizontal width of the second contact plug 30 along the X direction. The horizontal width of the third contact plug 40 along the Y direction can be the same as the horizontal width of the second contact plug 30 along the Y direction. In the cross-sectional view, the vertical central axis of the third contact plug 40 can be aligned with the vertical central axis of the second contact plug 30 in the X direction. The bottom of the third contact plug 40 can be positioned at a level higher than the upper surface of the active region 6a and the upper surface of the buffer layer 21, and can be positioned at a level higher than the bit line contact 25p.

[0037] The first contact plug 20, the second contact plug 30, and the third contact plug 40 may be made of a conductive material and may include at least one of, for example, polycrystalline silicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and aluminum (Al). In one or more embodiments, the first contact plug 20, the second contact plug 30, and the third contact plug 40 may include at least one of doped monocrystalline silicon and doped polycrystalline silicon, and may include n-type impurities such as phosphorus (P), arsenic (As), and antimony (Sb).

[0038] In one or more embodiments, the first contact plug 20 can be formed from the second impurity region 9b of the active region 6a using a selective epitaxial growth (SEG) method. In one or more embodiments, the crystal orientation of a portion of the first contact plug 20 may differ from the crystal orientation of the second impurity region 9b. For example, the first contact plug 20 may include a region 20a having a crystal orientation different from that of the second impurity region 9b. The crystal orientation of the first contact plug 20, excluding region 20a, may be the same as that of the second impurity region 9b. The doping concentration of the first contact plug 20 may be greater than that of the second impurity region 9b.

[0039] In one or more embodiments, the second contact plug 30 can be formed from the first contact plug 20 using a selective epitaxial growth method. In one or more embodiments, a portion of the second contact plug 30 may have a different crystal orientation than the first contact plug 20. For example, the second contact plug 30 may include a region 30a having a crystal orientation different from that of the first contact plug 20. The crystal orientation of the second contact plug 30, excluding region 30a, may be the same as that of the first contact plug 20 (e.g., the portion excluding region 20a). The doping concentration of the second contact plug 30 may be greater than that of the first contact plug 20.

[0040] In one or more embodiments, the third contact plug 40 can be formed by depositing polysilicon on the second contact plug 30 and subsequently annealing the polysilicon. In one or more embodiments, the crystal orientation of a portion of the third contact plug 40 may differ from the crystal orientation of the second contact plug 30. For example, the third contact plug 40 may include a region 40a having a crystal orientation different from that of the second contact plug 30. The crystal orientation of the third contact plug 40, excluding region 40a, may be the same as that of the second contact plug 30 (e.g., a portion excluding region 30a). The doping concentration of the third contact plug 40 may be greater than that of the second contact plug 30. The shape, size, and location of regions 20a, 30a, and 40a are illustrative and not limited thereto.

[0041] A gate structure 63 may be disposed between bit line structures BLS and may overlap with the gate structure GS in the vertical direction. The gate structure 63 may be alternately disposed with contact structures CS along the Y direction. The gate structure 63 may spatially separate and electrically insulate the contact structures CS from each other. The lower surface of the gate structure 63 may contact the gate cap layer 18 of the gate structure GS. In one or more embodiments, the bottom of the gate structure 63 may be located at a level lower than the upper surface of the substrate 3. The gate structure 63 may comprise an insulating material such as silicon nitride.

[0042] The semiconductor device 100 may further include a metal-semiconductor compound layer 66 disposed on the upper surface of the contact structure CS. The metal-semiconductor compound layer 66 may contact the side surfaces of the spacer structure SP and the side surfaces of the gate structure 63.

[0043] Landing pad 69 may be disposed on metal semiconductor compound layer 66 and may include barrier layer 69a covering bit line structure BLS, spacer structure SP and gate structure 63, and metal layer 69b on barrier layer 69a. Landing pad 69 may be electrically connected to second impurity region 9b of active region 6a via contact structure CS. Metal semiconductor compound layer 66 may include cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi) or other metal silicides. Barrier layer 69a may include at least one of metal nitrides (e.g., titanium nitride (TiN), tantalum nitride (TaN) and tungsten nitride (WN)). Metal layer 69b may include at least one of conductive materials (e.g., titanium (Ti), tantalum (Ta), tungsten (W) and aluminum (Al)).

[0044] The semiconductor device 100 may further include an upper insulating spacer 50 covering the upper portion of the bit line structure BLS, the spacer structure SP, and the gate structure 63. The upper insulating spacer 50 may be disposed between the bit line structure BLS and the barrier layer 69a, between the spacer structure SP and the barrier layer 69a, and between the gate structure 63 and the barrier layer 69a.

[0045] The semiconductor device 100 may further include an insulating pattern 72 disposed between the landing pads 69. The upper surface of the insulating pattern 72 may be coplanar with the upper surface of the landing pads 69, and the insulating pattern 72 may extend downward to partially contact the bit line structure BLS. The insulating pattern 72 may spatially separate the landing pads 69 from each other and electrically insulate the landing pads from each other.

[0046] The semiconductor device 100 may further include an etch stop layer 75 covering the upper surface of the landing pad 69 and the insulating pattern 72. A capacitor structure 80 may be disposed on the landing pad 69 and the insulating pattern 72. The capacitor structure 80 may include a lower electrode 82, a capacitor dielectric layer 84, and an upper electrode 86. The lower electrode 82 may penetrate the etch stop layer 75 and contact the upper surface of the landing pad 69. The capacitor dielectric layer 84 may cover the lower electrode 82 and the etch stop layer 75, and the upper electrode 86 may cover the capacitor dielectric layer 84. The capacitor structure 80 may be electrically connected to the landing pad 69 and the contact structure CS. The lower electrode 82 and the upper electrode 86 may include at least one of a doped semiconductor, a metal nitride, a metal, and a metal oxide. The lower electrode 82 and the upper electrode 86 may include at least one of, for example, polysilicon, titanium nitride (TiN), tungsten (W), titanium (Ti), ruthenium (Ru), and tungsten nitride (WN). For example, the capacitor dielectric layer 84 may include at least one of a high-k material, such as zirconium oxide (ZrO2), aluminum oxide (Al2O3), and hafnium oxide (Hf2O3).

[0047] Figures 5 to 7 It is a vertical cross-sectional view of a semiconductor device according to one or more embodiments.

[0048] Reference Figure 5 The semiconductor device 100a may include a first contact plug 20 between a second impurity region 9b and a second contact plug 30. In one or more embodiments, the first contact plug 20 may include regions with different crystal orientations. For example, the first contact plug 20 may include region 20b. Region 20b may include, as will be referred to below... Figures 14A to 14C The second contact material layer 20p2 is described. The crystal orientation of region 20b may differ from the crystal orientation of the first contact plug 20, excluding regions 20a and 20b.

[0049] Reference Figure 6 The semiconductor device 100b may include a first contact plug 20 between the second impurity region 9b and the second contact plug 30. In one or more embodiments, the side surface of the first contact plug 20 that contacts the upper portion 6s_2 of the device isolation layer 6s may be coplanar with the second contact plug 30. The side surface of the second contact plug 30 may contact the upper portion 6s_2 of the device isolation layer 6s.

[0050] Reference Figure 7The semiconductor device 100c may include a first contact plug 20 between the second impurity region 9b and the second contact plug 30. In one or more embodiments, the width of the first contact plug 20 along the X direction may be smaller than the width of the second contact plug 30 along the X direction. For example, the first contact plug 20 may completely overlap the second contact plug 30 in the vertical direction, and a portion of the second contact plug 30 may not overlap the first contact plug 20 in the vertical direction. The side surface of the second contact plug 30 may contact the upper portion 6s_2 of the device isolation layer 6s.

[0051] Figures 8A to 18C These are plan views and vertical cross-sectional views illustrating a method of manufacturing a semiconductor device according to one or more embodiments, arranged in process sequence. Specifically, Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A and Figure 18A It is a plan view showing the process sequence of a method for manufacturing a semiconductor device. Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12A , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B and Figure 18B They are respectively along Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A and Figure 18A Vertical cross-sectional views of lines I-I' and II-II'. Figure 8C , Figure 9C , Figure 10C , Figure 12B , Figure 13C , Figure 14C , Figure 15C , Figure 16C , Figure 17C and Figure 18C They are respectively along Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A and Figure 18A The vertical cross-section diagram taken from line III-III'.

[0052] Reference Figures 8A to 8C A device isolation layer 6s can be formed on the substrate 3. The device isolation layer 6s can define an active region 6a. The portion of the device isolation layer 6s disposed between four adjacent active regions 6a can be formed relatively deeper than the portion of the device isolation layer 6s disposed between two adjacent active regions 6a. The device isolation layer 6s can be formed by forming trenches on the upper surface of the substrate 3 and depositing insulating material to fill the trenches. The device isolation layer 6s can cover the upper surface of the active region 6a. The portion of the device isolation layer 6s below the upper surface of the active region 6a can be referred to as the lower portion 6s_1, and the portion of the device isolation layer 6s above the upper surface of the active region 6a can be referred to as the upper portion 6s_2.

[0053] The active region 6a may include a first impurity region 9a and a second impurity region 9b. The first impurity region 9a and the second impurity region 9b can be formed by doping the active region 6a with an n-type impurity. For example, after forming the device isolation layer 6s, the first impurity region 9a and the second impurity region 9b can be formed by a doping process.

[0054] Reference Figures 9A to 9C A gate trench 12 can be formed within the substrate 3, intersecting the device isolation layer 6s and the active region 6a. The gate trench 12 can be formed using an anisotropic etching process. The gate trench 12 can extend in the X direction and can be spaced apart from each other in the Y direction. The active region 6a and the device isolation layer 6s can be etched using an etching process. A gate dielectric layer 14 can be formed on the gate trench 12. The gate dielectric layer 14 can be conformally formed along the inner wall of the gate trench 12 and can contact the active region 6a and the device isolation layer 6s.

[0055] A first electrode layer 16a, a second electrode layer 16b, and a third electrode layer 16c may be sequentially formed on the gate dielectric layer 14 within the gate trench 12. The first electrode layer 16a, the second electrode layer 16b, and the third electrode layer 16c may form the gate electrode 16. A gate capping layer 18 may be formed on the third electrode layer 16c, and the gate capping layer 18 may completely fill the gate trench 12. The gate capping layer 18 may be formed to cover the device isolation layer 6s, and the gate capping layer 18 may include a material that has etch selectivity relative to the device isolation layer 6s.

[0056] Reference Figures 10A to 10CThe upper part of the gate cap layer 18 can be removed using a planarization process. The upper surface of the planarized gate cap layer 18 can be coplanar with the device isolation layer 6s and the gate dielectric layer 14. The gate dielectric layer 14, the gate electrode 16, and the gate cap layer 18 can form a gate structure GS. The gate structure GS can extend across the device isolation layer 6s and the active region 6a in the X direction and can be spaced apart from each other in the Y direction.

[0057] Reference Figure 11A and Figure 11B A mask layer M can be formed. The mask layer M can extend in the Y direction and can be spaced apart from each other in the X direction. The mask layer M can be configured to overlap with the first impurity region 9a of the active region 6a. For example, at least a portion of the first impurity region 9a of the active region 6a can vertically overlap with the mask layer M.

[0058] Reference Figure 12A and Figure 12B The device isolation layer 6s can be etched using an etching process that uses a mask layer M as an etching mask, and the second impurity region 9b of the active region 6a can be exposed. In one or more embodiments, the corresponding upper surface of the second impurity region 9b can be partially exposed rather than fully exposed.

[0059] Reference Figures 13A to 13C A first contact material layer 20p1 can be formed. In one or more embodiments, the first contact material layer 20p1 can be formed by growing from the upper surface of the second impurity region 9b of the active region 6a via a selective epitaxial growth method. The first contact material layer 20p1 may include at least one of doped monocrystalline silicon and doped polycrystalline silicon. For example, the first contact material layer 20p1 is grown from the second impurity region 9b formed of monocrystalline silicon, and the first contact material layer 20p1 may therefore include monocrystalline silicon having the same crystal orientation as the second impurity region 9b. According to one or more embodiments, a portion of the first contact material layer 20p1 may include doped polycrystalline silicon or monocrystalline silicon having a different crystal orientation than the second impurity region 9b. The first contact material layer 20p1 may include n-type impurities, and the doping concentration of the first contact material layer 20p1 may be greater than the doping concentration of the second impurity region 9b.

[0060] The first contact material layer 20p1 can be grown in both the horizontal and vertical directions to cover the lower part 6s_2 of the device isolation layer 6s, so that the lower part 6s_1 of the device isolation layer 6s is not exposed. The top of the first contact material layer 20p1 can be formed to be higher than the upper part 6s_2 of the device isolation layer 6s.

[0061] Reference Figures 14A to 14CA second contact material layer 20p2 can be formed on the first contact material layer 20p1. The second contact material layer 20p2 can extend horizontally and completely cover the device isolation layer 6s, the gate structure GS, and the first contact material layer 20p1. The second contact material layer 20p2 can be formed by depositing polycrystalline silicon, and at least a portion of the second contact material layer 20p2 can include crystallized monocrystalline silicon having the same crystal orientation as the first contact material layer 20p1. According to one or more embodiments, a portion of the second contact material layer 20p2 can include doped polycrystalline silicon or monocrystalline silicon having a different crystal orientation than the first contact material layer 20p1.

[0062] Reference Figures 15A to 15C The first contact material layer 20p1 and the second contact material layer 20p2 can be planarized, exposing the upper surface of the device isolation layer 6s and the upper surface of the gate structure GS, thereby forming the first contact plug 20. In one or more embodiments, the second contact material layer 20p2 can be completely removed, and the first contact material layer 20p1 can be planarized to form the first contact plug 20. In one or more embodiments, the second contact material layer 20p2 can not be completely removed, and the second contact material layer 20p2 can form the first contact plug 20 together with the first contact material layer 20p1. For example, in reference to Figures 13A to 13C In the described process of forming the first contact material layer 20p1, if the first contact material layer 20p1 is not sufficiently grown to cover the side surface of the upper portion 6s_2 of the device isolation layer 6s, then the second contact material layer 20p2 can be interposed between the first contact material layer 20p1 and the upper portion 6s_2 of the device isolation layer 6s (see [link to documentation]). Figure 5 ).

[0063] The upper surface of the first contact plug 20 may be coplanar with the device isolation layer 6s and the gate structure GS. A buffer layer 21 may be formed on the device isolation layer 6s, the first contact plug 20, and the gate structure GS. The buffer layer 21 may extend in the horizontal direction and may consist of a single layer or multiple layers.

[0064] Reference Figures 16A to 16CA bit line structure (BLS) can be formed on the buffer layer 21. The bit line structure BLS can be formed by the following steps: etching the buffer layer 21 to expose the first impurity region 9a of the active region 6a to form a contact hole H; stacking a conductive material layer on the contact hole H and the buffer layer 21; forming an insulating material layer on the conductive material layer; and patterning the conductive and insulating material layers. For example, the patterned conductive and insulating material layers can extend in the Y direction and form the bit line structure BLS. The inner wall of the contact hole H can be partially exposed by the patterning process. The bit line structures BLS can extend in the Y direction and can be spaced apart from each other in the X direction. In one or more embodiments, when forming the contact hole H, the first contact plug 20 can be partially etched, and when viewed in a plan view, the first contact plug 20 may include a recess R1 on its side surface.

[0065] The bitline structure BLS may include a bitline contact 25p having a conductive material, a bitline BL, and a bitline capping layer 28 having an insulating material. The bitline BL may include a first conductive layer 25a, a second conductive layer 25b, and a third conductive layer 25c stacked sequentially, and the first conductive layer 25a may be disposed on the bitline contact 25p disposed within a contact hole H. The bitline capping layer 28 may include a first capping layer 28a, a second capping layer 28b, and a third capping layer 28c stacked sequentially.

[0066] Spacer structures SP can be formed on the side surface of the bit line structure BLS. The spacer structure SP can extend along the bit line structure BLS in the Y direction. The spacer structure SP may include a first spacer SP1, a second spacer SP2, a third spacer SP3, and a fourth spacer SP4. The first spacer SP1 can be formed conformally along the side surface of the bit line structure BLS and the contact hole H. The second spacer SP2 can be disposed on the first spacer SP1 and can fill the contact hole H. The third spacer SP3 can cover the side surface of the first spacer SP1, and the fourth spacer SP4 can cover the side surface of the third spacer SP3.

[0067] After forming the spacer structure SP, an anisotropic etching process can be performed to expose the first contact plug 20, thereby forming a trench T. The buffer layer 21 can be etched by the etching process, and the first contact plug 20 can also be partially etched. The trench T can be defined by the side surface of the spacer structure SP, the side surface of the buffer layer 21, and the upper surface of the first contact plug 20. Since the trench T is formed to expose the first contact plug 20, the trench T can be relatively shallow compared to the case where the trench is formed to expose the second impurity region 9b. Therefore, the difficulty of the anisotropic etching process can be reduced, and a smaller semiconductor device 100 can be implemented.

[0068] Reference Figures 17A to 17C A second contact plug 30 may be formed on the first contact plug 20. The second contact plugs 30 may be disposed in the groove T and may be spaced apart from each other along the groove T in the Y direction.

[0069] In one or more embodiments, the second contact plug 30 can be formed by growing from the upper surface of the first contact plug 20 via a selective epitaxial growth method. The second contact plug 30 may comprise at least one of doped monocrystalline silicon and doped polycrystalline silicon. For example, the second contact plug 30 is grown from the first contact plug 20, which comprises monocrystalline silicon, and may therefore comprise monocrystalline silicon having the same crystal orientation as the first contact plug 20. According to one or more embodiments, a portion of the second contact plug 30 may comprise doped polycrystalline silicon or monocrystalline silicon having a different crystal orientation than the first contact plug 20. The second contact plug 30 may include n-type impurities, and the doping concentration of the second contact plug 30 may be greater than the doping concentration of the first contact plug 20.

[0070] Reference Figures 18A to 18C A contact material layer 40p can be formed on the second contact plug 30. The contact material layer 40p can completely fill the trench T and cover the bit line structure BLS and the spacer structure SP. The contact material layer 40p can be formed by depositing doped polysilicon and annealing the doped polysilicon. The annealing process can include a melt laser annealing (MLA) method using laser heating of the doped polysilicon. If the trench T is formed deep enough to expose the second impurity region 9b of the active region 6a, there is a concern that the bit line contact 25p, the first spacer SP1, and the second spacer SP2 may be heated and degraded during the process of annealing the contact material layer 40p. However, according to one or more embodiments, the first contact plug 20 and the second contact plug 30 are formed on the second impurity region 9b, and the contact material layer 40p is formed on the second contact plug 30, and an annealing process can then be performed. This method increases the distance between the lower end of the contact material layer 40p and the lower end of the bit line contact 25p, preventing the bit line contact 25p, the first spacer SP1, and the second spacer SP2 from deteriorating due to the annealing process, and preventing or reducing voids in the bit line contact 25p. Furthermore, according to one or more embodiments, the distance between the lower end of the contact material layer 40p and the lower end of the bit line contact 25p can be increased without decreasing the distance between the lower end of the bit line contact 25p and the upper surface of the gate electrode 16. Therefore, electrical coupling between the bit line BL and the gate electrode 16 can be prevented or reduced.

[0071] Refer again Figures 1 to 4A gate structure 63 can be formed. The gate structure 63 can be formed by the following steps: removing a portion of the contact material layer 40p using an anisotropic etching process to expose the upper surface of the gate cap layer 18, and subsequently filling the space removed from this portion of the contact material layer 40p with an insulating material. The gate structure can be formed such that it overlaps with the gate structure GS in the vertical direction between the bit line structures BLS. The gate structures 63 can be configured to be spaced apart from each other in the X and Y directions.

[0072] After forming the fence structure 63, the contact material layer 40p can be etched back so that the upper surface of the contact material layer 40p becomes lower than the upper surface of the fence structure 63, allowing the formation of the third contact plug 40. The first contact plug 20, the second contact plug 30, and the third contact plug 40 can constitute the contact structure CS. The contact structure CS can be alternately arranged with the fence structure 63 along the Y direction between the bit line structures BLS.

[0073] A metal semiconductor compound layer 66 and a landing pad 69 can be formed on the contact structure CS. An insulating material can be formed to cover the landing pad 69, and the insulating material can be planarized to expose the upper surface of the landing pad 69, thereby forming an insulating pattern 72. The landing pad 69 can be electrically connected to the second impurity region 9b through the contact structure CS. The landing pads 69 can be spatially separated from each other by the insulating pattern 72 and can be electrically insulated from each other. An etch stop layer 75 and a capacitor structure 80 can be formed on the landing pad 69 and the insulating pattern 72, thereby fabricating a semiconductor device 100.

[0074] As described above, according to one or more embodiments, a third contact plug can be formed on the first contact plug and the second contact plug. Therefore, voids in the bit line contacts can be prevented or reduced during the annealing process used to form the third contact plug, and deterioration of the bit line contacts can be prevented.

[0075] Although one or more embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and alterations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising: Substrate; The active region is located within the substrate; A device isolation layer that defines the active region; A gate structure located in the substrate and extending across the active region in a first horizontal direction; A bitline structure is located on the substrate, extends in a second horizontal direction intersecting the first horizontal direction, and intersects the gate structure; as well as A contact structure located between the bit line structures. The contact structure includes: The first contact plug is in contact with the active region; A second contact plug, located on top of the first contact plug; and The third contact plug is located on top of the second contact plug, and The first vertical central axis of the active region, the second vertical central axis of the first contact plug, and the third vertical central axis of the third contact plug are offset from each other in the first horizontal direction.

2. The semiconductor device according to claim 1, wherein, Each of the first contact plug, the second contact plug, and the third contact plug comprises monocrystalline silicon.

3. The semiconductor device according to claim 1, wherein, At least a portion of the first contact plug has a crystal orientation that is different from the crystal orientation of the active region.

4. The semiconductor device according to claim 1, wherein, At least a portion of the second contact plug has a crystal orientation that is different from that of the first contact plug.

5. The semiconductor device according to claim 1, wherein, At least a portion of the third contact plug has a crystal orientation that is different from that of the second contact plug.

6. The semiconductor device according to claim 1, wherein, The first contact plug has a first doping concentration, the second contact plug has a second doping concentration, and the third contact plug has a third doping concentration. Wherein, the second doping concentration is greater than the first doping concentration and less than the third doping concentration.

7. The semiconductor device according to claim 1, wherein, The first contact plug includes a recess in its upper surface. Wherein, at least a portion of the side surface of the second contact plug contacts the recess, and At least a portion of the lower surface of the second contact plug is in contact with the recess.

8. The semiconductor device according to claim 1, wherein, The first contact plug includes a first part and a second part, and The second part has a crystal orientation that is different from that of the first part.

9. The semiconductor device according to claim 1, wherein, The side surface of the second contact plug is in contact with the device isolation layer.

10. The semiconductor device according to claim 1, wherein, The width of the second contact plug in the first horizontal direction is the same as the width of the third contact plug in the first horizontal direction.

11. The semiconductor device according to claim 1, wherein, The lower surface of the first contact plug is coplanar with the upper surface of the active region.

12. The semiconductor device according to claim 1, wherein, At least a portion of the second contact plug is offset from the first contact plug in the first horizontal direction.

13. A semiconductor device, comprising: Substrate; The active region is located within the substrate; A device isolation layer that defines the active region; A gate structure located in the substrate and extending across the active region in a first horizontal direction; A bitline structure is located on the substrate, extends in a second horizontal direction intersecting the first horizontal direction, and intersects the gate structure; as well as A contact structure located between the bit line structures. The contact structure includes: The first contact plug is in contact with the active region; A second contact plug, located on top of the first contact plug; and The third contact plug is located on top of the second contact plug, and The device isolation layer includes a lower portion below the upper surface of the active region and an upper portion above the upper surface of the active region.

14. The semiconductor device according to claim 13, wherein, The lower surface of the first contact plug contacts the lower part, and the side surface of the first contact plug contacts the upper part.

15. The semiconductor device according to claim 13, wherein, The upper surface of the active region is in contact with the upper part.

16. The semiconductor device according to claim 13, wherein, The upper part has a greater horizontal width in the first horizontal direction than the lower part has a greater horizontal width in the first horizontal direction.

17. The semiconductor device of claim 13, further comprising a buffer layer extending in a horizontal direction between the device isolation layer and the bit line structure. in, The upper surface of the first contact plug is in contact with the lower surface of the buffer layer.

18. The semiconductor device according to claim 17, wherein, The lower end of the third contact plug is located at a level higher than the upper surface of the buffer layer.

19. The semiconductor device according to claim 13, wherein, The lower end of the third contact plug is located at a level higher than the upper surface of the active region.

20. A semiconductor device, comprising: Substrate; An active region located in the substrate and comprising a first impurity region and a second impurity region; A device isolation layer that defines the active region; A gate structure located in the substrate and extending across the active region in a first horizontal direction; A bitline structure is located on the substrate, extends in a second horizontal direction intersecting the first horizontal direction, and intersects the gate structure; A contact structure located between the bit line structures; A landing pad, located on the contact structure; as well as A capacitor structure is located on the landing pad. The bit line structure includes a bit line contact element that contacts the first impurity region. The contact structure includes: The first contact plug is in contact with the active region; A second contact plug, located on top of the first contact plug; and The third contact plug is located on top of the second contact plug. Wherein, the first contact plug, the second contact plug, and the third contact plug comprise monocrystalline silicon, and The first vertical center axis of the second impurity region, the second vertical center axis of the first contact plug, and the third vertical center axis of the third contact plug are offset from each other in the first horizontal direction.

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